1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NXP FXLS8962AF/FXLS8964AF Accelerometer Core Driver 4 * 5 * Copyright 2021 Connected Cars A/S 6 * 7 * Datasheet: 8 * https://www.nxp.com/docs/en/data-sheet/FXLS8962AF.pdf 9 * https://www.nxp.com/docs/en/data-sheet/FXLS8964AF.pdf 10 * 11 * Errata: 12 * https://www.nxp.com/docs/en/errata/ES_FXLS8962AF.pdf 13 */ 14 15 #include <linux/bits.h> 16 #include <linux/bitfield.h> 17 #include <linux/i2c.h> 18 #include <linux/irq.h> 19 #include <linux/module.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/property.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/regmap.h> 25 #include <linux/types.h> 26 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/events.h> 29 #include <linux/iio/iio.h> 30 #include <linux/iio/kfifo_buf.h> 31 #include <linux/iio/sysfs.h> 32 33 #include "fxls8962af.h" 34 35 #define FXLS8962AF_INT_STATUS 0x00 36 #define FXLS8962AF_INT_STATUS_SRC_BOOT BIT(0) 37 #define FXLS8962AF_INT_STATUS_SRC_SDCD_OT BIT(4) 38 #define FXLS8962AF_INT_STATUS_SRC_BUF BIT(5) 39 #define FXLS8962AF_INT_STATUS_SRC_DRDY BIT(7) 40 #define FXLS8962AF_TEMP_OUT 0x01 41 #define FXLS8962AF_VECM_LSB 0x02 42 #define FXLS8962AF_OUT_X_LSB 0x04 43 #define FXLS8962AF_OUT_Y_LSB 0x06 44 #define FXLS8962AF_OUT_Z_LSB 0x08 45 #define FXLS8962AF_BUF_STATUS 0x0b 46 #define FXLS8962AF_BUF_STATUS_BUF_CNT GENMASK(5, 0) 47 #define FXLS8962AF_BUF_STATUS_BUF_OVF BIT(6) 48 #define FXLS8962AF_BUF_STATUS_BUF_WMRK BIT(7) 49 #define FXLS8962AF_BUF_X_LSB 0x0c 50 #define FXLS8962AF_BUF_Y_LSB 0x0e 51 #define FXLS8962AF_BUF_Z_LSB 0x10 52 53 #define FXLS8962AF_PROD_REV 0x12 54 #define FXLS8962AF_WHO_AM_I 0x13 55 56 #define FXLS8962AF_SYS_MODE 0x14 57 #define FXLS8962AF_SENS_CONFIG1 0x15 58 #define FXLS8962AF_SENS_CONFIG1_ACTIVE BIT(0) 59 #define FXLS8962AF_SENS_CONFIG1_RST BIT(7) 60 #define FXLS8962AF_SC1_FSR_MASK GENMASK(2, 1) 61 #define FXLS8962AF_SC1_FSR_PREP(x) FIELD_PREP(FXLS8962AF_SC1_FSR_MASK, (x)) 62 #define FXLS8962AF_SC1_FSR_GET(x) FIELD_GET(FXLS8962AF_SC1_FSR_MASK, (x)) 63 64 #define FXLS8962AF_SENS_CONFIG2 0x16 65 #define FXLS8962AF_SENS_CONFIG3 0x17 66 #define FXLS8962AF_SC3_WAKE_ODR_MASK GENMASK(7, 4) 67 #define FXLS8962AF_SC3_WAKE_ODR_PREP(x) FIELD_PREP(FXLS8962AF_SC3_WAKE_ODR_MASK, (x)) 68 #define FXLS8962AF_SC3_WAKE_ODR_GET(x) FIELD_GET(FXLS8962AF_SC3_WAKE_ODR_MASK, (x)) 69 #define FXLS8962AF_SENS_CONFIG4 0x18 70 #define FXLS8962AF_SC4_INT_PP_OD_MASK BIT(1) 71 #define FXLS8962AF_SC4_INT_PP_OD_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_PP_OD_MASK, (x)) 72 #define FXLS8962AF_SC4_INT_POL_MASK BIT(0) 73 #define FXLS8962AF_SC4_INT_POL_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_POL_MASK, (x)) 74 #define FXLS8962AF_SENS_CONFIG5 0x19 75 76 #define FXLS8962AF_WAKE_IDLE_LSB 0x1b 77 #define FXLS8962AF_SLEEP_IDLE_LSB 0x1c 78 #define FXLS8962AF_ASLP_COUNT_LSB 0x1e 79 80 #define FXLS8962AF_INT_EN 0x20 81 #define FXLS8962AF_INT_EN_SDCD_OT_EN BIT(5) 82 #define FXLS8962AF_INT_EN_BUF_EN BIT(6) 83 #define FXLS8962AF_INT_PIN_SEL 0x21 84 #define FXLS8962AF_INT_PIN_SEL_MASK GENMASK(7, 0) 85 #define FXLS8962AF_INT_PIN_SEL_INT1 0x00 86 #define FXLS8962AF_INT_PIN_SEL_INT2 GENMASK(7, 0) 87 88 #define FXLS8962AF_OFF_X 0x22 89 #define FXLS8962AF_OFF_Y 0x23 90 #define FXLS8962AF_OFF_Z 0x24 91 92 #define FXLS8962AF_BUF_CONFIG1 0x26 93 #define FXLS8962AF_BC1_BUF_MODE_MASK GENMASK(6, 5) 94 #define FXLS8962AF_BC1_BUF_MODE_PREP(x) FIELD_PREP(FXLS8962AF_BC1_BUF_MODE_MASK, (x)) 95 #define FXLS8962AF_BUF_CONFIG2 0x27 96 #define FXLS8962AF_BUF_CONFIG2_BUF_WMRK GENMASK(5, 0) 97 98 #define FXLS8962AF_ORIENT_STATUS 0x28 99 #define FXLS8962AF_ORIENT_CONFIG 0x29 100 #define FXLS8962AF_ORIENT_DBCOUNT 0x2a 101 #define FXLS8962AF_ORIENT_BF_ZCOMP 0x2b 102 #define FXLS8962AF_ORIENT_THS_REG 0x2c 103 104 #define FXLS8962AF_SDCD_INT_SRC1 0x2d 105 #define FXLS8962AF_SDCD_INT_SRC1_X_OT BIT(5) 106 #define FXLS8962AF_SDCD_INT_SRC1_X_POL BIT(4) 107 #define FXLS8962AF_SDCD_INT_SRC1_Y_OT BIT(3) 108 #define FXLS8962AF_SDCD_INT_SRC1_Y_POL BIT(2) 109 #define FXLS8962AF_SDCD_INT_SRC1_Z_OT BIT(1) 110 #define FXLS8962AF_SDCD_INT_SRC1_Z_POL BIT(0) 111 #define FXLS8962AF_SDCD_INT_SRC2 0x2e 112 #define FXLS8962AF_SDCD_CONFIG1 0x2f 113 #define FXLS8962AF_SDCD_CONFIG1_Z_OT_EN BIT(3) 114 #define FXLS8962AF_SDCD_CONFIG1_Y_OT_EN BIT(4) 115 #define FXLS8962AF_SDCD_CONFIG1_X_OT_EN BIT(5) 116 #define FXLS8962AF_SDCD_CONFIG1_OT_ELE BIT(7) 117 #define FXLS8962AF_SDCD_CONFIG2 0x30 118 #define FXLS8962AF_SDCD_CONFIG2_SDCD_EN BIT(7) 119 #define FXLS8962AF_SC2_REF_UPDM_AC GENMASK(6, 5) 120 #define FXLS8962AF_SDCD_OT_DBCNT 0x31 121 #define FXLS8962AF_SDCD_WT_DBCNT 0x32 122 #define FXLS8962AF_SDCD_LTHS_LSB 0x33 123 #define FXLS8962AF_SDCD_UTHS_LSB 0x35 124 125 #define FXLS8962AF_SELF_TEST_CONFIG1 0x37 126 #define FXLS8962AF_SELF_TEST_CONFIG2 0x38 127 128 #define FXLS8962AF_MAX_REG 0x38 129 130 #define FXLS8962AF_DEVICE_ID 0x62 131 #define FXLS8964AF_DEVICE_ID 0x84 132 133 /* Raw temp channel offset */ 134 #define FXLS8962AF_TEMP_CENTER_VAL 25 135 136 #define FXLS8962AF_AUTO_SUSPEND_DELAY_MS 2000 137 138 #define FXLS8962AF_FIFO_LENGTH 32 139 #define FXLS8962AF_SCALE_TABLE_LEN 4 140 #define FXLS8962AF_SAMP_FREQ_TABLE_LEN 13 141 142 static const int fxls8962af_scale_table[FXLS8962AF_SCALE_TABLE_LEN][2] = { 143 {0, IIO_G_TO_M_S_2(980000)}, 144 {0, IIO_G_TO_M_S_2(1950000)}, 145 {0, IIO_G_TO_M_S_2(3910000)}, 146 {0, IIO_G_TO_M_S_2(7810000)}, 147 }; 148 149 static const int fxls8962af_samp_freq_table[FXLS8962AF_SAMP_FREQ_TABLE_LEN][2] = { 150 {3200, 0}, {1600, 0}, {800, 0}, {400, 0}, {200, 0}, {100, 0}, 151 {50, 0}, {25, 0}, {12, 500000}, {6, 250000}, {3, 125000}, 152 {1, 563000}, {0, 781000}, 153 }; 154 155 struct fxls8962af_chip_info { 156 const char *name; 157 const struct iio_chan_spec *channels; 158 int num_channels; 159 u8 chip_id; 160 }; 161 162 struct fxls8962af_data { 163 struct regmap *regmap; 164 const struct fxls8962af_chip_info *chip_info; 165 struct { 166 __le16 channels[3]; 167 aligned_s64 ts; 168 } scan; 169 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */ 170 struct iio_mount_matrix orientation; 171 int irq; 172 u8 watermark; 173 u8 enable_event; 174 u16 lower_thres; 175 u16 upper_thres; 176 }; 177 178 const struct regmap_config fxls8962af_i2c_regmap_conf = { 179 .reg_bits = 8, 180 .val_bits = 8, 181 .max_register = FXLS8962AF_MAX_REG, 182 }; 183 EXPORT_SYMBOL_NS_GPL(fxls8962af_i2c_regmap_conf, IIO_FXLS8962AF); 184 185 const struct regmap_config fxls8962af_spi_regmap_conf = { 186 .reg_bits = 8, 187 .pad_bits = 8, 188 .val_bits = 8, 189 .max_register = FXLS8962AF_MAX_REG, 190 }; 191 EXPORT_SYMBOL_NS_GPL(fxls8962af_spi_regmap_conf, IIO_FXLS8962AF); 192 193 enum { 194 fxls8962af_idx_x, 195 fxls8962af_idx_y, 196 fxls8962af_idx_z, 197 fxls8962af_idx_ts, 198 }; 199 200 enum fxls8962af_int_pin { 201 FXLS8962AF_PIN_INT1, 202 FXLS8962AF_PIN_INT2, 203 }; 204 205 static int fxls8962af_power_on(struct fxls8962af_data *data) 206 { 207 struct device *dev = regmap_get_device(data->regmap); 208 int ret; 209 210 ret = pm_runtime_resume_and_get(dev); 211 if (ret) 212 dev_err(dev, "failed to power on\n"); 213 214 return ret; 215 } 216 217 static int fxls8962af_power_off(struct fxls8962af_data *data) 218 { 219 struct device *dev = regmap_get_device(data->regmap); 220 int ret; 221 222 pm_runtime_mark_last_busy(dev); 223 ret = pm_runtime_put_autosuspend(dev); 224 if (ret) 225 dev_err(dev, "failed to power off\n"); 226 227 return ret; 228 } 229 230 static int fxls8962af_standby(struct fxls8962af_data *data) 231 { 232 return regmap_clear_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 233 FXLS8962AF_SENS_CONFIG1_ACTIVE); 234 } 235 236 static int fxls8962af_active(struct fxls8962af_data *data) 237 { 238 return regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 239 FXLS8962AF_SENS_CONFIG1_ACTIVE, 1); 240 } 241 242 static int fxls8962af_is_active(struct fxls8962af_data *data) 243 { 244 unsigned int reg; 245 int ret; 246 247 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®); 248 if (ret) 249 return ret; 250 251 return reg & FXLS8962AF_SENS_CONFIG1_ACTIVE; 252 } 253 254 static int fxls8962af_get_out(struct fxls8962af_data *data, 255 struct iio_chan_spec const *chan, int *val) 256 { 257 struct device *dev = regmap_get_device(data->regmap); 258 __le16 raw_val; 259 int is_active; 260 int ret; 261 262 is_active = fxls8962af_is_active(data); 263 if (!is_active) { 264 ret = fxls8962af_power_on(data); 265 if (ret) 266 return ret; 267 } 268 269 ret = regmap_bulk_read(data->regmap, chan->address, 270 &raw_val, sizeof(data->lower_thres)); 271 272 if (!is_active) 273 fxls8962af_power_off(data); 274 275 if (ret) { 276 dev_err(dev, "failed to get out reg 0x%lx\n", chan->address); 277 return ret; 278 } 279 280 *val = sign_extend32(le16_to_cpu(raw_val), 281 chan->scan_type.realbits - 1); 282 283 return IIO_VAL_INT; 284 } 285 286 static int fxls8962af_read_avail(struct iio_dev *indio_dev, 287 struct iio_chan_spec const *chan, 288 const int **vals, int *type, int *length, 289 long mask) 290 { 291 switch (mask) { 292 case IIO_CHAN_INFO_SCALE: 293 *type = IIO_VAL_INT_PLUS_NANO; 294 *vals = (int *)fxls8962af_scale_table; 295 *length = ARRAY_SIZE(fxls8962af_scale_table) * 2; 296 return IIO_AVAIL_LIST; 297 case IIO_CHAN_INFO_SAMP_FREQ: 298 *type = IIO_VAL_INT_PLUS_MICRO; 299 *vals = (int *)fxls8962af_samp_freq_table; 300 *length = ARRAY_SIZE(fxls8962af_samp_freq_table) * 2; 301 return IIO_AVAIL_LIST; 302 default: 303 return -EINVAL; 304 } 305 } 306 307 static int fxls8962af_write_raw_get_fmt(struct iio_dev *indio_dev, 308 struct iio_chan_spec const *chan, 309 long mask) 310 { 311 switch (mask) { 312 case IIO_CHAN_INFO_SCALE: 313 return IIO_VAL_INT_PLUS_NANO; 314 case IIO_CHAN_INFO_SAMP_FREQ: 315 return IIO_VAL_INT_PLUS_MICRO; 316 default: 317 return IIO_VAL_INT_PLUS_NANO; 318 } 319 } 320 321 static int fxls8962af_update_config(struct fxls8962af_data *data, u8 reg, 322 u8 mask, u8 val) 323 { 324 int ret; 325 int is_active; 326 327 is_active = fxls8962af_is_active(data); 328 if (is_active) { 329 ret = fxls8962af_standby(data); 330 if (ret) 331 return ret; 332 } 333 334 ret = regmap_update_bits(data->regmap, reg, mask, val); 335 if (ret) 336 return ret; 337 338 if (is_active) { 339 ret = fxls8962af_active(data); 340 if (ret) 341 return ret; 342 } 343 344 return 0; 345 } 346 347 static int fxls8962af_set_full_scale(struct fxls8962af_data *data, u32 scale) 348 { 349 int i; 350 351 for (i = 0; i < ARRAY_SIZE(fxls8962af_scale_table); i++) 352 if (scale == fxls8962af_scale_table[i][1]) 353 break; 354 355 if (i == ARRAY_SIZE(fxls8962af_scale_table)) 356 return -EINVAL; 357 358 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG1, 359 FXLS8962AF_SC1_FSR_MASK, 360 FXLS8962AF_SC1_FSR_PREP(i)); 361 } 362 363 static unsigned int fxls8962af_read_full_scale(struct fxls8962af_data *data, 364 int *val) 365 { 366 int ret; 367 unsigned int reg; 368 u8 range_idx; 369 370 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®); 371 if (ret) 372 return ret; 373 374 range_idx = FXLS8962AF_SC1_FSR_GET(reg); 375 376 *val = fxls8962af_scale_table[range_idx][1]; 377 378 return IIO_VAL_INT_PLUS_NANO; 379 } 380 381 static int fxls8962af_set_samp_freq(struct fxls8962af_data *data, u32 val, 382 u32 val2) 383 { 384 int i; 385 386 for (i = 0; i < ARRAY_SIZE(fxls8962af_samp_freq_table); i++) 387 if (val == fxls8962af_samp_freq_table[i][0] && 388 val2 == fxls8962af_samp_freq_table[i][1]) 389 break; 390 391 if (i == ARRAY_SIZE(fxls8962af_samp_freq_table)) 392 return -EINVAL; 393 394 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG3, 395 FXLS8962AF_SC3_WAKE_ODR_MASK, 396 FXLS8962AF_SC3_WAKE_ODR_PREP(i)); 397 } 398 399 static unsigned int fxls8962af_read_samp_freq(struct fxls8962af_data *data, 400 int *val, int *val2) 401 { 402 int ret; 403 unsigned int reg; 404 u8 range_idx; 405 406 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG3, ®); 407 if (ret) 408 return ret; 409 410 range_idx = FXLS8962AF_SC3_WAKE_ODR_GET(reg); 411 412 *val = fxls8962af_samp_freq_table[range_idx][0]; 413 *val2 = fxls8962af_samp_freq_table[range_idx][1]; 414 415 return IIO_VAL_INT_PLUS_MICRO; 416 } 417 418 static int fxls8962af_read_raw(struct iio_dev *indio_dev, 419 struct iio_chan_spec const *chan, 420 int *val, int *val2, long mask) 421 { 422 struct fxls8962af_data *data = iio_priv(indio_dev); 423 424 switch (mask) { 425 case IIO_CHAN_INFO_RAW: 426 switch (chan->type) { 427 case IIO_TEMP: 428 case IIO_ACCEL: 429 return fxls8962af_get_out(data, chan, val); 430 default: 431 return -EINVAL; 432 } 433 case IIO_CHAN_INFO_OFFSET: 434 if (chan->type != IIO_TEMP) 435 return -EINVAL; 436 437 *val = FXLS8962AF_TEMP_CENTER_VAL; 438 return IIO_VAL_INT; 439 case IIO_CHAN_INFO_SCALE: 440 *val = 0; 441 return fxls8962af_read_full_scale(data, val2); 442 case IIO_CHAN_INFO_SAMP_FREQ: 443 return fxls8962af_read_samp_freq(data, val, val2); 444 default: 445 return -EINVAL; 446 } 447 } 448 449 static int fxls8962af_write_raw(struct iio_dev *indio_dev, 450 struct iio_chan_spec const *chan, 451 int val, int val2, long mask) 452 { 453 struct fxls8962af_data *data = iio_priv(indio_dev); 454 int ret; 455 456 switch (mask) { 457 case IIO_CHAN_INFO_SCALE: 458 if (val != 0) 459 return -EINVAL; 460 461 ret = iio_device_claim_direct_mode(indio_dev); 462 if (ret) 463 return ret; 464 465 ret = fxls8962af_set_full_scale(data, val2); 466 467 iio_device_release_direct_mode(indio_dev); 468 return ret; 469 case IIO_CHAN_INFO_SAMP_FREQ: 470 ret = iio_device_claim_direct_mode(indio_dev); 471 if (ret) 472 return ret; 473 474 ret = fxls8962af_set_samp_freq(data, val, val2); 475 476 iio_device_release_direct_mode(indio_dev); 477 return ret; 478 default: 479 return -EINVAL; 480 } 481 } 482 483 static int fxls8962af_event_setup(struct fxls8962af_data *data, int state) 484 { 485 /* Enable wakeup interrupt */ 486 int mask = FXLS8962AF_INT_EN_SDCD_OT_EN; 487 int value = state ? mask : 0; 488 489 return regmap_update_bits(data->regmap, FXLS8962AF_INT_EN, mask, value); 490 } 491 492 static int fxls8962af_set_watermark(struct iio_dev *indio_dev, unsigned val) 493 { 494 struct fxls8962af_data *data = iio_priv(indio_dev); 495 496 if (val > FXLS8962AF_FIFO_LENGTH) 497 val = FXLS8962AF_FIFO_LENGTH; 498 499 data->watermark = val; 500 501 return 0; 502 } 503 504 static int __fxls8962af_set_thresholds(struct fxls8962af_data *data, 505 const struct iio_chan_spec *chan, 506 enum iio_event_direction dir, 507 int val) 508 { 509 switch (dir) { 510 case IIO_EV_DIR_FALLING: 511 data->lower_thres = val; 512 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_LTHS_LSB, 513 &data->lower_thres, sizeof(data->lower_thres)); 514 case IIO_EV_DIR_RISING: 515 data->upper_thres = val; 516 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_UTHS_LSB, 517 &data->upper_thres, sizeof(data->upper_thres)); 518 default: 519 return -EINVAL; 520 } 521 } 522 523 static int fxls8962af_read_event(struct iio_dev *indio_dev, 524 const struct iio_chan_spec *chan, 525 enum iio_event_type type, 526 enum iio_event_direction dir, 527 enum iio_event_info info, 528 int *val, int *val2) 529 { 530 struct fxls8962af_data *data = iio_priv(indio_dev); 531 int ret; 532 533 if (type != IIO_EV_TYPE_THRESH) 534 return -EINVAL; 535 536 switch (dir) { 537 case IIO_EV_DIR_FALLING: 538 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_LTHS_LSB, 539 &data->lower_thres, sizeof(data->lower_thres)); 540 if (ret) 541 return ret; 542 543 *val = sign_extend32(data->lower_thres, chan->scan_type.realbits - 1); 544 return IIO_VAL_INT; 545 case IIO_EV_DIR_RISING: 546 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_UTHS_LSB, 547 &data->upper_thres, sizeof(data->upper_thres)); 548 if (ret) 549 return ret; 550 551 *val = sign_extend32(data->upper_thres, chan->scan_type.realbits - 1); 552 return IIO_VAL_INT; 553 default: 554 return -EINVAL; 555 } 556 } 557 558 static int fxls8962af_write_event(struct iio_dev *indio_dev, 559 const struct iio_chan_spec *chan, 560 enum iio_event_type type, 561 enum iio_event_direction dir, 562 enum iio_event_info info, 563 int val, int val2) 564 { 565 struct fxls8962af_data *data = iio_priv(indio_dev); 566 int ret, val_masked; 567 568 if (type != IIO_EV_TYPE_THRESH) 569 return -EINVAL; 570 571 if (val < -2048 || val > 2047) 572 return -EINVAL; 573 574 if (data->enable_event) 575 return -EBUSY; 576 577 val_masked = val & GENMASK(11, 0); 578 if (fxls8962af_is_active(data)) { 579 ret = fxls8962af_standby(data); 580 if (ret) 581 return ret; 582 583 ret = __fxls8962af_set_thresholds(data, chan, dir, val_masked); 584 if (ret) 585 return ret; 586 587 return fxls8962af_active(data); 588 } else { 589 return __fxls8962af_set_thresholds(data, chan, dir, val_masked); 590 } 591 } 592 593 static int 594 fxls8962af_read_event_config(struct iio_dev *indio_dev, 595 const struct iio_chan_spec *chan, 596 enum iio_event_type type, 597 enum iio_event_direction dir) 598 { 599 struct fxls8962af_data *data = iio_priv(indio_dev); 600 601 if (type != IIO_EV_TYPE_THRESH) 602 return -EINVAL; 603 604 switch (chan->channel2) { 605 case IIO_MOD_X: 606 return !!(FXLS8962AF_SDCD_CONFIG1_X_OT_EN & data->enable_event); 607 case IIO_MOD_Y: 608 return !!(FXLS8962AF_SDCD_CONFIG1_Y_OT_EN & data->enable_event); 609 case IIO_MOD_Z: 610 return !!(FXLS8962AF_SDCD_CONFIG1_Z_OT_EN & data->enable_event); 611 default: 612 return -EINVAL; 613 } 614 } 615 616 static int 617 fxls8962af_write_event_config(struct iio_dev *indio_dev, 618 const struct iio_chan_spec *chan, 619 enum iio_event_type type, 620 enum iio_event_direction dir, bool state) 621 { 622 struct fxls8962af_data *data = iio_priv(indio_dev); 623 u8 enable_event, enable_bits; 624 int ret, value; 625 626 if (type != IIO_EV_TYPE_THRESH) 627 return -EINVAL; 628 629 switch (chan->channel2) { 630 case IIO_MOD_X: 631 enable_bits = FXLS8962AF_SDCD_CONFIG1_X_OT_EN; 632 break; 633 case IIO_MOD_Y: 634 enable_bits = FXLS8962AF_SDCD_CONFIG1_Y_OT_EN; 635 break; 636 case IIO_MOD_Z: 637 enable_bits = FXLS8962AF_SDCD_CONFIG1_Z_OT_EN; 638 break; 639 default: 640 return -EINVAL; 641 } 642 643 if (state) 644 enable_event = data->enable_event | enable_bits; 645 else 646 enable_event = data->enable_event & ~enable_bits; 647 648 if (data->enable_event == enable_event) 649 return 0; 650 651 ret = fxls8962af_standby(data); 652 if (ret) 653 return ret; 654 655 /* Enable events */ 656 value = enable_event | FXLS8962AF_SDCD_CONFIG1_OT_ELE; 657 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG1, value); 658 if (ret) 659 return ret; 660 661 /* 662 * Enable update of SDCD_REF_X/Y/Z values with the current decimated and 663 * trimmed X/Y/Z acceleration input data. This allows for acceleration 664 * slope detection with Data(n) to Data(n–1) always used as the input 665 * to the window comparator. 666 */ 667 value = enable_event ? 668 FXLS8962AF_SDCD_CONFIG2_SDCD_EN | FXLS8962AF_SC2_REF_UPDM_AC : 669 0x00; 670 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG2, value); 671 if (ret) 672 return ret; 673 674 ret = fxls8962af_event_setup(data, state); 675 if (ret) 676 return ret; 677 678 data->enable_event = enable_event; 679 680 if (data->enable_event) { 681 fxls8962af_active(data); 682 ret = fxls8962af_power_on(data); 683 } else { 684 ret = iio_device_claim_direct_mode(indio_dev); 685 if (ret) 686 return ret; 687 688 /* Not in buffered mode so disable power */ 689 ret = fxls8962af_power_off(data); 690 691 iio_device_release_direct_mode(indio_dev); 692 } 693 694 return ret; 695 } 696 697 static const struct iio_event_spec fxls8962af_event[] = { 698 { 699 .type = IIO_EV_TYPE_THRESH, 700 .dir = IIO_EV_DIR_EITHER, 701 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 702 }, 703 { 704 .type = IIO_EV_TYPE_THRESH, 705 .dir = IIO_EV_DIR_FALLING, 706 .mask_separate = BIT(IIO_EV_INFO_VALUE), 707 }, 708 { 709 .type = IIO_EV_TYPE_THRESH, 710 .dir = IIO_EV_DIR_RISING, 711 .mask_separate = BIT(IIO_EV_INFO_VALUE), 712 }, 713 }; 714 715 #define FXLS8962AF_CHANNEL(axis, reg, idx) { \ 716 .type = IIO_ACCEL, \ 717 .address = reg, \ 718 .modified = 1, \ 719 .channel2 = IIO_MOD_##axis, \ 720 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 721 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 722 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 723 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \ 724 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 725 .scan_index = idx, \ 726 .scan_type = { \ 727 .sign = 's', \ 728 .realbits = 12, \ 729 .storagebits = 16, \ 730 .endianness = IIO_LE, \ 731 }, \ 732 .event_spec = fxls8962af_event, \ 733 .num_event_specs = ARRAY_SIZE(fxls8962af_event), \ 734 } 735 736 #define FXLS8962AF_TEMP_CHANNEL { \ 737 .type = IIO_TEMP, \ 738 .address = FXLS8962AF_TEMP_OUT, \ 739 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 740 BIT(IIO_CHAN_INFO_OFFSET),\ 741 .scan_index = -1, \ 742 .scan_type = { \ 743 .realbits = 8, \ 744 .storagebits = 8, \ 745 }, \ 746 } 747 748 static const struct iio_chan_spec fxls8962af_channels[] = { 749 FXLS8962AF_CHANNEL(X, FXLS8962AF_OUT_X_LSB, fxls8962af_idx_x), 750 FXLS8962AF_CHANNEL(Y, FXLS8962AF_OUT_Y_LSB, fxls8962af_idx_y), 751 FXLS8962AF_CHANNEL(Z, FXLS8962AF_OUT_Z_LSB, fxls8962af_idx_z), 752 IIO_CHAN_SOFT_TIMESTAMP(fxls8962af_idx_ts), 753 FXLS8962AF_TEMP_CHANNEL, 754 }; 755 756 static const struct fxls8962af_chip_info fxls_chip_info_table[] = { 757 [fxls8962af] = { 758 .chip_id = FXLS8962AF_DEVICE_ID, 759 .name = "fxls8962af", 760 .channels = fxls8962af_channels, 761 .num_channels = ARRAY_SIZE(fxls8962af_channels), 762 }, 763 [fxls8964af] = { 764 .chip_id = FXLS8964AF_DEVICE_ID, 765 .name = "fxls8964af", 766 .channels = fxls8962af_channels, 767 .num_channels = ARRAY_SIZE(fxls8962af_channels), 768 }, 769 }; 770 771 static const struct iio_info fxls8962af_info = { 772 .read_raw = &fxls8962af_read_raw, 773 .write_raw = &fxls8962af_write_raw, 774 .write_raw_get_fmt = fxls8962af_write_raw_get_fmt, 775 .read_event_value = fxls8962af_read_event, 776 .write_event_value = fxls8962af_write_event, 777 .read_event_config = fxls8962af_read_event_config, 778 .write_event_config = fxls8962af_write_event_config, 779 .read_avail = fxls8962af_read_avail, 780 .hwfifo_set_watermark = fxls8962af_set_watermark, 781 }; 782 783 static int fxls8962af_reset(struct fxls8962af_data *data) 784 { 785 struct device *dev = regmap_get_device(data->regmap); 786 unsigned int reg; 787 int ret; 788 789 ret = regmap_set_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 790 FXLS8962AF_SENS_CONFIG1_RST); 791 if (ret) 792 return ret; 793 794 /* TBOOT1, TBOOT2, specifies we have to wait between 1 - 17.7ms */ 795 ret = regmap_read_poll_timeout(data->regmap, FXLS8962AF_INT_STATUS, reg, 796 (reg & FXLS8962AF_INT_STATUS_SRC_BOOT), 797 1000, 18000); 798 if (ret == -ETIMEDOUT) 799 dev_err(dev, "reset timeout, int_status = 0x%x\n", reg); 800 801 return ret; 802 } 803 804 static int __fxls8962af_fifo_set_mode(struct fxls8962af_data *data, bool onoff) 805 { 806 int ret; 807 808 /* Enable watermark at max fifo size */ 809 ret = regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG2, 810 FXLS8962AF_BUF_CONFIG2_BUF_WMRK, 811 data->watermark); 812 if (ret) 813 return ret; 814 815 return regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG1, 816 FXLS8962AF_BC1_BUF_MODE_MASK, 817 FXLS8962AF_BC1_BUF_MODE_PREP(onoff)); 818 } 819 820 static int fxls8962af_buffer_preenable(struct iio_dev *indio_dev) 821 { 822 return fxls8962af_power_on(iio_priv(indio_dev)); 823 } 824 825 static int fxls8962af_buffer_postenable(struct iio_dev *indio_dev) 826 { 827 struct fxls8962af_data *data = iio_priv(indio_dev); 828 int ret; 829 830 fxls8962af_standby(data); 831 832 /* Enable buffer interrupt */ 833 ret = regmap_set_bits(data->regmap, FXLS8962AF_INT_EN, 834 FXLS8962AF_INT_EN_BUF_EN); 835 if (ret) 836 return ret; 837 838 ret = __fxls8962af_fifo_set_mode(data, true); 839 840 fxls8962af_active(data); 841 842 return ret; 843 } 844 845 static int fxls8962af_buffer_predisable(struct iio_dev *indio_dev) 846 { 847 struct fxls8962af_data *data = iio_priv(indio_dev); 848 int ret; 849 850 fxls8962af_standby(data); 851 852 /* Disable buffer interrupt */ 853 ret = regmap_clear_bits(data->regmap, FXLS8962AF_INT_EN, 854 FXLS8962AF_INT_EN_BUF_EN); 855 if (ret) 856 return ret; 857 858 ret = __fxls8962af_fifo_set_mode(data, false); 859 860 if (data->enable_event) 861 fxls8962af_active(data); 862 863 return ret; 864 } 865 866 static int fxls8962af_buffer_postdisable(struct iio_dev *indio_dev) 867 { 868 struct fxls8962af_data *data = iio_priv(indio_dev); 869 870 if (!data->enable_event) 871 fxls8962af_power_off(data); 872 873 return 0; 874 } 875 876 static const struct iio_buffer_setup_ops fxls8962af_buffer_ops = { 877 .preenable = fxls8962af_buffer_preenable, 878 .postenable = fxls8962af_buffer_postenable, 879 .predisable = fxls8962af_buffer_predisable, 880 .postdisable = fxls8962af_buffer_postdisable, 881 }; 882 883 static int fxls8962af_i2c_raw_read_errata3(struct fxls8962af_data *data, 884 u16 *buffer, int samples, 885 int sample_length) 886 { 887 int i, ret; 888 889 for (i = 0; i < samples; i++) { 890 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, 891 &buffer[i * 3], sample_length); 892 if (ret) 893 return ret; 894 } 895 896 return 0; 897 } 898 899 static int fxls8962af_fifo_transfer(struct fxls8962af_data *data, 900 u16 *buffer, int samples) 901 { 902 struct device *dev = regmap_get_device(data->regmap); 903 int sample_length = 3 * sizeof(*buffer); 904 int total_length = samples * sample_length; 905 int ret; 906 907 if (i2c_verify_client(dev) && 908 data->chip_info->chip_id == FXLS8962AF_DEVICE_ID) 909 /* 910 * Due to errata bug (only applicable on fxls8962af): 911 * E3: FIFO burst read operation error using I2C interface 912 * We have to avoid burst reads on I2C.. 913 */ 914 ret = fxls8962af_i2c_raw_read_errata3(data, buffer, samples, 915 sample_length); 916 else 917 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, buffer, 918 total_length); 919 920 if (ret) 921 dev_err(dev, "Error transferring data from fifo: %d\n", ret); 922 923 return ret; 924 } 925 926 static int fxls8962af_fifo_flush(struct iio_dev *indio_dev) 927 { 928 struct fxls8962af_data *data = iio_priv(indio_dev); 929 struct device *dev = regmap_get_device(data->regmap); 930 u16 buffer[FXLS8962AF_FIFO_LENGTH * 3]; 931 uint64_t sample_period; 932 unsigned int reg; 933 int64_t tstamp; 934 int ret, i; 935 u8 count; 936 937 ret = regmap_read(data->regmap, FXLS8962AF_BUF_STATUS, ®); 938 if (ret) 939 return ret; 940 941 if (reg & FXLS8962AF_BUF_STATUS_BUF_OVF) { 942 dev_err(dev, "Buffer overflow"); 943 return -EOVERFLOW; 944 } 945 946 count = reg & FXLS8962AF_BUF_STATUS_BUF_CNT; 947 if (!count) 948 return 0; 949 950 data->old_timestamp = data->timestamp; 951 data->timestamp = iio_get_time_ns(indio_dev); 952 953 /* 954 * Approximate timestamps for each of the sample based on the sampling, 955 * frequency, timestamp for last sample and number of samples. 956 */ 957 sample_period = (data->timestamp - data->old_timestamp); 958 do_div(sample_period, count); 959 tstamp = data->timestamp - (count - 1) * sample_period; 960 961 ret = fxls8962af_fifo_transfer(data, buffer, count); 962 if (ret) 963 return ret; 964 965 /* Demux hw FIFO into kfifo. */ 966 for (i = 0; i < count; i++) { 967 int j, bit; 968 969 j = 0; 970 iio_for_each_active_channel(indio_dev, bit) { 971 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit], 972 sizeof(data->scan.channels[0])); 973 } 974 975 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, 976 tstamp); 977 978 tstamp += sample_period; 979 } 980 981 return count; 982 } 983 984 static int fxls8962af_event_interrupt(struct iio_dev *indio_dev) 985 { 986 struct fxls8962af_data *data = iio_priv(indio_dev); 987 s64 ts = iio_get_time_ns(indio_dev); 988 unsigned int reg; 989 u64 ev_code; 990 int ret; 991 992 ret = regmap_read(data->regmap, FXLS8962AF_SDCD_INT_SRC1, ®); 993 if (ret) 994 return ret; 995 996 if (reg & FXLS8962AF_SDCD_INT_SRC1_X_OT) { 997 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_X_POL ? 998 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 999 iio_push_event(indio_dev, 1000 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1001 IIO_EV_TYPE_THRESH, ev_code), ts); 1002 } 1003 1004 if (reg & FXLS8962AF_SDCD_INT_SRC1_Y_OT) { 1005 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Y_POL ? 1006 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1007 iio_push_event(indio_dev, 1008 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1009 IIO_EV_TYPE_THRESH, ev_code), ts); 1010 } 1011 1012 if (reg & FXLS8962AF_SDCD_INT_SRC1_Z_OT) { 1013 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Z_POL ? 1014 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1015 iio_push_event(indio_dev, 1016 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1017 IIO_EV_TYPE_THRESH, ev_code), ts); 1018 } 1019 1020 return 0; 1021 } 1022 1023 static irqreturn_t fxls8962af_interrupt(int irq, void *p) 1024 { 1025 struct iio_dev *indio_dev = p; 1026 struct fxls8962af_data *data = iio_priv(indio_dev); 1027 unsigned int reg; 1028 int ret; 1029 1030 ret = regmap_read(data->regmap, FXLS8962AF_INT_STATUS, ®); 1031 if (ret) 1032 return IRQ_NONE; 1033 1034 if (reg & FXLS8962AF_INT_STATUS_SRC_BUF) { 1035 ret = fxls8962af_fifo_flush(indio_dev); 1036 if (ret < 0) 1037 return IRQ_NONE; 1038 1039 return IRQ_HANDLED; 1040 } 1041 1042 if (reg & FXLS8962AF_INT_STATUS_SRC_SDCD_OT) { 1043 ret = fxls8962af_event_interrupt(indio_dev); 1044 if (ret < 0) 1045 return IRQ_NONE; 1046 1047 return IRQ_HANDLED; 1048 } 1049 1050 return IRQ_NONE; 1051 } 1052 1053 static void fxls8962af_pm_disable(void *dev_ptr) 1054 { 1055 struct device *dev = dev_ptr; 1056 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1057 1058 pm_runtime_disable(dev); 1059 pm_runtime_set_suspended(dev); 1060 pm_runtime_put_noidle(dev); 1061 1062 fxls8962af_standby(iio_priv(indio_dev)); 1063 } 1064 1065 static void fxls8962af_get_irq(struct device *dev, 1066 enum fxls8962af_int_pin *pin) 1067 { 1068 int irq; 1069 1070 irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT2"); 1071 if (irq > 0) { 1072 *pin = FXLS8962AF_PIN_INT2; 1073 return; 1074 } 1075 1076 *pin = FXLS8962AF_PIN_INT1; 1077 } 1078 1079 static int fxls8962af_irq_setup(struct iio_dev *indio_dev, int irq) 1080 { 1081 struct fxls8962af_data *data = iio_priv(indio_dev); 1082 struct device *dev = regmap_get_device(data->regmap); 1083 unsigned long irq_type; 1084 bool irq_active_high; 1085 enum fxls8962af_int_pin int_pin; 1086 u8 int_pin_sel; 1087 int ret; 1088 1089 fxls8962af_get_irq(dev, &int_pin); 1090 switch (int_pin) { 1091 case FXLS8962AF_PIN_INT1: 1092 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT1; 1093 break; 1094 case FXLS8962AF_PIN_INT2: 1095 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT2; 1096 break; 1097 default: 1098 dev_err(dev, "unsupported int pin selected\n"); 1099 return -EINVAL; 1100 } 1101 1102 ret = regmap_update_bits(data->regmap, FXLS8962AF_INT_PIN_SEL, 1103 FXLS8962AF_INT_PIN_SEL_MASK, int_pin_sel); 1104 if (ret) 1105 return ret; 1106 1107 irq_type = irq_get_trigger_type(irq); 1108 switch (irq_type) { 1109 case IRQF_TRIGGER_HIGH: 1110 case IRQF_TRIGGER_RISING: 1111 irq_active_high = true; 1112 break; 1113 case IRQF_TRIGGER_LOW: 1114 case IRQF_TRIGGER_FALLING: 1115 irq_active_high = false; 1116 break; 1117 default: 1118 dev_info(dev, "mode %lx unsupported\n", irq_type); 1119 return -EINVAL; 1120 } 1121 1122 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4, 1123 FXLS8962AF_SC4_INT_POL_MASK, 1124 FXLS8962AF_SC4_INT_POL_PREP(irq_active_high)); 1125 if (ret) 1126 return ret; 1127 1128 if (device_property_read_bool(dev, "drive-open-drain")) { 1129 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4, 1130 FXLS8962AF_SC4_INT_PP_OD_MASK, 1131 FXLS8962AF_SC4_INT_PP_OD_PREP(1)); 1132 if (ret) 1133 return ret; 1134 1135 irq_type |= IRQF_SHARED; 1136 } 1137 1138 return devm_request_threaded_irq(dev, 1139 irq, 1140 NULL, fxls8962af_interrupt, 1141 irq_type | IRQF_ONESHOT, 1142 indio_dev->name, indio_dev); 1143 } 1144 1145 int fxls8962af_core_probe(struct device *dev, struct regmap *regmap, int irq) 1146 { 1147 struct fxls8962af_data *data; 1148 struct iio_dev *indio_dev; 1149 unsigned int reg; 1150 int ret, i; 1151 1152 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1153 if (!indio_dev) 1154 return -ENOMEM; 1155 1156 data = iio_priv(indio_dev); 1157 dev_set_drvdata(dev, indio_dev); 1158 data->regmap = regmap; 1159 data->irq = irq; 1160 1161 ret = iio_read_mount_matrix(dev, &data->orientation); 1162 if (ret) 1163 return ret; 1164 1165 ret = devm_regulator_get_enable(dev, "vdd"); 1166 if (ret) 1167 return dev_err_probe(dev, ret, 1168 "Failed to get vdd regulator\n"); 1169 1170 ret = regmap_read(data->regmap, FXLS8962AF_WHO_AM_I, ®); 1171 if (ret) 1172 return ret; 1173 1174 for (i = 0; i < ARRAY_SIZE(fxls_chip_info_table); i++) { 1175 if (fxls_chip_info_table[i].chip_id == reg) { 1176 data->chip_info = &fxls_chip_info_table[i]; 1177 break; 1178 } 1179 } 1180 if (i == ARRAY_SIZE(fxls_chip_info_table)) { 1181 dev_err(dev, "failed to match device in table\n"); 1182 return -ENXIO; 1183 } 1184 1185 indio_dev->channels = data->chip_info->channels; 1186 indio_dev->num_channels = data->chip_info->num_channels; 1187 indio_dev->name = data->chip_info->name; 1188 indio_dev->info = &fxls8962af_info; 1189 indio_dev->modes = INDIO_DIRECT_MODE; 1190 1191 ret = fxls8962af_reset(data); 1192 if (ret) 1193 return ret; 1194 1195 if (irq) { 1196 ret = fxls8962af_irq_setup(indio_dev, irq); 1197 if (ret) 1198 return ret; 1199 1200 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, 1201 &fxls8962af_buffer_ops); 1202 if (ret) 1203 return ret; 1204 } 1205 1206 ret = pm_runtime_set_active(dev); 1207 if (ret) 1208 return ret; 1209 1210 pm_runtime_enable(dev); 1211 pm_runtime_set_autosuspend_delay(dev, FXLS8962AF_AUTO_SUSPEND_DELAY_MS); 1212 pm_runtime_use_autosuspend(dev); 1213 1214 ret = devm_add_action_or_reset(dev, fxls8962af_pm_disable, dev); 1215 if (ret) 1216 return ret; 1217 1218 if (device_property_read_bool(dev, "wakeup-source")) 1219 device_init_wakeup(dev, true); 1220 1221 return devm_iio_device_register(dev, indio_dev); 1222 } 1223 EXPORT_SYMBOL_NS_GPL(fxls8962af_core_probe, IIO_FXLS8962AF); 1224 1225 static int fxls8962af_runtime_suspend(struct device *dev) 1226 { 1227 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev)); 1228 int ret; 1229 1230 ret = fxls8962af_standby(data); 1231 if (ret) { 1232 dev_err(dev, "powering off device failed\n"); 1233 return ret; 1234 } 1235 1236 return 0; 1237 } 1238 1239 static int fxls8962af_runtime_resume(struct device *dev) 1240 { 1241 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev)); 1242 1243 return fxls8962af_active(data); 1244 } 1245 1246 static int fxls8962af_suspend(struct device *dev) 1247 { 1248 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1249 struct fxls8962af_data *data = iio_priv(indio_dev); 1250 1251 if (device_may_wakeup(dev) && data->enable_event) { 1252 enable_irq_wake(data->irq); 1253 1254 /* 1255 * Disable buffer, as the buffer is so small the device will wake 1256 * almost immediately. 1257 */ 1258 if (iio_buffer_enabled(indio_dev)) 1259 fxls8962af_buffer_predisable(indio_dev); 1260 } else { 1261 fxls8962af_runtime_suspend(dev); 1262 } 1263 1264 return 0; 1265 } 1266 1267 static int fxls8962af_resume(struct device *dev) 1268 { 1269 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1270 struct fxls8962af_data *data = iio_priv(indio_dev); 1271 1272 if (device_may_wakeup(dev) && data->enable_event) { 1273 disable_irq_wake(data->irq); 1274 1275 if (iio_buffer_enabled(indio_dev)) 1276 fxls8962af_buffer_postenable(indio_dev); 1277 } else { 1278 fxls8962af_runtime_resume(dev); 1279 } 1280 1281 return 0; 1282 } 1283 1284 EXPORT_NS_GPL_DEV_PM_OPS(fxls8962af_pm_ops, IIO_FXLS8962AF) = { 1285 SYSTEM_SLEEP_PM_OPS(fxls8962af_suspend, fxls8962af_resume) 1286 RUNTIME_PM_OPS(fxls8962af_runtime_suspend, fxls8962af_runtime_resume, NULL) 1287 }; 1288 1289 MODULE_AUTHOR("Sean Nyekjaer <sean@geanix.com>"); 1290 MODULE_DESCRIPTION("NXP FXLS8962AF/FXLS8964AF accelerometer driver"); 1291 MODULE_LICENSE("GPL v2"); 1292