1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NXP FXLS8962AF/FXLS8964AF Accelerometer Core Driver 4 * 5 * Copyright 2021 Connected Cars A/S 6 * 7 * Datasheet: 8 * https://www.nxp.com/docs/en/data-sheet/FXLS8962AF.pdf 9 * https://www.nxp.com/docs/en/data-sheet/FXLS8964AF.pdf 10 * 11 * Errata: 12 * https://www.nxp.com/docs/en/errata/ES_FXLS8962AF.pdf 13 */ 14 15 #include <linux/bits.h> 16 #include <linux/bitfield.h> 17 #include <linux/i2c.h> 18 #include <linux/irq.h> 19 #include <linux/module.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/property.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/regmap.h> 24 #include <linux/types.h> 25 #include <linux/units.h> 26 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/events.h> 29 #include <linux/iio/iio.h> 30 #include <linux/iio/kfifo_buf.h> 31 #include <linux/iio/sysfs.h> 32 33 #include "fxls8962af.h" 34 35 #define FXLS8962AF_INT_STATUS 0x00 36 #define FXLS8962AF_INT_STATUS_SRC_BOOT BIT(0) 37 #define FXLS8962AF_INT_STATUS_SRC_SDCD_OT BIT(4) 38 #define FXLS8962AF_INT_STATUS_SRC_BUF BIT(5) 39 #define FXLS8962AF_INT_STATUS_SRC_DRDY BIT(7) 40 #define FXLS8962AF_TEMP_OUT 0x01 41 #define FXLS8962AF_VECM_LSB 0x02 42 #define FXLS8962AF_OUT_X_LSB 0x04 43 #define FXLS8962AF_OUT_Y_LSB 0x06 44 #define FXLS8962AF_OUT_Z_LSB 0x08 45 #define FXLS8962AF_BUF_STATUS 0x0b 46 #define FXLS8962AF_BUF_STATUS_BUF_CNT GENMASK(5, 0) 47 #define FXLS8962AF_BUF_STATUS_BUF_OVF BIT(6) 48 #define FXLS8962AF_BUF_STATUS_BUF_WMRK BIT(7) 49 #define FXLS8962AF_BUF_X_LSB 0x0c 50 #define FXLS8962AF_BUF_Y_LSB 0x0e 51 #define FXLS8962AF_BUF_Z_LSB 0x10 52 53 #define FXLS8962AF_PROD_REV 0x12 54 #define FXLS8962AF_WHO_AM_I 0x13 55 56 #define FXLS8962AF_SYS_MODE 0x14 57 #define FXLS8962AF_SENS_CONFIG1 0x15 58 #define FXLS8962AF_SENS_CONFIG1_ACTIVE BIT(0) 59 #define FXLS8962AF_SENS_CONFIG1_RST BIT(7) 60 #define FXLS8962AF_SC1_FSR_MASK GENMASK(2, 1) 61 #define FXLS8962AF_SC1_FSR_PREP(x) FIELD_PREP(FXLS8962AF_SC1_FSR_MASK, (x)) 62 #define FXLS8962AF_SC1_FSR_GET(x) FIELD_GET(FXLS8962AF_SC1_FSR_MASK, (x)) 63 64 #define FXLS8962AF_SENS_CONFIG2 0x16 65 #define FXLS8962AF_SENS_CONFIG3 0x17 66 #define FXLS8962AF_SC3_WAKE_ODR_MASK GENMASK(7, 4) 67 #define FXLS8962AF_SC3_WAKE_ODR_PREP(x) FIELD_PREP(FXLS8962AF_SC3_WAKE_ODR_MASK, (x)) 68 #define FXLS8962AF_SC3_WAKE_ODR_GET(x) FIELD_GET(FXLS8962AF_SC3_WAKE_ODR_MASK, (x)) 69 #define FXLS8962AF_SENS_CONFIG4 0x18 70 #define FXLS8962AF_SC4_INT_PP_OD_MASK BIT(1) 71 #define FXLS8962AF_SC4_INT_PP_OD_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_PP_OD_MASK, (x)) 72 #define FXLS8962AF_SC4_INT_POL_MASK BIT(0) 73 #define FXLS8962AF_SC4_INT_POL_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_POL_MASK, (x)) 74 #define FXLS8962AF_SENS_CONFIG5 0x19 75 76 #define FXLS8962AF_WAKE_IDLE_LSB 0x1b 77 #define FXLS8962AF_SLEEP_IDLE_LSB 0x1c 78 #define FXLS8962AF_ASLP_COUNT_LSB 0x1e 79 80 #define FXLS8962AF_INT_EN 0x20 81 #define FXLS8962AF_INT_EN_SDCD_OT_EN BIT(5) 82 #define FXLS8962AF_INT_EN_BUF_EN BIT(6) 83 #define FXLS8962AF_INT_PIN_SEL 0x21 84 #define FXLS8962AF_INT_PIN_SEL_MASK GENMASK(7, 0) 85 #define FXLS8962AF_INT_PIN_SEL_INT1 0x00 86 #define FXLS8962AF_INT_PIN_SEL_INT2 GENMASK(7, 0) 87 88 #define FXLS8962AF_OFF_X 0x22 89 #define FXLS8962AF_OFF_Y 0x23 90 #define FXLS8962AF_OFF_Z 0x24 91 92 #define FXLS8962AF_BUF_CONFIG1 0x26 93 #define FXLS8962AF_BC1_BUF_MODE_MASK GENMASK(6, 5) 94 #define FXLS8962AF_BC1_BUF_MODE_PREP(x) FIELD_PREP(FXLS8962AF_BC1_BUF_MODE_MASK, (x)) 95 #define FXLS8962AF_BUF_CONFIG2 0x27 96 #define FXLS8962AF_BUF_CONFIG2_BUF_WMRK GENMASK(5, 0) 97 98 #define FXLS8962AF_ORIENT_STATUS 0x28 99 #define FXLS8962AF_ORIENT_CONFIG 0x29 100 #define FXLS8962AF_ORIENT_DBCOUNT 0x2a 101 #define FXLS8962AF_ORIENT_BF_ZCOMP 0x2b 102 #define FXLS8962AF_ORIENT_THS_REG 0x2c 103 104 #define FXLS8962AF_SDCD_INT_SRC1 0x2d 105 #define FXLS8962AF_SDCD_INT_SRC1_X_OT BIT(5) 106 #define FXLS8962AF_SDCD_INT_SRC1_X_POL BIT(4) 107 #define FXLS8962AF_SDCD_INT_SRC1_Y_OT BIT(3) 108 #define FXLS8962AF_SDCD_INT_SRC1_Y_POL BIT(2) 109 #define FXLS8962AF_SDCD_INT_SRC1_Z_OT BIT(1) 110 #define FXLS8962AF_SDCD_INT_SRC1_Z_POL BIT(0) 111 #define FXLS8962AF_SDCD_INT_SRC2 0x2e 112 #define FXLS8962AF_SDCD_CONFIG1 0x2f 113 #define FXLS8962AF_SDCD_CONFIG1_Z_OT_EN BIT(3) 114 #define FXLS8962AF_SDCD_CONFIG1_Y_OT_EN BIT(4) 115 #define FXLS8962AF_SDCD_CONFIG1_X_OT_EN BIT(5) 116 #define FXLS8962AF_SDCD_CONFIG1_OT_ELE BIT(7) 117 #define FXLS8962AF_SDCD_CONFIG2 0x30 118 #define FXLS8962AF_SDCD_CONFIG2_SDCD_EN BIT(7) 119 #define FXLS8962AF_SC2_REF_UPDM_AC GENMASK(6, 5) 120 #define FXLS8962AF_SDCD_OT_DBCNT 0x31 121 #define FXLS8962AF_SDCD_WT_DBCNT 0x32 122 #define FXLS8962AF_SDCD_LTHS_LSB 0x33 123 #define FXLS8962AF_SDCD_UTHS_LSB 0x35 124 125 #define FXLS8962AF_SELF_TEST_CONFIG1 0x37 126 #define FXLS8962AF_SELF_TEST_CONFIG2 0x38 127 128 #define FXLS8962AF_MAX_REG 0x38 129 130 #define FXLS8962AF_DEVICE_ID 0x62 131 #define FXLS8964AF_DEVICE_ID 0x84 132 #define FXLS8974CF_DEVICE_ID 0x86 133 #define FXLS8967AF_DEVICE_ID 0x87 134 135 /* Raw temp channel offset */ 136 #define FXLS8962AF_TEMP_CENTER_VAL 25 137 138 #define FXLS8962AF_AUTO_SUSPEND_DELAY_MS 2000 139 140 #define FXLS8962AF_FIFO_LENGTH 32 141 #define FXLS8962AF_SCALE_TABLE_LEN 4 142 #define FXLS8962AF_SAMP_FREQ_TABLE_LEN 13 143 144 static const int fxls8962af_scale_table[FXLS8962AF_SCALE_TABLE_LEN][2] = { 145 {0, IIO_G_TO_M_S_2(980000)}, 146 {0, IIO_G_TO_M_S_2(1950000)}, 147 {0, IIO_G_TO_M_S_2(3910000)}, 148 {0, IIO_G_TO_M_S_2(7810000)}, 149 }; 150 151 static const int fxls8962af_samp_freq_table[FXLS8962AF_SAMP_FREQ_TABLE_LEN][2] = { 152 {3200, 0}, {1600, 0}, {800, 0}, {400, 0}, {200, 0}, {100, 0}, 153 {50, 0}, {25, 0}, {12, 500000}, {6, 250000}, {3, 125000}, 154 {1, 563000}, {0, 781000}, 155 }; 156 157 struct fxls8962af_chip_info { 158 const char *name; 159 const struct iio_chan_spec *channels; 160 int num_channels; 161 u8 chip_id; 162 }; 163 164 struct fxls8962af_data { 165 struct regmap *regmap; 166 const struct fxls8962af_chip_info *chip_info; 167 struct { 168 __le16 channels[3]; 169 aligned_s64 ts; 170 } scan; 171 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */ 172 struct iio_mount_matrix orientation; 173 int irq; 174 u8 watermark; 175 u8 enable_event; 176 u16 lower_thres; 177 u16 upper_thres; 178 }; 179 180 const struct regmap_config fxls8962af_i2c_regmap_conf = { 181 .reg_bits = 8, 182 .val_bits = 8, 183 .max_register = FXLS8962AF_MAX_REG, 184 }; 185 EXPORT_SYMBOL_NS_GPL(fxls8962af_i2c_regmap_conf, "IIO_FXLS8962AF"); 186 187 const struct regmap_config fxls8962af_spi_regmap_conf = { 188 .reg_bits = 8, 189 .pad_bits = 8, 190 .val_bits = 8, 191 .max_register = FXLS8962AF_MAX_REG, 192 }; 193 EXPORT_SYMBOL_NS_GPL(fxls8962af_spi_regmap_conf, "IIO_FXLS8962AF"); 194 195 enum { 196 fxls8962af_idx_x, 197 fxls8962af_idx_y, 198 fxls8962af_idx_z, 199 fxls8962af_idx_ts, 200 }; 201 202 enum fxls8962af_int_pin { 203 FXLS8962AF_PIN_INT1, 204 FXLS8962AF_PIN_INT2, 205 }; 206 207 static int fxls8962af_power_on(struct fxls8962af_data *data) 208 { 209 struct device *dev = regmap_get_device(data->regmap); 210 int ret; 211 212 ret = pm_runtime_resume_and_get(dev); 213 if (ret) 214 dev_err(dev, "failed to power on\n"); 215 216 return ret; 217 } 218 219 static int fxls8962af_power_off(struct fxls8962af_data *data) 220 { 221 struct device *dev = regmap_get_device(data->regmap); 222 int ret; 223 224 ret = pm_runtime_put_autosuspend(dev); 225 if (ret) 226 dev_err(dev, "failed to power off\n"); 227 228 return ret; 229 } 230 231 static int fxls8962af_standby(struct fxls8962af_data *data) 232 { 233 return regmap_clear_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 234 FXLS8962AF_SENS_CONFIG1_ACTIVE); 235 } 236 237 static int fxls8962af_active(struct fxls8962af_data *data) 238 { 239 return regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 240 FXLS8962AF_SENS_CONFIG1_ACTIVE, 1); 241 } 242 243 static int fxls8962af_is_active(struct fxls8962af_data *data) 244 { 245 unsigned int reg; 246 int ret; 247 248 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®); 249 if (ret) 250 return ret; 251 252 return reg & FXLS8962AF_SENS_CONFIG1_ACTIVE; 253 } 254 255 static int fxls8962af_get_out(struct fxls8962af_data *data, 256 struct iio_chan_spec const *chan, int *val) 257 { 258 struct device *dev = regmap_get_device(data->regmap); 259 __le16 raw_val; 260 int is_active; 261 int ret; 262 263 is_active = fxls8962af_is_active(data); 264 if (!is_active) { 265 ret = fxls8962af_power_on(data); 266 if (ret) 267 return ret; 268 } 269 270 ret = regmap_bulk_read(data->regmap, chan->address, 271 &raw_val, sizeof(data->lower_thres)); 272 273 if (!is_active) 274 fxls8962af_power_off(data); 275 276 if (ret) { 277 dev_err(dev, "failed to get out reg 0x%lx\n", chan->address); 278 return ret; 279 } 280 281 *val = sign_extend32(le16_to_cpu(raw_val), 282 chan->scan_type.realbits - 1); 283 284 return IIO_VAL_INT; 285 } 286 287 static int fxls8962af_read_avail(struct iio_dev *indio_dev, 288 struct iio_chan_spec const *chan, 289 const int **vals, int *type, int *length, 290 long mask) 291 { 292 switch (mask) { 293 case IIO_CHAN_INFO_SCALE: 294 *type = IIO_VAL_INT_PLUS_NANO; 295 *vals = (int *)fxls8962af_scale_table; 296 *length = ARRAY_SIZE(fxls8962af_scale_table) * 2; 297 return IIO_AVAIL_LIST; 298 case IIO_CHAN_INFO_SAMP_FREQ: 299 *type = IIO_VAL_INT_PLUS_MICRO; 300 *vals = (int *)fxls8962af_samp_freq_table; 301 *length = ARRAY_SIZE(fxls8962af_samp_freq_table) * 2; 302 return IIO_AVAIL_LIST; 303 default: 304 return -EINVAL; 305 } 306 } 307 308 static int fxls8962af_write_raw_get_fmt(struct iio_dev *indio_dev, 309 struct iio_chan_spec const *chan, 310 long mask) 311 { 312 switch (mask) { 313 case IIO_CHAN_INFO_SCALE: 314 return IIO_VAL_INT_PLUS_NANO; 315 case IIO_CHAN_INFO_SAMP_FREQ: 316 return IIO_VAL_INT_PLUS_MICRO; 317 default: 318 return IIO_VAL_INT_PLUS_NANO; 319 } 320 } 321 322 static int fxls8962af_update_config(struct fxls8962af_data *data, u8 reg, 323 u8 mask, u8 val) 324 { 325 int ret; 326 int is_active; 327 328 is_active = fxls8962af_is_active(data); 329 if (is_active) { 330 ret = fxls8962af_standby(data); 331 if (ret) 332 return ret; 333 } 334 335 ret = regmap_update_bits(data->regmap, reg, mask, val); 336 if (ret) 337 return ret; 338 339 if (is_active) { 340 ret = fxls8962af_active(data); 341 if (ret) 342 return ret; 343 } 344 345 return 0; 346 } 347 348 static int fxls8962af_set_full_scale(struct fxls8962af_data *data, u32 scale) 349 { 350 int i; 351 352 for (i = 0; i < ARRAY_SIZE(fxls8962af_scale_table); i++) 353 if (scale == fxls8962af_scale_table[i][1]) 354 break; 355 356 if (i == ARRAY_SIZE(fxls8962af_scale_table)) 357 return -EINVAL; 358 359 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG1, 360 FXLS8962AF_SC1_FSR_MASK, 361 FXLS8962AF_SC1_FSR_PREP(i)); 362 } 363 364 static unsigned int fxls8962af_read_full_scale(struct fxls8962af_data *data, 365 int *val) 366 { 367 int ret; 368 unsigned int reg; 369 u8 range_idx; 370 371 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®); 372 if (ret) 373 return ret; 374 375 range_idx = FXLS8962AF_SC1_FSR_GET(reg); 376 377 *val = fxls8962af_scale_table[range_idx][1]; 378 379 return IIO_VAL_INT_PLUS_NANO; 380 } 381 382 static int fxls8962af_set_samp_freq(struct fxls8962af_data *data, u32 val, 383 u32 val2) 384 { 385 int i; 386 387 for (i = 0; i < ARRAY_SIZE(fxls8962af_samp_freq_table); i++) 388 if (val == fxls8962af_samp_freq_table[i][0] && 389 val2 == fxls8962af_samp_freq_table[i][1]) 390 break; 391 392 if (i == ARRAY_SIZE(fxls8962af_samp_freq_table)) 393 return -EINVAL; 394 395 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG3, 396 FXLS8962AF_SC3_WAKE_ODR_MASK, 397 FXLS8962AF_SC3_WAKE_ODR_PREP(i)); 398 } 399 400 static unsigned int fxls8962af_read_samp_freq(struct fxls8962af_data *data, 401 int *val, int *val2) 402 { 403 int ret; 404 unsigned int reg; 405 u8 range_idx; 406 407 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG3, ®); 408 if (ret) 409 return ret; 410 411 range_idx = FXLS8962AF_SC3_WAKE_ODR_GET(reg); 412 413 *val = fxls8962af_samp_freq_table[range_idx][0]; 414 *val2 = fxls8962af_samp_freq_table[range_idx][1]; 415 416 return IIO_VAL_INT_PLUS_MICRO; 417 } 418 419 static int fxls8962af_read_raw(struct iio_dev *indio_dev, 420 struct iio_chan_spec const *chan, 421 int *val, int *val2, long mask) 422 { 423 struct fxls8962af_data *data = iio_priv(indio_dev); 424 425 switch (mask) { 426 case IIO_CHAN_INFO_RAW: 427 switch (chan->type) { 428 case IIO_TEMP: 429 case IIO_ACCEL: 430 return fxls8962af_get_out(data, chan, val); 431 default: 432 return -EINVAL; 433 } 434 case IIO_CHAN_INFO_OFFSET: 435 if (chan->type != IIO_TEMP) 436 return -EINVAL; 437 438 *val = FXLS8962AF_TEMP_CENTER_VAL; 439 return IIO_VAL_INT; 440 case IIO_CHAN_INFO_SCALE: 441 switch (chan->type) { 442 case IIO_TEMP: 443 *val = MILLIDEGREE_PER_DEGREE; 444 return IIO_VAL_INT; 445 case IIO_ACCEL: 446 *val = 0; 447 return fxls8962af_read_full_scale(data, val2); 448 default: 449 return -EINVAL; 450 } 451 case IIO_CHAN_INFO_SAMP_FREQ: 452 return fxls8962af_read_samp_freq(data, val, val2); 453 default: 454 return -EINVAL; 455 } 456 } 457 458 static int fxls8962af_write_raw(struct iio_dev *indio_dev, 459 struct iio_chan_spec const *chan, 460 int val, int val2, long mask) 461 { 462 struct fxls8962af_data *data = iio_priv(indio_dev); 463 int ret; 464 465 switch (mask) { 466 case IIO_CHAN_INFO_SCALE: 467 if (val != 0) 468 return -EINVAL; 469 470 if (!iio_device_claim_direct(indio_dev)) 471 return -EBUSY; 472 473 ret = fxls8962af_set_full_scale(data, val2); 474 475 iio_device_release_direct(indio_dev); 476 return ret; 477 case IIO_CHAN_INFO_SAMP_FREQ: 478 if (!iio_device_claim_direct(indio_dev)) 479 return -EBUSY; 480 481 ret = fxls8962af_set_samp_freq(data, val, val2); 482 483 iio_device_release_direct(indio_dev); 484 return ret; 485 default: 486 return -EINVAL; 487 } 488 } 489 490 static int fxls8962af_event_setup(struct fxls8962af_data *data, int state) 491 { 492 /* Enable wakeup interrupt */ 493 int mask = FXLS8962AF_INT_EN_SDCD_OT_EN; 494 int value = state ? mask : 0; 495 496 return regmap_update_bits(data->regmap, FXLS8962AF_INT_EN, mask, value); 497 } 498 499 static int fxls8962af_set_watermark(struct iio_dev *indio_dev, unsigned val) 500 { 501 struct fxls8962af_data *data = iio_priv(indio_dev); 502 503 if (val > FXLS8962AF_FIFO_LENGTH) 504 val = FXLS8962AF_FIFO_LENGTH; 505 506 data->watermark = val; 507 508 return 0; 509 } 510 511 static int __fxls8962af_set_thresholds(struct fxls8962af_data *data, 512 const struct iio_chan_spec *chan, 513 enum iio_event_direction dir, 514 int val) 515 { 516 switch (dir) { 517 case IIO_EV_DIR_FALLING: 518 data->lower_thres = val; 519 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_LTHS_LSB, 520 &data->lower_thres, sizeof(data->lower_thres)); 521 case IIO_EV_DIR_RISING: 522 data->upper_thres = val; 523 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_UTHS_LSB, 524 &data->upper_thres, sizeof(data->upper_thres)); 525 default: 526 return -EINVAL; 527 } 528 } 529 530 static int fxls8962af_read_event(struct iio_dev *indio_dev, 531 const struct iio_chan_spec *chan, 532 enum iio_event_type type, 533 enum iio_event_direction dir, 534 enum iio_event_info info, 535 int *val, int *val2) 536 { 537 struct fxls8962af_data *data = iio_priv(indio_dev); 538 int ret; 539 540 if (type != IIO_EV_TYPE_THRESH) 541 return -EINVAL; 542 543 switch (dir) { 544 case IIO_EV_DIR_FALLING: 545 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_LTHS_LSB, 546 &data->lower_thres, sizeof(data->lower_thres)); 547 if (ret) 548 return ret; 549 550 *val = sign_extend32(data->lower_thres, chan->scan_type.realbits - 1); 551 return IIO_VAL_INT; 552 case IIO_EV_DIR_RISING: 553 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_UTHS_LSB, 554 &data->upper_thres, sizeof(data->upper_thres)); 555 if (ret) 556 return ret; 557 558 *val = sign_extend32(data->upper_thres, chan->scan_type.realbits - 1); 559 return IIO_VAL_INT; 560 default: 561 return -EINVAL; 562 } 563 } 564 565 static int fxls8962af_write_event(struct iio_dev *indio_dev, 566 const struct iio_chan_spec *chan, 567 enum iio_event_type type, 568 enum iio_event_direction dir, 569 enum iio_event_info info, 570 int val, int val2) 571 { 572 struct fxls8962af_data *data = iio_priv(indio_dev); 573 int ret, val_masked; 574 575 if (type != IIO_EV_TYPE_THRESH) 576 return -EINVAL; 577 578 if (val < -2048 || val > 2047) 579 return -EINVAL; 580 581 if (data->enable_event) 582 return -EBUSY; 583 584 val_masked = val & GENMASK(11, 0); 585 if (fxls8962af_is_active(data)) { 586 ret = fxls8962af_standby(data); 587 if (ret) 588 return ret; 589 590 ret = __fxls8962af_set_thresholds(data, chan, dir, val_masked); 591 if (ret) 592 return ret; 593 594 return fxls8962af_active(data); 595 } else { 596 return __fxls8962af_set_thresholds(data, chan, dir, val_masked); 597 } 598 } 599 600 static int 601 fxls8962af_read_event_config(struct iio_dev *indio_dev, 602 const struct iio_chan_spec *chan, 603 enum iio_event_type type, 604 enum iio_event_direction dir) 605 { 606 struct fxls8962af_data *data = iio_priv(indio_dev); 607 608 if (type != IIO_EV_TYPE_THRESH) 609 return -EINVAL; 610 611 switch (chan->channel2) { 612 case IIO_MOD_X: 613 return !!(FXLS8962AF_SDCD_CONFIG1_X_OT_EN & data->enable_event); 614 case IIO_MOD_Y: 615 return !!(FXLS8962AF_SDCD_CONFIG1_Y_OT_EN & data->enable_event); 616 case IIO_MOD_Z: 617 return !!(FXLS8962AF_SDCD_CONFIG1_Z_OT_EN & data->enable_event); 618 default: 619 return -EINVAL; 620 } 621 } 622 623 static int 624 fxls8962af_write_event_config(struct iio_dev *indio_dev, 625 const struct iio_chan_spec *chan, 626 enum iio_event_type type, 627 enum iio_event_direction dir, bool state) 628 { 629 struct fxls8962af_data *data = iio_priv(indio_dev); 630 u8 enable_event, enable_bits; 631 int ret, value; 632 633 if (type != IIO_EV_TYPE_THRESH) 634 return -EINVAL; 635 636 switch (chan->channel2) { 637 case IIO_MOD_X: 638 enable_bits = FXLS8962AF_SDCD_CONFIG1_X_OT_EN; 639 break; 640 case IIO_MOD_Y: 641 enable_bits = FXLS8962AF_SDCD_CONFIG1_Y_OT_EN; 642 break; 643 case IIO_MOD_Z: 644 enable_bits = FXLS8962AF_SDCD_CONFIG1_Z_OT_EN; 645 break; 646 default: 647 return -EINVAL; 648 } 649 650 if (state) 651 enable_event = data->enable_event | enable_bits; 652 else 653 enable_event = data->enable_event & ~enable_bits; 654 655 if (data->enable_event == enable_event) 656 return 0; 657 658 ret = fxls8962af_standby(data); 659 if (ret) 660 return ret; 661 662 /* Enable events */ 663 value = enable_event | FXLS8962AF_SDCD_CONFIG1_OT_ELE; 664 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG1, value); 665 if (ret) 666 return ret; 667 668 /* 669 * Enable update of SDCD_REF_X/Y/Z values with the current decimated and 670 * trimmed X/Y/Z acceleration input data. This allows for acceleration 671 * slope detection with Data(n) to Data(n–1) always used as the input 672 * to the window comparator. 673 */ 674 value = enable_event ? 675 FXLS8962AF_SDCD_CONFIG2_SDCD_EN | FXLS8962AF_SC2_REF_UPDM_AC : 676 0x00; 677 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG2, value); 678 if (ret) 679 return ret; 680 681 ret = fxls8962af_event_setup(data, state); 682 if (ret) 683 return ret; 684 685 data->enable_event = enable_event; 686 687 if (data->enable_event) { 688 fxls8962af_active(data); 689 ret = fxls8962af_power_on(data); 690 } else { 691 if (!iio_device_claim_direct(indio_dev)) 692 return -EBUSY; 693 694 /* Not in buffered mode so disable power */ 695 ret = fxls8962af_power_off(data); 696 697 iio_device_release_direct(indio_dev); 698 } 699 700 return ret; 701 } 702 703 static const struct iio_event_spec fxls8962af_event[] = { 704 { 705 .type = IIO_EV_TYPE_THRESH, 706 .dir = IIO_EV_DIR_EITHER, 707 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 708 }, 709 { 710 .type = IIO_EV_TYPE_THRESH, 711 .dir = IIO_EV_DIR_FALLING, 712 .mask_separate = BIT(IIO_EV_INFO_VALUE), 713 }, 714 { 715 .type = IIO_EV_TYPE_THRESH, 716 .dir = IIO_EV_DIR_RISING, 717 .mask_separate = BIT(IIO_EV_INFO_VALUE), 718 }, 719 }; 720 721 #define FXLS8962AF_CHANNEL(axis, reg, idx) { \ 722 .type = IIO_ACCEL, \ 723 .address = reg, \ 724 .modified = 1, \ 725 .channel2 = IIO_MOD_##axis, \ 726 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 727 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 728 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 729 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \ 730 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 731 .scan_index = idx, \ 732 .scan_type = { \ 733 .sign = 's', \ 734 .realbits = 12, \ 735 .storagebits = 16, \ 736 .endianness = IIO_LE, \ 737 }, \ 738 .event_spec = fxls8962af_event, \ 739 .num_event_specs = ARRAY_SIZE(fxls8962af_event), \ 740 } 741 742 #define FXLS8962AF_TEMP_CHANNEL { \ 743 .type = IIO_TEMP, \ 744 .address = FXLS8962AF_TEMP_OUT, \ 745 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 746 BIT(IIO_CHAN_INFO_SCALE) | \ 747 BIT(IIO_CHAN_INFO_OFFSET),\ 748 .scan_index = -1, \ 749 .scan_type = { \ 750 .sign = 's', \ 751 .realbits = 8, \ 752 .storagebits = 8, \ 753 }, \ 754 } 755 756 static const struct iio_chan_spec fxls8962af_channels[] = { 757 FXLS8962AF_CHANNEL(X, FXLS8962AF_OUT_X_LSB, fxls8962af_idx_x), 758 FXLS8962AF_CHANNEL(Y, FXLS8962AF_OUT_Y_LSB, fxls8962af_idx_y), 759 FXLS8962AF_CHANNEL(Z, FXLS8962AF_OUT_Z_LSB, fxls8962af_idx_z), 760 IIO_CHAN_SOFT_TIMESTAMP(fxls8962af_idx_ts), 761 FXLS8962AF_TEMP_CHANNEL, 762 }; 763 764 static const struct fxls8962af_chip_info fxls_chip_info_table[] = { 765 [fxls8962af] = { 766 .chip_id = FXLS8962AF_DEVICE_ID, 767 .name = "fxls8962af", 768 .channels = fxls8962af_channels, 769 .num_channels = ARRAY_SIZE(fxls8962af_channels), 770 }, 771 [fxls8964af] = { 772 .chip_id = FXLS8964AF_DEVICE_ID, 773 .name = "fxls8964af", 774 .channels = fxls8962af_channels, 775 .num_channels = ARRAY_SIZE(fxls8962af_channels), 776 }, 777 [fxls8967af] = { 778 .chip_id = FXLS8967AF_DEVICE_ID, 779 .name = "fxls8967af", 780 .channels = fxls8962af_channels, 781 .num_channels = ARRAY_SIZE(fxls8962af_channels), 782 }, 783 [fxls8974cf] = { 784 .chip_id = FXLS8974CF_DEVICE_ID, 785 .name = "fxls8974cf", 786 .channels = fxls8962af_channels, 787 .num_channels = ARRAY_SIZE(fxls8962af_channels), 788 }, 789 }; 790 791 static const struct iio_info fxls8962af_info = { 792 .read_raw = &fxls8962af_read_raw, 793 .write_raw = &fxls8962af_write_raw, 794 .write_raw_get_fmt = fxls8962af_write_raw_get_fmt, 795 .read_event_value = fxls8962af_read_event, 796 .write_event_value = fxls8962af_write_event, 797 .read_event_config = fxls8962af_read_event_config, 798 .write_event_config = fxls8962af_write_event_config, 799 .read_avail = fxls8962af_read_avail, 800 .hwfifo_set_watermark = fxls8962af_set_watermark, 801 }; 802 803 static int fxls8962af_reset(struct fxls8962af_data *data) 804 { 805 struct device *dev = regmap_get_device(data->regmap); 806 unsigned int reg; 807 int ret; 808 809 ret = regmap_set_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 810 FXLS8962AF_SENS_CONFIG1_RST); 811 if (ret) 812 return ret; 813 814 /* TBOOT1, TBOOT2, specifies we have to wait between 1 - 17.7ms */ 815 ret = regmap_read_poll_timeout(data->regmap, FXLS8962AF_INT_STATUS, reg, 816 (reg & FXLS8962AF_INT_STATUS_SRC_BOOT), 817 1000, 18000); 818 if (ret == -ETIMEDOUT) 819 dev_err(dev, "reset timeout, int_status = 0x%x\n", reg); 820 821 return ret; 822 } 823 824 static int __fxls8962af_fifo_set_mode(struct fxls8962af_data *data, bool onoff) 825 { 826 int ret; 827 828 /* Enable watermark at max fifo size */ 829 ret = regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG2, 830 FXLS8962AF_BUF_CONFIG2_BUF_WMRK, 831 data->watermark); 832 if (ret) 833 return ret; 834 835 return regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG1, 836 FXLS8962AF_BC1_BUF_MODE_MASK, 837 FXLS8962AF_BC1_BUF_MODE_PREP(onoff)); 838 } 839 840 static int fxls8962af_buffer_preenable(struct iio_dev *indio_dev) 841 { 842 return fxls8962af_power_on(iio_priv(indio_dev)); 843 } 844 845 static int fxls8962af_buffer_postenable(struct iio_dev *indio_dev) 846 { 847 struct fxls8962af_data *data = iio_priv(indio_dev); 848 int ret; 849 850 fxls8962af_standby(data); 851 852 /* Enable buffer interrupt */ 853 ret = regmap_set_bits(data->regmap, FXLS8962AF_INT_EN, 854 FXLS8962AF_INT_EN_BUF_EN); 855 if (ret) 856 return ret; 857 858 ret = __fxls8962af_fifo_set_mode(data, true); 859 860 fxls8962af_active(data); 861 862 return ret; 863 } 864 865 static int fxls8962af_buffer_predisable(struct iio_dev *indio_dev) 866 { 867 struct fxls8962af_data *data = iio_priv(indio_dev); 868 int ret; 869 870 fxls8962af_standby(data); 871 872 /* Disable buffer interrupt */ 873 ret = regmap_clear_bits(data->regmap, FXLS8962AF_INT_EN, 874 FXLS8962AF_INT_EN_BUF_EN); 875 if (ret) 876 return ret; 877 878 synchronize_irq(data->irq); 879 880 ret = __fxls8962af_fifo_set_mode(data, false); 881 882 if (data->enable_event) 883 fxls8962af_active(data); 884 885 return ret; 886 } 887 888 static int fxls8962af_buffer_postdisable(struct iio_dev *indio_dev) 889 { 890 struct fxls8962af_data *data = iio_priv(indio_dev); 891 892 if (!data->enable_event) 893 fxls8962af_power_off(data); 894 895 return 0; 896 } 897 898 static const struct iio_buffer_setup_ops fxls8962af_buffer_ops = { 899 .preenable = fxls8962af_buffer_preenable, 900 .postenable = fxls8962af_buffer_postenable, 901 .predisable = fxls8962af_buffer_predisable, 902 .postdisable = fxls8962af_buffer_postdisable, 903 }; 904 905 static int fxls8962af_i2c_raw_read_errata3(struct fxls8962af_data *data, 906 u16 *buffer, int samples, 907 int sample_length) 908 { 909 int i, ret; 910 911 for (i = 0; i < samples; i++) { 912 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, 913 &buffer[i * 3], sample_length); 914 if (ret) 915 return ret; 916 } 917 918 return 0; 919 } 920 921 static int fxls8962af_fifo_transfer(struct fxls8962af_data *data, 922 u16 *buffer, int samples) 923 { 924 struct device *dev = regmap_get_device(data->regmap); 925 int sample_length = 3 * sizeof(*buffer); 926 int total_length = samples * sample_length; 927 int ret; 928 929 if (i2c_verify_client(dev) && 930 data->chip_info->chip_id == FXLS8962AF_DEVICE_ID) 931 /* 932 * Due to errata bug (only applicable on fxls8962af): 933 * E3: FIFO burst read operation error using I2C interface 934 * We have to avoid burst reads on I2C.. 935 */ 936 ret = fxls8962af_i2c_raw_read_errata3(data, buffer, samples, 937 sample_length); 938 else 939 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, buffer, 940 total_length); 941 942 if (ret) 943 dev_err(dev, "Error transferring data from fifo: %d\n", ret); 944 945 return ret; 946 } 947 948 static int fxls8962af_fifo_flush(struct iio_dev *indio_dev) 949 { 950 struct fxls8962af_data *data = iio_priv(indio_dev); 951 struct device *dev = regmap_get_device(data->regmap); 952 u16 buffer[FXLS8962AF_FIFO_LENGTH * 3]; 953 uint64_t sample_period; 954 unsigned int reg; 955 int64_t tstamp; 956 int ret, i; 957 u8 count; 958 959 ret = regmap_read(data->regmap, FXLS8962AF_BUF_STATUS, ®); 960 if (ret) 961 return ret; 962 963 if (reg & FXLS8962AF_BUF_STATUS_BUF_OVF) { 964 dev_err(dev, "Buffer overflow"); 965 return -EOVERFLOW; 966 } 967 968 count = reg & FXLS8962AF_BUF_STATUS_BUF_CNT; 969 if (!count) 970 return 0; 971 972 count = min(count, FXLS8962AF_FIFO_LENGTH); 973 974 data->old_timestamp = data->timestamp; 975 data->timestamp = iio_get_time_ns(indio_dev); 976 977 /* 978 * Approximate timestamps for each of the sample based on the sampling, 979 * frequency, timestamp for last sample and number of samples. 980 */ 981 sample_period = (data->timestamp - data->old_timestamp); 982 do_div(sample_period, count); 983 tstamp = data->timestamp - (count - 1) * sample_period; 984 985 ret = fxls8962af_fifo_transfer(data, buffer, count); 986 if (ret) 987 return ret; 988 989 /* Demux hw FIFO into kfifo. */ 990 for (i = 0; i < count; i++) { 991 int j, bit; 992 993 j = 0; 994 iio_for_each_active_channel(indio_dev, bit) { 995 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit], 996 sizeof(data->scan.channels[0])); 997 } 998 999 iio_push_to_buffers_with_ts(indio_dev, &data->scan, 1000 sizeof(data->scan), tstamp); 1001 1002 tstamp += sample_period; 1003 } 1004 1005 return count; 1006 } 1007 1008 static int fxls8962af_event_interrupt(struct iio_dev *indio_dev) 1009 { 1010 struct fxls8962af_data *data = iio_priv(indio_dev); 1011 s64 ts = iio_get_time_ns(indio_dev); 1012 unsigned int reg; 1013 u64 ev_code; 1014 int ret; 1015 1016 ret = regmap_read(data->regmap, FXLS8962AF_SDCD_INT_SRC1, ®); 1017 if (ret) 1018 return ret; 1019 1020 if (reg & FXLS8962AF_SDCD_INT_SRC1_X_OT) { 1021 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_X_POL ? 1022 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1023 iio_push_event(indio_dev, 1024 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1025 IIO_EV_TYPE_THRESH, ev_code), ts); 1026 } 1027 1028 if (reg & FXLS8962AF_SDCD_INT_SRC1_Y_OT) { 1029 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Y_POL ? 1030 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1031 iio_push_event(indio_dev, 1032 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1033 IIO_EV_TYPE_THRESH, ev_code), ts); 1034 } 1035 1036 if (reg & FXLS8962AF_SDCD_INT_SRC1_Z_OT) { 1037 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Z_POL ? 1038 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1039 iio_push_event(indio_dev, 1040 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1041 IIO_EV_TYPE_THRESH, ev_code), ts); 1042 } 1043 1044 return 0; 1045 } 1046 1047 static irqreturn_t fxls8962af_interrupt(int irq, void *p) 1048 { 1049 struct iio_dev *indio_dev = p; 1050 struct fxls8962af_data *data = iio_priv(indio_dev); 1051 unsigned int reg; 1052 int ret; 1053 1054 ret = regmap_read(data->regmap, FXLS8962AF_INT_STATUS, ®); 1055 if (ret) 1056 return IRQ_NONE; 1057 1058 if (reg & FXLS8962AF_INT_STATUS_SRC_BUF) { 1059 ret = fxls8962af_fifo_flush(indio_dev); 1060 if (ret < 0) 1061 return IRQ_NONE; 1062 1063 return IRQ_HANDLED; 1064 } 1065 1066 if (reg & FXLS8962AF_INT_STATUS_SRC_SDCD_OT) { 1067 ret = fxls8962af_event_interrupt(indio_dev); 1068 if (ret < 0) 1069 return IRQ_NONE; 1070 1071 return IRQ_HANDLED; 1072 } 1073 1074 return IRQ_NONE; 1075 } 1076 1077 static void fxls8962af_pm_disable(void *dev_ptr) 1078 { 1079 struct device *dev = dev_ptr; 1080 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1081 1082 pm_runtime_disable(dev); 1083 pm_runtime_set_suspended(dev); 1084 pm_runtime_put_noidle(dev); 1085 1086 fxls8962af_standby(iio_priv(indio_dev)); 1087 } 1088 1089 static void fxls8962af_get_irq(struct device *dev, 1090 enum fxls8962af_int_pin *pin) 1091 { 1092 int irq; 1093 1094 irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT2"); 1095 if (irq > 0) { 1096 *pin = FXLS8962AF_PIN_INT2; 1097 return; 1098 } 1099 1100 *pin = FXLS8962AF_PIN_INT1; 1101 } 1102 1103 static int fxls8962af_irq_setup(struct iio_dev *indio_dev, int irq) 1104 { 1105 struct fxls8962af_data *data = iio_priv(indio_dev); 1106 struct device *dev = regmap_get_device(data->regmap); 1107 unsigned long irq_type; 1108 bool irq_active_high; 1109 enum fxls8962af_int_pin int_pin; 1110 u8 int_pin_sel; 1111 int ret; 1112 1113 fxls8962af_get_irq(dev, &int_pin); 1114 switch (int_pin) { 1115 case FXLS8962AF_PIN_INT1: 1116 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT1; 1117 break; 1118 case FXLS8962AF_PIN_INT2: 1119 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT2; 1120 break; 1121 default: 1122 dev_err(dev, "unsupported int pin selected\n"); 1123 return -EINVAL; 1124 } 1125 1126 ret = regmap_update_bits(data->regmap, FXLS8962AF_INT_PIN_SEL, 1127 FXLS8962AF_INT_PIN_SEL_MASK, int_pin_sel); 1128 if (ret) 1129 return ret; 1130 1131 irq_type = irq_get_trigger_type(irq); 1132 switch (irq_type) { 1133 case IRQF_TRIGGER_HIGH: 1134 case IRQF_TRIGGER_RISING: 1135 irq_active_high = true; 1136 break; 1137 case IRQF_TRIGGER_LOW: 1138 case IRQF_TRIGGER_FALLING: 1139 irq_active_high = false; 1140 break; 1141 default: 1142 dev_info(dev, "mode %lx unsupported\n", irq_type); 1143 return -EINVAL; 1144 } 1145 1146 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4, 1147 FXLS8962AF_SC4_INT_POL_MASK, 1148 FXLS8962AF_SC4_INT_POL_PREP(irq_active_high)); 1149 if (ret) 1150 return ret; 1151 1152 if (device_property_read_bool(dev, "drive-open-drain")) { 1153 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4, 1154 FXLS8962AF_SC4_INT_PP_OD_MASK, 1155 FXLS8962AF_SC4_INT_PP_OD_PREP(1)); 1156 if (ret) 1157 return ret; 1158 1159 irq_type |= IRQF_SHARED; 1160 } 1161 1162 return devm_request_threaded_irq(dev, 1163 irq, 1164 NULL, fxls8962af_interrupt, 1165 irq_type | IRQF_ONESHOT, 1166 indio_dev->name, indio_dev); 1167 } 1168 1169 int fxls8962af_core_probe(struct device *dev, struct regmap *regmap, int irq) 1170 { 1171 struct fxls8962af_data *data; 1172 struct iio_dev *indio_dev; 1173 unsigned int reg; 1174 int ret, i; 1175 1176 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1177 if (!indio_dev) 1178 return -ENOMEM; 1179 1180 data = iio_priv(indio_dev); 1181 dev_set_drvdata(dev, indio_dev); 1182 data->regmap = regmap; 1183 data->irq = irq; 1184 1185 ret = iio_read_mount_matrix(dev, &data->orientation); 1186 if (ret) 1187 return ret; 1188 1189 ret = devm_regulator_get_enable(dev, "vdd"); 1190 if (ret) 1191 return dev_err_probe(dev, ret, 1192 "Failed to get vdd regulator\n"); 1193 1194 ret = regmap_read(data->regmap, FXLS8962AF_WHO_AM_I, ®); 1195 if (ret) 1196 return ret; 1197 1198 for (i = 0; i < ARRAY_SIZE(fxls_chip_info_table); i++) { 1199 if (fxls_chip_info_table[i].chip_id == reg) { 1200 data->chip_info = &fxls_chip_info_table[i]; 1201 break; 1202 } 1203 } 1204 if (i == ARRAY_SIZE(fxls_chip_info_table)) { 1205 dev_err(dev, "failed to match device in table\n"); 1206 return -ENXIO; 1207 } 1208 1209 indio_dev->channels = data->chip_info->channels; 1210 indio_dev->num_channels = data->chip_info->num_channels; 1211 indio_dev->name = data->chip_info->name; 1212 indio_dev->info = &fxls8962af_info; 1213 indio_dev->modes = INDIO_DIRECT_MODE; 1214 1215 ret = fxls8962af_reset(data); 1216 if (ret) 1217 return ret; 1218 1219 if (irq) { 1220 ret = fxls8962af_irq_setup(indio_dev, irq); 1221 if (ret) 1222 return ret; 1223 1224 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, 1225 &fxls8962af_buffer_ops); 1226 if (ret) 1227 return ret; 1228 } 1229 1230 ret = pm_runtime_set_active(dev); 1231 if (ret) 1232 return ret; 1233 1234 pm_runtime_enable(dev); 1235 pm_runtime_set_autosuspend_delay(dev, FXLS8962AF_AUTO_SUSPEND_DELAY_MS); 1236 pm_runtime_use_autosuspend(dev); 1237 1238 ret = devm_add_action_or_reset(dev, fxls8962af_pm_disable, dev); 1239 if (ret) 1240 return ret; 1241 1242 if (device_property_read_bool(dev, "wakeup-source")) { 1243 ret = devm_device_init_wakeup(dev); 1244 if (ret) 1245 return dev_err_probe(dev, ret, "Failed to init wakeup\n"); 1246 } 1247 1248 return devm_iio_device_register(dev, indio_dev); 1249 } 1250 EXPORT_SYMBOL_NS_GPL(fxls8962af_core_probe, "IIO_FXLS8962AF"); 1251 1252 static int fxls8962af_runtime_suspend(struct device *dev) 1253 { 1254 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev)); 1255 int ret; 1256 1257 ret = fxls8962af_standby(data); 1258 if (ret) { 1259 dev_err(dev, "powering off device failed\n"); 1260 return ret; 1261 } 1262 1263 return 0; 1264 } 1265 1266 static int fxls8962af_runtime_resume(struct device *dev) 1267 { 1268 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev)); 1269 1270 return fxls8962af_active(data); 1271 } 1272 1273 static int fxls8962af_suspend(struct device *dev) 1274 { 1275 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1276 struct fxls8962af_data *data = iio_priv(indio_dev); 1277 1278 if (device_may_wakeup(dev) && data->enable_event) { 1279 enable_irq_wake(data->irq); 1280 1281 /* 1282 * Disable buffer, as the buffer is so small the device will wake 1283 * almost immediately. 1284 */ 1285 if (iio_buffer_enabled(indio_dev)) 1286 fxls8962af_buffer_predisable(indio_dev); 1287 } else { 1288 fxls8962af_runtime_suspend(dev); 1289 } 1290 1291 return 0; 1292 } 1293 1294 static int fxls8962af_resume(struct device *dev) 1295 { 1296 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1297 struct fxls8962af_data *data = iio_priv(indio_dev); 1298 1299 if (device_may_wakeup(dev) && data->enable_event) { 1300 disable_irq_wake(data->irq); 1301 1302 if (iio_buffer_enabled(indio_dev)) 1303 fxls8962af_buffer_postenable(indio_dev); 1304 } else { 1305 fxls8962af_runtime_resume(dev); 1306 } 1307 1308 return 0; 1309 } 1310 1311 EXPORT_NS_GPL_DEV_PM_OPS(fxls8962af_pm_ops, IIO_FXLS8962AF) = { 1312 SYSTEM_SLEEP_PM_OPS(fxls8962af_suspend, fxls8962af_resume) 1313 RUNTIME_PM_OPS(fxls8962af_runtime_suspend, fxls8962af_runtime_resume, NULL) 1314 }; 1315 1316 MODULE_AUTHOR("Sean Nyekjaer <sean@geanix.com>"); 1317 MODULE_DESCRIPTION("NXP FXLS8962AF/FXLS8964AF accelerometer driver"); 1318 MODULE_LICENSE("GPL v2"); 1319