1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NXP FXLS8962AF/FXLS8964AF Accelerometer Core Driver 4 * 5 * Copyright 2021 Connected Cars A/S 6 * 7 * Datasheet: 8 * https://www.nxp.com/docs/en/data-sheet/FXLS8962AF.pdf 9 * https://www.nxp.com/docs/en/data-sheet/FXLS8964AF.pdf 10 * 11 * Errata: 12 * https://www.nxp.com/docs/en/errata/ES_FXLS8962AF.pdf 13 */ 14 15 #include <linux/bits.h> 16 #include <linux/bitfield.h> 17 #include <linux/i2c.h> 18 #include <linux/irq.h> 19 #include <linux/module.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/property.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/regmap.h> 25 #include <linux/types.h> 26 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/events.h> 29 #include <linux/iio/iio.h> 30 #include <linux/iio/kfifo_buf.h> 31 #include <linux/iio/sysfs.h> 32 33 #include "fxls8962af.h" 34 35 #define FXLS8962AF_INT_STATUS 0x00 36 #define FXLS8962AF_INT_STATUS_SRC_BOOT BIT(0) 37 #define FXLS8962AF_INT_STATUS_SRC_SDCD_OT BIT(4) 38 #define FXLS8962AF_INT_STATUS_SRC_BUF BIT(5) 39 #define FXLS8962AF_INT_STATUS_SRC_DRDY BIT(7) 40 #define FXLS8962AF_TEMP_OUT 0x01 41 #define FXLS8962AF_VECM_LSB 0x02 42 #define FXLS8962AF_OUT_X_LSB 0x04 43 #define FXLS8962AF_OUT_Y_LSB 0x06 44 #define FXLS8962AF_OUT_Z_LSB 0x08 45 #define FXLS8962AF_BUF_STATUS 0x0b 46 #define FXLS8962AF_BUF_STATUS_BUF_CNT GENMASK(5, 0) 47 #define FXLS8962AF_BUF_STATUS_BUF_OVF BIT(6) 48 #define FXLS8962AF_BUF_STATUS_BUF_WMRK BIT(7) 49 #define FXLS8962AF_BUF_X_LSB 0x0c 50 #define FXLS8962AF_BUF_Y_LSB 0x0e 51 #define FXLS8962AF_BUF_Z_LSB 0x10 52 53 #define FXLS8962AF_PROD_REV 0x12 54 #define FXLS8962AF_WHO_AM_I 0x13 55 56 #define FXLS8962AF_SYS_MODE 0x14 57 #define FXLS8962AF_SENS_CONFIG1 0x15 58 #define FXLS8962AF_SENS_CONFIG1_ACTIVE BIT(0) 59 #define FXLS8962AF_SENS_CONFIG1_RST BIT(7) 60 #define FXLS8962AF_SC1_FSR_MASK GENMASK(2, 1) 61 #define FXLS8962AF_SC1_FSR_PREP(x) FIELD_PREP(FXLS8962AF_SC1_FSR_MASK, (x)) 62 #define FXLS8962AF_SC1_FSR_GET(x) FIELD_GET(FXLS8962AF_SC1_FSR_MASK, (x)) 63 64 #define FXLS8962AF_SENS_CONFIG2 0x16 65 #define FXLS8962AF_SENS_CONFIG3 0x17 66 #define FXLS8962AF_SC3_WAKE_ODR_MASK GENMASK(7, 4) 67 #define FXLS8962AF_SC3_WAKE_ODR_PREP(x) FIELD_PREP(FXLS8962AF_SC3_WAKE_ODR_MASK, (x)) 68 #define FXLS8962AF_SC3_WAKE_ODR_GET(x) FIELD_GET(FXLS8962AF_SC3_WAKE_ODR_MASK, (x)) 69 #define FXLS8962AF_SENS_CONFIG4 0x18 70 #define FXLS8962AF_SC4_INT_PP_OD_MASK BIT(1) 71 #define FXLS8962AF_SC4_INT_PP_OD_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_PP_OD_MASK, (x)) 72 #define FXLS8962AF_SC4_INT_POL_MASK BIT(0) 73 #define FXLS8962AF_SC4_INT_POL_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_POL_MASK, (x)) 74 #define FXLS8962AF_SENS_CONFIG5 0x19 75 76 #define FXLS8962AF_WAKE_IDLE_LSB 0x1b 77 #define FXLS8962AF_SLEEP_IDLE_LSB 0x1c 78 #define FXLS8962AF_ASLP_COUNT_LSB 0x1e 79 80 #define FXLS8962AF_INT_EN 0x20 81 #define FXLS8962AF_INT_EN_SDCD_OT_EN BIT(5) 82 #define FXLS8962AF_INT_EN_BUF_EN BIT(6) 83 #define FXLS8962AF_INT_PIN_SEL 0x21 84 #define FXLS8962AF_INT_PIN_SEL_MASK GENMASK(7, 0) 85 #define FXLS8962AF_INT_PIN_SEL_INT1 0x00 86 #define FXLS8962AF_INT_PIN_SEL_INT2 GENMASK(7, 0) 87 88 #define FXLS8962AF_OFF_X 0x22 89 #define FXLS8962AF_OFF_Y 0x23 90 #define FXLS8962AF_OFF_Z 0x24 91 92 #define FXLS8962AF_BUF_CONFIG1 0x26 93 #define FXLS8962AF_BC1_BUF_MODE_MASK GENMASK(6, 5) 94 #define FXLS8962AF_BC1_BUF_MODE_PREP(x) FIELD_PREP(FXLS8962AF_BC1_BUF_MODE_MASK, (x)) 95 #define FXLS8962AF_BUF_CONFIG2 0x27 96 #define FXLS8962AF_BUF_CONFIG2_BUF_WMRK GENMASK(5, 0) 97 98 #define FXLS8962AF_ORIENT_STATUS 0x28 99 #define FXLS8962AF_ORIENT_CONFIG 0x29 100 #define FXLS8962AF_ORIENT_DBCOUNT 0x2a 101 #define FXLS8962AF_ORIENT_BF_ZCOMP 0x2b 102 #define FXLS8962AF_ORIENT_THS_REG 0x2c 103 104 #define FXLS8962AF_SDCD_INT_SRC1 0x2d 105 #define FXLS8962AF_SDCD_INT_SRC1_X_OT BIT(5) 106 #define FXLS8962AF_SDCD_INT_SRC1_X_POL BIT(4) 107 #define FXLS8962AF_SDCD_INT_SRC1_Y_OT BIT(3) 108 #define FXLS8962AF_SDCD_INT_SRC1_Y_POL BIT(2) 109 #define FXLS8962AF_SDCD_INT_SRC1_Z_OT BIT(1) 110 #define FXLS8962AF_SDCD_INT_SRC1_Z_POL BIT(0) 111 #define FXLS8962AF_SDCD_INT_SRC2 0x2e 112 #define FXLS8962AF_SDCD_CONFIG1 0x2f 113 #define FXLS8962AF_SDCD_CONFIG1_Z_OT_EN BIT(3) 114 #define FXLS8962AF_SDCD_CONFIG1_Y_OT_EN BIT(4) 115 #define FXLS8962AF_SDCD_CONFIG1_X_OT_EN BIT(5) 116 #define FXLS8962AF_SDCD_CONFIG1_OT_ELE BIT(7) 117 #define FXLS8962AF_SDCD_CONFIG2 0x30 118 #define FXLS8962AF_SDCD_CONFIG2_SDCD_EN BIT(7) 119 #define FXLS8962AF_SC2_REF_UPDM_AC GENMASK(6, 5) 120 #define FXLS8962AF_SDCD_OT_DBCNT 0x31 121 #define FXLS8962AF_SDCD_WT_DBCNT 0x32 122 #define FXLS8962AF_SDCD_LTHS_LSB 0x33 123 #define FXLS8962AF_SDCD_UTHS_LSB 0x35 124 125 #define FXLS8962AF_SELF_TEST_CONFIG1 0x37 126 #define FXLS8962AF_SELF_TEST_CONFIG2 0x38 127 128 #define FXLS8962AF_MAX_REG 0x38 129 130 #define FXLS8962AF_DEVICE_ID 0x62 131 #define FXLS8964AF_DEVICE_ID 0x84 132 #define FXLS8974CF_DEVICE_ID 0x86 133 #define FXLS8967AF_DEVICE_ID 0x87 134 135 /* Raw temp channel offset */ 136 #define FXLS8962AF_TEMP_CENTER_VAL 25 137 138 #define FXLS8962AF_AUTO_SUSPEND_DELAY_MS 2000 139 140 #define FXLS8962AF_FIFO_LENGTH 32 141 #define FXLS8962AF_SCALE_TABLE_LEN 4 142 #define FXLS8962AF_SAMP_FREQ_TABLE_LEN 13 143 144 static const int fxls8962af_scale_table[FXLS8962AF_SCALE_TABLE_LEN][2] = { 145 {0, IIO_G_TO_M_S_2(980000)}, 146 {0, IIO_G_TO_M_S_2(1950000)}, 147 {0, IIO_G_TO_M_S_2(3910000)}, 148 {0, IIO_G_TO_M_S_2(7810000)}, 149 }; 150 151 static const int fxls8962af_samp_freq_table[FXLS8962AF_SAMP_FREQ_TABLE_LEN][2] = { 152 {3200, 0}, {1600, 0}, {800, 0}, {400, 0}, {200, 0}, {100, 0}, 153 {50, 0}, {25, 0}, {12, 500000}, {6, 250000}, {3, 125000}, 154 {1, 563000}, {0, 781000}, 155 }; 156 157 struct fxls8962af_chip_info { 158 const char *name; 159 const struct iio_chan_spec *channels; 160 int num_channels; 161 u8 chip_id; 162 }; 163 164 struct fxls8962af_data { 165 struct regmap *regmap; 166 const struct fxls8962af_chip_info *chip_info; 167 struct { 168 __le16 channels[3]; 169 aligned_s64 ts; 170 } scan; 171 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */ 172 struct iio_mount_matrix orientation; 173 int irq; 174 u8 watermark; 175 u8 enable_event; 176 u16 lower_thres; 177 u16 upper_thres; 178 }; 179 180 const struct regmap_config fxls8962af_i2c_regmap_conf = { 181 .reg_bits = 8, 182 .val_bits = 8, 183 .max_register = FXLS8962AF_MAX_REG, 184 }; 185 EXPORT_SYMBOL_NS_GPL(fxls8962af_i2c_regmap_conf, "IIO_FXLS8962AF"); 186 187 const struct regmap_config fxls8962af_spi_regmap_conf = { 188 .reg_bits = 8, 189 .pad_bits = 8, 190 .val_bits = 8, 191 .max_register = FXLS8962AF_MAX_REG, 192 }; 193 EXPORT_SYMBOL_NS_GPL(fxls8962af_spi_regmap_conf, "IIO_FXLS8962AF"); 194 195 enum { 196 fxls8962af_idx_x, 197 fxls8962af_idx_y, 198 fxls8962af_idx_z, 199 fxls8962af_idx_ts, 200 }; 201 202 enum fxls8962af_int_pin { 203 FXLS8962AF_PIN_INT1, 204 FXLS8962AF_PIN_INT2, 205 }; 206 207 static int fxls8962af_power_on(struct fxls8962af_data *data) 208 { 209 struct device *dev = regmap_get_device(data->regmap); 210 int ret; 211 212 ret = pm_runtime_resume_and_get(dev); 213 if (ret) 214 dev_err(dev, "failed to power on\n"); 215 216 return ret; 217 } 218 219 static int fxls8962af_power_off(struct fxls8962af_data *data) 220 { 221 struct device *dev = regmap_get_device(data->regmap); 222 int ret; 223 224 pm_runtime_mark_last_busy(dev); 225 ret = pm_runtime_put_autosuspend(dev); 226 if (ret) 227 dev_err(dev, "failed to power off\n"); 228 229 return ret; 230 } 231 232 static int fxls8962af_standby(struct fxls8962af_data *data) 233 { 234 return regmap_clear_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 235 FXLS8962AF_SENS_CONFIG1_ACTIVE); 236 } 237 238 static int fxls8962af_active(struct fxls8962af_data *data) 239 { 240 return regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 241 FXLS8962AF_SENS_CONFIG1_ACTIVE, 1); 242 } 243 244 static int fxls8962af_is_active(struct fxls8962af_data *data) 245 { 246 unsigned int reg; 247 int ret; 248 249 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®); 250 if (ret) 251 return ret; 252 253 return reg & FXLS8962AF_SENS_CONFIG1_ACTIVE; 254 } 255 256 static int fxls8962af_get_out(struct fxls8962af_data *data, 257 struct iio_chan_spec const *chan, int *val) 258 { 259 struct device *dev = regmap_get_device(data->regmap); 260 __le16 raw_val; 261 int is_active; 262 int ret; 263 264 is_active = fxls8962af_is_active(data); 265 if (!is_active) { 266 ret = fxls8962af_power_on(data); 267 if (ret) 268 return ret; 269 } 270 271 ret = regmap_bulk_read(data->regmap, chan->address, 272 &raw_val, sizeof(data->lower_thres)); 273 274 if (!is_active) 275 fxls8962af_power_off(data); 276 277 if (ret) { 278 dev_err(dev, "failed to get out reg 0x%lx\n", chan->address); 279 return ret; 280 } 281 282 *val = sign_extend32(le16_to_cpu(raw_val), 283 chan->scan_type.realbits - 1); 284 285 return IIO_VAL_INT; 286 } 287 288 static int fxls8962af_read_avail(struct iio_dev *indio_dev, 289 struct iio_chan_spec const *chan, 290 const int **vals, int *type, int *length, 291 long mask) 292 { 293 switch (mask) { 294 case IIO_CHAN_INFO_SCALE: 295 *type = IIO_VAL_INT_PLUS_NANO; 296 *vals = (int *)fxls8962af_scale_table; 297 *length = ARRAY_SIZE(fxls8962af_scale_table) * 2; 298 return IIO_AVAIL_LIST; 299 case IIO_CHAN_INFO_SAMP_FREQ: 300 *type = IIO_VAL_INT_PLUS_MICRO; 301 *vals = (int *)fxls8962af_samp_freq_table; 302 *length = ARRAY_SIZE(fxls8962af_samp_freq_table) * 2; 303 return IIO_AVAIL_LIST; 304 default: 305 return -EINVAL; 306 } 307 } 308 309 static int fxls8962af_write_raw_get_fmt(struct iio_dev *indio_dev, 310 struct iio_chan_spec const *chan, 311 long mask) 312 { 313 switch (mask) { 314 case IIO_CHAN_INFO_SCALE: 315 return IIO_VAL_INT_PLUS_NANO; 316 case IIO_CHAN_INFO_SAMP_FREQ: 317 return IIO_VAL_INT_PLUS_MICRO; 318 default: 319 return IIO_VAL_INT_PLUS_NANO; 320 } 321 } 322 323 static int fxls8962af_update_config(struct fxls8962af_data *data, u8 reg, 324 u8 mask, u8 val) 325 { 326 int ret; 327 int is_active; 328 329 is_active = fxls8962af_is_active(data); 330 if (is_active) { 331 ret = fxls8962af_standby(data); 332 if (ret) 333 return ret; 334 } 335 336 ret = regmap_update_bits(data->regmap, reg, mask, val); 337 if (ret) 338 return ret; 339 340 if (is_active) { 341 ret = fxls8962af_active(data); 342 if (ret) 343 return ret; 344 } 345 346 return 0; 347 } 348 349 static int fxls8962af_set_full_scale(struct fxls8962af_data *data, u32 scale) 350 { 351 int i; 352 353 for (i = 0; i < ARRAY_SIZE(fxls8962af_scale_table); i++) 354 if (scale == fxls8962af_scale_table[i][1]) 355 break; 356 357 if (i == ARRAY_SIZE(fxls8962af_scale_table)) 358 return -EINVAL; 359 360 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG1, 361 FXLS8962AF_SC1_FSR_MASK, 362 FXLS8962AF_SC1_FSR_PREP(i)); 363 } 364 365 static unsigned int fxls8962af_read_full_scale(struct fxls8962af_data *data, 366 int *val) 367 { 368 int ret; 369 unsigned int reg; 370 u8 range_idx; 371 372 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®); 373 if (ret) 374 return ret; 375 376 range_idx = FXLS8962AF_SC1_FSR_GET(reg); 377 378 *val = fxls8962af_scale_table[range_idx][1]; 379 380 return IIO_VAL_INT_PLUS_NANO; 381 } 382 383 static int fxls8962af_set_samp_freq(struct fxls8962af_data *data, u32 val, 384 u32 val2) 385 { 386 int i; 387 388 for (i = 0; i < ARRAY_SIZE(fxls8962af_samp_freq_table); i++) 389 if (val == fxls8962af_samp_freq_table[i][0] && 390 val2 == fxls8962af_samp_freq_table[i][1]) 391 break; 392 393 if (i == ARRAY_SIZE(fxls8962af_samp_freq_table)) 394 return -EINVAL; 395 396 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG3, 397 FXLS8962AF_SC3_WAKE_ODR_MASK, 398 FXLS8962AF_SC3_WAKE_ODR_PREP(i)); 399 } 400 401 static unsigned int fxls8962af_read_samp_freq(struct fxls8962af_data *data, 402 int *val, int *val2) 403 { 404 int ret; 405 unsigned int reg; 406 u8 range_idx; 407 408 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG3, ®); 409 if (ret) 410 return ret; 411 412 range_idx = FXLS8962AF_SC3_WAKE_ODR_GET(reg); 413 414 *val = fxls8962af_samp_freq_table[range_idx][0]; 415 *val2 = fxls8962af_samp_freq_table[range_idx][1]; 416 417 return IIO_VAL_INT_PLUS_MICRO; 418 } 419 420 static int fxls8962af_read_raw(struct iio_dev *indio_dev, 421 struct iio_chan_spec const *chan, 422 int *val, int *val2, long mask) 423 { 424 struct fxls8962af_data *data = iio_priv(indio_dev); 425 426 switch (mask) { 427 case IIO_CHAN_INFO_RAW: 428 switch (chan->type) { 429 case IIO_TEMP: 430 case IIO_ACCEL: 431 return fxls8962af_get_out(data, chan, val); 432 default: 433 return -EINVAL; 434 } 435 case IIO_CHAN_INFO_OFFSET: 436 if (chan->type != IIO_TEMP) 437 return -EINVAL; 438 439 *val = FXLS8962AF_TEMP_CENTER_VAL; 440 return IIO_VAL_INT; 441 case IIO_CHAN_INFO_SCALE: 442 *val = 0; 443 return fxls8962af_read_full_scale(data, val2); 444 case IIO_CHAN_INFO_SAMP_FREQ: 445 return fxls8962af_read_samp_freq(data, val, val2); 446 default: 447 return -EINVAL; 448 } 449 } 450 451 static int fxls8962af_write_raw(struct iio_dev *indio_dev, 452 struct iio_chan_spec const *chan, 453 int val, int val2, long mask) 454 { 455 struct fxls8962af_data *data = iio_priv(indio_dev); 456 int ret; 457 458 switch (mask) { 459 case IIO_CHAN_INFO_SCALE: 460 if (val != 0) 461 return -EINVAL; 462 463 ret = iio_device_claim_direct_mode(indio_dev); 464 if (ret) 465 return ret; 466 467 ret = fxls8962af_set_full_scale(data, val2); 468 469 iio_device_release_direct_mode(indio_dev); 470 return ret; 471 case IIO_CHAN_INFO_SAMP_FREQ: 472 ret = iio_device_claim_direct_mode(indio_dev); 473 if (ret) 474 return ret; 475 476 ret = fxls8962af_set_samp_freq(data, val, val2); 477 478 iio_device_release_direct_mode(indio_dev); 479 return ret; 480 default: 481 return -EINVAL; 482 } 483 } 484 485 static int fxls8962af_event_setup(struct fxls8962af_data *data, int state) 486 { 487 /* Enable wakeup interrupt */ 488 int mask = FXLS8962AF_INT_EN_SDCD_OT_EN; 489 int value = state ? mask : 0; 490 491 return regmap_update_bits(data->regmap, FXLS8962AF_INT_EN, mask, value); 492 } 493 494 static int fxls8962af_set_watermark(struct iio_dev *indio_dev, unsigned val) 495 { 496 struct fxls8962af_data *data = iio_priv(indio_dev); 497 498 if (val > FXLS8962AF_FIFO_LENGTH) 499 val = FXLS8962AF_FIFO_LENGTH; 500 501 data->watermark = val; 502 503 return 0; 504 } 505 506 static int __fxls8962af_set_thresholds(struct fxls8962af_data *data, 507 const struct iio_chan_spec *chan, 508 enum iio_event_direction dir, 509 int val) 510 { 511 switch (dir) { 512 case IIO_EV_DIR_FALLING: 513 data->lower_thres = val; 514 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_LTHS_LSB, 515 &data->lower_thres, sizeof(data->lower_thres)); 516 case IIO_EV_DIR_RISING: 517 data->upper_thres = val; 518 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_UTHS_LSB, 519 &data->upper_thres, sizeof(data->upper_thres)); 520 default: 521 return -EINVAL; 522 } 523 } 524 525 static int fxls8962af_read_event(struct iio_dev *indio_dev, 526 const struct iio_chan_spec *chan, 527 enum iio_event_type type, 528 enum iio_event_direction dir, 529 enum iio_event_info info, 530 int *val, int *val2) 531 { 532 struct fxls8962af_data *data = iio_priv(indio_dev); 533 int ret; 534 535 if (type != IIO_EV_TYPE_THRESH) 536 return -EINVAL; 537 538 switch (dir) { 539 case IIO_EV_DIR_FALLING: 540 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_LTHS_LSB, 541 &data->lower_thres, sizeof(data->lower_thres)); 542 if (ret) 543 return ret; 544 545 *val = sign_extend32(data->lower_thres, chan->scan_type.realbits - 1); 546 return IIO_VAL_INT; 547 case IIO_EV_DIR_RISING: 548 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_UTHS_LSB, 549 &data->upper_thres, sizeof(data->upper_thres)); 550 if (ret) 551 return ret; 552 553 *val = sign_extend32(data->upper_thres, chan->scan_type.realbits - 1); 554 return IIO_VAL_INT; 555 default: 556 return -EINVAL; 557 } 558 } 559 560 static int fxls8962af_write_event(struct iio_dev *indio_dev, 561 const struct iio_chan_spec *chan, 562 enum iio_event_type type, 563 enum iio_event_direction dir, 564 enum iio_event_info info, 565 int val, int val2) 566 { 567 struct fxls8962af_data *data = iio_priv(indio_dev); 568 int ret, val_masked; 569 570 if (type != IIO_EV_TYPE_THRESH) 571 return -EINVAL; 572 573 if (val < -2048 || val > 2047) 574 return -EINVAL; 575 576 if (data->enable_event) 577 return -EBUSY; 578 579 val_masked = val & GENMASK(11, 0); 580 if (fxls8962af_is_active(data)) { 581 ret = fxls8962af_standby(data); 582 if (ret) 583 return ret; 584 585 ret = __fxls8962af_set_thresholds(data, chan, dir, val_masked); 586 if (ret) 587 return ret; 588 589 return fxls8962af_active(data); 590 } else { 591 return __fxls8962af_set_thresholds(data, chan, dir, val_masked); 592 } 593 } 594 595 static int 596 fxls8962af_read_event_config(struct iio_dev *indio_dev, 597 const struct iio_chan_spec *chan, 598 enum iio_event_type type, 599 enum iio_event_direction dir) 600 { 601 struct fxls8962af_data *data = iio_priv(indio_dev); 602 603 if (type != IIO_EV_TYPE_THRESH) 604 return -EINVAL; 605 606 switch (chan->channel2) { 607 case IIO_MOD_X: 608 return !!(FXLS8962AF_SDCD_CONFIG1_X_OT_EN & data->enable_event); 609 case IIO_MOD_Y: 610 return !!(FXLS8962AF_SDCD_CONFIG1_Y_OT_EN & data->enable_event); 611 case IIO_MOD_Z: 612 return !!(FXLS8962AF_SDCD_CONFIG1_Z_OT_EN & data->enable_event); 613 default: 614 return -EINVAL; 615 } 616 } 617 618 static int 619 fxls8962af_write_event_config(struct iio_dev *indio_dev, 620 const struct iio_chan_spec *chan, 621 enum iio_event_type type, 622 enum iio_event_direction dir, bool state) 623 { 624 struct fxls8962af_data *data = iio_priv(indio_dev); 625 u8 enable_event, enable_bits; 626 int ret, value; 627 628 if (type != IIO_EV_TYPE_THRESH) 629 return -EINVAL; 630 631 switch (chan->channel2) { 632 case IIO_MOD_X: 633 enable_bits = FXLS8962AF_SDCD_CONFIG1_X_OT_EN; 634 break; 635 case IIO_MOD_Y: 636 enable_bits = FXLS8962AF_SDCD_CONFIG1_Y_OT_EN; 637 break; 638 case IIO_MOD_Z: 639 enable_bits = FXLS8962AF_SDCD_CONFIG1_Z_OT_EN; 640 break; 641 default: 642 return -EINVAL; 643 } 644 645 if (state) 646 enable_event = data->enable_event | enable_bits; 647 else 648 enable_event = data->enable_event & ~enable_bits; 649 650 if (data->enable_event == enable_event) 651 return 0; 652 653 ret = fxls8962af_standby(data); 654 if (ret) 655 return ret; 656 657 /* Enable events */ 658 value = enable_event | FXLS8962AF_SDCD_CONFIG1_OT_ELE; 659 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG1, value); 660 if (ret) 661 return ret; 662 663 /* 664 * Enable update of SDCD_REF_X/Y/Z values with the current decimated and 665 * trimmed X/Y/Z acceleration input data. This allows for acceleration 666 * slope detection with Data(n) to Data(n–1) always used as the input 667 * to the window comparator. 668 */ 669 value = enable_event ? 670 FXLS8962AF_SDCD_CONFIG2_SDCD_EN | FXLS8962AF_SC2_REF_UPDM_AC : 671 0x00; 672 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG2, value); 673 if (ret) 674 return ret; 675 676 ret = fxls8962af_event_setup(data, state); 677 if (ret) 678 return ret; 679 680 data->enable_event = enable_event; 681 682 if (data->enable_event) { 683 fxls8962af_active(data); 684 ret = fxls8962af_power_on(data); 685 } else { 686 ret = iio_device_claim_direct_mode(indio_dev); 687 if (ret) 688 return ret; 689 690 /* Not in buffered mode so disable power */ 691 ret = fxls8962af_power_off(data); 692 693 iio_device_release_direct_mode(indio_dev); 694 } 695 696 return ret; 697 } 698 699 static const struct iio_event_spec fxls8962af_event[] = { 700 { 701 .type = IIO_EV_TYPE_THRESH, 702 .dir = IIO_EV_DIR_EITHER, 703 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 704 }, 705 { 706 .type = IIO_EV_TYPE_THRESH, 707 .dir = IIO_EV_DIR_FALLING, 708 .mask_separate = BIT(IIO_EV_INFO_VALUE), 709 }, 710 { 711 .type = IIO_EV_TYPE_THRESH, 712 .dir = IIO_EV_DIR_RISING, 713 .mask_separate = BIT(IIO_EV_INFO_VALUE), 714 }, 715 }; 716 717 #define FXLS8962AF_CHANNEL(axis, reg, idx) { \ 718 .type = IIO_ACCEL, \ 719 .address = reg, \ 720 .modified = 1, \ 721 .channel2 = IIO_MOD_##axis, \ 722 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 723 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 724 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 725 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \ 726 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 727 .scan_index = idx, \ 728 .scan_type = { \ 729 .sign = 's', \ 730 .realbits = 12, \ 731 .storagebits = 16, \ 732 .endianness = IIO_LE, \ 733 }, \ 734 .event_spec = fxls8962af_event, \ 735 .num_event_specs = ARRAY_SIZE(fxls8962af_event), \ 736 } 737 738 #define FXLS8962AF_TEMP_CHANNEL { \ 739 .type = IIO_TEMP, \ 740 .address = FXLS8962AF_TEMP_OUT, \ 741 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 742 BIT(IIO_CHAN_INFO_OFFSET),\ 743 .scan_index = -1, \ 744 .scan_type = { \ 745 .realbits = 8, \ 746 .storagebits = 8, \ 747 }, \ 748 } 749 750 static const struct iio_chan_spec fxls8962af_channels[] = { 751 FXLS8962AF_CHANNEL(X, FXLS8962AF_OUT_X_LSB, fxls8962af_idx_x), 752 FXLS8962AF_CHANNEL(Y, FXLS8962AF_OUT_Y_LSB, fxls8962af_idx_y), 753 FXLS8962AF_CHANNEL(Z, FXLS8962AF_OUT_Z_LSB, fxls8962af_idx_z), 754 IIO_CHAN_SOFT_TIMESTAMP(fxls8962af_idx_ts), 755 FXLS8962AF_TEMP_CHANNEL, 756 }; 757 758 static const struct fxls8962af_chip_info fxls_chip_info_table[] = { 759 [fxls8962af] = { 760 .chip_id = FXLS8962AF_DEVICE_ID, 761 .name = "fxls8962af", 762 .channels = fxls8962af_channels, 763 .num_channels = ARRAY_SIZE(fxls8962af_channels), 764 }, 765 [fxls8964af] = { 766 .chip_id = FXLS8964AF_DEVICE_ID, 767 .name = "fxls8964af", 768 .channels = fxls8962af_channels, 769 .num_channels = ARRAY_SIZE(fxls8962af_channels), 770 }, 771 [fxls8967af] = { 772 .chip_id = FXLS8967AF_DEVICE_ID, 773 .name = "fxls8967af", 774 .channels = fxls8962af_channels, 775 .num_channels = ARRAY_SIZE(fxls8962af_channels), 776 }, 777 [fxls8974cf] = { 778 .chip_id = FXLS8974CF_DEVICE_ID, 779 .name = "fxls8974cf", 780 .channels = fxls8962af_channels, 781 .num_channels = ARRAY_SIZE(fxls8962af_channels), 782 }, 783 }; 784 785 static const struct iio_info fxls8962af_info = { 786 .read_raw = &fxls8962af_read_raw, 787 .write_raw = &fxls8962af_write_raw, 788 .write_raw_get_fmt = fxls8962af_write_raw_get_fmt, 789 .read_event_value = fxls8962af_read_event, 790 .write_event_value = fxls8962af_write_event, 791 .read_event_config = fxls8962af_read_event_config, 792 .write_event_config = fxls8962af_write_event_config, 793 .read_avail = fxls8962af_read_avail, 794 .hwfifo_set_watermark = fxls8962af_set_watermark, 795 }; 796 797 static int fxls8962af_reset(struct fxls8962af_data *data) 798 { 799 struct device *dev = regmap_get_device(data->regmap); 800 unsigned int reg; 801 int ret; 802 803 ret = regmap_set_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 804 FXLS8962AF_SENS_CONFIG1_RST); 805 if (ret) 806 return ret; 807 808 /* TBOOT1, TBOOT2, specifies we have to wait between 1 - 17.7ms */ 809 ret = regmap_read_poll_timeout(data->regmap, FXLS8962AF_INT_STATUS, reg, 810 (reg & FXLS8962AF_INT_STATUS_SRC_BOOT), 811 1000, 18000); 812 if (ret == -ETIMEDOUT) 813 dev_err(dev, "reset timeout, int_status = 0x%x\n", reg); 814 815 return ret; 816 } 817 818 static int __fxls8962af_fifo_set_mode(struct fxls8962af_data *data, bool onoff) 819 { 820 int ret; 821 822 /* Enable watermark at max fifo size */ 823 ret = regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG2, 824 FXLS8962AF_BUF_CONFIG2_BUF_WMRK, 825 data->watermark); 826 if (ret) 827 return ret; 828 829 return regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG1, 830 FXLS8962AF_BC1_BUF_MODE_MASK, 831 FXLS8962AF_BC1_BUF_MODE_PREP(onoff)); 832 } 833 834 static int fxls8962af_buffer_preenable(struct iio_dev *indio_dev) 835 { 836 return fxls8962af_power_on(iio_priv(indio_dev)); 837 } 838 839 static int fxls8962af_buffer_postenable(struct iio_dev *indio_dev) 840 { 841 struct fxls8962af_data *data = iio_priv(indio_dev); 842 int ret; 843 844 fxls8962af_standby(data); 845 846 /* Enable buffer interrupt */ 847 ret = regmap_set_bits(data->regmap, FXLS8962AF_INT_EN, 848 FXLS8962AF_INT_EN_BUF_EN); 849 if (ret) 850 return ret; 851 852 ret = __fxls8962af_fifo_set_mode(data, true); 853 854 fxls8962af_active(data); 855 856 return ret; 857 } 858 859 static int fxls8962af_buffer_predisable(struct iio_dev *indio_dev) 860 { 861 struct fxls8962af_data *data = iio_priv(indio_dev); 862 int ret; 863 864 fxls8962af_standby(data); 865 866 /* Disable buffer interrupt */ 867 ret = regmap_clear_bits(data->regmap, FXLS8962AF_INT_EN, 868 FXLS8962AF_INT_EN_BUF_EN); 869 if (ret) 870 return ret; 871 872 ret = __fxls8962af_fifo_set_mode(data, false); 873 874 if (data->enable_event) 875 fxls8962af_active(data); 876 877 return ret; 878 } 879 880 static int fxls8962af_buffer_postdisable(struct iio_dev *indio_dev) 881 { 882 struct fxls8962af_data *data = iio_priv(indio_dev); 883 884 if (!data->enable_event) 885 fxls8962af_power_off(data); 886 887 return 0; 888 } 889 890 static const struct iio_buffer_setup_ops fxls8962af_buffer_ops = { 891 .preenable = fxls8962af_buffer_preenable, 892 .postenable = fxls8962af_buffer_postenable, 893 .predisable = fxls8962af_buffer_predisable, 894 .postdisable = fxls8962af_buffer_postdisable, 895 }; 896 897 static int fxls8962af_i2c_raw_read_errata3(struct fxls8962af_data *data, 898 u16 *buffer, int samples, 899 int sample_length) 900 { 901 int i, ret; 902 903 for (i = 0; i < samples; i++) { 904 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, 905 &buffer[i * 3], sample_length); 906 if (ret) 907 return ret; 908 } 909 910 return 0; 911 } 912 913 static int fxls8962af_fifo_transfer(struct fxls8962af_data *data, 914 u16 *buffer, int samples) 915 { 916 struct device *dev = regmap_get_device(data->regmap); 917 int sample_length = 3 * sizeof(*buffer); 918 int total_length = samples * sample_length; 919 int ret; 920 921 if (i2c_verify_client(dev) && 922 data->chip_info->chip_id == FXLS8962AF_DEVICE_ID) 923 /* 924 * Due to errata bug (only applicable on fxls8962af): 925 * E3: FIFO burst read operation error using I2C interface 926 * We have to avoid burst reads on I2C.. 927 */ 928 ret = fxls8962af_i2c_raw_read_errata3(data, buffer, samples, 929 sample_length); 930 else 931 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, buffer, 932 total_length); 933 934 if (ret) 935 dev_err(dev, "Error transferring data from fifo: %d\n", ret); 936 937 return ret; 938 } 939 940 static int fxls8962af_fifo_flush(struct iio_dev *indio_dev) 941 { 942 struct fxls8962af_data *data = iio_priv(indio_dev); 943 struct device *dev = regmap_get_device(data->regmap); 944 u16 buffer[FXLS8962AF_FIFO_LENGTH * 3]; 945 uint64_t sample_period; 946 unsigned int reg; 947 int64_t tstamp; 948 int ret, i; 949 u8 count; 950 951 ret = regmap_read(data->regmap, FXLS8962AF_BUF_STATUS, ®); 952 if (ret) 953 return ret; 954 955 if (reg & FXLS8962AF_BUF_STATUS_BUF_OVF) { 956 dev_err(dev, "Buffer overflow"); 957 return -EOVERFLOW; 958 } 959 960 count = reg & FXLS8962AF_BUF_STATUS_BUF_CNT; 961 if (!count) 962 return 0; 963 964 data->old_timestamp = data->timestamp; 965 data->timestamp = iio_get_time_ns(indio_dev); 966 967 /* 968 * Approximate timestamps for each of the sample based on the sampling, 969 * frequency, timestamp for last sample and number of samples. 970 */ 971 sample_period = (data->timestamp - data->old_timestamp); 972 do_div(sample_period, count); 973 tstamp = data->timestamp - (count - 1) * sample_period; 974 975 ret = fxls8962af_fifo_transfer(data, buffer, count); 976 if (ret) 977 return ret; 978 979 /* Demux hw FIFO into kfifo. */ 980 for (i = 0; i < count; i++) { 981 int j, bit; 982 983 j = 0; 984 iio_for_each_active_channel(indio_dev, bit) { 985 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit], 986 sizeof(data->scan.channels[0])); 987 } 988 989 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, 990 tstamp); 991 992 tstamp += sample_period; 993 } 994 995 return count; 996 } 997 998 static int fxls8962af_event_interrupt(struct iio_dev *indio_dev) 999 { 1000 struct fxls8962af_data *data = iio_priv(indio_dev); 1001 s64 ts = iio_get_time_ns(indio_dev); 1002 unsigned int reg; 1003 u64 ev_code; 1004 int ret; 1005 1006 ret = regmap_read(data->regmap, FXLS8962AF_SDCD_INT_SRC1, ®); 1007 if (ret) 1008 return ret; 1009 1010 if (reg & FXLS8962AF_SDCD_INT_SRC1_X_OT) { 1011 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_X_POL ? 1012 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1013 iio_push_event(indio_dev, 1014 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1015 IIO_EV_TYPE_THRESH, ev_code), ts); 1016 } 1017 1018 if (reg & FXLS8962AF_SDCD_INT_SRC1_Y_OT) { 1019 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Y_POL ? 1020 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1021 iio_push_event(indio_dev, 1022 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1023 IIO_EV_TYPE_THRESH, ev_code), ts); 1024 } 1025 1026 if (reg & FXLS8962AF_SDCD_INT_SRC1_Z_OT) { 1027 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Z_POL ? 1028 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1029 iio_push_event(indio_dev, 1030 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1031 IIO_EV_TYPE_THRESH, ev_code), ts); 1032 } 1033 1034 return 0; 1035 } 1036 1037 static irqreturn_t fxls8962af_interrupt(int irq, void *p) 1038 { 1039 struct iio_dev *indio_dev = p; 1040 struct fxls8962af_data *data = iio_priv(indio_dev); 1041 unsigned int reg; 1042 int ret; 1043 1044 ret = regmap_read(data->regmap, FXLS8962AF_INT_STATUS, ®); 1045 if (ret) 1046 return IRQ_NONE; 1047 1048 if (reg & FXLS8962AF_INT_STATUS_SRC_BUF) { 1049 ret = fxls8962af_fifo_flush(indio_dev); 1050 if (ret < 0) 1051 return IRQ_NONE; 1052 1053 return IRQ_HANDLED; 1054 } 1055 1056 if (reg & FXLS8962AF_INT_STATUS_SRC_SDCD_OT) { 1057 ret = fxls8962af_event_interrupt(indio_dev); 1058 if (ret < 0) 1059 return IRQ_NONE; 1060 1061 return IRQ_HANDLED; 1062 } 1063 1064 return IRQ_NONE; 1065 } 1066 1067 static void fxls8962af_pm_disable(void *dev_ptr) 1068 { 1069 struct device *dev = dev_ptr; 1070 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1071 1072 pm_runtime_disable(dev); 1073 pm_runtime_set_suspended(dev); 1074 pm_runtime_put_noidle(dev); 1075 1076 fxls8962af_standby(iio_priv(indio_dev)); 1077 } 1078 1079 static void fxls8962af_get_irq(struct device *dev, 1080 enum fxls8962af_int_pin *pin) 1081 { 1082 int irq; 1083 1084 irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT2"); 1085 if (irq > 0) { 1086 *pin = FXLS8962AF_PIN_INT2; 1087 return; 1088 } 1089 1090 *pin = FXLS8962AF_PIN_INT1; 1091 } 1092 1093 static int fxls8962af_irq_setup(struct iio_dev *indio_dev, int irq) 1094 { 1095 struct fxls8962af_data *data = iio_priv(indio_dev); 1096 struct device *dev = regmap_get_device(data->regmap); 1097 unsigned long irq_type; 1098 bool irq_active_high; 1099 enum fxls8962af_int_pin int_pin; 1100 u8 int_pin_sel; 1101 int ret; 1102 1103 fxls8962af_get_irq(dev, &int_pin); 1104 switch (int_pin) { 1105 case FXLS8962AF_PIN_INT1: 1106 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT1; 1107 break; 1108 case FXLS8962AF_PIN_INT2: 1109 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT2; 1110 break; 1111 default: 1112 dev_err(dev, "unsupported int pin selected\n"); 1113 return -EINVAL; 1114 } 1115 1116 ret = regmap_update_bits(data->regmap, FXLS8962AF_INT_PIN_SEL, 1117 FXLS8962AF_INT_PIN_SEL_MASK, int_pin_sel); 1118 if (ret) 1119 return ret; 1120 1121 irq_type = irq_get_trigger_type(irq); 1122 switch (irq_type) { 1123 case IRQF_TRIGGER_HIGH: 1124 case IRQF_TRIGGER_RISING: 1125 irq_active_high = true; 1126 break; 1127 case IRQF_TRIGGER_LOW: 1128 case IRQF_TRIGGER_FALLING: 1129 irq_active_high = false; 1130 break; 1131 default: 1132 dev_info(dev, "mode %lx unsupported\n", irq_type); 1133 return -EINVAL; 1134 } 1135 1136 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4, 1137 FXLS8962AF_SC4_INT_POL_MASK, 1138 FXLS8962AF_SC4_INT_POL_PREP(irq_active_high)); 1139 if (ret) 1140 return ret; 1141 1142 if (device_property_read_bool(dev, "drive-open-drain")) { 1143 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4, 1144 FXLS8962AF_SC4_INT_PP_OD_MASK, 1145 FXLS8962AF_SC4_INT_PP_OD_PREP(1)); 1146 if (ret) 1147 return ret; 1148 1149 irq_type |= IRQF_SHARED; 1150 } 1151 1152 return devm_request_threaded_irq(dev, 1153 irq, 1154 NULL, fxls8962af_interrupt, 1155 irq_type | IRQF_ONESHOT, 1156 indio_dev->name, indio_dev); 1157 } 1158 1159 int fxls8962af_core_probe(struct device *dev, struct regmap *regmap, int irq) 1160 { 1161 struct fxls8962af_data *data; 1162 struct iio_dev *indio_dev; 1163 unsigned int reg; 1164 int ret, i; 1165 1166 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1167 if (!indio_dev) 1168 return -ENOMEM; 1169 1170 data = iio_priv(indio_dev); 1171 dev_set_drvdata(dev, indio_dev); 1172 data->regmap = regmap; 1173 data->irq = irq; 1174 1175 ret = iio_read_mount_matrix(dev, &data->orientation); 1176 if (ret) 1177 return ret; 1178 1179 ret = devm_regulator_get_enable(dev, "vdd"); 1180 if (ret) 1181 return dev_err_probe(dev, ret, 1182 "Failed to get vdd regulator\n"); 1183 1184 ret = regmap_read(data->regmap, FXLS8962AF_WHO_AM_I, ®); 1185 if (ret) 1186 return ret; 1187 1188 for (i = 0; i < ARRAY_SIZE(fxls_chip_info_table); i++) { 1189 if (fxls_chip_info_table[i].chip_id == reg) { 1190 data->chip_info = &fxls_chip_info_table[i]; 1191 break; 1192 } 1193 } 1194 if (i == ARRAY_SIZE(fxls_chip_info_table)) { 1195 dev_err(dev, "failed to match device in table\n"); 1196 return -ENXIO; 1197 } 1198 1199 indio_dev->channels = data->chip_info->channels; 1200 indio_dev->num_channels = data->chip_info->num_channels; 1201 indio_dev->name = data->chip_info->name; 1202 indio_dev->info = &fxls8962af_info; 1203 indio_dev->modes = INDIO_DIRECT_MODE; 1204 1205 ret = fxls8962af_reset(data); 1206 if (ret) 1207 return ret; 1208 1209 if (irq) { 1210 ret = fxls8962af_irq_setup(indio_dev, irq); 1211 if (ret) 1212 return ret; 1213 1214 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, 1215 &fxls8962af_buffer_ops); 1216 if (ret) 1217 return ret; 1218 } 1219 1220 ret = pm_runtime_set_active(dev); 1221 if (ret) 1222 return ret; 1223 1224 pm_runtime_enable(dev); 1225 pm_runtime_set_autosuspend_delay(dev, FXLS8962AF_AUTO_SUSPEND_DELAY_MS); 1226 pm_runtime_use_autosuspend(dev); 1227 1228 ret = devm_add_action_or_reset(dev, fxls8962af_pm_disable, dev); 1229 if (ret) 1230 return ret; 1231 1232 if (device_property_read_bool(dev, "wakeup-source")) 1233 device_init_wakeup(dev, true); 1234 1235 return devm_iio_device_register(dev, indio_dev); 1236 } 1237 EXPORT_SYMBOL_NS_GPL(fxls8962af_core_probe, "IIO_FXLS8962AF"); 1238 1239 static int fxls8962af_runtime_suspend(struct device *dev) 1240 { 1241 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev)); 1242 int ret; 1243 1244 ret = fxls8962af_standby(data); 1245 if (ret) { 1246 dev_err(dev, "powering off device failed\n"); 1247 return ret; 1248 } 1249 1250 return 0; 1251 } 1252 1253 static int fxls8962af_runtime_resume(struct device *dev) 1254 { 1255 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev)); 1256 1257 return fxls8962af_active(data); 1258 } 1259 1260 static int fxls8962af_suspend(struct device *dev) 1261 { 1262 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1263 struct fxls8962af_data *data = iio_priv(indio_dev); 1264 1265 if (device_may_wakeup(dev) && data->enable_event) { 1266 enable_irq_wake(data->irq); 1267 1268 /* 1269 * Disable buffer, as the buffer is so small the device will wake 1270 * almost immediately. 1271 */ 1272 if (iio_buffer_enabled(indio_dev)) 1273 fxls8962af_buffer_predisable(indio_dev); 1274 } else { 1275 fxls8962af_runtime_suspend(dev); 1276 } 1277 1278 return 0; 1279 } 1280 1281 static int fxls8962af_resume(struct device *dev) 1282 { 1283 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1284 struct fxls8962af_data *data = iio_priv(indio_dev); 1285 1286 if (device_may_wakeup(dev) && data->enable_event) { 1287 disable_irq_wake(data->irq); 1288 1289 if (iio_buffer_enabled(indio_dev)) 1290 fxls8962af_buffer_postenable(indio_dev); 1291 } else { 1292 fxls8962af_runtime_resume(dev); 1293 } 1294 1295 return 0; 1296 } 1297 1298 EXPORT_NS_GPL_DEV_PM_OPS(fxls8962af_pm_ops, IIO_FXLS8962AF) = { 1299 SYSTEM_SLEEP_PM_OPS(fxls8962af_suspend, fxls8962af_resume) 1300 RUNTIME_PM_OPS(fxls8962af_runtime_suspend, fxls8962af_runtime_resume, NULL) 1301 }; 1302 1303 MODULE_AUTHOR("Sean Nyekjaer <sean@geanix.com>"); 1304 MODULE_DESCRIPTION("NXP FXLS8962AF/FXLS8964AF accelerometer driver"); 1305 MODULE_LICENSE("GPL v2"); 1306