1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 3-axis accelerometer driver supporting many Bosch-Sensortec chips 4 * Copyright (c) 2014, Intel Corporation. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/delay.h> 11 #include <linux/slab.h> 12 #include <linux/acpi.h> 13 #include <linux/pm.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/property.h> 16 #include <linux/iio/iio.h> 17 #include <linux/iio/sysfs.h> 18 #include <linux/iio/buffer.h> 19 #include <linux/iio/events.h> 20 #include <linux/iio/trigger.h> 21 #include <linux/iio/trigger_consumer.h> 22 #include <linux/iio/triggered_buffer.h> 23 #include <linux/regmap.h> 24 #include <linux/regulator/consumer.h> 25 26 #include "bmc150-accel.h" 27 28 #define BMC150_ACCEL_REG_CHIP_ID 0x00 29 30 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B 31 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07 32 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0) 33 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1) 34 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2) 35 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3) 36 37 #define BMC150_ACCEL_REG_PMU_LPW 0x11 38 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0 39 #define BMC150_ACCEL_PMU_MODE_SHIFT 5 40 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17 41 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1 42 43 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F 44 45 #define BMC150_ACCEL_DEF_RANGE_2G 0x03 46 #define BMC150_ACCEL_DEF_RANGE_4G 0x05 47 #define BMC150_ACCEL_DEF_RANGE_8G 0x08 48 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C 49 50 /* Default BW: 125Hz */ 51 #define BMC150_ACCEL_REG_PMU_BW 0x10 52 #define BMC150_ACCEL_DEF_BW 125 53 54 #define BMC150_ACCEL_REG_RESET 0x14 55 #define BMC150_ACCEL_RESET_VAL 0xB6 56 57 #define BMC150_ACCEL_REG_INT_MAP_0 0x19 58 #define BMC150_ACCEL_INT_MAP_0_BIT_INT1_SLOPE BIT(2) 59 60 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A 61 #define BMC150_ACCEL_INT_MAP_1_BIT_INT1_DATA BIT(0) 62 #define BMC150_ACCEL_INT_MAP_1_BIT_INT1_FWM BIT(1) 63 #define BMC150_ACCEL_INT_MAP_1_BIT_INT1_FFULL BIT(2) 64 #define BMC150_ACCEL_INT_MAP_1_BIT_INT2_FFULL BIT(5) 65 #define BMC150_ACCEL_INT_MAP_1_BIT_INT2_FWM BIT(6) 66 #define BMC150_ACCEL_INT_MAP_1_BIT_INT2_DATA BIT(7) 67 68 #define BMC150_ACCEL_REG_INT_MAP_2 0x1B 69 #define BMC150_ACCEL_INT_MAP_2_BIT_INT2_SLOPE BIT(2) 70 71 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21 72 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80 73 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F 74 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00 75 76 #define BMC150_ACCEL_REG_INT_EN_0 0x16 77 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0) 78 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1) 79 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2) 80 81 #define BMC150_ACCEL_REG_INT_EN_1 0x17 82 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4) 83 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5) 84 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6) 85 86 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20 87 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0) 88 #define BMC150_ACCEL_INT_OUT_CTRL_INT2_LVL BIT(2) 89 90 #define BMC150_ACCEL_REG_INT_5 0x27 91 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03 92 93 #define BMC150_ACCEL_REG_INT_6 0x28 94 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF 95 96 /* Slope duration in terms of number of samples */ 97 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1 98 /* in terms of multiples of g's/LSB, based on range */ 99 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1 100 101 #define BMC150_ACCEL_REG_XOUT_L 0x02 102 103 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100 104 105 /* Sleep Duration values */ 106 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05 107 #define BMC150_ACCEL_SLEEP_1_MS 0x06 108 #define BMC150_ACCEL_SLEEP_2_MS 0x07 109 #define BMC150_ACCEL_SLEEP_4_MS 0x08 110 #define BMC150_ACCEL_SLEEP_6_MS 0x09 111 #define BMC150_ACCEL_SLEEP_10_MS 0x0A 112 #define BMC150_ACCEL_SLEEP_25_MS 0x0B 113 #define BMC150_ACCEL_SLEEP_50_MS 0x0C 114 #define BMC150_ACCEL_SLEEP_100_MS 0x0D 115 #define BMC150_ACCEL_SLEEP_500_MS 0x0E 116 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F 117 118 #define BMC150_ACCEL_REG_TEMP 0x08 119 #define BMC150_ACCEL_TEMP_CENTER_VAL 23 120 121 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2)) 122 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000 123 124 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E 125 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30 126 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E 127 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F 128 #define BMC150_ACCEL_FIFO_LENGTH 32 129 130 enum bmc150_accel_axis { 131 AXIS_X, 132 AXIS_Y, 133 AXIS_Z, 134 AXIS_MAX, 135 }; 136 137 enum bmc150_power_modes { 138 BMC150_ACCEL_SLEEP_MODE_NORMAL, 139 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 140 BMC150_ACCEL_SLEEP_MODE_LPM, 141 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04, 142 }; 143 144 struct bmc150_scale_info { 145 int scale; 146 u8 reg_range; 147 }; 148 149 struct bmc150_accel_chip_info { 150 const char *name; 151 u8 chip_id; 152 const struct iio_chan_spec *channels; 153 int num_channels; 154 const struct bmc150_scale_info scale_table[4]; 155 }; 156 157 static const struct { 158 int val; 159 int val2; 160 u8 bw_bits; 161 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08}, 162 {31, 260000, 0x09}, 163 {62, 500000, 0x0A}, 164 {125, 0, 0x0B}, 165 {250, 0, 0x0C}, 166 {500, 0, 0x0D}, 167 {1000, 0, 0x0E}, 168 {2000, 0, 0x0F} }; 169 170 static __maybe_unused const struct { 171 int bw_bits; 172 int msec; 173 } bmc150_accel_sample_upd_time[] = { {0x08, 64}, 174 {0x09, 32}, 175 {0x0A, 16}, 176 {0x0B, 8}, 177 {0x0C, 4}, 178 {0x0D, 2}, 179 {0x0E, 1}, 180 {0x0F, 1} }; 181 182 static const struct { 183 int sleep_dur; 184 u8 reg_value; 185 } bmc150_accel_sleep_value_table[] = { {0, 0}, 186 {500, BMC150_ACCEL_SLEEP_500_MICRO}, 187 {1000, BMC150_ACCEL_SLEEP_1_MS}, 188 {2000, BMC150_ACCEL_SLEEP_2_MS}, 189 {4000, BMC150_ACCEL_SLEEP_4_MS}, 190 {6000, BMC150_ACCEL_SLEEP_6_MS}, 191 {10000, BMC150_ACCEL_SLEEP_10_MS}, 192 {25000, BMC150_ACCEL_SLEEP_25_MS}, 193 {50000, BMC150_ACCEL_SLEEP_50_MS}, 194 {100000, BMC150_ACCEL_SLEEP_100_MS}, 195 {500000, BMC150_ACCEL_SLEEP_500_MS}, 196 {1000000, BMC150_ACCEL_SLEEP_1_SEC} }; 197 198 const struct regmap_config bmc150_regmap_conf = { 199 .reg_bits = 8, 200 .val_bits = 8, 201 .max_register = 0x3f, 202 }; 203 EXPORT_SYMBOL_NS_GPL(bmc150_regmap_conf, "IIO_BMC150"); 204 205 static int bmc150_accel_set_mode(struct bmc150_accel_data *data, 206 enum bmc150_power_modes mode, 207 int dur_us) 208 { 209 struct device *dev = regmap_get_device(data->regmap); 210 int i; 211 int ret; 212 u8 lpw_bits; 213 int dur_val = -1; 214 215 if (dur_us > 0) { 216 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table); 217 ++i) { 218 if (bmc150_accel_sleep_value_table[i].sleep_dur == 219 dur_us) 220 dur_val = 221 bmc150_accel_sleep_value_table[i].reg_value; 222 } 223 } else { 224 dur_val = 0; 225 } 226 227 if (dur_val < 0) 228 return -EINVAL; 229 230 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT; 231 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT); 232 233 dev_dbg(dev, "Set Mode bits %x\n", lpw_bits); 234 235 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits); 236 if (ret < 0) { 237 dev_err(dev, "Error writing reg_pmu_lpw\n"); 238 return ret; 239 } 240 241 return 0; 242 } 243 244 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val, 245 int val2) 246 { 247 int i; 248 int ret; 249 250 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { 251 if (bmc150_accel_samp_freq_table[i].val == val && 252 bmc150_accel_samp_freq_table[i].val2 == val2) { 253 ret = regmap_write(data->regmap, 254 BMC150_ACCEL_REG_PMU_BW, 255 bmc150_accel_samp_freq_table[i].bw_bits); 256 if (ret < 0) 257 return ret; 258 259 data->bw_bits = 260 bmc150_accel_samp_freq_table[i].bw_bits; 261 return 0; 262 } 263 } 264 265 return -EINVAL; 266 } 267 268 static int bmc150_accel_update_slope(struct bmc150_accel_data *data) 269 { 270 struct device *dev = regmap_get_device(data->regmap); 271 int ret; 272 273 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6, 274 data->slope_thres); 275 if (ret < 0) { 276 dev_err(dev, "Error writing reg_int_6\n"); 277 return ret; 278 } 279 280 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5, 281 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur); 282 if (ret < 0) { 283 dev_err(dev, "Error updating reg_int_5\n"); 284 return ret; 285 } 286 287 dev_dbg(dev, "%x %x\n", data->slope_thres, data->slope_dur); 288 289 return ret; 290 } 291 292 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t, 293 bool state) 294 { 295 if (state) 296 return bmc150_accel_update_slope(t->data); 297 298 return 0; 299 } 300 301 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val, 302 int *val2) 303 { 304 int i; 305 306 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { 307 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) { 308 *val = bmc150_accel_samp_freq_table[i].val; 309 *val2 = bmc150_accel_samp_freq_table[i].val2; 310 return IIO_VAL_INT_PLUS_MICRO; 311 } 312 } 313 314 return -EINVAL; 315 } 316 317 #ifdef CONFIG_PM 318 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data) 319 { 320 int i; 321 322 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) { 323 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits) 324 return bmc150_accel_sample_upd_time[i].msec; 325 } 326 327 return BMC150_ACCEL_MAX_STARTUP_TIME_MS; 328 } 329 330 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) 331 { 332 struct device *dev = regmap_get_device(data->regmap); 333 int ret; 334 335 if (on) 336 ret = pm_runtime_resume_and_get(dev); 337 else 338 ret = pm_runtime_put_autosuspend(dev); 339 if (ret < 0) { 340 dev_err(dev, 341 "Failed: %s for %d\n", __func__, on); 342 return ret; 343 } 344 345 return 0; 346 } 347 #else 348 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) 349 { 350 return 0; 351 } 352 #endif 353 354 #ifdef CONFIG_ACPI 355 /* 356 * Support for getting accelerometer information from BOSC0200 ACPI nodes. 357 * 358 * There are 2 variants of the BOSC0200 ACPI node. Some 2-in-1s with 360 degree 359 * hinges declare 2 I2C ACPI-resources for 2 accelerometers, 1 in the display 360 * and 1 in the base of the 2-in-1. On these 2-in-1s the ROMS ACPI object 361 * contains the mount-matrix for the sensor in the display and ROMK contains 362 * the mount-matrix for the sensor in the base. On devices using a single 363 * sensor there is a ROTM ACPI object which contains the mount-matrix. 364 * 365 * Here is an incomplete list of devices known to use 1 of these setups: 366 * 367 * Yoga devices with 2 accelerometers using ROMS + ROMK for the mount-matrices: 368 * Lenovo Thinkpad Yoga 11e 3th gen 369 * Lenovo Thinkpad Yoga 11e 4th gen 370 * 371 * Tablets using a single accelerometer using ROTM for the mount-matrix: 372 * Chuwi Hi8 Pro (CWI513) 373 * Chuwi Vi8 Plus (CWI519) 374 * Chuwi Hi13 375 * Irbis TW90 376 * Jumper EZpad mini 3 377 * Onda V80 plus 378 * Predia Basic Tablet 379 */ 380 static bool bmc150_apply_bosc0200_acpi_orientation(struct device *dev, 381 struct iio_mount_matrix *orientation) 382 { 383 struct iio_dev *indio_dev = dev_get_drvdata(dev); 384 acpi_handle handle = ACPI_HANDLE(dev); 385 char *name, *alt_name, *label; 386 387 if (strcmp(dev_name(dev), "i2c-BOSC0200:base") == 0) { 388 alt_name = "ROMK"; 389 label = "accel-base"; 390 } else { 391 alt_name = "ROMS"; 392 label = "accel-display"; 393 } 394 395 if (acpi_has_method(handle, "ROTM")) { 396 name = "ROTM"; 397 } else if (acpi_has_method(handle, alt_name)) { 398 name = alt_name; 399 indio_dev->label = label; 400 } else { 401 return false; 402 } 403 404 return iio_read_acpi_mount_matrix(dev, orientation, name); 405 } 406 407 static bool bmc150_apply_dual250e_acpi_orientation(struct device *dev, 408 struct iio_mount_matrix *orientation) 409 { 410 struct iio_dev *indio_dev = dev_get_drvdata(dev); 411 412 if (strcmp(dev_name(dev), "i2c-DUAL250E:base") == 0) 413 indio_dev->label = "accel-base"; 414 else 415 indio_dev->label = "accel-display"; 416 417 return false; /* DUAL250E fwnodes have no mount matrix info */ 418 } 419 420 static bool bmc150_apply_acpi_orientation(struct device *dev, 421 struct iio_mount_matrix *orientation) 422 { 423 struct acpi_device *adev = ACPI_COMPANION(dev); 424 425 if (adev && acpi_dev_hid_uid_match(adev, "BOSC0200", NULL)) 426 return bmc150_apply_bosc0200_acpi_orientation(dev, orientation); 427 428 if (adev && acpi_dev_hid_uid_match(adev, "DUAL250E", NULL)) 429 return bmc150_apply_dual250e_acpi_orientation(dev, orientation); 430 431 return false; 432 } 433 #else 434 static bool bmc150_apply_acpi_orientation(struct device *dev, 435 struct iio_mount_matrix *orientation) 436 { 437 return false; 438 } 439 #endif 440 441 struct bmc150_accel_interrupt_info { 442 u8 map_reg; 443 u8 map_bitmask; 444 u8 en_reg; 445 u8 en_bitmask; 446 }; 447 448 static const struct bmc150_accel_interrupt_info 449 bmc150_accel_interrupts_int1[BMC150_ACCEL_INTERRUPTS] = { 450 { /* data ready interrupt */ 451 .map_reg = BMC150_ACCEL_REG_INT_MAP_1, 452 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_INT1_DATA, 453 .en_reg = BMC150_ACCEL_REG_INT_EN_1, 454 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN, 455 }, 456 { /* motion interrupt */ 457 .map_reg = BMC150_ACCEL_REG_INT_MAP_0, 458 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_INT1_SLOPE, 459 .en_reg = BMC150_ACCEL_REG_INT_EN_0, 460 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X | 461 BMC150_ACCEL_INT_EN_BIT_SLP_Y | 462 BMC150_ACCEL_INT_EN_BIT_SLP_Z 463 }, 464 { /* fifo watermark interrupt */ 465 .map_reg = BMC150_ACCEL_REG_INT_MAP_1, 466 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_INT1_FWM, 467 .en_reg = BMC150_ACCEL_REG_INT_EN_1, 468 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN, 469 }, 470 }; 471 472 static const struct bmc150_accel_interrupt_info 473 bmc150_accel_interrupts_int2[BMC150_ACCEL_INTERRUPTS] = { 474 { /* data ready interrupt */ 475 .map_reg = BMC150_ACCEL_REG_INT_MAP_1, 476 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_INT2_DATA, 477 .en_reg = BMC150_ACCEL_REG_INT_EN_1, 478 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN, 479 }, 480 { /* motion interrupt */ 481 .map_reg = BMC150_ACCEL_REG_INT_MAP_2, 482 .map_bitmask = BMC150_ACCEL_INT_MAP_2_BIT_INT2_SLOPE, 483 .en_reg = BMC150_ACCEL_REG_INT_EN_0, 484 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X | 485 BMC150_ACCEL_INT_EN_BIT_SLP_Y | 486 BMC150_ACCEL_INT_EN_BIT_SLP_Z 487 }, 488 { /* fifo watermark interrupt */ 489 .map_reg = BMC150_ACCEL_REG_INT_MAP_1, 490 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_INT2_FWM, 491 .en_reg = BMC150_ACCEL_REG_INT_EN_1, 492 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN, 493 }, 494 }; 495 496 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev, 497 struct bmc150_accel_data *data, int irq) 498 { 499 const struct bmc150_accel_interrupt_info *irq_info = NULL; 500 struct device *dev = regmap_get_device(data->regmap); 501 int i; 502 503 /* 504 * For now we map all interrupts to the same output pin. 505 * However, some boards may have just INT2 (and not INT1) connected, 506 * so we try to detect which IRQ it is based on the interrupt-names. 507 * Without interrupt-names, we assume the irq belongs to INT1. 508 */ 509 irq_info = bmc150_accel_interrupts_int1; 510 if (data->type == BOSCH_BMC156 || 511 irq == fwnode_irq_get_byname(dev_fwnode(dev), "INT2")) 512 irq_info = bmc150_accel_interrupts_int2; 513 514 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++) 515 data->interrupts[i].info = &irq_info[i]; 516 } 517 518 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i, 519 bool state) 520 { 521 struct device *dev = regmap_get_device(data->regmap); 522 struct bmc150_accel_interrupt *intr = &data->interrupts[i]; 523 const struct bmc150_accel_interrupt_info *info = intr->info; 524 int ret; 525 526 if (state) { 527 if (atomic_inc_return(&intr->users) > 1) 528 return 0; 529 } else { 530 if (atomic_dec_return(&intr->users) > 0) 531 return 0; 532 } 533 534 /* 535 * We will expect the enable and disable to do operation in reverse 536 * order. This will happen here anyway, as our resume operation uses 537 * sync mode runtime pm calls. The suspend operation will be delayed 538 * by autosuspend delay. 539 * So the disable operation will still happen in reverse order of 540 * enable operation. When runtime pm is disabled the mode is always on, 541 * so sequence doesn't matter. 542 */ 543 ret = bmc150_accel_set_power_state(data, state); 544 if (ret < 0) 545 return ret; 546 547 /* map the interrupt to the appropriate pins */ 548 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask, 549 (state ? info->map_bitmask : 0)); 550 if (ret < 0) { 551 dev_err(dev, "Error updating reg_int_map\n"); 552 goto out_fix_power_state; 553 } 554 555 /* enable/disable the interrupt */ 556 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask, 557 (state ? info->en_bitmask : 0)); 558 if (ret < 0) { 559 dev_err(dev, "Error updating reg_int_en\n"); 560 goto out_fix_power_state; 561 } 562 563 return 0; 564 565 out_fix_power_state: 566 bmc150_accel_set_power_state(data, false); 567 return ret; 568 } 569 570 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val) 571 { 572 struct device *dev = regmap_get_device(data->regmap); 573 int ret, i; 574 575 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) { 576 if (data->chip_info->scale_table[i].scale == val) { 577 ret = regmap_write(data->regmap, 578 BMC150_ACCEL_REG_PMU_RANGE, 579 data->chip_info->scale_table[i].reg_range); 580 if (ret < 0) { 581 dev_err(dev, "Error writing pmu_range\n"); 582 return ret; 583 } 584 585 data->range = data->chip_info->scale_table[i].reg_range; 586 return 0; 587 } 588 } 589 590 return -EINVAL; 591 } 592 593 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val) 594 { 595 struct device *dev = regmap_get_device(data->regmap); 596 int ret; 597 unsigned int value; 598 599 mutex_lock(&data->mutex); 600 601 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value); 602 if (ret < 0) { 603 dev_err(dev, "Error reading reg_temp\n"); 604 mutex_unlock(&data->mutex); 605 return ret; 606 } 607 *val = sign_extend32(value, 7); 608 609 mutex_unlock(&data->mutex); 610 611 return IIO_VAL_INT; 612 } 613 614 static int bmc150_accel_get_axis(struct bmc150_accel_data *data, 615 struct iio_chan_spec const *chan, 616 int *val) 617 { 618 struct device *dev = regmap_get_device(data->regmap); 619 int ret; 620 int axis = chan->scan_index; 621 __le16 raw_val; 622 623 mutex_lock(&data->mutex); 624 ret = bmc150_accel_set_power_state(data, true); 625 if (ret < 0) { 626 mutex_unlock(&data->mutex); 627 return ret; 628 } 629 630 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis), 631 &raw_val, sizeof(raw_val)); 632 if (ret < 0) { 633 dev_err(dev, "Error reading axis %d\n", axis); 634 bmc150_accel_set_power_state(data, false); 635 mutex_unlock(&data->mutex); 636 return ret; 637 } 638 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift, 639 chan->scan_type.realbits - 1); 640 ret = bmc150_accel_set_power_state(data, false); 641 mutex_unlock(&data->mutex); 642 if (ret < 0) 643 return ret; 644 645 return IIO_VAL_INT; 646 } 647 648 static int bmc150_accel_read_raw(struct iio_dev *indio_dev, 649 struct iio_chan_spec const *chan, 650 int *val, int *val2, long mask) 651 { 652 struct bmc150_accel_data *data = iio_priv(indio_dev); 653 int ret; 654 655 switch (mask) { 656 case IIO_CHAN_INFO_RAW: 657 switch (chan->type) { 658 case IIO_TEMP: 659 return bmc150_accel_get_temp(data, val); 660 case IIO_ACCEL: 661 if (iio_buffer_enabled(indio_dev)) 662 return -EBUSY; 663 else 664 return bmc150_accel_get_axis(data, chan, val); 665 default: 666 return -EINVAL; 667 } 668 case IIO_CHAN_INFO_OFFSET: 669 if (chan->type == IIO_TEMP) { 670 *val = BMC150_ACCEL_TEMP_CENTER_VAL; 671 return IIO_VAL_INT; 672 } else { 673 return -EINVAL; 674 } 675 case IIO_CHAN_INFO_SCALE: 676 *val = 0; 677 switch (chan->type) { 678 case IIO_TEMP: 679 *val2 = 500000; 680 return IIO_VAL_INT_PLUS_MICRO; 681 case IIO_ACCEL: 682 { 683 int i; 684 const struct bmc150_scale_info *si; 685 int st_size = ARRAY_SIZE(data->chip_info->scale_table); 686 687 for (i = 0; i < st_size; ++i) { 688 si = &data->chip_info->scale_table[i]; 689 if (si->reg_range == data->range) { 690 *val2 = si->scale; 691 return IIO_VAL_INT_PLUS_MICRO; 692 } 693 } 694 return -EINVAL; 695 } 696 default: 697 return -EINVAL; 698 } 699 case IIO_CHAN_INFO_SAMP_FREQ: 700 mutex_lock(&data->mutex); 701 ret = bmc150_accel_get_bw(data, val, val2); 702 mutex_unlock(&data->mutex); 703 return ret; 704 default: 705 return -EINVAL; 706 } 707 } 708 709 static int bmc150_accel_write_raw(struct iio_dev *indio_dev, 710 struct iio_chan_spec const *chan, 711 int val, int val2, long mask) 712 { 713 struct bmc150_accel_data *data = iio_priv(indio_dev); 714 int ret; 715 716 switch (mask) { 717 case IIO_CHAN_INFO_SAMP_FREQ: 718 mutex_lock(&data->mutex); 719 ret = bmc150_accel_set_bw(data, val, val2); 720 mutex_unlock(&data->mutex); 721 break; 722 case IIO_CHAN_INFO_SCALE: 723 if (val) 724 return -EINVAL; 725 726 mutex_lock(&data->mutex); 727 ret = bmc150_accel_set_scale(data, val2); 728 mutex_unlock(&data->mutex); 729 return ret; 730 default: 731 ret = -EINVAL; 732 } 733 734 return ret; 735 } 736 737 static int bmc150_accel_read_event(struct iio_dev *indio_dev, 738 const struct iio_chan_spec *chan, 739 enum iio_event_type type, 740 enum iio_event_direction dir, 741 enum iio_event_info info, 742 int *val, int *val2) 743 { 744 struct bmc150_accel_data *data = iio_priv(indio_dev); 745 746 *val2 = 0; 747 switch (info) { 748 case IIO_EV_INFO_VALUE: 749 *val = data->slope_thres; 750 break; 751 case IIO_EV_INFO_PERIOD: 752 *val = data->slope_dur; 753 break; 754 default: 755 return -EINVAL; 756 } 757 758 return IIO_VAL_INT; 759 } 760 761 static int bmc150_accel_write_event(struct iio_dev *indio_dev, 762 const struct iio_chan_spec *chan, 763 enum iio_event_type type, 764 enum iio_event_direction dir, 765 enum iio_event_info info, 766 int val, int val2) 767 { 768 struct bmc150_accel_data *data = iio_priv(indio_dev); 769 770 if (data->ev_enable_state) 771 return -EBUSY; 772 773 switch (info) { 774 case IIO_EV_INFO_VALUE: 775 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK; 776 break; 777 case IIO_EV_INFO_PERIOD: 778 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK; 779 break; 780 default: 781 return -EINVAL; 782 } 783 784 return 0; 785 } 786 787 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev, 788 const struct iio_chan_spec *chan, 789 enum iio_event_type type, 790 enum iio_event_direction dir) 791 { 792 struct bmc150_accel_data *data = iio_priv(indio_dev); 793 794 return data->ev_enable_state; 795 } 796 797 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev, 798 const struct iio_chan_spec *chan, 799 enum iio_event_type type, 800 enum iio_event_direction dir, 801 bool state) 802 { 803 struct bmc150_accel_data *data = iio_priv(indio_dev); 804 int ret; 805 806 if (state == data->ev_enable_state) 807 return 0; 808 809 mutex_lock(&data->mutex); 810 811 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION, 812 state); 813 if (ret < 0) { 814 mutex_unlock(&data->mutex); 815 return ret; 816 } 817 818 data->ev_enable_state = state; 819 mutex_unlock(&data->mutex); 820 821 return 0; 822 } 823 824 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev, 825 struct iio_trigger *trig) 826 { 827 struct bmc150_accel_data *data = iio_priv(indio_dev); 828 int i; 829 830 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 831 if (data->triggers[i].indio_trig == trig) 832 return 0; 833 } 834 835 return -EINVAL; 836 } 837 838 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev, 839 struct device_attribute *attr, 840 char *buf) 841 { 842 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 843 struct bmc150_accel_data *data = iio_priv(indio_dev); 844 int wm; 845 846 mutex_lock(&data->mutex); 847 wm = data->watermark; 848 mutex_unlock(&data->mutex); 849 850 return sprintf(buf, "%d\n", wm); 851 } 852 853 static ssize_t bmc150_accel_get_fifo_state(struct device *dev, 854 struct device_attribute *attr, 855 char *buf) 856 { 857 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 858 struct bmc150_accel_data *data = iio_priv(indio_dev); 859 bool state; 860 861 mutex_lock(&data->mutex); 862 state = data->fifo_mode; 863 mutex_unlock(&data->mutex); 864 865 return sprintf(buf, "%d\n", state); 866 } 867 868 static const struct iio_mount_matrix * 869 bmc150_accel_get_mount_matrix(const struct iio_dev *indio_dev, 870 const struct iio_chan_spec *chan) 871 { 872 struct bmc150_accel_data *data = iio_priv(indio_dev); 873 874 return &data->orientation; 875 } 876 877 static const struct iio_chan_spec_ext_info bmc150_accel_ext_info[] = { 878 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmc150_accel_get_mount_matrix), 879 { } 880 }; 881 882 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "1"); 883 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max, 884 __stringify(BMC150_ACCEL_FIFO_LENGTH)); 885 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO, 886 bmc150_accel_get_fifo_state, NULL, 0); 887 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO, 888 bmc150_accel_get_fifo_watermark, NULL, 0); 889 890 static const struct iio_dev_attr *bmc150_accel_fifo_attributes[] = { 891 &iio_dev_attr_hwfifo_watermark_min, 892 &iio_dev_attr_hwfifo_watermark_max, 893 &iio_dev_attr_hwfifo_watermark, 894 &iio_dev_attr_hwfifo_enabled, 895 NULL, 896 }; 897 898 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val) 899 { 900 struct bmc150_accel_data *data = iio_priv(indio_dev); 901 902 if (val > BMC150_ACCEL_FIFO_LENGTH) 903 val = BMC150_ACCEL_FIFO_LENGTH; 904 905 mutex_lock(&data->mutex); 906 data->watermark = val; 907 mutex_unlock(&data->mutex); 908 909 return 0; 910 } 911 912 /* 913 * We must read at least one full frame in one burst, otherwise the rest of the 914 * frame data is discarded. 915 */ 916 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data, 917 char *buffer, int samples) 918 { 919 struct device *dev = regmap_get_device(data->regmap); 920 int sample_length = 3 * 2; 921 int ret; 922 int total_length = samples * sample_length; 923 924 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA, 925 buffer, total_length); 926 if (ret) 927 dev_err(dev, 928 "Error transferring data from fifo: %d\n", ret); 929 930 return ret; 931 } 932 933 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev, 934 unsigned samples, bool irq) 935 { 936 struct bmc150_accel_data *data = iio_priv(indio_dev); 937 struct device *dev = regmap_get_device(data->regmap); 938 int ret, i; 939 u8 count; 940 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3]; 941 int64_t tstamp; 942 uint64_t sample_period; 943 unsigned int val; 944 945 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val); 946 if (ret < 0) { 947 dev_err(dev, "Error reading reg_fifo_status\n"); 948 return ret; 949 } 950 951 count = val & 0x7F; 952 953 if (!count) 954 return 0; 955 956 /* 957 * If we getting called from IRQ handler we know the stored timestamp is 958 * fairly accurate for the last stored sample. Otherwise, if we are 959 * called as a result of a read operation from userspace and hence 960 * before the watermark interrupt was triggered, take a timestamp 961 * now. We can fall anywhere in between two samples so the error in this 962 * case is at most one sample period. 963 */ 964 if (!irq) { 965 data->old_timestamp = data->timestamp; 966 data->timestamp = iio_get_time_ns(indio_dev); 967 } 968 969 /* 970 * Approximate timestamps for each of the sample based on the sampling 971 * frequency, timestamp for last sample and number of samples. 972 * 973 * Note that we can't use the current bandwidth settings to compute the 974 * sample period because the sample rate varies with the device 975 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That 976 * small variation adds when we store a large number of samples and 977 * creates significant jitter between the last and first samples in 978 * different batches (e.g. 32ms vs 21ms). 979 * 980 * To avoid this issue we compute the actual sample period ourselves 981 * based on the timestamp delta between the last two flush operations. 982 */ 983 sample_period = (data->timestamp - data->old_timestamp); 984 do_div(sample_period, count); 985 tstamp = data->timestamp - (count - 1) * sample_period; 986 987 if (samples && count > samples) 988 count = samples; 989 990 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count); 991 if (ret) 992 return ret; 993 994 /* 995 * Ideally we want the IIO core to handle the demux when running in fifo 996 * mode but not when running in triggered buffer mode. Unfortunately 997 * this does not seem to be possible, so stick with driver demux for 998 * now. 999 */ 1000 for (i = 0; i < count; i++) { 1001 int j, bit; 1002 1003 j = 0; 1004 iio_for_each_active_channel(indio_dev, bit) 1005 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit], 1006 sizeof(data->scan.channels[0])); 1007 1008 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, 1009 tstamp); 1010 1011 tstamp += sample_period; 1012 } 1013 1014 return count; 1015 } 1016 1017 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples) 1018 { 1019 struct bmc150_accel_data *data = iio_priv(indio_dev); 1020 int ret; 1021 1022 mutex_lock(&data->mutex); 1023 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false); 1024 mutex_unlock(&data->mutex); 1025 1026 return ret; 1027 } 1028 1029 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( 1030 "15.620000 31.260000 62.50000 125 250 500 1000 2000"); 1031 1032 static struct attribute *bmc150_accel_attributes[] = { 1033 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 1034 NULL, 1035 }; 1036 1037 static const struct attribute_group bmc150_accel_attrs_group = { 1038 .attrs = bmc150_accel_attributes, 1039 }; 1040 1041 static const struct iio_event_spec bmc150_accel_event = { 1042 .type = IIO_EV_TYPE_ROC, 1043 .dir = IIO_EV_DIR_EITHER, 1044 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 1045 BIT(IIO_EV_INFO_ENABLE) | 1046 BIT(IIO_EV_INFO_PERIOD) 1047 }; 1048 1049 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \ 1050 .type = IIO_ACCEL, \ 1051 .modified = 1, \ 1052 .channel2 = IIO_MOD_##_axis, \ 1053 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 1054 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 1055 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1056 .scan_index = AXIS_##_axis, \ 1057 .scan_type = { \ 1058 .sign = 's', \ 1059 .realbits = (bits), \ 1060 .storagebits = 16, \ 1061 .shift = 16 - (bits), \ 1062 .endianness = IIO_LE, \ 1063 }, \ 1064 .ext_info = bmc150_accel_ext_info, \ 1065 .event_spec = &bmc150_accel_event, \ 1066 .num_event_specs = 1 \ 1067 } 1068 1069 #define BMC150_ACCEL_CHANNELS(bits) { \ 1070 { \ 1071 .type = IIO_TEMP, \ 1072 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1073 BIT(IIO_CHAN_INFO_SCALE) | \ 1074 BIT(IIO_CHAN_INFO_OFFSET), \ 1075 .scan_index = -1, \ 1076 }, \ 1077 BMC150_ACCEL_CHANNEL(X, bits), \ 1078 BMC150_ACCEL_CHANNEL(Y, bits), \ 1079 BMC150_ACCEL_CHANNEL(Z, bits), \ 1080 IIO_CHAN_SOFT_TIMESTAMP(3), \ 1081 } 1082 1083 static const struct iio_chan_spec bma222e_accel_channels[] = 1084 BMC150_ACCEL_CHANNELS(8); 1085 static const struct iio_chan_spec bma250e_accel_channels[] = 1086 BMC150_ACCEL_CHANNELS(10); 1087 static const struct iio_chan_spec bmc150_accel_channels[] = 1088 BMC150_ACCEL_CHANNELS(12); 1089 static const struct iio_chan_spec bma280_accel_channels[] = 1090 BMC150_ACCEL_CHANNELS(14); 1091 1092 /* 1093 * The range for the Bosch sensors is typically +-2g/4g/8g/16g, distributed 1094 * over the amount of bits (see above). The scale table can be calculated using 1095 * (range / 2^bits) * g = (range / 2^bits) * 9.80665 m/s^2 1096 * e.g. for +-2g and 12 bits: (4 / 2^12) * 9.80665 m/s^2 = 0.0095768... m/s^2 1097 * Multiply 10^6 and round to get the values listed below. 1098 */ 1099 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = { 1100 { 1101 .name = "BMA222", 1102 .chip_id = 0x03, 1103 .channels = bma222e_accel_channels, 1104 .num_channels = ARRAY_SIZE(bma222e_accel_channels), 1105 .scale_table = { {153229, BMC150_ACCEL_DEF_RANGE_2G}, 1106 {306458, BMC150_ACCEL_DEF_RANGE_4G}, 1107 {612916, BMC150_ACCEL_DEF_RANGE_8G}, 1108 {1225831, BMC150_ACCEL_DEF_RANGE_16G} }, 1109 }, 1110 { 1111 .name = "BMA222E", 1112 .chip_id = 0xF8, 1113 .channels = bma222e_accel_channels, 1114 .num_channels = ARRAY_SIZE(bma222e_accel_channels), 1115 .scale_table = { {153229, BMC150_ACCEL_DEF_RANGE_2G}, 1116 {306458, BMC150_ACCEL_DEF_RANGE_4G}, 1117 {612916, BMC150_ACCEL_DEF_RANGE_8G}, 1118 {1225831, BMC150_ACCEL_DEF_RANGE_16G} }, 1119 }, 1120 { 1121 .name = "BMA250E", 1122 .chip_id = 0xF9, 1123 .channels = bma250e_accel_channels, 1124 .num_channels = ARRAY_SIZE(bma250e_accel_channels), 1125 .scale_table = { {38307, BMC150_ACCEL_DEF_RANGE_2G}, 1126 {76614, BMC150_ACCEL_DEF_RANGE_4G}, 1127 {153229, BMC150_ACCEL_DEF_RANGE_8G}, 1128 {306458, BMC150_ACCEL_DEF_RANGE_16G} }, 1129 }, 1130 { 1131 .name = "BMA253/BMA254/BMA255/BMC150/BMC156/BMI055", 1132 .chip_id = 0xFA, 1133 .channels = bmc150_accel_channels, 1134 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1135 .scale_table = { {9577, BMC150_ACCEL_DEF_RANGE_2G}, 1136 {19154, BMC150_ACCEL_DEF_RANGE_4G}, 1137 {38307, BMC150_ACCEL_DEF_RANGE_8G}, 1138 {76614, BMC150_ACCEL_DEF_RANGE_16G} }, 1139 }, 1140 { 1141 .name = "BMA280", 1142 .chip_id = 0xFB, 1143 .channels = bma280_accel_channels, 1144 .num_channels = ARRAY_SIZE(bma280_accel_channels), 1145 .scale_table = { {2394, BMC150_ACCEL_DEF_RANGE_2G}, 1146 {4788, BMC150_ACCEL_DEF_RANGE_4G}, 1147 {9577, BMC150_ACCEL_DEF_RANGE_8G}, 1148 {19154, BMC150_ACCEL_DEF_RANGE_16G} }, 1149 }, 1150 }; 1151 1152 static const struct iio_info bmc150_accel_info = { 1153 .attrs = &bmc150_accel_attrs_group, 1154 .read_raw = bmc150_accel_read_raw, 1155 .write_raw = bmc150_accel_write_raw, 1156 .read_event_value = bmc150_accel_read_event, 1157 .write_event_value = bmc150_accel_write_event, 1158 .write_event_config = bmc150_accel_write_event_config, 1159 .read_event_config = bmc150_accel_read_event_config, 1160 }; 1161 1162 static const struct iio_info bmc150_accel_info_fifo = { 1163 .attrs = &bmc150_accel_attrs_group, 1164 .read_raw = bmc150_accel_read_raw, 1165 .write_raw = bmc150_accel_write_raw, 1166 .read_event_value = bmc150_accel_read_event, 1167 .write_event_value = bmc150_accel_write_event, 1168 .write_event_config = bmc150_accel_write_event_config, 1169 .read_event_config = bmc150_accel_read_event_config, 1170 .validate_trigger = bmc150_accel_validate_trigger, 1171 .hwfifo_set_watermark = bmc150_accel_set_watermark, 1172 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush, 1173 }; 1174 1175 static const unsigned long bmc150_accel_scan_masks[] = { 1176 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 1177 0}; 1178 1179 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p) 1180 { 1181 struct iio_poll_func *pf = p; 1182 struct iio_dev *indio_dev = pf->indio_dev; 1183 struct bmc150_accel_data *data = iio_priv(indio_dev); 1184 int ret; 1185 1186 mutex_lock(&data->mutex); 1187 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L, 1188 data->buffer, AXIS_MAX * 2); 1189 mutex_unlock(&data->mutex); 1190 if (ret < 0) 1191 goto err_read; 1192 1193 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, 1194 pf->timestamp); 1195 err_read: 1196 iio_trigger_notify_done(indio_dev->trig); 1197 1198 return IRQ_HANDLED; 1199 } 1200 1201 static void bmc150_accel_trig_reen(struct iio_trigger *trig) 1202 { 1203 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); 1204 struct bmc150_accel_data *data = t->data; 1205 struct device *dev = regmap_get_device(data->regmap); 1206 int ret; 1207 1208 /* new data interrupts don't need ack */ 1209 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY]) 1210 return; 1211 1212 mutex_lock(&data->mutex); 1213 /* clear any latched interrupt */ 1214 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1215 BMC150_ACCEL_INT_MODE_LATCH_INT | 1216 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1217 mutex_unlock(&data->mutex); 1218 if (ret < 0) 1219 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1220 } 1221 1222 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig, 1223 bool state) 1224 { 1225 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); 1226 struct bmc150_accel_data *data = t->data; 1227 int ret; 1228 1229 mutex_lock(&data->mutex); 1230 1231 if (t->enabled == state) { 1232 mutex_unlock(&data->mutex); 1233 return 0; 1234 } 1235 1236 if (t->setup) { 1237 ret = t->setup(t, state); 1238 if (ret < 0) { 1239 mutex_unlock(&data->mutex); 1240 return ret; 1241 } 1242 } 1243 1244 ret = bmc150_accel_set_interrupt(data, t->intr, state); 1245 if (ret < 0) { 1246 mutex_unlock(&data->mutex); 1247 return ret; 1248 } 1249 1250 t->enabled = state; 1251 1252 mutex_unlock(&data->mutex); 1253 1254 return ret; 1255 } 1256 1257 static const struct iio_trigger_ops bmc150_accel_trigger_ops = { 1258 .set_trigger_state = bmc150_accel_trigger_set_state, 1259 .reenable = bmc150_accel_trig_reen, 1260 }; 1261 1262 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev) 1263 { 1264 struct bmc150_accel_data *data = iio_priv(indio_dev); 1265 struct device *dev = regmap_get_device(data->regmap); 1266 int dir; 1267 int ret; 1268 unsigned int val; 1269 1270 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val); 1271 if (ret < 0) { 1272 dev_err(dev, "Error reading reg_int_status_2\n"); 1273 return ret; 1274 } 1275 1276 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN) 1277 dir = IIO_EV_DIR_FALLING; 1278 else 1279 dir = IIO_EV_DIR_RISING; 1280 1281 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X) 1282 iio_push_event(indio_dev, 1283 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1284 0, 1285 IIO_MOD_X, 1286 IIO_EV_TYPE_ROC, 1287 dir), 1288 data->timestamp); 1289 1290 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y) 1291 iio_push_event(indio_dev, 1292 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1293 0, 1294 IIO_MOD_Y, 1295 IIO_EV_TYPE_ROC, 1296 dir), 1297 data->timestamp); 1298 1299 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z) 1300 iio_push_event(indio_dev, 1301 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1302 0, 1303 IIO_MOD_Z, 1304 IIO_EV_TYPE_ROC, 1305 dir), 1306 data->timestamp); 1307 1308 return ret; 1309 } 1310 1311 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private) 1312 { 1313 struct iio_dev *indio_dev = private; 1314 struct bmc150_accel_data *data = iio_priv(indio_dev); 1315 struct device *dev = regmap_get_device(data->regmap); 1316 bool ack = false; 1317 int ret; 1318 1319 mutex_lock(&data->mutex); 1320 1321 if (data->fifo_mode) { 1322 ret = __bmc150_accel_fifo_flush(indio_dev, 1323 BMC150_ACCEL_FIFO_LENGTH, true); 1324 if (ret > 0) 1325 ack = true; 1326 } 1327 1328 if (data->ev_enable_state) { 1329 ret = bmc150_accel_handle_roc_event(indio_dev); 1330 if (ret > 0) 1331 ack = true; 1332 } 1333 1334 if (ack) { 1335 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1336 BMC150_ACCEL_INT_MODE_LATCH_INT | 1337 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1338 if (ret) 1339 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1340 1341 ret = IRQ_HANDLED; 1342 } else { 1343 ret = IRQ_NONE; 1344 } 1345 1346 mutex_unlock(&data->mutex); 1347 1348 return ret; 1349 } 1350 1351 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private) 1352 { 1353 struct iio_dev *indio_dev = private; 1354 struct bmc150_accel_data *data = iio_priv(indio_dev); 1355 bool ack = false; 1356 int i; 1357 1358 data->old_timestamp = data->timestamp; 1359 data->timestamp = iio_get_time_ns(indio_dev); 1360 1361 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 1362 if (data->triggers[i].enabled) { 1363 iio_trigger_poll(data->triggers[i].indio_trig); 1364 ack = true; 1365 break; 1366 } 1367 } 1368 1369 if (data->ev_enable_state || data->fifo_mode) 1370 return IRQ_WAKE_THREAD; 1371 1372 if (ack) 1373 return IRQ_HANDLED; 1374 1375 return IRQ_NONE; 1376 } 1377 1378 static const struct { 1379 int intr; 1380 const char *name; 1381 int (*setup)(struct bmc150_accel_trigger *t, bool state); 1382 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = { 1383 { 1384 .intr = 0, 1385 .name = "%s-dev%d", 1386 }, 1387 { 1388 .intr = 1, 1389 .name = "%s-any-motion-dev%d", 1390 .setup = bmc150_accel_any_motion_setup, 1391 }, 1392 }; 1393 1394 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data, 1395 int from) 1396 { 1397 int i; 1398 1399 for (i = from; i >= 0; i--) { 1400 if (data->triggers[i].indio_trig) { 1401 iio_trigger_unregister(data->triggers[i].indio_trig); 1402 data->triggers[i].indio_trig = NULL; 1403 } 1404 } 1405 } 1406 1407 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev, 1408 struct bmc150_accel_data *data) 1409 { 1410 struct device *dev = regmap_get_device(data->regmap); 1411 int i, ret; 1412 1413 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 1414 struct bmc150_accel_trigger *t = &data->triggers[i]; 1415 1416 t->indio_trig = devm_iio_trigger_alloc(dev, 1417 bmc150_accel_triggers[i].name, 1418 indio_dev->name, 1419 iio_device_id(indio_dev)); 1420 if (!t->indio_trig) { 1421 ret = -ENOMEM; 1422 break; 1423 } 1424 1425 t->indio_trig->ops = &bmc150_accel_trigger_ops; 1426 t->intr = bmc150_accel_triggers[i].intr; 1427 t->data = data; 1428 t->setup = bmc150_accel_triggers[i].setup; 1429 iio_trigger_set_drvdata(t->indio_trig, t); 1430 1431 ret = iio_trigger_register(t->indio_trig); 1432 if (ret) 1433 break; 1434 } 1435 1436 if (ret) 1437 bmc150_accel_unregister_triggers(data, i - 1); 1438 1439 return ret; 1440 } 1441 1442 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80 1443 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40 1444 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00 1445 1446 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data) 1447 { 1448 struct device *dev = regmap_get_device(data->regmap); 1449 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1; 1450 int ret; 1451 1452 ret = regmap_write(data->regmap, reg, data->fifo_mode); 1453 if (ret < 0) { 1454 dev_err(dev, "Error writing reg_fifo_config1\n"); 1455 return ret; 1456 } 1457 1458 if (!data->fifo_mode) 1459 return 0; 1460 1461 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0, 1462 data->watermark); 1463 if (ret < 0) 1464 dev_err(dev, "Error writing reg_fifo_config0\n"); 1465 1466 return ret; 1467 } 1468 1469 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev) 1470 { 1471 struct bmc150_accel_data *data = iio_priv(indio_dev); 1472 1473 return bmc150_accel_set_power_state(data, true); 1474 } 1475 1476 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev) 1477 { 1478 struct bmc150_accel_data *data = iio_priv(indio_dev); 1479 int ret = 0; 1480 1481 if (iio_device_get_current_mode(indio_dev) == INDIO_BUFFER_TRIGGERED) 1482 return 0; 1483 1484 mutex_lock(&data->mutex); 1485 1486 if (!data->watermark) 1487 goto out; 1488 1489 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, 1490 true); 1491 if (ret) 1492 goto out; 1493 1494 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO; 1495 1496 ret = bmc150_accel_fifo_set_mode(data); 1497 if (ret) { 1498 data->fifo_mode = 0; 1499 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, 1500 false); 1501 } 1502 1503 out: 1504 mutex_unlock(&data->mutex); 1505 1506 return ret; 1507 } 1508 1509 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev) 1510 { 1511 struct bmc150_accel_data *data = iio_priv(indio_dev); 1512 1513 if (iio_device_get_current_mode(indio_dev) == INDIO_BUFFER_TRIGGERED) 1514 return 0; 1515 1516 mutex_lock(&data->mutex); 1517 1518 if (!data->fifo_mode) 1519 goto out; 1520 1521 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false); 1522 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false); 1523 data->fifo_mode = 0; 1524 bmc150_accel_fifo_set_mode(data); 1525 1526 out: 1527 mutex_unlock(&data->mutex); 1528 1529 return 0; 1530 } 1531 1532 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev) 1533 { 1534 struct bmc150_accel_data *data = iio_priv(indio_dev); 1535 1536 return bmc150_accel_set_power_state(data, false); 1537 } 1538 1539 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = { 1540 .preenable = bmc150_accel_buffer_preenable, 1541 .postenable = bmc150_accel_buffer_postenable, 1542 .predisable = bmc150_accel_buffer_predisable, 1543 .postdisable = bmc150_accel_buffer_postdisable, 1544 }; 1545 1546 static int bmc150_accel_chip_init(struct bmc150_accel_data *data) 1547 { 1548 struct device *dev = regmap_get_device(data->regmap); 1549 int ret, i; 1550 unsigned int val; 1551 1552 /* 1553 * Reset chip to get it in a known good state. A delay of 1.8ms after 1554 * reset is required according to the data sheets of supported chips. 1555 */ 1556 regmap_write(data->regmap, BMC150_ACCEL_REG_RESET, 1557 BMC150_ACCEL_RESET_VAL); 1558 usleep_range(1800, 2500); 1559 1560 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val); 1561 if (ret < 0) { 1562 dev_err(dev, "Error: Reading chip id\n"); 1563 return ret; 1564 } 1565 1566 dev_dbg(dev, "Chip Id %x\n", val); 1567 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) { 1568 if (bmc150_accel_chip_info_tbl[i].chip_id == val) { 1569 data->chip_info = &bmc150_accel_chip_info_tbl[i]; 1570 break; 1571 } 1572 } 1573 1574 if (!data->chip_info) { 1575 dev_err(dev, "Invalid chip %x\n", val); 1576 return -ENODEV; 1577 } 1578 1579 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1580 if (ret < 0) 1581 return ret; 1582 1583 /* Set Bandwidth */ 1584 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0); 1585 if (ret < 0) 1586 return ret; 1587 1588 /* Set Default Range */ 1589 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE, 1590 BMC150_ACCEL_DEF_RANGE_4G); 1591 if (ret < 0) { 1592 dev_err(dev, "Error writing reg_pmu_range\n"); 1593 return ret; 1594 } 1595 1596 data->range = BMC150_ACCEL_DEF_RANGE_4G; 1597 1598 /* Set default slope duration and thresholds */ 1599 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD; 1600 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION; 1601 ret = bmc150_accel_update_slope(data); 1602 if (ret < 0) 1603 return ret; 1604 1605 /* Set default as latched interrupts */ 1606 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1607 BMC150_ACCEL_INT_MODE_LATCH_INT | 1608 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1609 if (ret < 0) { 1610 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1611 return ret; 1612 } 1613 1614 return 0; 1615 } 1616 1617 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq, 1618 enum bmc150_type type, const char *name, 1619 bool block_supported) 1620 { 1621 const struct iio_dev_attr **fifo_attrs; 1622 struct bmc150_accel_data *data; 1623 struct iio_dev *indio_dev; 1624 int ret; 1625 1626 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1627 if (!indio_dev) 1628 return -ENOMEM; 1629 1630 data = iio_priv(indio_dev); 1631 dev_set_drvdata(dev, indio_dev); 1632 1633 data->regmap = regmap; 1634 data->type = type; 1635 1636 if (!bmc150_apply_acpi_orientation(dev, &data->orientation)) { 1637 ret = iio_read_mount_matrix(dev, &data->orientation); 1638 if (ret) 1639 return ret; 1640 } 1641 1642 /* 1643 * VDD is the analog and digital domain voltage supply 1644 * VDDIO is the digital I/O voltage supply 1645 */ 1646 data->regulators[0].supply = "vdd"; 1647 data->regulators[1].supply = "vddio"; 1648 ret = devm_regulator_bulk_get(dev, 1649 ARRAY_SIZE(data->regulators), 1650 data->regulators); 1651 if (ret) 1652 return dev_err_probe(dev, ret, "failed to get regulators\n"); 1653 1654 ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators), 1655 data->regulators); 1656 if (ret) { 1657 dev_err(dev, "failed to enable regulators: %d\n", ret); 1658 return ret; 1659 } 1660 /* 1661 * 2ms or 3ms power-on time according to datasheets, let's better 1662 * be safe than sorry and set this delay to 5ms. 1663 */ 1664 msleep(5); 1665 1666 ret = bmc150_accel_chip_init(data); 1667 if (ret < 0) 1668 goto err_disable_regulators; 1669 1670 mutex_init(&data->mutex); 1671 1672 indio_dev->channels = data->chip_info->channels; 1673 indio_dev->num_channels = data->chip_info->num_channels; 1674 indio_dev->name = name ? name : data->chip_info->name; 1675 indio_dev->available_scan_masks = bmc150_accel_scan_masks; 1676 indio_dev->modes = INDIO_DIRECT_MODE; 1677 indio_dev->info = &bmc150_accel_info; 1678 1679 if (block_supported) { 1680 indio_dev->modes |= INDIO_BUFFER_SOFTWARE; 1681 indio_dev->info = &bmc150_accel_info_fifo; 1682 fifo_attrs = bmc150_accel_fifo_attributes; 1683 } else { 1684 fifo_attrs = NULL; 1685 } 1686 1687 ret = iio_triggered_buffer_setup_ext(indio_dev, 1688 &iio_pollfunc_store_time, 1689 bmc150_accel_trigger_handler, 1690 IIO_BUFFER_DIRECTION_IN, 1691 &bmc150_accel_buffer_ops, 1692 fifo_attrs); 1693 if (ret < 0) { 1694 dev_err(dev, "Failed: iio triggered buffer setup\n"); 1695 goto err_disable_regulators; 1696 } 1697 1698 if (irq > 0) { 1699 ret = devm_request_threaded_irq(dev, irq, 1700 bmc150_accel_irq_handler, 1701 bmc150_accel_irq_thread_handler, 1702 IRQF_TRIGGER_RISING, 1703 "bmc150_accel_event", 1704 indio_dev); 1705 if (ret) 1706 goto err_buffer_cleanup; 1707 1708 /* 1709 * Set latched mode interrupt. While certain interrupts are 1710 * non-latched regardless of this settings (e.g. new data) we 1711 * want to use latch mode when we can to prevent interrupt 1712 * flooding. 1713 */ 1714 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1715 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1716 if (ret < 0) { 1717 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1718 goto err_buffer_cleanup; 1719 } 1720 1721 bmc150_accel_interrupts_setup(indio_dev, data, irq); 1722 1723 ret = bmc150_accel_triggers_setup(indio_dev, data); 1724 if (ret) 1725 goto err_buffer_cleanup; 1726 } 1727 1728 ret = pm_runtime_set_active(dev); 1729 if (ret) 1730 goto err_trigger_unregister; 1731 1732 pm_runtime_enable(dev); 1733 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS); 1734 pm_runtime_use_autosuspend(dev); 1735 1736 ret = iio_device_register(indio_dev); 1737 if (ret < 0) { 1738 dev_err(dev, "Unable to register iio device\n"); 1739 goto err_pm_cleanup; 1740 } 1741 1742 return 0; 1743 1744 err_pm_cleanup: 1745 pm_runtime_dont_use_autosuspend(dev); 1746 pm_runtime_disable(dev); 1747 err_trigger_unregister: 1748 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); 1749 err_buffer_cleanup: 1750 iio_triggered_buffer_cleanup(indio_dev); 1751 err_disable_regulators: 1752 regulator_bulk_disable(ARRAY_SIZE(data->regulators), 1753 data->regulators); 1754 1755 return ret; 1756 } 1757 EXPORT_SYMBOL_NS_GPL(bmc150_accel_core_probe, "IIO_BMC150"); 1758 1759 void bmc150_accel_core_remove(struct device *dev) 1760 { 1761 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1762 struct bmc150_accel_data *data = iio_priv(indio_dev); 1763 1764 iio_device_unregister(indio_dev); 1765 1766 pm_runtime_disable(dev); 1767 pm_runtime_set_suspended(dev); 1768 1769 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); 1770 1771 iio_triggered_buffer_cleanup(indio_dev); 1772 1773 mutex_lock(&data->mutex); 1774 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0); 1775 mutex_unlock(&data->mutex); 1776 1777 regulator_bulk_disable(ARRAY_SIZE(data->regulators), 1778 data->regulators); 1779 } 1780 EXPORT_SYMBOL_NS_GPL(bmc150_accel_core_remove, "IIO_BMC150"); 1781 1782 #ifdef CONFIG_PM_SLEEP 1783 static int bmc150_accel_suspend(struct device *dev) 1784 { 1785 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1786 struct bmc150_accel_data *data = iio_priv(indio_dev); 1787 1788 mutex_lock(&data->mutex); 1789 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); 1790 mutex_unlock(&data->mutex); 1791 1792 return 0; 1793 } 1794 1795 static int bmc150_accel_resume(struct device *dev) 1796 { 1797 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1798 struct bmc150_accel_data *data = iio_priv(indio_dev); 1799 1800 mutex_lock(&data->mutex); 1801 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1802 bmc150_accel_fifo_set_mode(data); 1803 mutex_unlock(&data->mutex); 1804 1805 if (data->resume_callback) 1806 data->resume_callback(dev); 1807 1808 return 0; 1809 } 1810 #endif 1811 1812 #ifdef CONFIG_PM 1813 static int bmc150_accel_runtime_suspend(struct device *dev) 1814 { 1815 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1816 struct bmc150_accel_data *data = iio_priv(indio_dev); 1817 int ret; 1818 1819 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); 1820 if (ret < 0) 1821 return -EAGAIN; 1822 1823 return 0; 1824 } 1825 1826 static int bmc150_accel_runtime_resume(struct device *dev) 1827 { 1828 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1829 struct bmc150_accel_data *data = iio_priv(indio_dev); 1830 int ret; 1831 int sleep_val; 1832 1833 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1834 if (ret < 0) 1835 return ret; 1836 ret = bmc150_accel_fifo_set_mode(data); 1837 if (ret < 0) 1838 return ret; 1839 1840 sleep_val = bmc150_accel_get_startup_times(data); 1841 if (sleep_val < 20) 1842 usleep_range(sleep_val * 1000, 20000); 1843 else 1844 msleep_interruptible(sleep_val); 1845 1846 return 0; 1847 } 1848 #endif 1849 1850 const struct dev_pm_ops bmc150_accel_pm_ops = { 1851 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume) 1852 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend, 1853 bmc150_accel_runtime_resume, NULL) 1854 }; 1855 EXPORT_SYMBOL_NS_GPL(bmc150_accel_pm_ops, "IIO_BMC150"); 1856 1857 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); 1858 MODULE_LICENSE("GPL v2"); 1859 MODULE_DESCRIPTION("BMC150 accelerometer driver"); 1860