1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips: 4 * - BMC150 5 * - BMI055 6 * - BMA255 7 * - BMA250E 8 * - BMA222E 9 * - BMA280 10 * 11 * Copyright (c) 2014, Intel Corporation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/i2c.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/slab.h> 19 #include <linux/acpi.h> 20 #include <linux/pm.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/iio/iio.h> 23 #include <linux/iio/sysfs.h> 24 #include <linux/iio/buffer.h> 25 #include <linux/iio/events.h> 26 #include <linux/iio/trigger.h> 27 #include <linux/iio/trigger_consumer.h> 28 #include <linux/iio/triggered_buffer.h> 29 #include <linux/regmap.h> 30 31 #include "bmc150-accel.h" 32 33 #define BMC150_ACCEL_DRV_NAME "bmc150_accel" 34 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event" 35 36 #define BMC150_ACCEL_REG_CHIP_ID 0x00 37 38 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B 39 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07 40 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0) 41 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1) 42 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2) 43 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3) 44 45 #define BMC150_ACCEL_REG_PMU_LPW 0x11 46 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0 47 #define BMC150_ACCEL_PMU_MODE_SHIFT 5 48 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17 49 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1 50 51 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F 52 53 #define BMC150_ACCEL_DEF_RANGE_2G 0x03 54 #define BMC150_ACCEL_DEF_RANGE_4G 0x05 55 #define BMC150_ACCEL_DEF_RANGE_8G 0x08 56 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C 57 58 /* Default BW: 125Hz */ 59 #define BMC150_ACCEL_REG_PMU_BW 0x10 60 #define BMC150_ACCEL_DEF_BW 125 61 62 #define BMC150_ACCEL_REG_RESET 0x14 63 #define BMC150_ACCEL_RESET_VAL 0xB6 64 65 #define BMC150_ACCEL_REG_INT_MAP_0 0x19 66 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2) 67 68 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A 69 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0) 70 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1) 71 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2) 72 73 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21 74 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80 75 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F 76 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00 77 78 #define BMC150_ACCEL_REG_INT_EN_0 0x16 79 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0) 80 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1) 81 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2) 82 83 #define BMC150_ACCEL_REG_INT_EN_1 0x17 84 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4) 85 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5) 86 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6) 87 88 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20 89 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0) 90 91 #define BMC150_ACCEL_REG_INT_5 0x27 92 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03 93 94 #define BMC150_ACCEL_REG_INT_6 0x28 95 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF 96 97 /* Slope duration in terms of number of samples */ 98 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1 99 /* in terms of multiples of g's/LSB, based on range */ 100 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1 101 102 #define BMC150_ACCEL_REG_XOUT_L 0x02 103 104 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100 105 106 /* Sleep Duration values */ 107 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05 108 #define BMC150_ACCEL_SLEEP_1_MS 0x06 109 #define BMC150_ACCEL_SLEEP_2_MS 0x07 110 #define BMC150_ACCEL_SLEEP_4_MS 0x08 111 #define BMC150_ACCEL_SLEEP_6_MS 0x09 112 #define BMC150_ACCEL_SLEEP_10_MS 0x0A 113 #define BMC150_ACCEL_SLEEP_25_MS 0x0B 114 #define BMC150_ACCEL_SLEEP_50_MS 0x0C 115 #define BMC150_ACCEL_SLEEP_100_MS 0x0D 116 #define BMC150_ACCEL_SLEEP_500_MS 0x0E 117 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F 118 119 #define BMC150_ACCEL_REG_TEMP 0x08 120 #define BMC150_ACCEL_TEMP_CENTER_VAL 23 121 122 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2)) 123 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000 124 125 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E 126 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30 127 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E 128 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F 129 #define BMC150_ACCEL_FIFO_LENGTH 32 130 131 enum bmc150_accel_axis { 132 AXIS_X, 133 AXIS_Y, 134 AXIS_Z, 135 AXIS_MAX, 136 }; 137 138 enum bmc150_power_modes { 139 BMC150_ACCEL_SLEEP_MODE_NORMAL, 140 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 141 BMC150_ACCEL_SLEEP_MODE_LPM, 142 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04, 143 }; 144 145 struct bmc150_scale_info { 146 int scale; 147 u8 reg_range; 148 }; 149 150 struct bmc150_accel_chip_info { 151 const char *name; 152 u8 chip_id; 153 const struct iio_chan_spec *channels; 154 int num_channels; 155 const struct bmc150_scale_info scale_table[4]; 156 }; 157 158 struct bmc150_accel_interrupt { 159 const struct bmc150_accel_interrupt_info *info; 160 atomic_t users; 161 }; 162 163 struct bmc150_accel_trigger { 164 struct bmc150_accel_data *data; 165 struct iio_trigger *indio_trig; 166 int (*setup)(struct bmc150_accel_trigger *t, bool state); 167 int intr; 168 bool enabled; 169 }; 170 171 enum bmc150_accel_interrupt_id { 172 BMC150_ACCEL_INT_DATA_READY, 173 BMC150_ACCEL_INT_ANY_MOTION, 174 BMC150_ACCEL_INT_WATERMARK, 175 BMC150_ACCEL_INTERRUPTS, 176 }; 177 178 enum bmc150_accel_trigger_id { 179 BMC150_ACCEL_TRIGGER_DATA_READY, 180 BMC150_ACCEL_TRIGGER_ANY_MOTION, 181 BMC150_ACCEL_TRIGGERS, 182 }; 183 184 struct bmc150_accel_data { 185 struct regmap *regmap; 186 int irq; 187 struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS]; 188 struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS]; 189 struct mutex mutex; 190 u8 fifo_mode, watermark; 191 s16 buffer[8]; 192 u8 bw_bits; 193 u32 slope_dur; 194 u32 slope_thres; 195 u32 range; 196 int ev_enable_state; 197 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */ 198 const struct bmc150_accel_chip_info *chip_info; 199 struct iio_mount_matrix orientation; 200 }; 201 202 static const struct { 203 int val; 204 int val2; 205 u8 bw_bits; 206 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08}, 207 {31, 260000, 0x09}, 208 {62, 500000, 0x0A}, 209 {125, 0, 0x0B}, 210 {250, 0, 0x0C}, 211 {500, 0, 0x0D}, 212 {1000, 0, 0x0E}, 213 {2000, 0, 0x0F} }; 214 215 static const struct { 216 int bw_bits; 217 int msec; 218 } bmc150_accel_sample_upd_time[] = { {0x08, 64}, 219 {0x09, 32}, 220 {0x0A, 16}, 221 {0x0B, 8}, 222 {0x0C, 4}, 223 {0x0D, 2}, 224 {0x0E, 1}, 225 {0x0F, 1} }; 226 227 static const struct { 228 int sleep_dur; 229 u8 reg_value; 230 } bmc150_accel_sleep_value_table[] = { {0, 0}, 231 {500, BMC150_ACCEL_SLEEP_500_MICRO}, 232 {1000, BMC150_ACCEL_SLEEP_1_MS}, 233 {2000, BMC150_ACCEL_SLEEP_2_MS}, 234 {4000, BMC150_ACCEL_SLEEP_4_MS}, 235 {6000, BMC150_ACCEL_SLEEP_6_MS}, 236 {10000, BMC150_ACCEL_SLEEP_10_MS}, 237 {25000, BMC150_ACCEL_SLEEP_25_MS}, 238 {50000, BMC150_ACCEL_SLEEP_50_MS}, 239 {100000, BMC150_ACCEL_SLEEP_100_MS}, 240 {500000, BMC150_ACCEL_SLEEP_500_MS}, 241 {1000000, BMC150_ACCEL_SLEEP_1_SEC} }; 242 243 const struct regmap_config bmc150_regmap_conf = { 244 .reg_bits = 8, 245 .val_bits = 8, 246 .max_register = 0x3f, 247 }; 248 EXPORT_SYMBOL_GPL(bmc150_regmap_conf); 249 250 static int bmc150_accel_set_mode(struct bmc150_accel_data *data, 251 enum bmc150_power_modes mode, 252 int dur_us) 253 { 254 struct device *dev = regmap_get_device(data->regmap); 255 int i; 256 int ret; 257 u8 lpw_bits; 258 int dur_val = -1; 259 260 if (dur_us > 0) { 261 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table); 262 ++i) { 263 if (bmc150_accel_sleep_value_table[i].sleep_dur == 264 dur_us) 265 dur_val = 266 bmc150_accel_sleep_value_table[i].reg_value; 267 } 268 } else { 269 dur_val = 0; 270 } 271 272 if (dur_val < 0) 273 return -EINVAL; 274 275 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT; 276 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT); 277 278 dev_dbg(dev, "Set Mode bits %x\n", lpw_bits); 279 280 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits); 281 if (ret < 0) { 282 dev_err(dev, "Error writing reg_pmu_lpw\n"); 283 return ret; 284 } 285 286 return 0; 287 } 288 289 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val, 290 int val2) 291 { 292 int i; 293 int ret; 294 295 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { 296 if (bmc150_accel_samp_freq_table[i].val == val && 297 bmc150_accel_samp_freq_table[i].val2 == val2) { 298 ret = regmap_write(data->regmap, 299 BMC150_ACCEL_REG_PMU_BW, 300 bmc150_accel_samp_freq_table[i].bw_bits); 301 if (ret < 0) 302 return ret; 303 304 data->bw_bits = 305 bmc150_accel_samp_freq_table[i].bw_bits; 306 return 0; 307 } 308 } 309 310 return -EINVAL; 311 } 312 313 static int bmc150_accel_update_slope(struct bmc150_accel_data *data) 314 { 315 struct device *dev = regmap_get_device(data->regmap); 316 int ret; 317 318 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6, 319 data->slope_thres); 320 if (ret < 0) { 321 dev_err(dev, "Error writing reg_int_6\n"); 322 return ret; 323 } 324 325 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5, 326 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur); 327 if (ret < 0) { 328 dev_err(dev, "Error updating reg_int_5\n"); 329 return ret; 330 } 331 332 dev_dbg(dev, "%x %x\n", data->slope_thres, data->slope_dur); 333 334 return ret; 335 } 336 337 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t, 338 bool state) 339 { 340 if (state) 341 return bmc150_accel_update_slope(t->data); 342 343 return 0; 344 } 345 346 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val, 347 int *val2) 348 { 349 int i; 350 351 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { 352 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) { 353 *val = bmc150_accel_samp_freq_table[i].val; 354 *val2 = bmc150_accel_samp_freq_table[i].val2; 355 return IIO_VAL_INT_PLUS_MICRO; 356 } 357 } 358 359 return -EINVAL; 360 } 361 362 #ifdef CONFIG_PM 363 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data) 364 { 365 int i; 366 367 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) { 368 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits) 369 return bmc150_accel_sample_upd_time[i].msec; 370 } 371 372 return BMC150_ACCEL_MAX_STARTUP_TIME_MS; 373 } 374 375 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) 376 { 377 struct device *dev = regmap_get_device(data->regmap); 378 int ret; 379 380 if (on) { 381 ret = pm_runtime_get_sync(dev); 382 } else { 383 pm_runtime_mark_last_busy(dev); 384 ret = pm_runtime_put_autosuspend(dev); 385 } 386 387 if (ret < 0) { 388 dev_err(dev, 389 "Failed: %s for %d\n", __func__, on); 390 if (on) 391 pm_runtime_put_noidle(dev); 392 393 return ret; 394 } 395 396 return 0; 397 } 398 #else 399 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) 400 { 401 return 0; 402 } 403 #endif 404 405 static const struct bmc150_accel_interrupt_info { 406 u8 map_reg; 407 u8 map_bitmask; 408 u8 en_reg; 409 u8 en_bitmask; 410 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = { 411 { /* data ready interrupt */ 412 .map_reg = BMC150_ACCEL_REG_INT_MAP_1, 413 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA, 414 .en_reg = BMC150_ACCEL_REG_INT_EN_1, 415 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN, 416 }, 417 { /* motion interrupt */ 418 .map_reg = BMC150_ACCEL_REG_INT_MAP_0, 419 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE, 420 .en_reg = BMC150_ACCEL_REG_INT_EN_0, 421 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X | 422 BMC150_ACCEL_INT_EN_BIT_SLP_Y | 423 BMC150_ACCEL_INT_EN_BIT_SLP_Z 424 }, 425 { /* fifo watermark interrupt */ 426 .map_reg = BMC150_ACCEL_REG_INT_MAP_1, 427 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM, 428 .en_reg = BMC150_ACCEL_REG_INT_EN_1, 429 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN, 430 }, 431 }; 432 433 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev, 434 struct bmc150_accel_data *data) 435 { 436 int i; 437 438 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++) 439 data->interrupts[i].info = &bmc150_accel_interrupts[i]; 440 } 441 442 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i, 443 bool state) 444 { 445 struct device *dev = regmap_get_device(data->regmap); 446 struct bmc150_accel_interrupt *intr = &data->interrupts[i]; 447 const struct bmc150_accel_interrupt_info *info = intr->info; 448 int ret; 449 450 if (state) { 451 if (atomic_inc_return(&intr->users) > 1) 452 return 0; 453 } else { 454 if (atomic_dec_return(&intr->users) > 0) 455 return 0; 456 } 457 458 /* 459 * We will expect the enable and disable to do operation in reverse 460 * order. This will happen here anyway, as our resume operation uses 461 * sync mode runtime pm calls. The suspend operation will be delayed 462 * by autosuspend delay. 463 * So the disable operation will still happen in reverse order of 464 * enable operation. When runtime pm is disabled the mode is always on, 465 * so sequence doesn't matter. 466 */ 467 ret = bmc150_accel_set_power_state(data, state); 468 if (ret < 0) 469 return ret; 470 471 /* map the interrupt to the appropriate pins */ 472 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask, 473 (state ? info->map_bitmask : 0)); 474 if (ret < 0) { 475 dev_err(dev, "Error updating reg_int_map\n"); 476 goto out_fix_power_state; 477 } 478 479 /* enable/disable the interrupt */ 480 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask, 481 (state ? info->en_bitmask : 0)); 482 if (ret < 0) { 483 dev_err(dev, "Error updating reg_int_en\n"); 484 goto out_fix_power_state; 485 } 486 487 return 0; 488 489 out_fix_power_state: 490 bmc150_accel_set_power_state(data, false); 491 return ret; 492 } 493 494 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val) 495 { 496 struct device *dev = regmap_get_device(data->regmap); 497 int ret, i; 498 499 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) { 500 if (data->chip_info->scale_table[i].scale == val) { 501 ret = regmap_write(data->regmap, 502 BMC150_ACCEL_REG_PMU_RANGE, 503 data->chip_info->scale_table[i].reg_range); 504 if (ret < 0) { 505 dev_err(dev, "Error writing pmu_range\n"); 506 return ret; 507 } 508 509 data->range = data->chip_info->scale_table[i].reg_range; 510 return 0; 511 } 512 } 513 514 return -EINVAL; 515 } 516 517 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val) 518 { 519 struct device *dev = regmap_get_device(data->regmap); 520 int ret; 521 unsigned int value; 522 523 mutex_lock(&data->mutex); 524 525 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value); 526 if (ret < 0) { 527 dev_err(dev, "Error reading reg_temp\n"); 528 mutex_unlock(&data->mutex); 529 return ret; 530 } 531 *val = sign_extend32(value, 7); 532 533 mutex_unlock(&data->mutex); 534 535 return IIO_VAL_INT; 536 } 537 538 static int bmc150_accel_get_axis(struct bmc150_accel_data *data, 539 struct iio_chan_spec const *chan, 540 int *val) 541 { 542 struct device *dev = regmap_get_device(data->regmap); 543 int ret; 544 int axis = chan->scan_index; 545 __le16 raw_val; 546 547 mutex_lock(&data->mutex); 548 ret = bmc150_accel_set_power_state(data, true); 549 if (ret < 0) { 550 mutex_unlock(&data->mutex); 551 return ret; 552 } 553 554 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis), 555 &raw_val, sizeof(raw_val)); 556 if (ret < 0) { 557 dev_err(dev, "Error reading axis %d\n", axis); 558 bmc150_accel_set_power_state(data, false); 559 mutex_unlock(&data->mutex); 560 return ret; 561 } 562 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift, 563 chan->scan_type.realbits - 1); 564 ret = bmc150_accel_set_power_state(data, false); 565 mutex_unlock(&data->mutex); 566 if (ret < 0) 567 return ret; 568 569 return IIO_VAL_INT; 570 } 571 572 static int bmc150_accel_read_raw(struct iio_dev *indio_dev, 573 struct iio_chan_spec const *chan, 574 int *val, int *val2, long mask) 575 { 576 struct bmc150_accel_data *data = iio_priv(indio_dev); 577 int ret; 578 579 switch (mask) { 580 case IIO_CHAN_INFO_RAW: 581 switch (chan->type) { 582 case IIO_TEMP: 583 return bmc150_accel_get_temp(data, val); 584 case IIO_ACCEL: 585 if (iio_buffer_enabled(indio_dev)) 586 return -EBUSY; 587 else 588 return bmc150_accel_get_axis(data, chan, val); 589 default: 590 return -EINVAL; 591 } 592 case IIO_CHAN_INFO_OFFSET: 593 if (chan->type == IIO_TEMP) { 594 *val = BMC150_ACCEL_TEMP_CENTER_VAL; 595 return IIO_VAL_INT; 596 } else { 597 return -EINVAL; 598 } 599 case IIO_CHAN_INFO_SCALE: 600 *val = 0; 601 switch (chan->type) { 602 case IIO_TEMP: 603 *val2 = 500000; 604 return IIO_VAL_INT_PLUS_MICRO; 605 case IIO_ACCEL: 606 { 607 int i; 608 const struct bmc150_scale_info *si; 609 int st_size = ARRAY_SIZE(data->chip_info->scale_table); 610 611 for (i = 0; i < st_size; ++i) { 612 si = &data->chip_info->scale_table[i]; 613 if (si->reg_range == data->range) { 614 *val2 = si->scale; 615 return IIO_VAL_INT_PLUS_MICRO; 616 } 617 } 618 return -EINVAL; 619 } 620 default: 621 return -EINVAL; 622 } 623 case IIO_CHAN_INFO_SAMP_FREQ: 624 mutex_lock(&data->mutex); 625 ret = bmc150_accel_get_bw(data, val, val2); 626 mutex_unlock(&data->mutex); 627 return ret; 628 default: 629 return -EINVAL; 630 } 631 } 632 633 static int bmc150_accel_write_raw(struct iio_dev *indio_dev, 634 struct iio_chan_spec const *chan, 635 int val, int val2, long mask) 636 { 637 struct bmc150_accel_data *data = iio_priv(indio_dev); 638 int ret; 639 640 switch (mask) { 641 case IIO_CHAN_INFO_SAMP_FREQ: 642 mutex_lock(&data->mutex); 643 ret = bmc150_accel_set_bw(data, val, val2); 644 mutex_unlock(&data->mutex); 645 break; 646 case IIO_CHAN_INFO_SCALE: 647 if (val) 648 return -EINVAL; 649 650 mutex_lock(&data->mutex); 651 ret = bmc150_accel_set_scale(data, val2); 652 mutex_unlock(&data->mutex); 653 return ret; 654 default: 655 ret = -EINVAL; 656 } 657 658 return ret; 659 } 660 661 static int bmc150_accel_read_event(struct iio_dev *indio_dev, 662 const struct iio_chan_spec *chan, 663 enum iio_event_type type, 664 enum iio_event_direction dir, 665 enum iio_event_info info, 666 int *val, int *val2) 667 { 668 struct bmc150_accel_data *data = iio_priv(indio_dev); 669 670 *val2 = 0; 671 switch (info) { 672 case IIO_EV_INFO_VALUE: 673 *val = data->slope_thres; 674 break; 675 case IIO_EV_INFO_PERIOD: 676 *val = data->slope_dur; 677 break; 678 default: 679 return -EINVAL; 680 } 681 682 return IIO_VAL_INT; 683 } 684 685 static int bmc150_accel_write_event(struct iio_dev *indio_dev, 686 const struct iio_chan_spec *chan, 687 enum iio_event_type type, 688 enum iio_event_direction dir, 689 enum iio_event_info info, 690 int val, int val2) 691 { 692 struct bmc150_accel_data *data = iio_priv(indio_dev); 693 694 if (data->ev_enable_state) 695 return -EBUSY; 696 697 switch (info) { 698 case IIO_EV_INFO_VALUE: 699 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK; 700 break; 701 case IIO_EV_INFO_PERIOD: 702 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK; 703 break; 704 default: 705 return -EINVAL; 706 } 707 708 return 0; 709 } 710 711 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev, 712 const struct iio_chan_spec *chan, 713 enum iio_event_type type, 714 enum iio_event_direction dir) 715 { 716 struct bmc150_accel_data *data = iio_priv(indio_dev); 717 718 return data->ev_enable_state; 719 } 720 721 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev, 722 const struct iio_chan_spec *chan, 723 enum iio_event_type type, 724 enum iio_event_direction dir, 725 int state) 726 { 727 struct bmc150_accel_data *data = iio_priv(indio_dev); 728 int ret; 729 730 if (state == data->ev_enable_state) 731 return 0; 732 733 mutex_lock(&data->mutex); 734 735 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION, 736 state); 737 if (ret < 0) { 738 mutex_unlock(&data->mutex); 739 return ret; 740 } 741 742 data->ev_enable_state = state; 743 mutex_unlock(&data->mutex); 744 745 return 0; 746 } 747 748 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev, 749 struct iio_trigger *trig) 750 { 751 struct bmc150_accel_data *data = iio_priv(indio_dev); 752 int i; 753 754 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 755 if (data->triggers[i].indio_trig == trig) 756 return 0; 757 } 758 759 return -EINVAL; 760 } 761 762 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev, 763 struct device_attribute *attr, 764 char *buf) 765 { 766 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 767 struct bmc150_accel_data *data = iio_priv(indio_dev); 768 int wm; 769 770 mutex_lock(&data->mutex); 771 wm = data->watermark; 772 mutex_unlock(&data->mutex); 773 774 return sprintf(buf, "%d\n", wm); 775 } 776 777 static ssize_t bmc150_accel_get_fifo_state(struct device *dev, 778 struct device_attribute *attr, 779 char *buf) 780 { 781 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 782 struct bmc150_accel_data *data = iio_priv(indio_dev); 783 bool state; 784 785 mutex_lock(&data->mutex); 786 state = data->fifo_mode; 787 mutex_unlock(&data->mutex); 788 789 return sprintf(buf, "%d\n", state); 790 } 791 792 static const struct iio_mount_matrix * 793 bmc150_accel_get_mount_matrix(const struct iio_dev *indio_dev, 794 const struct iio_chan_spec *chan) 795 { 796 struct bmc150_accel_data *data = iio_priv(indio_dev); 797 798 return &data->orientation; 799 } 800 801 static const struct iio_chan_spec_ext_info bmc150_accel_ext_info[] = { 802 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmc150_accel_get_mount_matrix), 803 { } 804 }; 805 806 static IIO_CONST_ATTR(hwfifo_watermark_min, "1"); 807 static IIO_CONST_ATTR(hwfifo_watermark_max, 808 __stringify(BMC150_ACCEL_FIFO_LENGTH)); 809 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO, 810 bmc150_accel_get_fifo_state, NULL, 0); 811 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO, 812 bmc150_accel_get_fifo_watermark, NULL, 0); 813 814 static const struct attribute *bmc150_accel_fifo_attributes[] = { 815 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, 816 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, 817 &iio_dev_attr_hwfifo_watermark.dev_attr.attr, 818 &iio_dev_attr_hwfifo_enabled.dev_attr.attr, 819 NULL, 820 }; 821 822 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val) 823 { 824 struct bmc150_accel_data *data = iio_priv(indio_dev); 825 826 if (val > BMC150_ACCEL_FIFO_LENGTH) 827 val = BMC150_ACCEL_FIFO_LENGTH; 828 829 mutex_lock(&data->mutex); 830 data->watermark = val; 831 mutex_unlock(&data->mutex); 832 833 return 0; 834 } 835 836 /* 837 * We must read at least one full frame in one burst, otherwise the rest of the 838 * frame data is discarded. 839 */ 840 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data, 841 char *buffer, int samples) 842 { 843 struct device *dev = regmap_get_device(data->regmap); 844 int sample_length = 3 * 2; 845 int ret; 846 int total_length = samples * sample_length; 847 848 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA, 849 buffer, total_length); 850 if (ret) 851 dev_err(dev, 852 "Error transferring data from fifo: %d\n", ret); 853 854 return ret; 855 } 856 857 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev, 858 unsigned samples, bool irq) 859 { 860 struct bmc150_accel_data *data = iio_priv(indio_dev); 861 struct device *dev = regmap_get_device(data->regmap); 862 int ret, i; 863 u8 count; 864 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3]; 865 int64_t tstamp; 866 uint64_t sample_period; 867 unsigned int val; 868 869 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val); 870 if (ret < 0) { 871 dev_err(dev, "Error reading reg_fifo_status\n"); 872 return ret; 873 } 874 875 count = val & 0x7F; 876 877 if (!count) 878 return 0; 879 880 /* 881 * If we getting called from IRQ handler we know the stored timestamp is 882 * fairly accurate for the last stored sample. Otherwise, if we are 883 * called as a result of a read operation from userspace and hence 884 * before the watermark interrupt was triggered, take a timestamp 885 * now. We can fall anywhere in between two samples so the error in this 886 * case is at most one sample period. 887 */ 888 if (!irq) { 889 data->old_timestamp = data->timestamp; 890 data->timestamp = iio_get_time_ns(indio_dev); 891 } 892 893 /* 894 * Approximate timestamps for each of the sample based on the sampling 895 * frequency, timestamp for last sample and number of samples. 896 * 897 * Note that we can't use the current bandwidth settings to compute the 898 * sample period because the sample rate varies with the device 899 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That 900 * small variation adds when we store a large number of samples and 901 * creates significant jitter between the last and first samples in 902 * different batches (e.g. 32ms vs 21ms). 903 * 904 * To avoid this issue we compute the actual sample period ourselves 905 * based on the timestamp delta between the last two flush operations. 906 */ 907 sample_period = (data->timestamp - data->old_timestamp); 908 do_div(sample_period, count); 909 tstamp = data->timestamp - (count - 1) * sample_period; 910 911 if (samples && count > samples) 912 count = samples; 913 914 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count); 915 if (ret) 916 return ret; 917 918 /* 919 * Ideally we want the IIO core to handle the demux when running in fifo 920 * mode but not when running in triggered buffer mode. Unfortunately 921 * this does not seem to be possible, so stick with driver demux for 922 * now. 923 */ 924 for (i = 0; i < count; i++) { 925 u16 sample[8]; 926 int j, bit; 927 928 j = 0; 929 for_each_set_bit(bit, indio_dev->active_scan_mask, 930 indio_dev->masklength) 931 memcpy(&sample[j++], &buffer[i * 3 + bit], 2); 932 933 iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp); 934 935 tstamp += sample_period; 936 } 937 938 return count; 939 } 940 941 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples) 942 { 943 struct bmc150_accel_data *data = iio_priv(indio_dev); 944 int ret; 945 946 mutex_lock(&data->mutex); 947 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false); 948 mutex_unlock(&data->mutex); 949 950 return ret; 951 } 952 953 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( 954 "15.620000 31.260000 62.50000 125 250 500 1000 2000"); 955 956 static struct attribute *bmc150_accel_attributes[] = { 957 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 958 NULL, 959 }; 960 961 static const struct attribute_group bmc150_accel_attrs_group = { 962 .attrs = bmc150_accel_attributes, 963 }; 964 965 static const struct iio_event_spec bmc150_accel_event = { 966 .type = IIO_EV_TYPE_ROC, 967 .dir = IIO_EV_DIR_EITHER, 968 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 969 BIT(IIO_EV_INFO_ENABLE) | 970 BIT(IIO_EV_INFO_PERIOD) 971 }; 972 973 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \ 974 .type = IIO_ACCEL, \ 975 .modified = 1, \ 976 .channel2 = IIO_MOD_##_axis, \ 977 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 978 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 979 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 980 .scan_index = AXIS_##_axis, \ 981 .scan_type = { \ 982 .sign = 's', \ 983 .realbits = (bits), \ 984 .storagebits = 16, \ 985 .shift = 16 - (bits), \ 986 .endianness = IIO_LE, \ 987 }, \ 988 .ext_info = bmc150_accel_ext_info, \ 989 .event_spec = &bmc150_accel_event, \ 990 .num_event_specs = 1 \ 991 } 992 993 #define BMC150_ACCEL_CHANNELS(bits) { \ 994 { \ 995 .type = IIO_TEMP, \ 996 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 997 BIT(IIO_CHAN_INFO_SCALE) | \ 998 BIT(IIO_CHAN_INFO_OFFSET), \ 999 .scan_index = -1, \ 1000 }, \ 1001 BMC150_ACCEL_CHANNEL(X, bits), \ 1002 BMC150_ACCEL_CHANNEL(Y, bits), \ 1003 BMC150_ACCEL_CHANNEL(Z, bits), \ 1004 IIO_CHAN_SOFT_TIMESTAMP(3), \ 1005 } 1006 1007 static const struct iio_chan_spec bma222e_accel_channels[] = 1008 BMC150_ACCEL_CHANNELS(8); 1009 static const struct iio_chan_spec bma250e_accel_channels[] = 1010 BMC150_ACCEL_CHANNELS(10); 1011 static const struct iio_chan_spec bmc150_accel_channels[] = 1012 BMC150_ACCEL_CHANNELS(12); 1013 static const struct iio_chan_spec bma280_accel_channels[] = 1014 BMC150_ACCEL_CHANNELS(14); 1015 1016 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = { 1017 [bmc150] = { 1018 .name = "BMC150A", 1019 .chip_id = 0xFA, 1020 .channels = bmc150_accel_channels, 1021 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1022 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 1023 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 1024 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 1025 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 1026 }, 1027 [bmi055] = { 1028 .name = "BMI055A", 1029 .chip_id = 0xFA, 1030 .channels = bmc150_accel_channels, 1031 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1032 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 1033 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 1034 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 1035 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 1036 }, 1037 [bma255] = { 1038 .name = "BMA0255", 1039 .chip_id = 0xFA, 1040 .channels = bmc150_accel_channels, 1041 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1042 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 1043 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 1044 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 1045 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 1046 }, 1047 [bma250e] = { 1048 .name = "BMA250E", 1049 .chip_id = 0xF9, 1050 .channels = bma250e_accel_channels, 1051 .num_channels = ARRAY_SIZE(bma250e_accel_channels), 1052 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G}, 1053 {76590, BMC150_ACCEL_DEF_RANGE_4G}, 1054 {153277, BMC150_ACCEL_DEF_RANGE_8G}, 1055 {306457, BMC150_ACCEL_DEF_RANGE_16G} }, 1056 }, 1057 [bma222e] = { 1058 .name = "BMA222E", 1059 .chip_id = 0xF8, 1060 .channels = bma222e_accel_channels, 1061 .num_channels = ARRAY_SIZE(bma222e_accel_channels), 1062 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G}, 1063 {306457, BMC150_ACCEL_DEF_RANGE_4G}, 1064 {612915, BMC150_ACCEL_DEF_RANGE_8G}, 1065 {1225831, BMC150_ACCEL_DEF_RANGE_16G} }, 1066 }, 1067 [bma280] = { 1068 .name = "BMA0280", 1069 .chip_id = 0xFB, 1070 .channels = bma280_accel_channels, 1071 .num_channels = ARRAY_SIZE(bma280_accel_channels), 1072 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G}, 1073 {4785, BMC150_ACCEL_DEF_RANGE_4G}, 1074 {9581, BMC150_ACCEL_DEF_RANGE_8G}, 1075 {19152, BMC150_ACCEL_DEF_RANGE_16G} }, 1076 }, 1077 }; 1078 1079 static const struct iio_info bmc150_accel_info = { 1080 .attrs = &bmc150_accel_attrs_group, 1081 .read_raw = bmc150_accel_read_raw, 1082 .write_raw = bmc150_accel_write_raw, 1083 .read_event_value = bmc150_accel_read_event, 1084 .write_event_value = bmc150_accel_write_event, 1085 .write_event_config = bmc150_accel_write_event_config, 1086 .read_event_config = bmc150_accel_read_event_config, 1087 }; 1088 1089 static const struct iio_info bmc150_accel_info_fifo = { 1090 .attrs = &bmc150_accel_attrs_group, 1091 .read_raw = bmc150_accel_read_raw, 1092 .write_raw = bmc150_accel_write_raw, 1093 .read_event_value = bmc150_accel_read_event, 1094 .write_event_value = bmc150_accel_write_event, 1095 .write_event_config = bmc150_accel_write_event_config, 1096 .read_event_config = bmc150_accel_read_event_config, 1097 .validate_trigger = bmc150_accel_validate_trigger, 1098 .hwfifo_set_watermark = bmc150_accel_set_watermark, 1099 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush, 1100 }; 1101 1102 static const unsigned long bmc150_accel_scan_masks[] = { 1103 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 1104 0}; 1105 1106 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p) 1107 { 1108 struct iio_poll_func *pf = p; 1109 struct iio_dev *indio_dev = pf->indio_dev; 1110 struct bmc150_accel_data *data = iio_priv(indio_dev); 1111 int ret; 1112 1113 mutex_lock(&data->mutex); 1114 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L, 1115 data->buffer, AXIS_MAX * 2); 1116 mutex_unlock(&data->mutex); 1117 if (ret < 0) 1118 goto err_read; 1119 1120 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, 1121 pf->timestamp); 1122 err_read: 1123 iio_trigger_notify_done(indio_dev->trig); 1124 1125 return IRQ_HANDLED; 1126 } 1127 1128 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig) 1129 { 1130 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); 1131 struct bmc150_accel_data *data = t->data; 1132 struct device *dev = regmap_get_device(data->regmap); 1133 int ret; 1134 1135 /* new data interrupts don't need ack */ 1136 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY]) 1137 return 0; 1138 1139 mutex_lock(&data->mutex); 1140 /* clear any latched interrupt */ 1141 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1142 BMC150_ACCEL_INT_MODE_LATCH_INT | 1143 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1144 mutex_unlock(&data->mutex); 1145 if (ret < 0) { 1146 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1147 return ret; 1148 } 1149 1150 return 0; 1151 } 1152 1153 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig, 1154 bool state) 1155 { 1156 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); 1157 struct bmc150_accel_data *data = t->data; 1158 int ret; 1159 1160 mutex_lock(&data->mutex); 1161 1162 if (t->enabled == state) { 1163 mutex_unlock(&data->mutex); 1164 return 0; 1165 } 1166 1167 if (t->setup) { 1168 ret = t->setup(t, state); 1169 if (ret < 0) { 1170 mutex_unlock(&data->mutex); 1171 return ret; 1172 } 1173 } 1174 1175 ret = bmc150_accel_set_interrupt(data, t->intr, state); 1176 if (ret < 0) { 1177 mutex_unlock(&data->mutex); 1178 return ret; 1179 } 1180 1181 t->enabled = state; 1182 1183 mutex_unlock(&data->mutex); 1184 1185 return ret; 1186 } 1187 1188 static const struct iio_trigger_ops bmc150_accel_trigger_ops = { 1189 .set_trigger_state = bmc150_accel_trigger_set_state, 1190 .try_reenable = bmc150_accel_trig_try_reen, 1191 }; 1192 1193 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev) 1194 { 1195 struct bmc150_accel_data *data = iio_priv(indio_dev); 1196 struct device *dev = regmap_get_device(data->regmap); 1197 int dir; 1198 int ret; 1199 unsigned int val; 1200 1201 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val); 1202 if (ret < 0) { 1203 dev_err(dev, "Error reading reg_int_status_2\n"); 1204 return ret; 1205 } 1206 1207 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN) 1208 dir = IIO_EV_DIR_FALLING; 1209 else 1210 dir = IIO_EV_DIR_RISING; 1211 1212 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X) 1213 iio_push_event(indio_dev, 1214 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1215 0, 1216 IIO_MOD_X, 1217 IIO_EV_TYPE_ROC, 1218 dir), 1219 data->timestamp); 1220 1221 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y) 1222 iio_push_event(indio_dev, 1223 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1224 0, 1225 IIO_MOD_Y, 1226 IIO_EV_TYPE_ROC, 1227 dir), 1228 data->timestamp); 1229 1230 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z) 1231 iio_push_event(indio_dev, 1232 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1233 0, 1234 IIO_MOD_Z, 1235 IIO_EV_TYPE_ROC, 1236 dir), 1237 data->timestamp); 1238 1239 return ret; 1240 } 1241 1242 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private) 1243 { 1244 struct iio_dev *indio_dev = private; 1245 struct bmc150_accel_data *data = iio_priv(indio_dev); 1246 struct device *dev = regmap_get_device(data->regmap); 1247 bool ack = false; 1248 int ret; 1249 1250 mutex_lock(&data->mutex); 1251 1252 if (data->fifo_mode) { 1253 ret = __bmc150_accel_fifo_flush(indio_dev, 1254 BMC150_ACCEL_FIFO_LENGTH, true); 1255 if (ret > 0) 1256 ack = true; 1257 } 1258 1259 if (data->ev_enable_state) { 1260 ret = bmc150_accel_handle_roc_event(indio_dev); 1261 if (ret > 0) 1262 ack = true; 1263 } 1264 1265 if (ack) { 1266 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1267 BMC150_ACCEL_INT_MODE_LATCH_INT | 1268 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1269 if (ret) 1270 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1271 1272 ret = IRQ_HANDLED; 1273 } else { 1274 ret = IRQ_NONE; 1275 } 1276 1277 mutex_unlock(&data->mutex); 1278 1279 return ret; 1280 } 1281 1282 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private) 1283 { 1284 struct iio_dev *indio_dev = private; 1285 struct bmc150_accel_data *data = iio_priv(indio_dev); 1286 bool ack = false; 1287 int i; 1288 1289 data->old_timestamp = data->timestamp; 1290 data->timestamp = iio_get_time_ns(indio_dev); 1291 1292 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 1293 if (data->triggers[i].enabled) { 1294 iio_trigger_poll(data->triggers[i].indio_trig); 1295 ack = true; 1296 break; 1297 } 1298 } 1299 1300 if (data->ev_enable_state || data->fifo_mode) 1301 return IRQ_WAKE_THREAD; 1302 1303 if (ack) 1304 return IRQ_HANDLED; 1305 1306 return IRQ_NONE; 1307 } 1308 1309 static const struct { 1310 int intr; 1311 const char *name; 1312 int (*setup)(struct bmc150_accel_trigger *t, bool state); 1313 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = { 1314 { 1315 .intr = 0, 1316 .name = "%s-dev%d", 1317 }, 1318 { 1319 .intr = 1, 1320 .name = "%s-any-motion-dev%d", 1321 .setup = bmc150_accel_any_motion_setup, 1322 }, 1323 }; 1324 1325 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data, 1326 int from) 1327 { 1328 int i; 1329 1330 for (i = from; i >= 0; i--) { 1331 if (data->triggers[i].indio_trig) { 1332 iio_trigger_unregister(data->triggers[i].indio_trig); 1333 data->triggers[i].indio_trig = NULL; 1334 } 1335 } 1336 } 1337 1338 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev, 1339 struct bmc150_accel_data *data) 1340 { 1341 struct device *dev = regmap_get_device(data->regmap); 1342 int i, ret; 1343 1344 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 1345 struct bmc150_accel_trigger *t = &data->triggers[i]; 1346 1347 t->indio_trig = devm_iio_trigger_alloc(dev, 1348 bmc150_accel_triggers[i].name, 1349 indio_dev->name, 1350 indio_dev->id); 1351 if (!t->indio_trig) { 1352 ret = -ENOMEM; 1353 break; 1354 } 1355 1356 t->indio_trig->dev.parent = dev; 1357 t->indio_trig->ops = &bmc150_accel_trigger_ops; 1358 t->intr = bmc150_accel_triggers[i].intr; 1359 t->data = data; 1360 t->setup = bmc150_accel_triggers[i].setup; 1361 iio_trigger_set_drvdata(t->indio_trig, t); 1362 1363 ret = iio_trigger_register(t->indio_trig); 1364 if (ret) 1365 break; 1366 } 1367 1368 if (ret) 1369 bmc150_accel_unregister_triggers(data, i - 1); 1370 1371 return ret; 1372 } 1373 1374 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80 1375 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40 1376 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00 1377 1378 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data) 1379 { 1380 struct device *dev = regmap_get_device(data->regmap); 1381 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1; 1382 int ret; 1383 1384 ret = regmap_write(data->regmap, reg, data->fifo_mode); 1385 if (ret < 0) { 1386 dev_err(dev, "Error writing reg_fifo_config1\n"); 1387 return ret; 1388 } 1389 1390 if (!data->fifo_mode) 1391 return 0; 1392 1393 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0, 1394 data->watermark); 1395 if (ret < 0) 1396 dev_err(dev, "Error writing reg_fifo_config0\n"); 1397 1398 return ret; 1399 } 1400 1401 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev) 1402 { 1403 struct bmc150_accel_data *data = iio_priv(indio_dev); 1404 1405 return bmc150_accel_set_power_state(data, true); 1406 } 1407 1408 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev) 1409 { 1410 struct bmc150_accel_data *data = iio_priv(indio_dev); 1411 int ret = 0; 1412 1413 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) 1414 return iio_triggered_buffer_postenable(indio_dev); 1415 1416 mutex_lock(&data->mutex); 1417 1418 if (!data->watermark) 1419 goto out; 1420 1421 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, 1422 true); 1423 if (ret) 1424 goto out; 1425 1426 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO; 1427 1428 ret = bmc150_accel_fifo_set_mode(data); 1429 if (ret) { 1430 data->fifo_mode = 0; 1431 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, 1432 false); 1433 } 1434 1435 out: 1436 mutex_unlock(&data->mutex); 1437 1438 return ret; 1439 } 1440 1441 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev) 1442 { 1443 struct bmc150_accel_data *data = iio_priv(indio_dev); 1444 1445 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) 1446 return iio_triggered_buffer_predisable(indio_dev); 1447 1448 mutex_lock(&data->mutex); 1449 1450 if (!data->fifo_mode) 1451 goto out; 1452 1453 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false); 1454 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false); 1455 data->fifo_mode = 0; 1456 bmc150_accel_fifo_set_mode(data); 1457 1458 out: 1459 mutex_unlock(&data->mutex); 1460 1461 return 0; 1462 } 1463 1464 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev) 1465 { 1466 struct bmc150_accel_data *data = iio_priv(indio_dev); 1467 1468 return bmc150_accel_set_power_state(data, false); 1469 } 1470 1471 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = { 1472 .preenable = bmc150_accel_buffer_preenable, 1473 .postenable = bmc150_accel_buffer_postenable, 1474 .predisable = bmc150_accel_buffer_predisable, 1475 .postdisable = bmc150_accel_buffer_postdisable, 1476 }; 1477 1478 static int bmc150_accel_chip_init(struct bmc150_accel_data *data) 1479 { 1480 struct device *dev = regmap_get_device(data->regmap); 1481 int ret, i; 1482 unsigned int val; 1483 1484 /* 1485 * Reset chip to get it in a known good state. A delay of 1.8ms after 1486 * reset is required according to the data sheets of supported chips. 1487 */ 1488 regmap_write(data->regmap, BMC150_ACCEL_REG_RESET, 1489 BMC150_ACCEL_RESET_VAL); 1490 usleep_range(1800, 2500); 1491 1492 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val); 1493 if (ret < 0) { 1494 dev_err(dev, "Error: Reading chip id\n"); 1495 return ret; 1496 } 1497 1498 dev_dbg(dev, "Chip Id %x\n", val); 1499 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) { 1500 if (bmc150_accel_chip_info_tbl[i].chip_id == val) { 1501 data->chip_info = &bmc150_accel_chip_info_tbl[i]; 1502 break; 1503 } 1504 } 1505 1506 if (!data->chip_info) { 1507 dev_err(dev, "Invalid chip %x\n", val); 1508 return -ENODEV; 1509 } 1510 1511 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1512 if (ret < 0) 1513 return ret; 1514 1515 /* Set Bandwidth */ 1516 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0); 1517 if (ret < 0) 1518 return ret; 1519 1520 /* Set Default Range */ 1521 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE, 1522 BMC150_ACCEL_DEF_RANGE_4G); 1523 if (ret < 0) { 1524 dev_err(dev, "Error writing reg_pmu_range\n"); 1525 return ret; 1526 } 1527 1528 data->range = BMC150_ACCEL_DEF_RANGE_4G; 1529 1530 /* Set default slope duration and thresholds */ 1531 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD; 1532 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION; 1533 ret = bmc150_accel_update_slope(data); 1534 if (ret < 0) 1535 return ret; 1536 1537 /* Set default as latched interrupts */ 1538 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1539 BMC150_ACCEL_INT_MODE_LATCH_INT | 1540 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1541 if (ret < 0) { 1542 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1543 return ret; 1544 } 1545 1546 return 0; 1547 } 1548 1549 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq, 1550 const char *name, bool block_supported) 1551 { 1552 struct bmc150_accel_data *data; 1553 struct iio_dev *indio_dev; 1554 int ret; 1555 1556 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1557 if (!indio_dev) 1558 return -ENOMEM; 1559 1560 data = iio_priv(indio_dev); 1561 dev_set_drvdata(dev, indio_dev); 1562 data->irq = irq; 1563 1564 data->regmap = regmap; 1565 1566 ret = iio_read_mount_matrix(dev, "mount-matrix", 1567 &data->orientation); 1568 if (ret) 1569 return ret; 1570 1571 ret = bmc150_accel_chip_init(data); 1572 if (ret < 0) 1573 return ret; 1574 1575 mutex_init(&data->mutex); 1576 1577 indio_dev->dev.parent = dev; 1578 indio_dev->channels = data->chip_info->channels; 1579 indio_dev->num_channels = data->chip_info->num_channels; 1580 indio_dev->name = name ? name : data->chip_info->name; 1581 indio_dev->available_scan_masks = bmc150_accel_scan_masks; 1582 indio_dev->modes = INDIO_DIRECT_MODE; 1583 indio_dev->info = &bmc150_accel_info; 1584 1585 ret = iio_triggered_buffer_setup(indio_dev, 1586 &iio_pollfunc_store_time, 1587 bmc150_accel_trigger_handler, 1588 &bmc150_accel_buffer_ops); 1589 if (ret < 0) { 1590 dev_err(dev, "Failed: iio triggered buffer setup\n"); 1591 return ret; 1592 } 1593 1594 if (data->irq > 0) { 1595 ret = devm_request_threaded_irq( 1596 dev, data->irq, 1597 bmc150_accel_irq_handler, 1598 bmc150_accel_irq_thread_handler, 1599 IRQF_TRIGGER_RISING, 1600 BMC150_ACCEL_IRQ_NAME, 1601 indio_dev); 1602 if (ret) 1603 goto err_buffer_cleanup; 1604 1605 /* 1606 * Set latched mode interrupt. While certain interrupts are 1607 * non-latched regardless of this settings (e.g. new data) we 1608 * want to use latch mode when we can to prevent interrupt 1609 * flooding. 1610 */ 1611 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1612 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1613 if (ret < 0) { 1614 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1615 goto err_buffer_cleanup; 1616 } 1617 1618 bmc150_accel_interrupts_setup(indio_dev, data); 1619 1620 ret = bmc150_accel_triggers_setup(indio_dev, data); 1621 if (ret) 1622 goto err_buffer_cleanup; 1623 1624 if (block_supported) { 1625 indio_dev->modes |= INDIO_BUFFER_SOFTWARE; 1626 indio_dev->info = &bmc150_accel_info_fifo; 1627 iio_buffer_set_attrs(indio_dev->buffer, 1628 bmc150_accel_fifo_attributes); 1629 } 1630 } 1631 1632 ret = pm_runtime_set_active(dev); 1633 if (ret) 1634 goto err_trigger_unregister; 1635 1636 pm_runtime_enable(dev); 1637 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS); 1638 pm_runtime_use_autosuspend(dev); 1639 1640 ret = iio_device_register(indio_dev); 1641 if (ret < 0) { 1642 dev_err(dev, "Unable to register iio device\n"); 1643 goto err_trigger_unregister; 1644 } 1645 1646 return 0; 1647 1648 err_trigger_unregister: 1649 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); 1650 err_buffer_cleanup: 1651 iio_triggered_buffer_cleanup(indio_dev); 1652 1653 return ret; 1654 } 1655 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe); 1656 1657 int bmc150_accel_core_remove(struct device *dev) 1658 { 1659 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1660 struct bmc150_accel_data *data = iio_priv(indio_dev); 1661 1662 iio_device_unregister(indio_dev); 1663 1664 pm_runtime_disable(dev); 1665 pm_runtime_set_suspended(dev); 1666 pm_runtime_put_noidle(dev); 1667 1668 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); 1669 1670 iio_triggered_buffer_cleanup(indio_dev); 1671 1672 mutex_lock(&data->mutex); 1673 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0); 1674 mutex_unlock(&data->mutex); 1675 1676 return 0; 1677 } 1678 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove); 1679 1680 #ifdef CONFIG_PM_SLEEP 1681 static int bmc150_accel_suspend(struct device *dev) 1682 { 1683 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1684 struct bmc150_accel_data *data = iio_priv(indio_dev); 1685 1686 mutex_lock(&data->mutex); 1687 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); 1688 mutex_unlock(&data->mutex); 1689 1690 return 0; 1691 } 1692 1693 static int bmc150_accel_resume(struct device *dev) 1694 { 1695 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1696 struct bmc150_accel_data *data = iio_priv(indio_dev); 1697 1698 mutex_lock(&data->mutex); 1699 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1700 bmc150_accel_fifo_set_mode(data); 1701 mutex_unlock(&data->mutex); 1702 1703 return 0; 1704 } 1705 #endif 1706 1707 #ifdef CONFIG_PM 1708 static int bmc150_accel_runtime_suspend(struct device *dev) 1709 { 1710 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1711 struct bmc150_accel_data *data = iio_priv(indio_dev); 1712 int ret; 1713 1714 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); 1715 if (ret < 0) 1716 return -EAGAIN; 1717 1718 return 0; 1719 } 1720 1721 static int bmc150_accel_runtime_resume(struct device *dev) 1722 { 1723 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1724 struct bmc150_accel_data *data = iio_priv(indio_dev); 1725 int ret; 1726 int sleep_val; 1727 1728 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1729 if (ret < 0) 1730 return ret; 1731 ret = bmc150_accel_fifo_set_mode(data); 1732 if (ret < 0) 1733 return ret; 1734 1735 sleep_val = bmc150_accel_get_startup_times(data); 1736 if (sleep_val < 20) 1737 usleep_range(sleep_val * 1000, 20000); 1738 else 1739 msleep_interruptible(sleep_val); 1740 1741 return 0; 1742 } 1743 #endif 1744 1745 const struct dev_pm_ops bmc150_accel_pm_ops = { 1746 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume) 1747 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend, 1748 bmc150_accel_runtime_resume, NULL) 1749 }; 1750 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops); 1751 1752 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); 1753 MODULE_LICENSE("GPL v2"); 1754 MODULE_DESCRIPTION("BMC150 accelerometer driver"); 1755