1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Core IIO driver for Bosch BMA400 triaxial acceleration sensor. 4 * 5 * Copyright 2019 Dan Robertson <dan@dlrobertson.com> 6 * 7 * TODO: 8 * - Support for power management 9 * - Support events and interrupts 10 * - Create channel for step count 11 * - Create channel for sensor time 12 */ 13 14 #include <linux/bitfield.h> 15 #include <linux/bitops.h> 16 #include <linux/cleanup.h> 17 #include <linux/device.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/mutex.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 25 #include <linux/unaligned.h> 26 27 #include <linux/iio/iio.h> 28 #include <linux/iio/buffer.h> 29 #include <linux/iio/events.h> 30 #include <linux/iio/sysfs.h> 31 #include <linux/iio/trigger.h> 32 #include <linux/iio/trigger_consumer.h> 33 #include <linux/iio/triggered_buffer.h> 34 35 #include "bma400.h" 36 37 /* 38 * The G-range selection may be one of 2g, 4g, 8, or 16g. The scale may 39 * be selected with the acc_range bits of the ACC_CONFIG1 register. 40 * NB: This buffer is populated in the device init. 41 */ 42 static int bma400_scales[8]; 43 44 /* 45 * See the ACC_CONFIG1 section of the datasheet. 46 * NB: This buffer is populated in the device init. 47 */ 48 static int bma400_sample_freqs[14]; 49 50 static const int bma400_osr_range[] = { 0, 1, 3 }; 51 52 static int tap_reset_timeout[BMA400_TAP_TIM_LIST_LEN] = { 53 300000, 54 400000, 55 500000, 56 600000 57 }; 58 59 static int tap_max2min_time[BMA400_TAP_TIM_LIST_LEN] = { 60 30000, 61 45000, 62 60000, 63 90000 64 }; 65 66 static int double_tap2_min_delay[BMA400_TAP_TIM_LIST_LEN] = { 67 20000, 68 40000, 69 60000, 70 80000 71 }; 72 73 /* See the ACC_CONFIG0 section of the datasheet */ 74 enum bma400_power_mode { 75 POWER_MODE_SLEEP = 0x00, 76 POWER_MODE_LOW = 0x01, 77 POWER_MODE_NORMAL = 0x02, 78 POWER_MODE_INVALID = 0x03, 79 }; 80 81 enum bma400_scan { 82 BMA400_ACCL_X, 83 BMA400_ACCL_Y, 84 BMA400_ACCL_Z, 85 BMA400_TEMP, 86 }; 87 88 struct bma400_sample_freq { 89 int hz; 90 int uhz; 91 }; 92 93 enum bma400_activity { 94 BMA400_STILL, 95 BMA400_WALKING, 96 BMA400_RUNNING, 97 }; 98 99 struct bma400_data { 100 struct device *dev; 101 struct regmap *regmap; 102 struct mutex mutex; /* data register lock */ 103 struct iio_mount_matrix orientation; 104 enum bma400_power_mode power_mode; 105 struct bma400_sample_freq sample_freq; 106 int oversampling_ratio; 107 int scale; 108 struct iio_trigger *trig; 109 int steps_enabled; 110 bool step_event_en; 111 bool activity_event_en; 112 unsigned int generic_event_en; 113 unsigned int tap_event_en_bitmask; 114 /* Correct time stamp alignment */ 115 struct { 116 __le16 buff[3]; 117 u8 temperature; 118 aligned_s64 ts; 119 } buffer __aligned(IIO_DMA_MINALIGN); 120 __le16 status; 121 __be16 duration; 122 }; 123 124 struct bma400_genintr_info { 125 enum bma400_generic_intr genintr; 126 unsigned int intrmask; 127 enum iio_event_direction dir; 128 enum bma400_detect_criterion detect_mode; 129 }; 130 131 /* Lookup struct for determining GEN1/GEN2 based on dir */ 132 static const struct bma400_genintr_info bma400_genintrs[] = { 133 [IIO_EV_DIR_RISING] = { 134 .genintr = BMA400_GEN1_INTR, 135 .intrmask = BMA400_INT_CONFIG0_GEN1_MASK, 136 .dir = IIO_EV_DIR_RISING, 137 .detect_mode = BMA400_DETECT_ACTIVITY, 138 }, 139 [IIO_EV_DIR_FALLING] = { 140 .genintr = BMA400_GEN2_INTR, 141 .intrmask = BMA400_INT_CONFIG0_GEN2_MASK, 142 .dir = IIO_EV_DIR_FALLING, 143 .detect_mode = BMA400_DETECT_INACTIVITY, 144 } 145 }; 146 147 static inline const struct bma400_genintr_info * 148 get_bma400_genintr_info(enum iio_event_direction dir) 149 { 150 switch (dir) { 151 case IIO_EV_DIR_RISING: 152 case IIO_EV_DIR_FALLING: 153 return &bma400_genintrs[dir]; 154 default: 155 return NULL; 156 }; 157 } 158 159 static bool bma400_is_writable_reg(struct device *dev, unsigned int reg) 160 { 161 switch (reg) { 162 case BMA400_CHIP_ID_REG: 163 case BMA400_ERR_REG: 164 case BMA400_STATUS_REG: 165 case BMA400_ACC_X_LSB_REG: 166 case BMA400_ACC_X_MSB_REG: 167 case BMA400_ACC_Y_LSB_REG: 168 case BMA400_ACC_Y_MSB_REG: 169 case BMA400_ACC_Z_LSB_REG: 170 case BMA400_ACC_Z_MSB_REG: 171 case BMA400_SENSOR_TIME0_REG: 172 case BMA400_SENSOR_TIME1_REG: 173 case BMA400_SENSOR_TIME2_REG: 174 case BMA400_EVENT_REG: 175 case BMA400_INT_STAT0_REG: 176 case BMA400_INT_STAT1_REG: 177 case BMA400_INT_STAT2_REG: 178 case BMA400_TEMP_DATA_REG: 179 case BMA400_FIFO_LENGTH0_REG: 180 case BMA400_FIFO_LENGTH1_REG: 181 case BMA400_FIFO_DATA_REG: 182 case BMA400_STEP_CNT0_REG: 183 case BMA400_STEP_CNT1_REG: 184 case BMA400_STEP_CNT3_REG: 185 case BMA400_STEP_STAT_REG: 186 return false; 187 default: 188 return true; 189 } 190 } 191 192 static bool bma400_is_volatile_reg(struct device *dev, unsigned int reg) 193 { 194 switch (reg) { 195 case BMA400_ERR_REG: 196 case BMA400_STATUS_REG: 197 case BMA400_ACC_X_LSB_REG: 198 case BMA400_ACC_X_MSB_REG: 199 case BMA400_ACC_Y_LSB_REG: 200 case BMA400_ACC_Y_MSB_REG: 201 case BMA400_ACC_Z_LSB_REG: 202 case BMA400_ACC_Z_MSB_REG: 203 case BMA400_SENSOR_TIME0_REG: 204 case BMA400_SENSOR_TIME1_REG: 205 case BMA400_SENSOR_TIME2_REG: 206 case BMA400_EVENT_REG: 207 case BMA400_INT_STAT0_REG: 208 case BMA400_INT_STAT1_REG: 209 case BMA400_INT_STAT2_REG: 210 case BMA400_TEMP_DATA_REG: 211 case BMA400_FIFO_LENGTH0_REG: 212 case BMA400_FIFO_LENGTH1_REG: 213 case BMA400_FIFO_DATA_REG: 214 case BMA400_STEP_CNT0_REG: 215 case BMA400_STEP_CNT1_REG: 216 case BMA400_STEP_CNT3_REG: 217 case BMA400_STEP_STAT_REG: 218 return true; 219 default: 220 return false; 221 } 222 } 223 224 const struct regmap_config bma400_regmap_config = { 225 .reg_bits = 8, 226 .val_bits = 8, 227 .max_register = BMA400_CMD_REG, 228 .cache_type = REGCACHE_MAPLE, 229 .writeable_reg = bma400_is_writable_reg, 230 .volatile_reg = bma400_is_volatile_reg, 231 }; 232 EXPORT_SYMBOL_NS(bma400_regmap_config, "IIO_BMA400"); 233 234 static const struct iio_mount_matrix * 235 bma400_accel_get_mount_matrix(const struct iio_dev *indio_dev, 236 const struct iio_chan_spec *chan) 237 { 238 struct bma400_data *data = iio_priv(indio_dev); 239 240 return &data->orientation; 241 } 242 243 static const struct iio_chan_spec_ext_info bma400_ext_info[] = { 244 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bma400_accel_get_mount_matrix), 245 { } 246 }; 247 248 static const struct iio_event_spec bma400_step_detect_event = { 249 .type = IIO_EV_TYPE_CHANGE, 250 .dir = IIO_EV_DIR_NONE, 251 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 252 }; 253 254 static const struct iio_event_spec bma400_activity_event = { 255 .type = IIO_EV_TYPE_CHANGE, 256 .dir = IIO_EV_DIR_NONE, 257 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE), 258 }; 259 260 static const struct iio_event_spec bma400_accel_event[] = { 261 { 262 .type = IIO_EV_TYPE_MAG, 263 .dir = IIO_EV_DIR_FALLING, 264 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 265 BIT(IIO_EV_INFO_PERIOD) | 266 BIT(IIO_EV_INFO_HYSTERESIS) | 267 BIT(IIO_EV_INFO_ENABLE), 268 }, 269 { 270 .type = IIO_EV_TYPE_MAG, 271 .dir = IIO_EV_DIR_RISING, 272 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 273 BIT(IIO_EV_INFO_PERIOD) | 274 BIT(IIO_EV_INFO_HYSTERESIS) | 275 BIT(IIO_EV_INFO_ENABLE), 276 }, 277 { 278 .type = IIO_EV_TYPE_GESTURE, 279 .dir = IIO_EV_DIR_SINGLETAP, 280 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 281 BIT(IIO_EV_INFO_ENABLE) | 282 BIT(IIO_EV_INFO_RESET_TIMEOUT), 283 }, 284 { 285 .type = IIO_EV_TYPE_GESTURE, 286 .dir = IIO_EV_DIR_DOUBLETAP, 287 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 288 BIT(IIO_EV_INFO_ENABLE) | 289 BIT(IIO_EV_INFO_RESET_TIMEOUT) | 290 BIT(IIO_EV_INFO_TAP2_MIN_DELAY), 291 }, 292 }; 293 294 static int usec_to_tapreg_raw(int usec, const int *time_list) 295 { 296 int index; 297 298 for (index = 0; index < BMA400_TAP_TIM_LIST_LEN; index++) { 299 if (usec == time_list[index]) 300 return index; 301 } 302 return -EINVAL; 303 } 304 305 static ssize_t in_accel_gesture_tap_maxtomin_time_show(struct device *dev, 306 struct device_attribute *attr, 307 char *buf) 308 { 309 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 310 struct bma400_data *data = iio_priv(indio_dev); 311 int ret, reg_val, raw, vals[2]; 312 313 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1_REG, ®_val); 314 if (ret) 315 return ret; 316 317 raw = FIELD_GET(BMA400_TAP_CONFIG1_TICSTH_MASK, reg_val); 318 vals[0] = 0; 319 vals[1] = tap_max2min_time[raw]; 320 321 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals); 322 } 323 324 static ssize_t in_accel_gesture_tap_maxtomin_time_store(struct device *dev, 325 struct device_attribute *attr, 326 const char *buf, size_t len) 327 { 328 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 329 struct bma400_data *data = iio_priv(indio_dev); 330 int ret, val_int, val_fract, raw; 331 332 ret = iio_str_to_fixpoint(buf, 100000, &val_int, &val_fract); 333 if (ret) 334 return ret; 335 336 raw = usec_to_tapreg_raw(val_fract, tap_max2min_time); 337 if (raw < 0) 338 return -EINVAL; 339 340 ret = regmap_update_bits(data->regmap, BMA400_TAP_CONFIG1_REG, 341 BMA400_TAP_CONFIG1_TICSTH_MASK, 342 FIELD_PREP(BMA400_TAP_CONFIG1_TICSTH_MASK, raw)); 343 if (ret) 344 return ret; 345 346 return len; 347 } 348 349 static IIO_DEVICE_ATTR_RW(in_accel_gesture_tap_maxtomin_time, 0); 350 351 /* 352 * Tap interrupts works with 200 Hz input data rate and the time based tap 353 * controls are in the terms of data samples so the below calculation is 354 * used to convert the configuration values into seconds. 355 * e.g.: 356 * 60 data samples * 0.005 ms = 0.3 seconds. 357 * 80 data samples * 0.005 ms = 0.4 seconds. 358 */ 359 360 /* quiet configuration values in seconds */ 361 static IIO_CONST_ATTR(in_accel_gesture_tap_reset_timeout_available, 362 "0.3 0.4 0.5 0.6"); 363 364 /* tics_th configuration values in seconds */ 365 static IIO_CONST_ATTR(in_accel_gesture_tap_maxtomin_time_available, 366 "0.03 0.045 0.06 0.09"); 367 368 /* quiet_dt configuration values in seconds */ 369 static IIO_CONST_ATTR(in_accel_gesture_doubletap_tap2_min_delay_available, 370 "0.02 0.04 0.06 0.08"); 371 372 /* List of sensitivity values available to configure tap interrupts */ 373 static IIO_CONST_ATTR(in_accel_gesture_tap_value_available, "0 1 2 3 4 5 6 7"); 374 375 static struct attribute *bma400_event_attributes[] = { 376 &iio_const_attr_in_accel_gesture_tap_value_available.dev_attr.attr, 377 &iio_const_attr_in_accel_gesture_tap_reset_timeout_available.dev_attr.attr, 378 &iio_const_attr_in_accel_gesture_tap_maxtomin_time_available.dev_attr.attr, 379 &iio_const_attr_in_accel_gesture_doubletap_tap2_min_delay_available.dev_attr.attr, 380 &iio_dev_attr_in_accel_gesture_tap_maxtomin_time.dev_attr.attr, 381 NULL 382 }; 383 384 static const struct attribute_group bma400_event_attribute_group = { 385 .attrs = bma400_event_attributes, 386 }; 387 388 #define BMA400_ACC_CHANNEL(_index, _axis) { \ 389 .type = IIO_ACCEL, \ 390 .modified = 1, \ 391 .channel2 = IIO_MOD_##_axis, \ 392 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 393 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 394 BIT(IIO_CHAN_INFO_SCALE) | \ 395 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 396 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 397 BIT(IIO_CHAN_INFO_SCALE) | \ 398 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 399 .ext_info = bma400_ext_info, \ 400 .scan_index = _index, \ 401 .scan_type = { \ 402 .sign = 's', \ 403 .realbits = 12, \ 404 .storagebits = 16, \ 405 .endianness = IIO_LE, \ 406 }, \ 407 .event_spec = bma400_accel_event, \ 408 .num_event_specs = ARRAY_SIZE(bma400_accel_event) \ 409 } 410 411 #define BMA400_ACTIVITY_CHANNEL(_chan2) { \ 412 .type = IIO_ACTIVITY, \ 413 .modified = 1, \ 414 .channel2 = _chan2, \ 415 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ 416 .scan_index = -1, /* No buffer support */ \ 417 .event_spec = &bma400_activity_event, \ 418 .num_event_specs = 1, \ 419 } 420 421 static const struct iio_chan_spec bma400_channels[] = { 422 BMA400_ACC_CHANNEL(0, X), 423 BMA400_ACC_CHANNEL(1, Y), 424 BMA400_ACC_CHANNEL(2, Z), 425 { 426 .type = IIO_TEMP, 427 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), 428 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), 429 .scan_index = 3, 430 .scan_type = { 431 .sign = 's', 432 .realbits = 8, 433 .storagebits = 8, 434 .endianness = IIO_LE, 435 }, 436 }, 437 { 438 .type = IIO_STEPS, 439 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | 440 BIT(IIO_CHAN_INFO_ENABLE), 441 .scan_index = -1, /* No buffer support */ 442 .event_spec = &bma400_step_detect_event, 443 .num_event_specs = 1, 444 }, 445 BMA400_ACTIVITY_CHANNEL(IIO_MOD_STILL), 446 BMA400_ACTIVITY_CHANNEL(IIO_MOD_WALKING), 447 BMA400_ACTIVITY_CHANNEL(IIO_MOD_RUNNING), 448 IIO_CHAN_SOFT_TIMESTAMP(4), 449 }; 450 451 static int bma400_get_temp_reg(struct bma400_data *data, int *val, int *val2) 452 { 453 unsigned int raw_temp; 454 int host_temp; 455 int ret; 456 457 if (data->power_mode == POWER_MODE_SLEEP) 458 return -EBUSY; 459 460 ret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &raw_temp); 461 if (ret) 462 return ret; 463 464 host_temp = sign_extend32(raw_temp, 7); 465 /* 466 * The formula for the TEMP_DATA register in the datasheet 467 * is: x * 0.5 + 23 468 */ 469 *val = (host_temp >> 1) + 23; 470 *val2 = (host_temp & 0x1) * 500000; 471 return IIO_VAL_INT_PLUS_MICRO; 472 } 473 474 static int bma400_get_accel_reg(struct bma400_data *data, 475 const struct iio_chan_spec *chan, 476 int *val) 477 { 478 __le16 raw_accel; 479 int lsb_reg; 480 int ret; 481 482 if (data->power_mode == POWER_MODE_SLEEP) 483 return -EBUSY; 484 485 switch (chan->channel2) { 486 case IIO_MOD_X: 487 lsb_reg = BMA400_ACC_X_LSB_REG; 488 break; 489 case IIO_MOD_Y: 490 lsb_reg = BMA400_ACC_Y_LSB_REG; 491 break; 492 case IIO_MOD_Z: 493 lsb_reg = BMA400_ACC_Z_LSB_REG; 494 break; 495 default: 496 dev_err(data->dev, "invalid axis channel modifier\n"); 497 return -EINVAL; 498 } 499 500 /* bulk read two registers, with the base being the LSB register */ 501 ret = regmap_bulk_read(data->regmap, lsb_reg, &raw_accel, 502 sizeof(raw_accel)); 503 if (ret) 504 return ret; 505 506 *val = sign_extend32(le16_to_cpu(raw_accel), 11); 507 return IIO_VAL_INT; 508 } 509 510 static void bma400_output_data_rate_from_raw(int raw, unsigned int *val, 511 unsigned int *val2) 512 { 513 *val = BMA400_ACC_CONFIG1_ODR_MAX_HZ >> (BMA400_ACC_CONFIG1_ODR_MAX_RAW - raw); 514 if (raw > BMA400_ACC_CONFIG1_ODR_MIN_RAW) 515 *val2 = 0; 516 else 517 *val2 = 500000; 518 } 519 520 static int bma400_get_accel_output_data_rate(struct bma400_data *data) 521 { 522 unsigned int val; 523 unsigned int odr; 524 int ret; 525 526 switch (data->power_mode) { 527 case POWER_MODE_LOW: 528 /* 529 * Runs at a fixed rate in low-power mode. See section 4.3 530 * in the datasheet. 531 */ 532 bma400_output_data_rate_from_raw(BMA400_ACC_CONFIG1_ODR_LP_RAW, 533 &data->sample_freq.hz, 534 &data->sample_freq.uhz); 535 return 0; 536 case POWER_MODE_NORMAL: 537 /* 538 * In normal mode the ODR can be found in the ACC_CONFIG1 539 * register. 540 */ 541 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val); 542 if (ret) 543 goto error; 544 545 odr = val & BMA400_ACC_CONFIG1_ODR_MASK; 546 if (odr < BMA400_ACC_CONFIG1_ODR_MIN_RAW || 547 odr > BMA400_ACC_CONFIG1_ODR_MAX_RAW) { 548 ret = -EINVAL; 549 goto error; 550 } 551 552 bma400_output_data_rate_from_raw(odr, &data->sample_freq.hz, 553 &data->sample_freq.uhz); 554 return 0; 555 case POWER_MODE_SLEEP: 556 data->sample_freq.hz = 0; 557 data->sample_freq.uhz = 0; 558 return 0; 559 default: 560 ret = 0; 561 goto error; 562 } 563 error: 564 data->sample_freq.hz = -1; 565 data->sample_freq.uhz = -1; 566 return ret; 567 } 568 569 static int bma400_set_accel_output_data_rate(struct bma400_data *data, 570 int hz, int uhz) 571 { 572 unsigned int idx; 573 unsigned int odr; 574 unsigned int val; 575 int ret; 576 577 if (hz >= BMA400_ACC_CONFIG1_ODR_MIN_WHOLE_HZ) { 578 if (uhz || hz > BMA400_ACC_CONFIG1_ODR_MAX_HZ) 579 return -EINVAL; 580 581 /* Note this works because MIN_WHOLE_HZ is odd */ 582 idx = __ffs(hz); 583 584 if (hz >> idx != BMA400_ACC_CONFIG1_ODR_MIN_WHOLE_HZ) 585 return -EINVAL; 586 587 idx += BMA400_ACC_CONFIG1_ODR_MIN_RAW + 1; 588 } else if (hz == BMA400_ACC_CONFIG1_ODR_MIN_HZ && uhz == 500000) { 589 idx = BMA400_ACC_CONFIG1_ODR_MIN_RAW; 590 } else { 591 return -EINVAL; 592 } 593 594 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val); 595 if (ret) 596 return ret; 597 598 /* preserve the range and normal mode osr */ 599 odr = (~BMA400_ACC_CONFIG1_ODR_MASK & val) | idx; 600 601 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, odr); 602 if (ret) 603 return ret; 604 605 bma400_output_data_rate_from_raw(idx, &data->sample_freq.hz, 606 &data->sample_freq.uhz); 607 return 0; 608 } 609 610 static int bma400_get_accel_oversampling_ratio(struct bma400_data *data) 611 { 612 unsigned int val; 613 unsigned int osr; 614 int ret; 615 616 /* 617 * The oversampling ratio is stored in a different register 618 * based on the power-mode. In normal mode the OSR is stored 619 * in ACC_CONFIG1. In low-power mode it is stored in 620 * ACC_CONFIG0. 621 */ 622 switch (data->power_mode) { 623 case POWER_MODE_LOW: 624 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val); 625 if (ret) { 626 data->oversampling_ratio = -1; 627 return ret; 628 } 629 630 osr = FIELD_GET(BMA400_ACC_CONFIG0_LP_OSR_MASK, val); 631 632 data->oversampling_ratio = osr; 633 return 0; 634 case POWER_MODE_NORMAL: 635 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val); 636 if (ret) { 637 data->oversampling_ratio = -1; 638 return ret; 639 } 640 641 osr = FIELD_GET(BMA400_ACC_CONFIG1_NP_OSR_MASK, val); 642 643 data->oversampling_ratio = osr; 644 return 0; 645 case POWER_MODE_SLEEP: 646 data->oversampling_ratio = 0; 647 return 0; 648 default: 649 data->oversampling_ratio = -1; 650 return -EINVAL; 651 } 652 } 653 654 static int bma400_set_accel_oversampling_ratio(struct bma400_data *data, 655 int val) 656 { 657 unsigned int acc_config; 658 int ret; 659 660 if (val & ~BMA400_TWO_BITS_MASK) 661 return -EINVAL; 662 663 /* 664 * The oversampling ratio is stored in a different register 665 * based on the power-mode. 666 */ 667 switch (data->power_mode) { 668 case POWER_MODE_LOW: 669 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, 670 &acc_config); 671 if (ret) 672 return ret; 673 674 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG, 675 (acc_config & ~BMA400_ACC_CONFIG0_LP_OSR_MASK) | 676 FIELD_PREP(BMA400_ACC_CONFIG0_LP_OSR_MASK, val)); 677 if (ret) { 678 dev_err(data->dev, "Failed to write out OSR\n"); 679 return ret; 680 } 681 682 data->oversampling_ratio = val; 683 return 0; 684 case POWER_MODE_NORMAL: 685 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, 686 &acc_config); 687 if (ret) 688 return ret; 689 690 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, 691 (acc_config & ~BMA400_ACC_CONFIG1_NP_OSR_MASK) | 692 FIELD_PREP(BMA400_ACC_CONFIG1_NP_OSR_MASK, val)); 693 if (ret) { 694 dev_err(data->dev, "Failed to write out OSR\n"); 695 return ret; 696 } 697 698 data->oversampling_ratio = val; 699 return 0; 700 default: 701 return -EINVAL; 702 } 703 return ret; 704 } 705 706 static int bma400_accel_scale_to_raw(struct bma400_data *data, 707 unsigned int val) 708 { 709 int raw; 710 711 if (val == 0) 712 return -EINVAL; 713 714 /* Note this works because BMA400_SCALE_MIN is odd */ 715 raw = __ffs(val); 716 717 if (val >> raw != BMA400_ACC_SCALE_MIN) 718 return -EINVAL; 719 720 return raw; 721 } 722 723 static int bma400_get_accel_scale(struct bma400_data *data) 724 { 725 unsigned int raw_scale; 726 unsigned int val; 727 int ret; 728 729 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val); 730 if (ret) 731 return ret; 732 733 raw_scale = FIELD_GET(BMA400_ACC_CONFIG1_ACC_RANGE_MASK, val); 734 if (raw_scale > BMA400_TWO_BITS_MASK) 735 return -EINVAL; 736 737 data->scale = BMA400_ACC_SCALE_MIN << raw_scale; 738 739 return 0; 740 } 741 742 static int bma400_set_accel_scale(struct bma400_data *data, unsigned int val) 743 { 744 unsigned int acc_config; 745 int raw; 746 int ret; 747 748 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &acc_config); 749 if (ret) 750 return ret; 751 752 raw = bma400_accel_scale_to_raw(data, val); 753 if (raw < 0) 754 return raw; 755 756 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, 757 (acc_config & ~BMA400_ACC_CONFIG1_ACC_RANGE_MASK) | 758 FIELD_PREP(BMA400_ACC_CONFIG1_ACC_RANGE_MASK, raw)); 759 if (ret) 760 return ret; 761 762 data->scale = val; 763 return 0; 764 } 765 766 static int bma400_get_power_mode(struct bma400_data *data) 767 { 768 unsigned int val; 769 int ret; 770 771 ret = regmap_read(data->regmap, BMA400_STATUS_REG, &val); 772 if (ret) { 773 dev_err(data->dev, "Failed to read status register\n"); 774 return ret; 775 } 776 777 data->power_mode = (val >> 1) & BMA400_TWO_BITS_MASK; 778 return 0; 779 } 780 781 static int bma400_set_power_mode(struct bma400_data *data, 782 enum bma400_power_mode mode) 783 { 784 unsigned int val; 785 int ret; 786 787 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val); 788 if (ret) 789 return ret; 790 791 if (data->power_mode == mode) 792 return 0; 793 794 if (mode == POWER_MODE_INVALID) 795 return -EINVAL; 796 797 /* Preserve the low-power oversample ratio etc */ 798 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG, 799 mode | (val & ~BMA400_TWO_BITS_MASK)); 800 if (ret) { 801 dev_err(data->dev, "Failed to write to power-mode\n"); 802 return ret; 803 } 804 805 data->power_mode = mode; 806 807 /* 808 * Update our cached osr and odr based on the new 809 * power-mode. 810 */ 811 bma400_get_accel_output_data_rate(data); 812 bma400_get_accel_oversampling_ratio(data); 813 return 0; 814 } 815 816 static int bma400_enable_steps(struct bma400_data *data, int val) 817 { 818 int ret; 819 820 if (data->steps_enabled == val) 821 return 0; 822 823 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG, 824 BMA400_INT_CONFIG1_STEP_INT_MASK, 825 FIELD_PREP(BMA400_INT_CONFIG1_STEP_INT_MASK, val ? 1 : 0)); 826 if (ret) 827 return ret; 828 data->steps_enabled = val; 829 return ret; 830 } 831 832 static int bma400_get_steps_reg(struct bma400_data *data, int *val) 833 { 834 int ret; 835 836 u8 *steps_raw __free(kfree) = kmalloc(BMA400_STEP_RAW_LEN, GFP_KERNEL); 837 if (!steps_raw) 838 return -ENOMEM; 839 840 ret = regmap_bulk_read(data->regmap, BMA400_STEP_CNT0_REG, 841 steps_raw, BMA400_STEP_RAW_LEN); 842 if (ret) 843 return ret; 844 845 *val = get_unaligned_le24(steps_raw); 846 847 return IIO_VAL_INT; 848 } 849 850 static void bma400_init_tables(void) 851 { 852 int raw; 853 int i; 854 855 for (i = 0; i + 1 < ARRAY_SIZE(bma400_sample_freqs); i += 2) { 856 raw = (i / 2) + 5; 857 bma400_output_data_rate_from_raw(raw, &bma400_sample_freqs[i], 858 &bma400_sample_freqs[i + 1]); 859 } 860 861 for (i = 0; i + 1 < ARRAY_SIZE(bma400_scales); i += 2) { 862 raw = i / 2; 863 bma400_scales[i] = 0; 864 bma400_scales[i + 1] = BMA400_ACC_SCALE_MIN << raw; 865 } 866 } 867 868 static void bma400_power_disable(void *data_ptr) 869 { 870 struct bma400_data *data = data_ptr; 871 int ret; 872 873 mutex_lock(&data->mutex); 874 ret = bma400_set_power_mode(data, POWER_MODE_SLEEP); 875 mutex_unlock(&data->mutex); 876 if (ret) 877 dev_warn(data->dev, "Failed to put device into sleep mode (%pe)\n", 878 ERR_PTR(ret)); 879 } 880 881 static enum iio_modifier bma400_act_to_mod(enum bma400_activity activity) 882 { 883 switch (activity) { 884 case BMA400_STILL: 885 return IIO_MOD_STILL; 886 case BMA400_WALKING: 887 return IIO_MOD_WALKING; 888 case BMA400_RUNNING: 889 return IIO_MOD_RUNNING; 890 default: 891 return IIO_NO_MOD; 892 } 893 } 894 895 static int bma400_init(struct bma400_data *data) 896 { 897 static const char * const regulator_names[] = { "vdd", "vddio" }; 898 unsigned int val; 899 int ret; 900 901 ret = devm_regulator_bulk_get_enable(data->dev, 902 ARRAY_SIZE(regulator_names), 903 regulator_names); 904 if (ret) 905 return dev_err_probe(data->dev, ret, "Failed to get regulators\n"); 906 907 /* Try to read chip_id register. It must return 0x90. */ 908 ret = regmap_read(data->regmap, BMA400_CHIP_ID_REG, &val); 909 if (ret) { 910 dev_err(data->dev, "Failed to read chip id register\n"); 911 return ret; 912 } 913 914 if (val != BMA400_ID_REG_VAL) { 915 dev_err(data->dev, "Chip ID mismatch\n"); 916 return -ENODEV; 917 } 918 919 ret = bma400_get_power_mode(data); 920 if (ret) { 921 dev_err(data->dev, "Failed to get the initial power-mode\n"); 922 return ret; 923 } 924 925 if (data->power_mode != POWER_MODE_NORMAL) { 926 ret = bma400_set_power_mode(data, POWER_MODE_NORMAL); 927 if (ret) { 928 dev_err(data->dev, "Failed to wake up the device\n"); 929 return ret; 930 } 931 /* 932 * TODO: The datasheet waits 1500us here in the example, but 933 * lists 2/ODR as the wakeup time. 934 */ 935 usleep_range(1500, 2000); 936 } 937 938 ret = devm_add_action_or_reset(data->dev, bma400_power_disable, data); 939 if (ret) 940 return ret; 941 942 bma400_init_tables(); 943 944 ret = bma400_get_accel_output_data_rate(data); 945 if (ret) 946 return ret; 947 948 ret = bma400_get_accel_oversampling_ratio(data); 949 if (ret) 950 return ret; 951 952 ret = bma400_get_accel_scale(data); 953 if (ret) 954 return ret; 955 956 /* Configure INT1 pin to open drain */ 957 ret = regmap_write(data->regmap, BMA400_INT_IO_CTRL_REG, 0x06); 958 if (ret) 959 return ret; 960 /* 961 * Once the interrupt engine is supported we might use the 962 * data_src_reg, but for now ensure this is set to the 963 * variable ODR filter selectable by the sample frequency 964 * channel. 965 */ 966 return regmap_write(data->regmap, BMA400_ACC_CONFIG2_REG, 0x00); 967 } 968 969 static int bma400_read_raw(struct iio_dev *indio_dev, 970 struct iio_chan_spec const *chan, int *val, 971 int *val2, long mask) 972 { 973 struct bma400_data *data = iio_priv(indio_dev); 974 unsigned int activity; 975 int ret; 976 977 switch (mask) { 978 case IIO_CHAN_INFO_PROCESSED: 979 switch (chan->type) { 980 case IIO_TEMP: 981 mutex_lock(&data->mutex); 982 ret = bma400_get_temp_reg(data, val, val2); 983 mutex_unlock(&data->mutex); 984 return ret; 985 case IIO_STEPS: 986 return bma400_get_steps_reg(data, val); 987 case IIO_ACTIVITY: 988 ret = regmap_read(data->regmap, BMA400_STEP_STAT_REG, 989 &activity); 990 if (ret) 991 return ret; 992 /* 993 * The device does not support confidence value levels, 994 * so we will always have 100% for current activity and 995 * 0% for the others. 996 */ 997 if (chan->channel2 == bma400_act_to_mod(activity)) 998 *val = 100; 999 else 1000 *val = 0; 1001 return IIO_VAL_INT; 1002 default: 1003 return -EINVAL; 1004 } 1005 case IIO_CHAN_INFO_RAW: 1006 mutex_lock(&data->mutex); 1007 ret = bma400_get_accel_reg(data, chan, val); 1008 mutex_unlock(&data->mutex); 1009 return ret; 1010 case IIO_CHAN_INFO_SAMP_FREQ: 1011 switch (chan->type) { 1012 case IIO_ACCEL: 1013 if (data->sample_freq.hz < 0) 1014 return -EINVAL; 1015 1016 *val = data->sample_freq.hz; 1017 *val2 = data->sample_freq.uhz; 1018 return IIO_VAL_INT_PLUS_MICRO; 1019 case IIO_TEMP: 1020 /* 1021 * Runs at a fixed sampling frequency. See Section 4.4 1022 * of the datasheet. 1023 */ 1024 *val = 6; 1025 *val2 = 250000; 1026 return IIO_VAL_INT_PLUS_MICRO; 1027 default: 1028 return -EINVAL; 1029 } 1030 case IIO_CHAN_INFO_SCALE: 1031 *val = 0; 1032 *val2 = data->scale; 1033 return IIO_VAL_INT_PLUS_MICRO; 1034 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1035 /* 1036 * TODO: We could avoid this logic and returning -EINVAL here if 1037 * we set both the low-power and normal mode OSR registers when 1038 * we configure the device. 1039 */ 1040 if (data->oversampling_ratio < 0) 1041 return -EINVAL; 1042 1043 *val = data->oversampling_ratio; 1044 return IIO_VAL_INT; 1045 case IIO_CHAN_INFO_ENABLE: 1046 *val = data->steps_enabled; 1047 return IIO_VAL_INT; 1048 default: 1049 return -EINVAL; 1050 } 1051 } 1052 1053 static int bma400_read_avail(struct iio_dev *indio_dev, 1054 struct iio_chan_spec const *chan, 1055 const int **vals, int *type, int *length, 1056 long mask) 1057 { 1058 switch (mask) { 1059 case IIO_CHAN_INFO_SCALE: 1060 *type = IIO_VAL_INT_PLUS_MICRO; 1061 *vals = bma400_scales; 1062 *length = ARRAY_SIZE(bma400_scales); 1063 return IIO_AVAIL_LIST; 1064 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1065 *type = IIO_VAL_INT; 1066 *vals = bma400_osr_range; 1067 *length = ARRAY_SIZE(bma400_osr_range); 1068 return IIO_AVAIL_RANGE; 1069 case IIO_CHAN_INFO_SAMP_FREQ: 1070 *type = IIO_VAL_INT_PLUS_MICRO; 1071 *vals = bma400_sample_freqs; 1072 *length = ARRAY_SIZE(bma400_sample_freqs); 1073 return IIO_AVAIL_LIST; 1074 default: 1075 return -EINVAL; 1076 } 1077 } 1078 1079 static int bma400_write_raw(struct iio_dev *indio_dev, 1080 struct iio_chan_spec const *chan, int val, int val2, 1081 long mask) 1082 { 1083 struct bma400_data *data = iio_priv(indio_dev); 1084 int ret; 1085 1086 switch (mask) { 1087 case IIO_CHAN_INFO_SAMP_FREQ: 1088 /* 1089 * The sample frequency is readonly for the temperature 1090 * register and a fixed value in low-power mode. 1091 */ 1092 if (chan->type != IIO_ACCEL) 1093 return -EINVAL; 1094 1095 mutex_lock(&data->mutex); 1096 ret = bma400_set_accel_output_data_rate(data, val, val2); 1097 mutex_unlock(&data->mutex); 1098 return ret; 1099 case IIO_CHAN_INFO_SCALE: 1100 if (val != 0 || 1101 val2 < BMA400_ACC_SCALE_MIN || val2 > BMA400_ACC_SCALE_MAX) 1102 return -EINVAL; 1103 1104 mutex_lock(&data->mutex); 1105 ret = bma400_set_accel_scale(data, val2); 1106 mutex_unlock(&data->mutex); 1107 return ret; 1108 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1109 mutex_lock(&data->mutex); 1110 ret = bma400_set_accel_oversampling_ratio(data, val); 1111 mutex_unlock(&data->mutex); 1112 return ret; 1113 case IIO_CHAN_INFO_ENABLE: 1114 mutex_lock(&data->mutex); 1115 ret = bma400_enable_steps(data, val); 1116 mutex_unlock(&data->mutex); 1117 return ret; 1118 default: 1119 return -EINVAL; 1120 } 1121 } 1122 1123 static int bma400_write_raw_get_fmt(struct iio_dev *indio_dev, 1124 struct iio_chan_spec const *chan, 1125 long mask) 1126 { 1127 switch (mask) { 1128 case IIO_CHAN_INFO_SAMP_FREQ: 1129 return IIO_VAL_INT_PLUS_MICRO; 1130 case IIO_CHAN_INFO_SCALE: 1131 return IIO_VAL_INT_PLUS_MICRO; 1132 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1133 return IIO_VAL_INT; 1134 case IIO_CHAN_INFO_ENABLE: 1135 return IIO_VAL_INT; 1136 default: 1137 return -EINVAL; 1138 } 1139 } 1140 1141 static int bma400_read_event_config(struct iio_dev *indio_dev, 1142 const struct iio_chan_spec *chan, 1143 enum iio_event_type type, 1144 enum iio_event_direction dir) 1145 { 1146 struct bma400_data *data = iio_priv(indio_dev); 1147 1148 switch (chan->type) { 1149 case IIO_ACCEL: 1150 switch (dir) { 1151 case IIO_EV_DIR_RISING: 1152 return FIELD_GET(BMA400_INT_CONFIG0_GEN1_MASK, 1153 data->generic_event_en); 1154 case IIO_EV_DIR_FALLING: 1155 return FIELD_GET(BMA400_INT_CONFIG0_GEN2_MASK, 1156 data->generic_event_en); 1157 case IIO_EV_DIR_SINGLETAP: 1158 return FIELD_GET(BMA400_INT_CONFIG1_S_TAP_MASK, 1159 data->tap_event_en_bitmask); 1160 case IIO_EV_DIR_DOUBLETAP: 1161 return FIELD_GET(BMA400_INT_CONFIG1_D_TAP_MASK, 1162 data->tap_event_en_bitmask); 1163 default: 1164 return -EINVAL; 1165 } 1166 case IIO_STEPS: 1167 return data->step_event_en; 1168 case IIO_ACTIVITY: 1169 return data->activity_event_en; 1170 default: 1171 return -EINVAL; 1172 } 1173 } 1174 1175 static int bma400_steps_event_enable(struct bma400_data *data, int state) 1176 { 1177 int ret; 1178 1179 ret = bma400_enable_steps(data, 1); 1180 if (ret) 1181 return ret; 1182 1183 ret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG, 1184 BMA400_INT_CONFIG1_STEP_INT_MASK, 1185 FIELD_PREP(BMA400_INT_CONFIG1_STEP_INT_MASK, 1186 state)); 1187 if (ret) 1188 return ret; 1189 data->step_event_en = state; 1190 return 0; 1191 } 1192 1193 static int bma400_generic_event_en(struct bma400_data *data, 1194 enum iio_event_direction dir, 1195 int state) 1196 { 1197 int ret; 1198 unsigned int intrmask, regval; 1199 enum bma400_generic_intr genintr; 1200 enum bma400_detect_criterion detect_criterion; 1201 const struct bma400_genintr_info *bma400_genintr; 1202 1203 bma400_genintr = get_bma400_genintr_info(dir); 1204 if (!bma400_genintr) 1205 return -EINVAL; 1206 1207 genintr = bma400_genintr->genintr; 1208 detect_criterion = bma400_genintr->detect_mode; 1209 intrmask = bma400_genintr->intrmask; 1210 1211 /* 1212 * Enabling all axis for interrupt evaluation 1213 * Acc_filt2 is recommended as data source in datasheet (Section 4.7) 1214 */ 1215 ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 0), 1216 BMA400_GENINT_CONFIG0_X_EN_MASK | 1217 BMA400_GENINT_CONFIG0_Y_EN_MASK | 1218 BMA400_GENINT_CONFIG0_Z_EN_MASK| 1219 FIELD_PREP(BMA400_GENINT_CONFIG0_DATA_SRC_MASK, ACCEL_FILT2)| 1220 FIELD_PREP(BMA400_GENINT_CONFIG0_REF_UPD_MODE_MASK, 1221 BMA400_REF_EVERYTIME_UPDT_MODE)); 1222 if (ret) 1223 return ret; 1224 1225 /* OR combination of all axis for interrupt evaluation */ 1226 regval = FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X_OR_Y_OR_Z) | 1227 FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, detect_criterion); 1228 ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 1), regval); 1229 if (ret) 1230 return ret; 1231 1232 /* 1233 * Initial value to avoid interrupts while enabling 1234 * Value is in units of 8mg/lsb, i.e. effective val is val * 8mg/lsb 1235 */ 1236 ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 2), 0x0A); 1237 if (ret) 1238 return ret; 1239 1240 /* Initial duration value to avoid interrupts while enabling*/ 1241 ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 4), 0x0F); 1242 if (ret) 1243 return ret; 1244 1245 regval = state ? intrmask : 0; 1246 ret = regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, intrmask, regval); 1247 if (ret) 1248 return ret; 1249 1250 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, intrmask, regval); 1251 if (ret) 1252 return ret; 1253 1254 set_mask_bits(&data->generic_event_en, intrmask, regval); 1255 return 0; 1256 } 1257 1258 static int bma400_tap_event_en(struct bma400_data *data, 1259 enum iio_event_direction dir, int state) 1260 { 1261 unsigned int mask; 1262 unsigned int field_value = 0; 1263 int ret; 1264 1265 /* 1266 * Tap interrupts can be configured only in normal mode. 1267 * See table in section 4.3 "Power modes - performance modes" of 1268 * datasheet v1.2. 1269 */ 1270 if (data->power_mode != POWER_MODE_NORMAL) 1271 return -EINVAL; 1272 1273 /* 1274 * Tap interrupts are operating with a data rate of 200Hz. 1275 * See section 4.7 "Tap sensing interrupt" in datasheet v1.2. 1276 */ 1277 if (data->sample_freq.hz != 200 && state) { 1278 dev_err(data->dev, "Invalid data rate for tap interrupts.\n"); 1279 return -EINVAL; 1280 } 1281 1282 ret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG, 1283 BMA400_INT_CONFIG1_S_TAP_MASK, 1284 FIELD_PREP(BMA400_INT_CONFIG1_S_TAP_MASK, state)); 1285 if (ret) 1286 return ret; 1287 1288 switch (dir) { 1289 case IIO_EV_DIR_SINGLETAP: 1290 mask = BMA400_INT_CONFIG1_S_TAP_MASK; 1291 set_mask_bits(&field_value, BMA400_INT_CONFIG1_S_TAP_MASK, 1292 FIELD_PREP(BMA400_INT_CONFIG1_S_TAP_MASK, state)); 1293 break; 1294 case IIO_EV_DIR_DOUBLETAP: 1295 mask = BMA400_INT_CONFIG1_D_TAP_MASK; 1296 set_mask_bits(&field_value, BMA400_INT_CONFIG1_D_TAP_MASK, 1297 FIELD_PREP(BMA400_INT_CONFIG1_D_TAP_MASK, state)); 1298 break; 1299 default: 1300 return -EINVAL; 1301 } 1302 1303 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG, mask, 1304 field_value); 1305 if (ret) 1306 return ret; 1307 1308 set_mask_bits(&data->tap_event_en_bitmask, mask, field_value); 1309 1310 return 0; 1311 } 1312 1313 static int bma400_disable_adv_interrupt(struct bma400_data *data) 1314 { 1315 int ret; 1316 1317 ret = regmap_write(data->regmap, BMA400_INT_CONFIG0_REG, 0); 1318 if (ret) 1319 return ret; 1320 1321 ret = regmap_write(data->regmap, BMA400_INT_CONFIG1_REG, 0); 1322 if (ret) 1323 return ret; 1324 1325 data->tap_event_en_bitmask = 0; 1326 data->generic_event_en = 0; 1327 data->step_event_en = false; 1328 data->activity_event_en = false; 1329 1330 return 0; 1331 } 1332 1333 static int bma400_write_event_config(struct iio_dev *indio_dev, 1334 const struct iio_chan_spec *chan, 1335 enum iio_event_type type, 1336 enum iio_event_direction dir, bool state) 1337 { 1338 struct bma400_data *data = iio_priv(indio_dev); 1339 int ret; 1340 1341 switch (chan->type) { 1342 case IIO_ACCEL: 1343 switch (type) { 1344 case IIO_EV_TYPE_MAG: 1345 mutex_lock(&data->mutex); 1346 ret = bma400_generic_event_en(data, dir, state); 1347 mutex_unlock(&data->mutex); 1348 return ret; 1349 case IIO_EV_TYPE_GESTURE: 1350 mutex_lock(&data->mutex); 1351 ret = bma400_tap_event_en(data, dir, state); 1352 mutex_unlock(&data->mutex); 1353 return ret; 1354 default: 1355 return -EINVAL; 1356 } 1357 case IIO_STEPS: 1358 mutex_lock(&data->mutex); 1359 ret = bma400_steps_event_enable(data, state); 1360 mutex_unlock(&data->mutex); 1361 return ret; 1362 case IIO_ACTIVITY: 1363 mutex_lock(&data->mutex); 1364 if (!data->step_event_en) { 1365 ret = bma400_steps_event_enable(data, true); 1366 if (ret) { 1367 mutex_unlock(&data->mutex); 1368 return ret; 1369 } 1370 } 1371 data->activity_event_en = state; 1372 mutex_unlock(&data->mutex); 1373 return 0; 1374 default: 1375 return -EINVAL; 1376 } 1377 } 1378 1379 static int bma400_read_event_value(struct iio_dev *indio_dev, 1380 const struct iio_chan_spec *chan, 1381 enum iio_event_type type, 1382 enum iio_event_direction dir, 1383 enum iio_event_info info, 1384 int *val, int *val2) 1385 { 1386 struct bma400_data *data = iio_priv(indio_dev); 1387 int ret, reg_val, raw; 1388 enum bma400_generic_intr genintr; 1389 const struct bma400_genintr_info *bma400_genintr; 1390 1391 if (chan->type != IIO_ACCEL) 1392 return -EINVAL; 1393 1394 switch (type) { 1395 case IIO_EV_TYPE_MAG: 1396 bma400_genintr = get_bma400_genintr_info(dir); 1397 if (!bma400_genintr) 1398 return -EINVAL; 1399 genintr = bma400_genintr->genintr; 1400 1401 *val2 = 0; 1402 switch (info) { 1403 case IIO_EV_INFO_VALUE: 1404 ret = regmap_read(data->regmap, 1405 BMA400_GENINT_CONFIG_REG(genintr, 2), 1406 val); 1407 if (ret) 1408 return ret; 1409 return IIO_VAL_INT; 1410 case IIO_EV_INFO_PERIOD: 1411 mutex_lock(&data->mutex); 1412 ret = regmap_bulk_read(data->regmap, 1413 BMA400_GENINT_CONFIG_REG(genintr, 3), 1414 &data->duration, 1415 sizeof(data->duration)); 1416 if (ret) { 1417 mutex_unlock(&data->mutex); 1418 return ret; 1419 } 1420 *val = be16_to_cpu(data->duration); 1421 mutex_unlock(&data->mutex); 1422 return IIO_VAL_INT; 1423 case IIO_EV_INFO_HYSTERESIS: 1424 ret = regmap_read(data->regmap, 1425 BMA400_GENINT_CONFIG_REG(genintr, 0), 1426 val); 1427 if (ret) 1428 return ret; 1429 *val = FIELD_GET(BMA400_GENINT_CONFIG0_HYST_MASK, *val); 1430 return IIO_VAL_INT; 1431 default: 1432 return -EINVAL; 1433 } 1434 case IIO_EV_TYPE_GESTURE: 1435 switch (info) { 1436 case IIO_EV_INFO_VALUE: 1437 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG_REG, 1438 ®_val); 1439 if (ret) 1440 return ret; 1441 1442 *val = FIELD_GET(BMA400_TAP_CONFIG_SEN_MASK, reg_val); 1443 return IIO_VAL_INT; 1444 case IIO_EV_INFO_RESET_TIMEOUT: 1445 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1_REG, 1446 ®_val); 1447 if (ret) 1448 return ret; 1449 1450 raw = FIELD_GET(BMA400_TAP_CONFIG1_QUIET_MASK, reg_val); 1451 *val = 0; 1452 *val2 = tap_reset_timeout[raw]; 1453 return IIO_VAL_INT_PLUS_MICRO; 1454 case IIO_EV_INFO_TAP2_MIN_DELAY: 1455 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1_REG, 1456 ®_val); 1457 if (ret) 1458 return ret; 1459 1460 raw = FIELD_GET(BMA400_TAP_CONFIG1_QUIETDT_MASK, reg_val); 1461 *val = 0; 1462 *val2 = double_tap2_min_delay[raw]; 1463 return IIO_VAL_INT_PLUS_MICRO; 1464 default: 1465 return -EINVAL; 1466 } 1467 default: 1468 return -EINVAL; 1469 } 1470 } 1471 1472 static int bma400_write_event_value(struct iio_dev *indio_dev, 1473 const struct iio_chan_spec *chan, 1474 enum iio_event_type type, 1475 enum iio_event_direction dir, 1476 enum iio_event_info info, 1477 int val, int val2) 1478 { 1479 struct bma400_data *data = iio_priv(indio_dev); 1480 int ret, raw; 1481 enum bma400_generic_intr genintr; 1482 const struct bma400_genintr_info *bma400_genintr; 1483 1484 if (chan->type != IIO_ACCEL) 1485 return -EINVAL; 1486 1487 switch (type) { 1488 case IIO_EV_TYPE_MAG: 1489 bma400_genintr = get_bma400_genintr_info(dir); 1490 if (!bma400_genintr) 1491 return -EINVAL; 1492 genintr = bma400_genintr->genintr; 1493 1494 switch (info) { 1495 case IIO_EV_INFO_VALUE: 1496 if (val < 1 || val > 255) 1497 return -EINVAL; 1498 1499 return regmap_write(data->regmap, 1500 BMA400_GENINT_CONFIG_REG(genintr, 2), 1501 val); 1502 case IIO_EV_INFO_PERIOD: 1503 if (val < 1 || val > 65535) 1504 return -EINVAL; 1505 1506 mutex_lock(&data->mutex); 1507 put_unaligned_be16(val, &data->duration); 1508 ret = regmap_bulk_write(data->regmap, 1509 BMA400_GENINT_CONFIG_REG(genintr, 3), 1510 &data->duration, 1511 sizeof(data->duration)); 1512 mutex_unlock(&data->mutex); 1513 return ret; 1514 case IIO_EV_INFO_HYSTERESIS: 1515 if (val < 0 || val > 3) 1516 return -EINVAL; 1517 1518 return regmap_update_bits(data->regmap, 1519 BMA400_GENINT_CONFIG_REG(genintr, 0), 1520 BMA400_GENINT_CONFIG0_HYST_MASK, 1521 FIELD_PREP(BMA400_GENINT_CONFIG0_HYST_MASK, 1522 val)); 1523 default: 1524 return -EINVAL; 1525 } 1526 case IIO_EV_TYPE_GESTURE: 1527 switch (info) { 1528 case IIO_EV_INFO_VALUE: 1529 if (val < 0 || val > 7) 1530 return -EINVAL; 1531 1532 return regmap_update_bits(data->regmap, 1533 BMA400_TAP_CONFIG_REG, 1534 BMA400_TAP_CONFIG_SEN_MASK, 1535 FIELD_PREP(BMA400_TAP_CONFIG_SEN_MASK, 1536 val)); 1537 case IIO_EV_INFO_RESET_TIMEOUT: 1538 raw = usec_to_tapreg_raw(val2, tap_reset_timeout); 1539 if (raw < 0) 1540 return -EINVAL; 1541 1542 return regmap_update_bits(data->regmap, 1543 BMA400_TAP_CONFIG1_REG, 1544 BMA400_TAP_CONFIG1_QUIET_MASK, 1545 FIELD_PREP(BMA400_TAP_CONFIG1_QUIET_MASK, 1546 raw)); 1547 case IIO_EV_INFO_TAP2_MIN_DELAY: 1548 raw = usec_to_tapreg_raw(val2, double_tap2_min_delay); 1549 if (raw < 0) 1550 return -EINVAL; 1551 1552 return regmap_update_bits(data->regmap, 1553 BMA400_TAP_CONFIG1_REG, 1554 BMA400_TAP_CONFIG1_QUIETDT_MASK, 1555 FIELD_PREP(BMA400_TAP_CONFIG1_QUIETDT_MASK, 1556 raw)); 1557 default: 1558 return -EINVAL; 1559 } 1560 default: 1561 return -EINVAL; 1562 } 1563 } 1564 1565 static int bma400_data_rdy_trigger_set_state(struct iio_trigger *trig, 1566 bool state) 1567 { 1568 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1569 struct bma400_data *data = iio_priv(indio_dev); 1570 int ret; 1571 1572 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, 1573 BMA400_INT_CONFIG0_DRDY_MASK, 1574 FIELD_PREP(BMA400_INT_CONFIG0_DRDY_MASK, state)); 1575 if (ret) 1576 return ret; 1577 1578 return regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, 1579 BMA400_INT_CONFIG0_DRDY_MASK, 1580 FIELD_PREP(BMA400_INT_CONFIG0_DRDY_MASK, state)); 1581 } 1582 1583 static const unsigned long bma400_avail_scan_masks[] = { 1584 BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z), 1585 BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z) 1586 | BIT(BMA400_TEMP), 1587 0 1588 }; 1589 1590 static const struct iio_info bma400_info = { 1591 .read_raw = bma400_read_raw, 1592 .read_avail = bma400_read_avail, 1593 .write_raw = bma400_write_raw, 1594 .write_raw_get_fmt = bma400_write_raw_get_fmt, 1595 .read_event_config = bma400_read_event_config, 1596 .write_event_config = bma400_write_event_config, 1597 .write_event_value = bma400_write_event_value, 1598 .read_event_value = bma400_read_event_value, 1599 .event_attrs = &bma400_event_attribute_group, 1600 }; 1601 1602 static const struct iio_trigger_ops bma400_trigger_ops = { 1603 .set_trigger_state = &bma400_data_rdy_trigger_set_state, 1604 .validate_device = &iio_trigger_validate_own_device, 1605 }; 1606 1607 static irqreturn_t bma400_trigger_handler(int irq, void *p) 1608 { 1609 struct iio_poll_func *pf = p; 1610 struct iio_dev *indio_dev = pf->indio_dev; 1611 struct bma400_data *data = iio_priv(indio_dev); 1612 int ret, temp; 1613 1614 /* Lock to protect the data->buffer */ 1615 mutex_lock(&data->mutex); 1616 1617 /* bulk read six registers, with the base being the LSB register */ 1618 ret = regmap_bulk_read(data->regmap, BMA400_ACC_X_LSB_REG, 1619 &data->buffer.buff, sizeof(data->buffer.buff)); 1620 if (ret) 1621 goto unlock_err; 1622 1623 if (test_bit(BMA400_TEMP, indio_dev->active_scan_mask)) { 1624 ret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &temp); 1625 if (ret) 1626 goto unlock_err; 1627 1628 data->buffer.temperature = temp; 1629 } 1630 1631 iio_push_to_buffers_with_ts(indio_dev, &data->buffer, 1632 sizeof(data->buffer), 1633 iio_get_time_ns(indio_dev)); 1634 1635 mutex_unlock(&data->mutex); 1636 iio_trigger_notify_done(indio_dev->trig); 1637 return IRQ_HANDLED; 1638 1639 unlock_err: 1640 mutex_unlock(&data->mutex); 1641 return IRQ_NONE; 1642 } 1643 1644 static irqreturn_t bma400_interrupt(int irq, void *private) 1645 { 1646 struct iio_dev *indio_dev = private; 1647 struct bma400_data *data = iio_priv(indio_dev); 1648 s64 timestamp = iio_get_time_ns(indio_dev); 1649 unsigned int act, ev_dir = IIO_EV_DIR_NONE; 1650 int ret; 1651 1652 /* Lock to protect the data->status */ 1653 mutex_lock(&data->mutex); 1654 ret = regmap_bulk_read(data->regmap, BMA400_INT_STAT0_REG, 1655 &data->status, 1656 sizeof(data->status)); 1657 /* 1658 * if none of the bit is set in the status register then it is 1659 * spurious interrupt. 1660 */ 1661 if (ret || !data->status) 1662 goto unlock_err; 1663 1664 /* 1665 * Disable all advance interrupts if interrupt engine overrun occurs. 1666 * See section 4.7 "Interrupt engine overrun" in datasheet v1.2. 1667 */ 1668 if (FIELD_GET(BMA400_INT_STAT_ENG_OVRRUN_MASK, le16_to_cpu(data->status))) { 1669 bma400_disable_adv_interrupt(data); 1670 dev_err(data->dev, "Interrupt engine overrun\n"); 1671 goto unlock_err; 1672 } 1673 1674 if (FIELD_GET(BMA400_INT_STAT1_S_TAP_MASK, le16_to_cpu(data->status))) 1675 iio_push_event(indio_dev, 1676 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1677 IIO_MOD_X_OR_Y_OR_Z, 1678 IIO_EV_TYPE_GESTURE, 1679 IIO_EV_DIR_SINGLETAP), 1680 timestamp); 1681 1682 if (FIELD_GET(BMA400_INT_STAT1_D_TAP_MASK, le16_to_cpu(data->status))) 1683 iio_push_event(indio_dev, 1684 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1685 IIO_MOD_X_OR_Y_OR_Z, 1686 IIO_EV_TYPE_GESTURE, 1687 IIO_EV_DIR_DOUBLETAP), 1688 timestamp); 1689 1690 if (FIELD_GET(BMA400_INT_STAT0_GEN1_MASK, le16_to_cpu(data->status))) 1691 ev_dir = IIO_EV_DIR_RISING; 1692 1693 if (FIELD_GET(BMA400_INT_STAT0_GEN2_MASK, le16_to_cpu(data->status))) 1694 ev_dir = IIO_EV_DIR_FALLING; 1695 1696 if (ev_dir != IIO_EV_DIR_NONE) { 1697 iio_push_event(indio_dev, 1698 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1699 IIO_MOD_X_OR_Y_OR_Z, 1700 IIO_EV_TYPE_MAG, ev_dir), 1701 timestamp); 1702 } 1703 1704 if (FIELD_GET(BMA400_INT_STAT1_STEP_INT_MASK, le16_to_cpu(data->status))) { 1705 iio_push_event(indio_dev, 1706 IIO_MOD_EVENT_CODE(IIO_STEPS, 0, IIO_NO_MOD, 1707 IIO_EV_TYPE_CHANGE, 1708 IIO_EV_DIR_NONE), 1709 timestamp); 1710 1711 if (data->activity_event_en) { 1712 ret = regmap_read(data->regmap, BMA400_STEP_STAT_REG, 1713 &act); 1714 if (ret) 1715 goto unlock_err; 1716 1717 iio_push_event(indio_dev, 1718 IIO_MOD_EVENT_CODE(IIO_ACTIVITY, 0, 1719 bma400_act_to_mod(act), 1720 IIO_EV_TYPE_CHANGE, 1721 IIO_EV_DIR_NONE), 1722 timestamp); 1723 } 1724 } 1725 1726 if (FIELD_GET(BMA400_INT_STAT0_DRDY_MASK, le16_to_cpu(data->status))) { 1727 mutex_unlock(&data->mutex); 1728 iio_trigger_poll_nested(data->trig); 1729 return IRQ_HANDLED; 1730 } 1731 1732 mutex_unlock(&data->mutex); 1733 return IRQ_HANDLED; 1734 1735 unlock_err: 1736 mutex_unlock(&data->mutex); 1737 return IRQ_NONE; 1738 } 1739 1740 int bma400_probe(struct device *dev, struct regmap *regmap, int irq, 1741 const char *name) 1742 { 1743 struct iio_dev *indio_dev; 1744 struct bma400_data *data; 1745 int ret; 1746 1747 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1748 if (!indio_dev) 1749 return -ENOMEM; 1750 1751 data = iio_priv(indio_dev); 1752 data->regmap = regmap; 1753 data->dev = dev; 1754 1755 ret = bma400_init(data); 1756 if (ret) 1757 return ret; 1758 1759 ret = iio_read_mount_matrix(dev, &data->orientation); 1760 if (ret) 1761 return ret; 1762 1763 mutex_init(&data->mutex); 1764 indio_dev->name = name; 1765 indio_dev->info = &bma400_info; 1766 indio_dev->channels = bma400_channels; 1767 indio_dev->num_channels = ARRAY_SIZE(bma400_channels); 1768 indio_dev->available_scan_masks = bma400_avail_scan_masks; 1769 indio_dev->modes = INDIO_DIRECT_MODE; 1770 1771 if (irq > 0) { 1772 data->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", 1773 indio_dev->name, 1774 iio_device_id(indio_dev)); 1775 if (!data->trig) 1776 return -ENOMEM; 1777 1778 data->trig->ops = &bma400_trigger_ops; 1779 iio_trigger_set_drvdata(data->trig, indio_dev); 1780 1781 ret = devm_iio_trigger_register(data->dev, data->trig); 1782 if (ret) 1783 return dev_err_probe(data->dev, ret, 1784 "iio trigger register fail\n"); 1785 1786 indio_dev->trig = iio_trigger_get(data->trig); 1787 ret = devm_request_threaded_irq(dev, irq, NULL, 1788 &bma400_interrupt, 1789 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1790 indio_dev->name, indio_dev); 1791 if (ret) 1792 return dev_err_probe(data->dev, ret, 1793 "request irq %d failed\n", irq); 1794 } 1795 1796 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 1797 &bma400_trigger_handler, NULL); 1798 if (ret) 1799 return dev_err_probe(data->dev, ret, 1800 "iio triggered buffer setup failed\n"); 1801 1802 return devm_iio_device_register(dev, indio_dev); 1803 } 1804 EXPORT_SYMBOL_NS(bma400_probe, "IIO_BMA400"); 1805 1806 MODULE_AUTHOR("Dan Robertson <dan@dlrobertson.com>"); 1807 MODULE_AUTHOR("Jagath Jog J <jagathjog1996@gmail.com>"); 1808 MODULE_DESCRIPTION("Bosch BMA400 triaxial acceleration sensor core"); 1809 MODULE_LICENSE("GPL"); 1810