1465c811fSDan Robertson /* SPDX-License-Identifier: GPL-2.0-only */ 2465c811fSDan Robertson /* 3465c811fSDan Robertson * Register constants and other forward declarations needed by the bma400 4465c811fSDan Robertson * sources. 5465c811fSDan Robertson * 6465c811fSDan Robertson * Copyright 2019 Dan Robertson <dan@dlrobertson.com> 7465c811fSDan Robertson */ 8465c811fSDan Robertson 9465c811fSDan Robertson #ifndef _BMA400_H_ 10465c811fSDan Robertson #define _BMA400_H_ 11465c811fSDan Robertson 12465c811fSDan Robertson #include <linux/bits.h> 13465c811fSDan Robertson #include <linux/regmap.h> 14465c811fSDan Robertson 15465c811fSDan Robertson /* 16465c811fSDan Robertson * Read-Only Registers 17465c811fSDan Robertson */ 18465c811fSDan Robertson 19465c811fSDan Robertson /* Status and ID registers */ 20465c811fSDan Robertson #define BMA400_CHIP_ID_REG 0x00 21465c811fSDan Robertson #define BMA400_ERR_REG 0x02 22465c811fSDan Robertson #define BMA400_STATUS_REG 0x03 23465c811fSDan Robertson 24465c811fSDan Robertson /* Acceleration registers */ 25465c811fSDan Robertson #define BMA400_X_AXIS_LSB_REG 0x04 26465c811fSDan Robertson #define BMA400_X_AXIS_MSB_REG 0x05 27465c811fSDan Robertson #define BMA400_Y_AXIS_LSB_REG 0x06 28465c811fSDan Robertson #define BMA400_Y_AXIS_MSB_REG 0x07 29465c811fSDan Robertson #define BMA400_Z_AXIS_LSB_REG 0x08 30465c811fSDan Robertson #define BMA400_Z_AXIS_MSB_REG 0x09 31465c811fSDan Robertson 32465c811fSDan Robertson /* Sensor time registers */ 33465c811fSDan Robertson #define BMA400_SENSOR_TIME0 0x0a 34465c811fSDan Robertson #define BMA400_SENSOR_TIME1 0x0b 35465c811fSDan Robertson #define BMA400_SENSOR_TIME2 0x0c 36465c811fSDan Robertson 37465c811fSDan Robertson /* Event and interrupt registers */ 38465c811fSDan Robertson #define BMA400_EVENT_REG 0x0d 39465c811fSDan Robertson #define BMA400_INT_STAT0_REG 0x0e 40465c811fSDan Robertson #define BMA400_INT_STAT1_REG 0x0f 41465c811fSDan Robertson #define BMA400_INT_STAT2_REG 0x10 42d024af5bSJagath Jog J #define BMA400_INT12_MAP_REG 0x23 43*961db2daSJagath Jog J #define BMA400_INT_ENG_OVRUN_MSK BIT(4) 44465c811fSDan Robertson 45465c811fSDan Robertson /* Temperature register */ 46465c811fSDan Robertson #define BMA400_TEMP_DATA_REG 0x11 47465c811fSDan Robertson 48465c811fSDan Robertson /* FIFO length and data registers */ 49465c811fSDan Robertson #define BMA400_FIFO_LENGTH0_REG 0x12 50465c811fSDan Robertson #define BMA400_FIFO_LENGTH1_REG 0x13 51465c811fSDan Robertson #define BMA400_FIFO_DATA_REG 0x14 52465c811fSDan Robertson 53465c811fSDan Robertson /* Step count registers */ 54465c811fSDan Robertson #define BMA400_STEP_CNT0_REG 0x15 55465c811fSDan Robertson #define BMA400_STEP_CNT1_REG 0x16 56465c811fSDan Robertson #define BMA400_STEP_CNT3_REG 0x17 57465c811fSDan Robertson #define BMA400_STEP_STAT_REG 0x18 58d221de60SJagath Jog J #define BMA400_STEP_INT_MSK BIT(0) 59d221de60SJagath Jog J #define BMA400_STEP_RAW_LEN 0x03 60d024af5bSJagath Jog J #define BMA400_STEP_STAT_MASK GENMASK(9, 8) 61465c811fSDan Robertson 62465c811fSDan Robertson /* 63465c811fSDan Robertson * Read-write configuration registers 64465c811fSDan Robertson */ 65465c811fSDan Robertson #define BMA400_ACC_CONFIG0_REG 0x19 66465c811fSDan Robertson #define BMA400_ACC_CONFIG1_REG 0x1a 67465c811fSDan Robertson #define BMA400_ACC_CONFIG2_REG 0x1b 68465c811fSDan Robertson #define BMA400_CMD_REG 0x7e 69465c811fSDan Robertson 70ffe0ab6aSJagath Jog J /* Interrupt registers */ 71ffe0ab6aSJagath Jog J #define BMA400_INT_CONFIG0_REG 0x1f 72ffe0ab6aSJagath Jog J #define BMA400_INT_CONFIG1_REG 0x20 73ffe0ab6aSJagath Jog J #define BMA400_INT1_MAP_REG 0x21 74ffe0ab6aSJagath Jog J #define BMA400_INT_IO_CTRL_REG 0x24 75ffe0ab6aSJagath Jog J #define BMA400_INT_DRDY_MSK BIT(7) 76ffe0ab6aSJagath Jog J 77465c811fSDan Robertson /* Chip ID of BMA 400 devices found in the chip ID register. */ 78465c811fSDan Robertson #define BMA400_ID_REG_VAL 0x90 79465c811fSDan Robertson 80465c811fSDan Robertson #define BMA400_LP_OSR_SHIFT 5 81465c811fSDan Robertson #define BMA400_NP_OSR_SHIFT 4 82465c811fSDan Robertson #define BMA400_SCALE_SHIFT 6 83465c811fSDan Robertson 84465c811fSDan Robertson #define BMA400_TWO_BITS_MASK GENMASK(1, 0) 85465c811fSDan Robertson #define BMA400_LP_OSR_MASK GENMASK(6, 5) 86465c811fSDan Robertson #define BMA400_NP_OSR_MASK GENMASK(5, 4) 87465c811fSDan Robertson #define BMA400_ACC_ODR_MASK GENMASK(3, 0) 88465c811fSDan Robertson #define BMA400_ACC_SCALE_MASK GENMASK(7, 6) 89465c811fSDan Robertson 90465c811fSDan Robertson #define BMA400_ACC_ODR_MIN_RAW 0x05 91465c811fSDan Robertson #define BMA400_ACC_ODR_LP_RAW 0x06 92465c811fSDan Robertson #define BMA400_ACC_ODR_MAX_RAW 0x0b 93465c811fSDan Robertson 94465c811fSDan Robertson #define BMA400_ACC_ODR_MAX_HZ 800 95465c811fSDan Robertson #define BMA400_ACC_ODR_MIN_WHOLE_HZ 25 96465c811fSDan Robertson #define BMA400_ACC_ODR_MIN_HZ 12 97465c811fSDan Robertson 983cf122c2SJagath Jog J /* Generic interrupts register */ 993cf122c2SJagath Jog J #define BMA400_GEN1INT_CONFIG0 0x3f 1003cf122c2SJagath Jog J #define BMA400_GEN2INT_CONFIG0 0x4A 1013cf122c2SJagath Jog J #define BMA400_GEN_CONFIG1_OFF 0x01 1023cf122c2SJagath Jog J #define BMA400_GEN_CONFIG2_OFF 0x02 1033cf122c2SJagath Jog J #define BMA400_GEN_CONFIG3_OFF 0x03 1043cf122c2SJagath Jog J #define BMA400_GEN_CONFIG31_OFF 0x04 1053cf122c2SJagath Jog J #define BMA400_INT_GEN1_MSK BIT(2) 1063cf122c2SJagath Jog J #define BMA400_INT_GEN2_MSK BIT(3) 1073cf122c2SJagath Jog J #define BMA400_GEN_HYST_MSK GENMASK(1, 0) 1083cf122c2SJagath Jog J 109*961db2daSJagath Jog J /* TAP config registers */ 110*961db2daSJagath Jog J #define BMA400_TAP_CONFIG 0x57 111*961db2daSJagath Jog J #define BMA400_TAP_CONFIG1 0x58 112*961db2daSJagath Jog J #define BMA400_S_TAP_MSK BIT(2) 113*961db2daSJagath Jog J #define BMA400_D_TAP_MSK BIT(3) 114*961db2daSJagath Jog J #define BMA400_INT_S_TAP_MSK BIT(10) 115*961db2daSJagath Jog J #define BMA400_INT_D_TAP_MSK BIT(11) 116*961db2daSJagath Jog J #define BMA400_TAP_SEN_MSK GENMASK(2, 0) 117*961db2daSJagath Jog J #define BMA400_TAP_TICSTH_MSK GENMASK(1, 0) 118*961db2daSJagath Jog J #define BMA400_TAP_QUIET_MSK GENMASK(3, 2) 119*961db2daSJagath Jog J #define BMA400_TAP_QUIETDT_MSK GENMASK(5, 4) 120*961db2daSJagath Jog J #define BMA400_TAP_TIM_LIST_LEN 4 121*961db2daSJagath Jog J 122747c7cf1SJagath Jog J /* 123747c7cf1SJagath Jog J * BMA400_SCALE_MIN macro value represents m/s^2 for 1 LSB before 124747c7cf1SJagath Jog J * converting to micro values for +-2g range. 125747c7cf1SJagath Jog J * 126747c7cf1SJagath Jog J * For +-2g - 1 LSB = 0.976562 milli g = 0.009576 m/s^2 127747c7cf1SJagath Jog J * For +-4g - 1 LSB = 1.953125 milli g = 0.019153 m/s^2 128747c7cf1SJagath Jog J * For +-16g - 1 LSB = 7.8125 milli g = 0.076614 m/s^2 129747c7cf1SJagath Jog J * 130747c7cf1SJagath Jog J * The raw value which is used to select the different ranges is determined 131747c7cf1SJagath Jog J * by the first bit set position from the scale value, so BMA400_SCALE_MIN 132747c7cf1SJagath Jog J * should be odd. 133747c7cf1SJagath Jog J * 134747c7cf1SJagath Jog J * Scale values for +-2g, +-4g, +-8g and +-16g are populated into bma400_scales 135747c7cf1SJagath Jog J * array by left shifting BMA400_SCALE_MIN. 136747c7cf1SJagath Jog J * e.g.: 137747c7cf1SJagath Jog J * To select +-2g = 9577 << 0 = raw value to write is 0. 138747c7cf1SJagath Jog J * To select +-8g = 9577 << 2 = raw value to write is 2. 139747c7cf1SJagath Jog J * To select +-16g = 9577 << 3 = raw value to write is 3. 140747c7cf1SJagath Jog J */ 141747c7cf1SJagath Jog J #define BMA400_SCALE_MIN 9577 142747c7cf1SJagath Jog J #define BMA400_SCALE_MAX 76617 143465c811fSDan Robertson 144465c811fSDan Robertson extern const struct regmap_config bma400_regmap_config; 145465c811fSDan Robertson 146ffe0ab6aSJagath Jog J int bma400_probe(struct device *dev, struct regmap *regmap, int irq, 147ffe0ab6aSJagath Jog J const char *name); 148465c811fSDan Robertson 149465c811fSDan Robertson #endif 150