1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * ADXL372 3-Axis Digital Accelerometer core driver 4 * 5 * Copyright 2018 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/spi/spi.h> 15 16 #include <linux/iio/iio.h> 17 #include <linux/iio/sysfs.h> 18 #include <linux/iio/buffer.h> 19 #include <linux/iio/events.h> 20 #include <linux/iio/trigger.h> 21 #include <linux/iio/trigger_consumer.h> 22 #include <linux/iio/triggered_buffer.h> 23 24 #include "adxl372.h" 25 26 /* ADXL372 registers definition */ 27 #define ADXL372_DEVID 0x00 28 #define ADXL372_DEVID_MST 0x01 29 #define ADXL372_PARTID 0x02 30 #define ADXL372_STATUS_1 0x04 31 #define ADXL372_STATUS_2 0x05 32 #define ADXL372_FIFO_ENTRIES_2 0x06 33 #define ADXL372_FIFO_ENTRIES_1 0x07 34 #define ADXL372_X_DATA_H 0x08 35 #define ADXL372_X_DATA_L 0x09 36 #define ADXL372_Y_DATA_H 0x0A 37 #define ADXL372_Y_DATA_L 0x0B 38 #define ADXL372_Z_DATA_H 0x0C 39 #define ADXL372_Z_DATA_L 0x0D 40 #define ADXL372_X_MAXPEAK_H 0x15 41 #define ADXL372_X_MAXPEAK_L 0x16 42 #define ADXL372_Y_MAXPEAK_H 0x17 43 #define ADXL372_Y_MAXPEAK_L 0x18 44 #define ADXL372_Z_MAXPEAK_H 0x19 45 #define ADXL372_Z_MAXPEAK_L 0x1A 46 #define ADXL372_OFFSET_X 0x20 47 #define ADXL372_OFFSET_Y 0x21 48 #define ADXL372_OFFSET_Z 0x22 49 #define ADXL372_X_THRESH_ACT_H 0x23 50 #define ADXL372_X_THRESH_ACT_L 0x24 51 #define ADXL372_Y_THRESH_ACT_H 0x25 52 #define ADXL372_Y_THRESH_ACT_L 0x26 53 #define ADXL372_Z_THRESH_ACT_H 0x27 54 #define ADXL372_Z_THRESH_ACT_L 0x28 55 #define ADXL372_TIME_ACT 0x29 56 #define ADXL372_X_THRESH_INACT_H 0x2A 57 #define ADXL372_X_THRESH_INACT_L 0x2B 58 #define ADXL372_Y_THRESH_INACT_H 0x2C 59 #define ADXL372_Y_THRESH_INACT_L 0x2D 60 #define ADXL372_Z_THRESH_INACT_H 0x2E 61 #define ADXL372_Z_THRESH_INACT_L 0x2F 62 #define ADXL372_TIME_INACT_H 0x30 63 #define ADXL372_TIME_INACT_L 0x31 64 #define ADXL372_X_THRESH_ACT2_H 0x32 65 #define ADXL372_X_THRESH_ACT2_L 0x33 66 #define ADXL372_Y_THRESH_ACT2_H 0x34 67 #define ADXL372_Y_THRESH_ACT2_L 0x35 68 #define ADXL372_Z_THRESH_ACT2_H 0x36 69 #define ADXL372_Z_THRESH_ACT2_L 0x37 70 #define ADXL372_HPF 0x38 71 #define ADXL372_FIFO_SAMPLES 0x39 72 #define ADXL372_FIFO_CTL 0x3A 73 #define ADXL372_INT1_MAP 0x3B 74 #define ADXL372_INT2_MAP 0x3C 75 #define ADXL372_TIMING 0x3D 76 #define ADXL372_MEASURE 0x3E 77 #define ADXL372_POWER_CTL 0x3F 78 #define ADXL372_SELF_TEST 0x40 79 #define ADXL372_RESET 0x41 80 #define ADXL372_FIFO_DATA 0x42 81 82 #define ADXL372_DEVID_VAL 0xAD 83 #define ADXL372_PARTID_VAL 0xFA 84 #define ADXL372_RESET_CODE 0x52 85 86 /* ADXL372_POWER_CTL */ 87 #define ADXL372_POWER_CTL_MODE_MSK GENMASK_ULL(1, 0) 88 #define ADXL372_POWER_CTL_MODE(x) (((x) & 0x3) << 0) 89 90 /* ADXL372_MEASURE */ 91 #define ADXL372_MEASURE_LINKLOOP_MSK GENMASK_ULL(5, 4) 92 #define ADXL372_MEASURE_LINKLOOP_MODE(x) (((x) & 0x3) << 4) 93 #define ADXL372_MEASURE_BANDWIDTH_MSK GENMASK_ULL(2, 0) 94 #define ADXL372_MEASURE_BANDWIDTH_MODE(x) (((x) & 0x7) << 0) 95 96 /* ADXL372_TIMING */ 97 #define ADXL372_TIMING_ODR_MSK GENMASK_ULL(7, 5) 98 #define ADXL372_TIMING_ODR_MODE(x) (((x) & 0x7) << 5) 99 100 /* ADXL372_FIFO_CTL */ 101 #define ADXL372_FIFO_CTL_FORMAT_MSK GENMASK(5, 3) 102 #define ADXL372_FIFO_CTL_FORMAT_MODE(x) (((x) & 0x7) << 3) 103 #define ADXL372_FIFO_CTL_MODE_MSK GENMASK(2, 1) 104 #define ADXL372_FIFO_CTL_MODE_MODE(x) (((x) & 0x3) << 1) 105 #define ADXL372_FIFO_CTL_SAMPLES_MSK BIT(1) 106 #define ADXL372_FIFO_CTL_SAMPLES_MODE(x) (((x) > 0xFF) ? 1 : 0) 107 108 /* ADXL372_STATUS_1 */ 109 #define ADXL372_STATUS_1_DATA_RDY(x) (((x) >> 0) & 0x1) 110 #define ADXL372_STATUS_1_FIFO_RDY(x) (((x) >> 1) & 0x1) 111 #define ADXL372_STATUS_1_FIFO_FULL(x) (((x) >> 2) & 0x1) 112 #define ADXL372_STATUS_1_FIFO_OVR(x) (((x) >> 3) & 0x1) 113 #define ADXL372_STATUS_1_USR_NVM_BUSY(x) (((x) >> 5) & 0x1) 114 #define ADXL372_STATUS_1_AWAKE(x) (((x) >> 6) & 0x1) 115 #define ADXL372_STATUS_1_ERR_USR_REGS(x) (((x) >> 7) & 0x1) 116 117 /* ADXL372_STATUS_2 */ 118 #define ADXL372_STATUS_2_INACT(x) (((x) >> 4) & 0x1) 119 #define ADXL372_STATUS_2_ACT(x) (((x) >> 5) & 0x1) 120 #define ADXL372_STATUS_2_AC2(x) (((x) >> 6) & 0x1) 121 122 /* ADXL372_INT1_MAP */ 123 #define ADXL372_INT1_MAP_DATA_RDY_MSK BIT(0) 124 #define ADXL372_INT1_MAP_DATA_RDY_MODE(x) (((x) & 0x1) << 0) 125 #define ADXL372_INT1_MAP_FIFO_RDY_MSK BIT(1) 126 #define ADXL372_INT1_MAP_FIFO_RDY_MODE(x) (((x) & 0x1) << 1) 127 #define ADXL372_INT1_MAP_FIFO_FULL_MSK BIT(2) 128 #define ADXL372_INT1_MAP_FIFO_FULL_MODE(x) (((x) & 0x1) << 2) 129 #define ADXL372_INT1_MAP_FIFO_OVR_MSK BIT(3) 130 #define ADXL372_INT1_MAP_FIFO_OVR_MODE(x) (((x) & 0x1) << 3) 131 #define ADXL372_INT1_MAP_INACT_MSK BIT(4) 132 #define ADXL372_INT1_MAP_INACT_MODE(x) (((x) & 0x1) << 4) 133 #define ADXL372_INT1_MAP_ACT_MSK BIT(5) 134 #define ADXL372_INT1_MAP_ACT_MODE(x) (((x) & 0x1) << 5) 135 #define ADXL372_INT1_MAP_AWAKE_MSK BIT(6) 136 #define ADXL372_INT1_MAP_AWAKE_MODE(x) (((x) & 0x1) << 6) 137 #define ADXL372_INT1_MAP_LOW_MSK BIT(7) 138 #define ADXL372_INT1_MAP_LOW_MODE(x) (((x) & 0x1) << 7) 139 140 /* ADX372_THRESH */ 141 #define ADXL372_THRESH_VAL_H_MSK GENMASK(10, 3) 142 #define ADXL372_THRESH_VAL_H_SEL(x) FIELD_GET(ADXL372_THRESH_VAL_H_MSK, x) 143 #define ADXL372_THRESH_VAL_L_MSK GENMASK(2, 0) 144 #define ADXL372_THRESH_VAL_L_SEL(x) FIELD_GET(ADXL372_THRESH_VAL_L_MSK, x) 145 146 /* The ADXL372 includes a deep, 512 sample FIFO buffer */ 147 #define ADXL372_FIFO_SIZE 512 148 #define ADXL372_X_AXIS_EN(x) ((x) & BIT(0)) 149 #define ADXL372_Y_AXIS_EN(x) ((x) & BIT(1)) 150 #define ADXL372_Z_AXIS_EN(x) ((x) & BIT(2)) 151 152 /* 153 * At +/- 200g with 12-bit resolution, scale is computed as: 154 * (200 + 200) * 9.81 / (2^12 - 1) = 0.958241 155 */ 156 #define ADXL372_USCALE 958241 157 158 enum adxl372_op_mode { 159 ADXL372_STANDBY, 160 ADXL372_WAKE_UP, 161 ADXL372_INSTANT_ON, 162 ADXL372_FULL_BW_MEASUREMENT, 163 }; 164 165 enum adxl372_act_proc_mode { 166 ADXL372_DEFAULT, 167 ADXL372_LINKED, 168 ADXL372_LOOPED, 169 }; 170 171 enum adxl372_th_activity { 172 ADXL372_ACTIVITY, 173 ADXL372_ACTIVITY2, 174 ADXL372_INACTIVITY, 175 }; 176 177 enum adxl372_odr { 178 ADXL372_ODR_400HZ, 179 ADXL372_ODR_800HZ, 180 ADXL372_ODR_1600HZ, 181 ADXL372_ODR_3200HZ, 182 ADXL372_ODR_6400HZ, 183 }; 184 185 enum adxl372_bandwidth { 186 ADXL372_BW_200HZ, 187 ADXL372_BW_400HZ, 188 ADXL372_BW_800HZ, 189 ADXL372_BW_1600HZ, 190 ADXL372_BW_3200HZ, 191 }; 192 193 static const unsigned int adxl372_th_reg_high_addr[3] = { 194 [ADXL372_ACTIVITY] = ADXL372_X_THRESH_ACT_H, 195 [ADXL372_ACTIVITY2] = ADXL372_X_THRESH_ACT2_H, 196 [ADXL372_INACTIVITY] = ADXL372_X_THRESH_INACT_H, 197 }; 198 199 enum adxl372_fifo_format { 200 ADXL372_XYZ_FIFO, 201 ADXL372_X_FIFO, 202 ADXL372_Y_FIFO, 203 ADXL372_XY_FIFO, 204 ADXL372_Z_FIFO, 205 ADXL372_XZ_FIFO, 206 ADXL372_YZ_FIFO, 207 ADXL372_XYZ_PEAK_FIFO, 208 }; 209 210 enum adxl372_fifo_mode { 211 ADXL372_FIFO_BYPASSED, 212 ADXL372_FIFO_STREAMED, 213 ADXL372_FIFO_TRIGGERED, 214 ADXL372_FIFO_OLD_SAVED 215 }; 216 217 static const int adxl372_samp_freq_tbl[5] = { 218 400, 800, 1600, 3200, 6400, 219 }; 220 221 static const int adxl372_bw_freq_tbl[5] = { 222 200, 400, 800, 1600, 3200, 223 }; 224 225 struct adxl372_axis_lookup { 226 unsigned int bits; 227 enum adxl372_fifo_format fifo_format; 228 }; 229 230 static const struct adxl372_axis_lookup adxl372_axis_lookup_table[] = { 231 { BIT(0), ADXL372_X_FIFO }, 232 { BIT(1), ADXL372_Y_FIFO }, 233 { BIT(2), ADXL372_Z_FIFO }, 234 { BIT(0) | BIT(1), ADXL372_XY_FIFO }, 235 { BIT(0) | BIT(2), ADXL372_XZ_FIFO }, 236 { BIT(1) | BIT(2), ADXL372_YZ_FIFO }, 237 { BIT(0) | BIT(1) | BIT(2), ADXL372_XYZ_FIFO }, 238 }; 239 240 static const struct iio_event_spec adxl372_events[] = { 241 { 242 .type = IIO_EV_TYPE_THRESH, 243 .dir = IIO_EV_DIR_RISING, 244 .mask_separate = BIT(IIO_EV_INFO_VALUE), 245 .mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD) | BIT(IIO_EV_INFO_ENABLE), 246 }, { 247 .type = IIO_EV_TYPE_THRESH, 248 .dir = IIO_EV_DIR_FALLING, 249 .mask_separate = BIT(IIO_EV_INFO_VALUE), 250 .mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD) | BIT(IIO_EV_INFO_ENABLE), 251 }, 252 }; 253 254 #define ADXL372_ACCEL_CHANNEL(index, reg, axis) { \ 255 .type = IIO_ACCEL, \ 256 .address = reg, \ 257 .modified = 1, \ 258 .channel2 = IIO_MOD_##axis, \ 259 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 260 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 261 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 262 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 263 .scan_index = index, \ 264 .scan_type = { \ 265 .sign = 's', \ 266 .realbits = 12, \ 267 .storagebits = 16, \ 268 .shift = 4, \ 269 .endianness = IIO_BE, \ 270 }, \ 271 .event_spec = adxl372_events, \ 272 .num_event_specs = ARRAY_SIZE(adxl372_events) \ 273 } 274 275 static const struct iio_chan_spec adxl372_channels[] = { 276 ADXL372_ACCEL_CHANNEL(0, ADXL372_X_DATA_H, X), 277 ADXL372_ACCEL_CHANNEL(1, ADXL372_Y_DATA_H, Y), 278 ADXL372_ACCEL_CHANNEL(2, ADXL372_Z_DATA_H, Z), 279 }; 280 281 struct adxl372_state { 282 int irq; 283 struct device *dev; 284 struct regmap *regmap; 285 struct iio_trigger *dready_trig; 286 struct iio_trigger *peak_datardy_trig; 287 enum adxl372_fifo_mode fifo_mode; 288 enum adxl372_fifo_format fifo_format; 289 unsigned int fifo_axis_mask; 290 enum adxl372_op_mode op_mode; 291 enum adxl372_act_proc_mode act_proc_mode; 292 enum adxl372_odr odr; 293 enum adxl372_bandwidth bw; 294 u32 act_time_ms; 295 u32 inact_time_ms; 296 u8 fifo_set_size; 297 unsigned long int1_bitmask; 298 u16 watermark; 299 __be16 fifo_buf[ADXL372_FIFO_SIZE]; 300 bool peak_fifo_mode_en; 301 struct mutex threshold_m; /* lock for threshold */ 302 }; 303 304 static const unsigned long adxl372_channel_masks[] = { 305 BIT(0), BIT(1), BIT(2), 306 BIT(0) | BIT(1), 307 BIT(0) | BIT(2), 308 BIT(1) | BIT(2), 309 BIT(0) | BIT(1) | BIT(2), 310 0 311 }; 312 313 static ssize_t adxl372_read_threshold_value(struct iio_dev *indio_dev, unsigned int addr, 314 u16 *threshold) 315 { 316 struct adxl372_state *st = iio_priv(indio_dev); 317 __be16 raw_regval; 318 u16 regval; 319 int ret; 320 321 ret = regmap_bulk_read(st->regmap, addr, &raw_regval, sizeof(raw_regval)); 322 if (ret < 0) 323 return ret; 324 325 regval = be16_to_cpu(raw_regval); 326 regval >>= 5; 327 328 *threshold = regval; 329 330 return 0; 331 } 332 333 static ssize_t adxl372_write_threshold_value(struct iio_dev *indio_dev, unsigned int addr, 334 u16 threshold) 335 { 336 struct adxl372_state *st = iio_priv(indio_dev); 337 int ret; 338 339 mutex_lock(&st->threshold_m); 340 ret = regmap_write(st->regmap, addr, ADXL372_THRESH_VAL_H_SEL(threshold)); 341 if (ret < 0) 342 goto unlock; 343 344 ret = regmap_update_bits(st->regmap, addr + 1, GENMASK(7, 5), 345 ADXL372_THRESH_VAL_L_SEL(threshold) << 5); 346 347 unlock: 348 mutex_unlock(&st->threshold_m); 349 350 return ret; 351 } 352 353 static int adxl372_read_axis(struct adxl372_state *st, u8 addr) 354 { 355 __be16 regval; 356 int ret; 357 358 ret = regmap_bulk_read(st->regmap, addr, ®val, sizeof(regval)); 359 if (ret < 0) 360 return ret; 361 362 return be16_to_cpu(regval); 363 } 364 365 static int adxl372_set_op_mode(struct adxl372_state *st, 366 enum adxl372_op_mode op_mode) 367 { 368 int ret; 369 370 ret = regmap_update_bits(st->regmap, ADXL372_POWER_CTL, 371 ADXL372_POWER_CTL_MODE_MSK, 372 ADXL372_POWER_CTL_MODE(op_mode)); 373 if (ret < 0) 374 return ret; 375 376 st->op_mode = op_mode; 377 378 return ret; 379 } 380 381 static int adxl372_set_odr(struct adxl372_state *st, 382 enum adxl372_odr odr) 383 { 384 int ret; 385 386 ret = regmap_update_bits(st->regmap, ADXL372_TIMING, 387 ADXL372_TIMING_ODR_MSK, 388 ADXL372_TIMING_ODR_MODE(odr)); 389 if (ret < 0) 390 return ret; 391 392 st->odr = odr; 393 394 return ret; 395 } 396 397 static int adxl372_find_closest_match(const int *array, 398 unsigned int size, int val) 399 { 400 int i; 401 402 for (i = 0; i < size; i++) { 403 if (val <= array[i]) 404 return i; 405 } 406 407 return size - 1; 408 } 409 410 static int adxl372_set_bandwidth(struct adxl372_state *st, 411 enum adxl372_bandwidth bw) 412 { 413 int ret; 414 415 ret = regmap_update_bits(st->regmap, ADXL372_MEASURE, 416 ADXL372_MEASURE_BANDWIDTH_MSK, 417 ADXL372_MEASURE_BANDWIDTH_MODE(bw)); 418 if (ret < 0) 419 return ret; 420 421 st->bw = bw; 422 423 return ret; 424 } 425 426 static int adxl372_set_act_proc_mode(struct adxl372_state *st, 427 enum adxl372_act_proc_mode mode) 428 { 429 int ret; 430 431 ret = regmap_update_bits(st->regmap, 432 ADXL372_MEASURE, 433 ADXL372_MEASURE_LINKLOOP_MSK, 434 ADXL372_MEASURE_LINKLOOP_MODE(mode)); 435 if (ret < 0) 436 return ret; 437 438 st->act_proc_mode = mode; 439 440 return ret; 441 } 442 443 static int adxl372_set_activity_threshold(struct adxl372_state *st, 444 enum adxl372_th_activity act, 445 bool ref_en, bool enable, 446 unsigned int threshold) 447 { 448 unsigned char buf[6]; 449 unsigned char th_reg_high_val, th_reg_low_val, th_reg_high_addr; 450 451 /* scale factor is 100 mg/code */ 452 th_reg_high_val = (threshold / 100) >> 3; 453 th_reg_low_val = ((threshold / 100) << 5) | (ref_en << 1) | enable; 454 th_reg_high_addr = adxl372_th_reg_high_addr[act]; 455 456 buf[0] = th_reg_high_val; 457 buf[1] = th_reg_low_val; 458 buf[2] = th_reg_high_val; 459 buf[3] = th_reg_low_val; 460 buf[4] = th_reg_high_val; 461 buf[5] = th_reg_low_val; 462 463 return regmap_bulk_write(st->regmap, th_reg_high_addr, 464 buf, ARRAY_SIZE(buf)); 465 } 466 467 static int adxl372_set_activity_time_ms(struct adxl372_state *st, 468 unsigned int act_time_ms) 469 { 470 unsigned int reg_val, scale_factor; 471 int ret; 472 473 /* 474 * 3.3 ms per code is the scale factor of the TIME_ACT register for 475 * ODR = 6400 Hz. It is 6.6 ms per code for ODR = 3200 Hz and below. 476 */ 477 if (st->odr == ADXL372_ODR_6400HZ) 478 scale_factor = 3300; 479 else 480 scale_factor = 6600; 481 482 reg_val = DIV_ROUND_CLOSEST(act_time_ms * 1000, scale_factor); 483 484 /* TIME_ACT register is 8 bits wide */ 485 if (reg_val > 0xFF) 486 reg_val = 0xFF; 487 488 ret = regmap_write(st->regmap, ADXL372_TIME_ACT, reg_val); 489 if (ret < 0) 490 return ret; 491 492 st->act_time_ms = act_time_ms; 493 494 return ret; 495 } 496 497 static int adxl372_set_inactivity_time_ms(struct adxl372_state *st, 498 unsigned int inact_time_ms) 499 { 500 unsigned int reg_val_h, reg_val_l, res, scale_factor; 501 int ret; 502 503 /* 504 * 13 ms per code is the scale factor of the TIME_INACT register for 505 * ODR = 6400 Hz. It is 26 ms per code for ODR = 3200 Hz and below. 506 */ 507 if (st->odr == ADXL372_ODR_6400HZ) 508 scale_factor = 13; 509 else 510 scale_factor = 26; 511 512 res = DIV_ROUND_CLOSEST(inact_time_ms, scale_factor); 513 reg_val_h = (res >> 8) & 0xFF; 514 reg_val_l = res & 0xFF; 515 516 ret = regmap_write(st->regmap, ADXL372_TIME_INACT_H, reg_val_h); 517 if (ret < 0) 518 return ret; 519 520 ret = regmap_write(st->regmap, ADXL372_TIME_INACT_L, reg_val_l); 521 if (ret < 0) 522 return ret; 523 524 st->inact_time_ms = inact_time_ms; 525 526 return ret; 527 } 528 529 static int adxl372_set_interrupts(struct adxl372_state *st, 530 unsigned long int1_bitmask, 531 unsigned long int2_bitmask) 532 { 533 int ret; 534 535 ret = regmap_write(st->regmap, ADXL372_INT1_MAP, int1_bitmask); 536 if (ret < 0) 537 return ret; 538 539 return regmap_write(st->regmap, ADXL372_INT2_MAP, int2_bitmask); 540 } 541 542 static int adxl372_configure_fifo(struct adxl372_state *st) 543 { 544 unsigned int fifo_samples, fifo_ctl; 545 int ret; 546 547 /* FIFO must be configured while in standby mode */ 548 ret = adxl372_set_op_mode(st, ADXL372_STANDBY); 549 if (ret < 0) 550 return ret; 551 552 /* 553 * watermark stores the number of sets; we need to write the FIFO 554 * registers with the number of samples 555 */ 556 fifo_samples = (st->watermark * st->fifo_set_size); 557 fifo_ctl = ADXL372_FIFO_CTL_FORMAT_MODE(st->fifo_format) | 558 ADXL372_FIFO_CTL_MODE_MODE(st->fifo_mode) | 559 ADXL372_FIFO_CTL_SAMPLES_MODE(fifo_samples); 560 561 ret = regmap_write(st->regmap, 562 ADXL372_FIFO_SAMPLES, fifo_samples & 0xFF); 563 if (ret < 0) 564 return ret; 565 566 ret = regmap_write(st->regmap, ADXL372_FIFO_CTL, fifo_ctl); 567 if (ret < 0) 568 return ret; 569 570 return adxl372_set_op_mode(st, ADXL372_FULL_BW_MEASUREMENT); 571 } 572 573 static int adxl372_get_status(struct adxl372_state *st, 574 u8 *status1, u8 *status2, 575 u16 *fifo_entries) 576 { 577 __be32 buf; 578 u32 val; 579 int ret; 580 581 /* STATUS1, STATUS2, FIFO_ENTRIES2 and FIFO_ENTRIES are adjacent regs */ 582 ret = regmap_bulk_read(st->regmap, ADXL372_STATUS_1, 583 &buf, sizeof(buf)); 584 if (ret < 0) 585 return ret; 586 587 val = be32_to_cpu(buf); 588 589 *status1 = (val >> 24) & 0x0F; 590 *status2 = (val >> 16) & 0x0F; 591 /* 592 * FIFO_ENTRIES contains the least significant byte, and FIFO_ENTRIES2 593 * contains the two most significant bits 594 */ 595 *fifo_entries = val & 0x3FF; 596 597 return ret; 598 } 599 600 static void adxl372_arrange_axis_data(struct adxl372_state *st, __be16 *sample) 601 { 602 __be16 axis_sample[3] = { }; 603 int i = 0; 604 605 if (ADXL372_X_AXIS_EN(st->fifo_axis_mask)) 606 axis_sample[i++] = sample[0]; 607 if (ADXL372_Y_AXIS_EN(st->fifo_axis_mask)) 608 axis_sample[i++] = sample[1]; 609 if (ADXL372_Z_AXIS_EN(st->fifo_axis_mask)) 610 axis_sample[i++] = sample[2]; 611 612 memcpy(sample, axis_sample, 3 * sizeof(__be16)); 613 } 614 615 static void adxl372_push_event(struct iio_dev *indio_dev, s64 timestamp, u8 status2) 616 { 617 unsigned int ev_dir = IIO_EV_DIR_NONE; 618 619 if (ADXL372_STATUS_2_ACT(status2)) 620 ev_dir = IIO_EV_DIR_RISING; 621 622 if (ADXL372_STATUS_2_INACT(status2)) 623 ev_dir = IIO_EV_DIR_FALLING; 624 625 if (ev_dir != IIO_EV_DIR_NONE) 626 iio_push_event(indio_dev, 627 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z, 628 IIO_EV_TYPE_THRESH, ev_dir), 629 timestamp); 630 } 631 632 static irqreturn_t adxl372_trigger_handler(int irq, void *p) 633 { 634 struct iio_poll_func *pf = p; 635 struct iio_dev *indio_dev = pf->indio_dev; 636 struct adxl372_state *st = iio_priv(indio_dev); 637 u8 status1, status2; 638 u16 fifo_entries; 639 int i, ret; 640 641 ret = adxl372_get_status(st, &status1, &status2, &fifo_entries); 642 if (ret < 0) 643 goto err; 644 645 adxl372_push_event(indio_dev, iio_get_time_ns(indio_dev), status2); 646 647 if (st->fifo_mode != ADXL372_FIFO_BYPASSED && 648 ADXL372_STATUS_1_FIFO_FULL(status1)) { 649 /* 650 * When reading data from multiple axes from the FIFO, 651 * to ensure that data is not overwritten and stored out 652 * of order at least one sample set must be left in the 653 * FIFO after every read. 654 */ 655 fifo_entries -= st->fifo_set_size; 656 657 /* Read data from the FIFO */ 658 ret = regmap_noinc_read(st->regmap, ADXL372_FIFO_DATA, 659 st->fifo_buf, 660 fifo_entries * sizeof(u16)); 661 if (ret < 0) 662 goto err; 663 664 /* Each sample is 2 bytes */ 665 for (i = 0; i < fifo_entries; i += st->fifo_set_size) { 666 /* filter peak detection data */ 667 if (st->peak_fifo_mode_en) 668 adxl372_arrange_axis_data(st, &st->fifo_buf[i]); 669 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]); 670 } 671 } 672 err: 673 iio_trigger_notify_done(indio_dev->trig); 674 return IRQ_HANDLED; 675 } 676 677 static int adxl372_setup(struct adxl372_state *st) 678 { 679 unsigned int regval; 680 int ret; 681 682 ret = regmap_read(st->regmap, ADXL372_DEVID, ®val); 683 if (ret < 0) 684 return ret; 685 686 if (regval != ADXL372_DEVID_VAL) { 687 dev_err(st->dev, "Invalid chip id %x\n", regval); 688 return -ENODEV; 689 } 690 691 /* 692 * Perform a software reset to make sure the device is in a consistent 693 * state after start up. 694 */ 695 ret = regmap_write(st->regmap, ADXL372_RESET, ADXL372_RESET_CODE); 696 if (ret < 0) 697 return ret; 698 699 ret = adxl372_set_op_mode(st, ADXL372_STANDBY); 700 if (ret < 0) 701 return ret; 702 703 /* Set threshold for activity detection to 1g */ 704 ret = adxl372_set_activity_threshold(st, ADXL372_ACTIVITY, 705 true, true, 1000); 706 if (ret < 0) 707 return ret; 708 709 /* Set threshold for inactivity detection to 100mg */ 710 ret = adxl372_set_activity_threshold(st, ADXL372_INACTIVITY, 711 true, true, 100); 712 if (ret < 0) 713 return ret; 714 715 /* Set activity processing in Looped mode */ 716 ret = adxl372_set_act_proc_mode(st, ADXL372_LOOPED); 717 if (ret < 0) 718 return ret; 719 720 ret = adxl372_set_odr(st, ADXL372_ODR_6400HZ); 721 if (ret < 0) 722 return ret; 723 724 ret = adxl372_set_bandwidth(st, ADXL372_BW_3200HZ); 725 if (ret < 0) 726 return ret; 727 728 /* Set activity timer to 1ms */ 729 ret = adxl372_set_activity_time_ms(st, 1); 730 if (ret < 0) 731 return ret; 732 733 /* Set inactivity timer to 10s */ 734 ret = adxl372_set_inactivity_time_ms(st, 10000); 735 if (ret < 0) 736 return ret; 737 738 /* Set the mode of operation to full bandwidth measurement mode */ 739 return adxl372_set_op_mode(st, ADXL372_FULL_BW_MEASUREMENT); 740 } 741 742 static int adxl372_reg_access(struct iio_dev *indio_dev, 743 unsigned int reg, 744 unsigned int writeval, 745 unsigned int *readval) 746 { 747 struct adxl372_state *st = iio_priv(indio_dev); 748 749 if (readval) 750 return regmap_read(st->regmap, reg, readval); 751 else 752 return regmap_write(st->regmap, reg, writeval); 753 } 754 755 static int adxl372_read_raw(struct iio_dev *indio_dev, 756 struct iio_chan_spec const *chan, 757 int *val, int *val2, long info) 758 { 759 struct adxl372_state *st = iio_priv(indio_dev); 760 int ret; 761 762 switch (info) { 763 case IIO_CHAN_INFO_RAW: 764 if (!iio_device_claim_direct(indio_dev)) 765 return -EBUSY; 766 767 ret = adxl372_read_axis(st, chan->address); 768 iio_device_release_direct(indio_dev); 769 if (ret < 0) 770 return ret; 771 772 *val = sign_extend32(ret >> chan->scan_type.shift, 773 chan->scan_type.realbits - 1); 774 return IIO_VAL_INT; 775 case IIO_CHAN_INFO_SCALE: 776 *val = 0; 777 *val2 = ADXL372_USCALE; 778 return IIO_VAL_INT_PLUS_MICRO; 779 case IIO_CHAN_INFO_SAMP_FREQ: 780 *val = adxl372_samp_freq_tbl[st->odr]; 781 return IIO_VAL_INT; 782 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 783 *val = adxl372_bw_freq_tbl[st->bw]; 784 return IIO_VAL_INT; 785 } 786 787 return -EINVAL; 788 } 789 790 static int adxl372_write_raw(struct iio_dev *indio_dev, 791 struct iio_chan_spec const *chan, 792 int val, int val2, long info) 793 { 794 struct adxl372_state *st = iio_priv(indio_dev); 795 int odr_index, bw_index, ret; 796 797 switch (info) { 798 case IIO_CHAN_INFO_SAMP_FREQ: 799 odr_index = adxl372_find_closest_match(adxl372_samp_freq_tbl, 800 ARRAY_SIZE(adxl372_samp_freq_tbl), 801 val); 802 ret = adxl372_set_odr(st, odr_index); 803 if (ret < 0) 804 return ret; 805 /* 806 * The timer period depends on the ODR selected. 807 * At 3200 Hz and below, it is 6.6 ms; at 6400 Hz, it is 3.3 ms 808 */ 809 ret = adxl372_set_activity_time_ms(st, st->act_time_ms); 810 if (ret < 0) 811 return ret; 812 /* 813 * The timer period depends on the ODR selected. 814 * At 3200 Hz and below, it is 26 ms; at 6400 Hz, it is 13 ms 815 */ 816 ret = adxl372_set_inactivity_time_ms(st, st->inact_time_ms); 817 if (ret < 0) 818 return ret; 819 /* 820 * The maximum bandwidth is constrained to at most half of 821 * the ODR to ensure that the Nyquist criteria is not violated 822 */ 823 if (st->bw > odr_index) 824 ret = adxl372_set_bandwidth(st, odr_index); 825 826 return ret; 827 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 828 bw_index = adxl372_find_closest_match(adxl372_bw_freq_tbl, 829 ARRAY_SIZE(adxl372_bw_freq_tbl), 830 val); 831 return adxl372_set_bandwidth(st, bw_index); 832 default: 833 return -EINVAL; 834 } 835 } 836 837 static int adxl372_read_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, 838 enum iio_event_type type, enum iio_event_direction dir, 839 enum iio_event_info info, int *val, int *val2) 840 { 841 struct adxl372_state *st = iio_priv(indio_dev); 842 unsigned int addr; 843 u16 raw_value; 844 int ret; 845 846 switch (info) { 847 case IIO_EV_INFO_VALUE: 848 switch (dir) { 849 case IIO_EV_DIR_RISING: 850 addr = ADXL372_X_THRESH_ACT_H + 2 * chan->scan_index; 851 ret = adxl372_read_threshold_value(indio_dev, addr, &raw_value); 852 if (ret < 0) 853 return ret; 854 *val = raw_value * ADXL372_USCALE; 855 *val2 = 1000000; 856 return IIO_VAL_FRACTIONAL; 857 case IIO_EV_DIR_FALLING: 858 addr = ADXL372_X_THRESH_INACT_H + 2 * chan->scan_index; 859 ret = adxl372_read_threshold_value(indio_dev, addr, &raw_value); 860 if (ret < 0) 861 return ret; 862 *val = raw_value * ADXL372_USCALE; 863 *val2 = 1000000; 864 return IIO_VAL_FRACTIONAL; 865 default: 866 return -EINVAL; 867 } 868 case IIO_EV_INFO_PERIOD: 869 switch (dir) { 870 case IIO_EV_DIR_RISING: 871 *val = st->act_time_ms; 872 *val2 = 1000; 873 return IIO_VAL_FRACTIONAL; 874 case IIO_EV_DIR_FALLING: 875 *val = st->inact_time_ms; 876 *val2 = 1000; 877 return IIO_VAL_FRACTIONAL; 878 default: 879 return -EINVAL; 880 } 881 default: 882 return -EINVAL; 883 } 884 } 885 886 static int adxl372_write_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, 887 enum iio_event_type type, enum iio_event_direction dir, 888 enum iio_event_info info, int val, int val2) 889 { 890 struct adxl372_state *st = iio_priv(indio_dev); 891 unsigned int val_ms; 892 unsigned int addr; 893 u16 raw_val; 894 895 switch (info) { 896 case IIO_EV_INFO_VALUE: 897 raw_val = DIV_ROUND_UP(val * 1000000, ADXL372_USCALE); 898 switch (dir) { 899 case IIO_EV_DIR_RISING: 900 addr = ADXL372_X_THRESH_ACT_H + 2 * chan->scan_index; 901 return adxl372_write_threshold_value(indio_dev, addr, raw_val); 902 case IIO_EV_DIR_FALLING: 903 addr = ADXL372_X_THRESH_INACT_H + 2 * chan->scan_index; 904 return adxl372_write_threshold_value(indio_dev, addr, raw_val); 905 default: 906 return -EINVAL; 907 } 908 case IIO_EV_INFO_PERIOD: 909 val_ms = val * 1000 + DIV_ROUND_UP(val2, 1000); 910 switch (dir) { 911 case IIO_EV_DIR_RISING: 912 return adxl372_set_activity_time_ms(st, val_ms); 913 case IIO_EV_DIR_FALLING: 914 return adxl372_set_inactivity_time_ms(st, val_ms); 915 default: 916 return -EINVAL; 917 } 918 default: 919 return -EINVAL; 920 } 921 } 922 923 static int adxl372_read_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, 924 enum iio_event_type type, enum iio_event_direction dir) 925 { 926 struct adxl372_state *st = iio_priv(indio_dev); 927 928 switch (dir) { 929 case IIO_EV_DIR_RISING: 930 return FIELD_GET(ADXL372_INT1_MAP_ACT_MSK, st->int1_bitmask); 931 case IIO_EV_DIR_FALLING: 932 return FIELD_GET(ADXL372_INT1_MAP_INACT_MSK, st->int1_bitmask); 933 default: 934 return -EINVAL; 935 } 936 } 937 938 static int adxl372_write_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, 939 enum iio_event_type type, enum iio_event_direction dir, 940 bool state) 941 { 942 struct adxl372_state *st = iio_priv(indio_dev); 943 944 switch (dir) { 945 case IIO_EV_DIR_RISING: 946 set_mask_bits(&st->int1_bitmask, ADXL372_INT1_MAP_ACT_MSK, 947 ADXL372_INT1_MAP_ACT_MODE(state)); 948 break; 949 case IIO_EV_DIR_FALLING: 950 set_mask_bits(&st->int1_bitmask, ADXL372_INT1_MAP_INACT_MSK, 951 ADXL372_INT1_MAP_INACT_MODE(state)); 952 break; 953 default: 954 return -EINVAL; 955 } 956 957 return adxl372_set_interrupts(st, st->int1_bitmask, 0); 958 } 959 960 static ssize_t adxl372_show_filter_freq_avail(struct device *dev, 961 struct device_attribute *attr, 962 char *buf) 963 { 964 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 965 struct adxl372_state *st = iio_priv(indio_dev); 966 int i; 967 size_t len = 0; 968 969 for (i = 0; i <= st->odr; i++) 970 len += scnprintf(buf + len, PAGE_SIZE - len, 971 "%d ", adxl372_bw_freq_tbl[i]); 972 973 buf[len - 1] = '\n'; 974 975 return len; 976 } 977 978 static ssize_t adxl372_get_fifo_enabled(struct device *dev, 979 struct device_attribute *attr, 980 char *buf) 981 { 982 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 983 struct adxl372_state *st = iio_priv(indio_dev); 984 985 return sprintf(buf, "%d\n", st->fifo_mode); 986 } 987 988 static ssize_t adxl372_get_fifo_watermark(struct device *dev, 989 struct device_attribute *attr, 990 char *buf) 991 { 992 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 993 struct adxl372_state *st = iio_priv(indio_dev); 994 995 return sprintf(buf, "%d\n", st->watermark); 996 } 997 998 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "1"); 999 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max, 1000 __stringify(ADXL372_FIFO_SIZE)); 1001 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 1002 adxl372_get_fifo_watermark, NULL, 0); 1003 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 1004 adxl372_get_fifo_enabled, NULL, 0); 1005 1006 static const struct iio_dev_attr *adxl372_fifo_attributes[] = { 1007 &iio_dev_attr_hwfifo_watermark_min, 1008 &iio_dev_attr_hwfifo_watermark_max, 1009 &iio_dev_attr_hwfifo_watermark, 1010 &iio_dev_attr_hwfifo_enabled, 1011 NULL, 1012 }; 1013 1014 static int adxl372_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1015 { 1016 struct adxl372_state *st = iio_priv(indio_dev); 1017 1018 if (val > ADXL372_FIFO_SIZE) 1019 val = ADXL372_FIFO_SIZE; 1020 1021 st->watermark = val; 1022 1023 return 0; 1024 } 1025 1026 static int adxl372_buffer_postenable(struct iio_dev *indio_dev) 1027 { 1028 struct adxl372_state *st = iio_priv(indio_dev); 1029 unsigned int mask; 1030 int i, ret; 1031 1032 st->int1_bitmask |= ADXL372_INT1_MAP_FIFO_FULL_MSK; 1033 ret = adxl372_set_interrupts(st, st->int1_bitmask, 0); 1034 if (ret < 0) 1035 return ret; 1036 1037 mask = *indio_dev->active_scan_mask; 1038 1039 for (i = 0; i < ARRAY_SIZE(adxl372_axis_lookup_table); i++) { 1040 if (mask == adxl372_axis_lookup_table[i].bits) 1041 break; 1042 } 1043 1044 if (i == ARRAY_SIZE(adxl372_axis_lookup_table)) 1045 return -EINVAL; 1046 1047 st->fifo_format = adxl372_axis_lookup_table[i].fifo_format; 1048 st->fifo_axis_mask = adxl372_axis_lookup_table[i].bits; 1049 st->fifo_set_size = bitmap_weight(indio_dev->active_scan_mask, 1050 iio_get_masklength(indio_dev)); 1051 1052 /* Configure the FIFO to store sets of impact event peak. */ 1053 if (st->peak_fifo_mode_en) { 1054 st->fifo_set_size = 3; 1055 st->fifo_format = ADXL372_XYZ_PEAK_FIFO; 1056 } 1057 1058 /* 1059 * The 512 FIFO samples can be allotted in several ways, such as: 1060 * 170 sample sets of concurrent 3-axis data 1061 * 256 sample sets of concurrent 2-axis data (user selectable) 1062 * 512 sample sets of single-axis data 1063 * 170 sets of impact event peak (x, y, z) 1064 */ 1065 if ((st->watermark * st->fifo_set_size) > ADXL372_FIFO_SIZE) 1066 st->watermark = (ADXL372_FIFO_SIZE / st->fifo_set_size); 1067 1068 st->fifo_mode = ADXL372_FIFO_STREAMED; 1069 1070 ret = adxl372_configure_fifo(st); 1071 if (ret < 0) { 1072 st->fifo_mode = ADXL372_FIFO_BYPASSED; 1073 st->int1_bitmask &= ~ADXL372_INT1_MAP_FIFO_FULL_MSK; 1074 adxl372_set_interrupts(st, st->int1_bitmask, 0); 1075 return ret; 1076 } 1077 1078 return 0; 1079 } 1080 1081 static int adxl372_buffer_predisable(struct iio_dev *indio_dev) 1082 { 1083 struct adxl372_state *st = iio_priv(indio_dev); 1084 1085 st->int1_bitmask &= ~ADXL372_INT1_MAP_FIFO_FULL_MSK; 1086 adxl372_set_interrupts(st, st->int1_bitmask, 0); 1087 st->fifo_mode = ADXL372_FIFO_BYPASSED; 1088 adxl372_configure_fifo(st); 1089 1090 return 0; 1091 } 1092 1093 static const struct iio_buffer_setup_ops adxl372_buffer_ops = { 1094 .postenable = adxl372_buffer_postenable, 1095 .predisable = adxl372_buffer_predisable, 1096 }; 1097 1098 static int adxl372_dready_trig_set_state(struct iio_trigger *trig, 1099 bool state) 1100 { 1101 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1102 struct adxl372_state *st = iio_priv(indio_dev); 1103 1104 if (state) 1105 st->int1_bitmask |= ADXL372_INT1_MAP_FIFO_FULL_MSK; 1106 1107 return adxl372_set_interrupts(st, st->int1_bitmask, 0); 1108 } 1109 1110 static int adxl372_validate_trigger(struct iio_dev *indio_dev, 1111 struct iio_trigger *trig) 1112 { 1113 struct adxl372_state *st = iio_priv(indio_dev); 1114 1115 if (st->dready_trig != trig && st->peak_datardy_trig != trig) 1116 return -EINVAL; 1117 1118 return 0; 1119 } 1120 1121 static const struct iio_trigger_ops adxl372_trigger_ops = { 1122 .validate_device = &iio_trigger_validate_own_device, 1123 .set_trigger_state = adxl372_dready_trig_set_state, 1124 }; 1125 1126 static int adxl372_peak_dready_trig_set_state(struct iio_trigger *trig, 1127 bool state) 1128 { 1129 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1130 struct adxl372_state *st = iio_priv(indio_dev); 1131 1132 if (state) 1133 st->int1_bitmask |= ADXL372_INT1_MAP_FIFO_FULL_MSK; 1134 1135 st->peak_fifo_mode_en = state; 1136 1137 return adxl372_set_interrupts(st, st->int1_bitmask, 0); 1138 } 1139 1140 static const struct iio_trigger_ops adxl372_peak_data_trigger_ops = { 1141 .validate_device = &iio_trigger_validate_own_device, 1142 .set_trigger_state = adxl372_peak_dready_trig_set_state, 1143 }; 1144 1145 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("400 800 1600 3200 6400"); 1146 static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available, 1147 0444, adxl372_show_filter_freq_avail, NULL, 0); 1148 1149 static struct attribute *adxl372_attributes[] = { 1150 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 1151 &iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available.dev_attr.attr, 1152 NULL, 1153 }; 1154 1155 static const struct attribute_group adxl372_attrs_group = { 1156 .attrs = adxl372_attributes, 1157 }; 1158 1159 static const struct iio_info adxl372_info = { 1160 .validate_trigger = &adxl372_validate_trigger, 1161 .attrs = &adxl372_attrs_group, 1162 .read_raw = adxl372_read_raw, 1163 .write_raw = adxl372_write_raw, 1164 .read_event_config = adxl372_read_event_config, 1165 .write_event_config = adxl372_write_event_config, 1166 .read_event_value = adxl372_read_event_value, 1167 .write_event_value = adxl372_write_event_value, 1168 .debugfs_reg_access = &adxl372_reg_access, 1169 .hwfifo_set_watermark = adxl372_set_watermark, 1170 }; 1171 1172 bool adxl372_readable_noinc_reg(struct device *dev, unsigned int reg) 1173 { 1174 return (reg == ADXL372_FIFO_DATA); 1175 } 1176 EXPORT_SYMBOL_NS_GPL(adxl372_readable_noinc_reg, "IIO_ADXL372"); 1177 1178 int adxl372_probe(struct device *dev, struct regmap *regmap, 1179 int irq, const char *name) 1180 { 1181 struct iio_dev *indio_dev; 1182 struct adxl372_state *st; 1183 int ret; 1184 1185 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1186 if (!indio_dev) 1187 return -ENOMEM; 1188 1189 st = iio_priv(indio_dev); 1190 dev_set_drvdata(dev, indio_dev); 1191 1192 st->dev = dev; 1193 st->regmap = regmap; 1194 st->irq = irq; 1195 1196 mutex_init(&st->threshold_m); 1197 1198 indio_dev->channels = adxl372_channels; 1199 indio_dev->num_channels = ARRAY_SIZE(adxl372_channels); 1200 indio_dev->available_scan_masks = adxl372_channel_masks; 1201 indio_dev->name = name; 1202 indio_dev->info = &adxl372_info; 1203 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 1204 1205 ret = adxl372_setup(st); 1206 if (ret < 0) { 1207 dev_err(dev, "ADXL372 setup failed\n"); 1208 return ret; 1209 } 1210 1211 ret = devm_iio_triggered_buffer_setup_ext(dev, 1212 indio_dev, NULL, 1213 adxl372_trigger_handler, 1214 IIO_BUFFER_DIRECTION_IN, 1215 &adxl372_buffer_ops, 1216 adxl372_fifo_attributes); 1217 if (ret < 0) 1218 return ret; 1219 1220 if (st->irq) { 1221 st->dready_trig = devm_iio_trigger_alloc(dev, 1222 "%s-dev%d", 1223 indio_dev->name, 1224 iio_device_id(indio_dev)); 1225 if (st->dready_trig == NULL) 1226 return -ENOMEM; 1227 1228 st->peak_datardy_trig = devm_iio_trigger_alloc(dev, 1229 "%s-dev%d-peak", 1230 indio_dev->name, 1231 iio_device_id(indio_dev)); 1232 if (!st->peak_datardy_trig) 1233 return -ENOMEM; 1234 1235 st->dready_trig->ops = &adxl372_trigger_ops; 1236 st->peak_datardy_trig->ops = &adxl372_peak_data_trigger_ops; 1237 iio_trigger_set_drvdata(st->dready_trig, indio_dev); 1238 iio_trigger_set_drvdata(st->peak_datardy_trig, indio_dev); 1239 ret = devm_iio_trigger_register(dev, st->dready_trig); 1240 if (ret < 0) 1241 return ret; 1242 1243 ret = devm_iio_trigger_register(dev, st->peak_datardy_trig); 1244 if (ret < 0) 1245 return ret; 1246 1247 indio_dev->trig = iio_trigger_get(st->dready_trig); 1248 1249 ret = devm_request_irq(dev, st->irq, 1250 iio_trigger_generic_data_rdy_poll, 1251 IRQF_TRIGGER_RISING | IRQF_NO_THREAD, 1252 indio_dev->name, st->dready_trig); 1253 if (ret < 0) 1254 return ret; 1255 } 1256 1257 return devm_iio_device_register(dev, indio_dev); 1258 } 1259 EXPORT_SYMBOL_NS_GPL(adxl372_probe, "IIO_ADXL372"); 1260 1261 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 1262 MODULE_DESCRIPTION("Analog Devices ADXL372 3-axis accelerometer driver"); 1263 MODULE_LICENSE("GPL"); 1264