1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2021 Analog Devices, Inc. 4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/iio/buffer.h> 10 #include <linux/iio/events.h> 11 #include <linux/iio/iio.h> 12 #include <linux/iio/kfifo_buf.h> 13 #include <linux/iio/sysfs.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <asm/unaligned.h> 20 21 #include "adxl367.h" 22 23 #define ADXL367_REG_DEVID 0x00 24 #define ADXL367_DEVID_AD 0xAD 25 26 #define ADXL367_REG_STATUS 0x0B 27 #define ADXL367_STATUS_INACT_MASK BIT(5) 28 #define ADXL367_STATUS_ACT_MASK BIT(4) 29 #define ADXL367_STATUS_FIFO_FULL_MASK BIT(2) 30 31 #define ADXL367_FIFO_ENT_H_MASK GENMASK(1, 0) 32 33 #define ADXL367_REG_X_DATA_H 0x0E 34 #define ADXL367_REG_Y_DATA_H 0x10 35 #define ADXL367_REG_Z_DATA_H 0x12 36 #define ADXL367_REG_TEMP_DATA_H 0x14 37 #define ADXL367_REG_EX_ADC_DATA_H 0x16 38 #define ADXL367_DATA_MASK GENMASK(15, 2) 39 40 #define ADXL367_TEMP_25C 165 41 #define ADXL367_TEMP_PER_C 54 42 43 #define ADXL367_VOLTAGE_OFFSET 8192 44 #define ADXL367_VOLTAGE_MAX_MV 1000 45 #define ADXL367_VOLTAGE_MAX_RAW GENMASK(13, 0) 46 47 #define ADXL367_REG_RESET 0x1F 48 #define ADXL367_RESET_CODE 0x52 49 50 #define ADXL367_REG_THRESH_ACT_H 0x20 51 #define ADXL367_REG_THRESH_INACT_H 0x23 52 #define ADXL367_THRESH_MAX GENMASK(12, 0) 53 #define ADXL367_THRESH_VAL_H_MASK GENMASK(12, 6) 54 #define ADXL367_THRESH_H_MASK GENMASK(6, 0) 55 #define ADXL367_THRESH_VAL_L_MASK GENMASK(5, 0) 56 #define ADXL367_THRESH_L_MASK GENMASK(7, 2) 57 58 #define ADXL367_REG_TIME_ACT 0x22 59 #define ADXL367_REG_TIME_INACT_H 0x25 60 #define ADXL367_TIME_ACT_MAX GENMASK(7, 0) 61 #define ADXL367_TIME_INACT_MAX GENMASK(15, 0) 62 #define ADXL367_TIME_INACT_VAL_H_MASK GENMASK(15, 8) 63 #define ADXL367_TIME_INACT_H_MASK GENMASK(7, 0) 64 #define ADXL367_TIME_INACT_VAL_L_MASK GENMASK(7, 0) 65 #define ADXL367_TIME_INACT_L_MASK GENMASK(7, 0) 66 67 #define ADXL367_REG_ACT_INACT_CTL 0x27 68 #define ADXL367_ACT_EN_MASK GENMASK(1, 0) 69 #define ADXL367_ACT_LINKLOOP_MASK GENMASK(5, 4) 70 71 #define ADXL367_REG_FIFO_CTL 0x28 72 #define ADXL367_FIFO_CTL_FORMAT_MASK GENMASK(6, 3) 73 #define ADXL367_FIFO_CTL_MODE_MASK GENMASK(1, 0) 74 75 #define ADXL367_REG_FIFO_SAMPLES 0x29 76 #define ADXL367_FIFO_SIZE 512 77 #define ADXL367_FIFO_MAX_WATERMARK 511 78 79 #define ADXL367_SAMPLES_VAL_H_MASK BIT(8) 80 #define ADXL367_SAMPLES_H_MASK BIT(2) 81 #define ADXL367_SAMPLES_VAL_L_MASK GENMASK(7, 0) 82 #define ADXL367_SAMPLES_L_MASK GENMASK(7, 0) 83 84 #define ADXL367_REG_INT1_MAP 0x2A 85 #define ADXL367_INT_INACT_MASK BIT(5) 86 #define ADXL367_INT_ACT_MASK BIT(4) 87 #define ADXL367_INT_FIFO_WATERMARK_MASK BIT(2) 88 89 #define ADXL367_REG_FILTER_CTL 0x2C 90 #define ADXL367_FILTER_CTL_RANGE_MASK GENMASK(7, 6) 91 #define ADXL367_2G_RANGE_1G 4095 92 #define ADXL367_2G_RANGE_100MG 409 93 #define ADXL367_FILTER_CTL_ODR_MASK GENMASK(2, 0) 94 95 #define ADXL367_REG_POWER_CTL 0x2D 96 #define ADXL367_POWER_CTL_MODE_MASK GENMASK(1, 0) 97 98 #define ADXL367_REG_ADC_CTL 0x3C 99 #define ADXL367_REG_TEMP_CTL 0x3D 100 #define ADXL367_ADC_EN_MASK BIT(0) 101 102 enum adxl367_range { 103 ADXL367_2G_RANGE, 104 ADXL367_4G_RANGE, 105 ADXL367_8G_RANGE, 106 }; 107 108 enum adxl367_fifo_mode { 109 ADXL367_FIFO_MODE_DISABLED = 0b00, 110 ADXL367_FIFO_MODE_STREAM = 0b10, 111 }; 112 113 enum adxl367_fifo_format { 114 ADXL367_FIFO_FORMAT_XYZ, 115 ADXL367_FIFO_FORMAT_X, 116 ADXL367_FIFO_FORMAT_Y, 117 ADXL367_FIFO_FORMAT_Z, 118 ADXL367_FIFO_FORMAT_XYZT, 119 ADXL367_FIFO_FORMAT_XT, 120 ADXL367_FIFO_FORMAT_YT, 121 ADXL367_FIFO_FORMAT_ZT, 122 ADXL367_FIFO_FORMAT_XYZA, 123 ADXL367_FIFO_FORMAT_XA, 124 ADXL367_FIFO_FORMAT_YA, 125 ADXL367_FIFO_FORMAT_ZA, 126 }; 127 128 enum adxl367_op_mode { 129 ADXL367_OP_STANDBY = 0b00, 130 ADXL367_OP_MEASURE = 0b10, 131 }; 132 133 enum adxl367_act_proc_mode { 134 ADXL367_LOOPED = 0b11, 135 }; 136 137 enum adxl367_act_en_mode { 138 ADXL367_ACT_DISABLED = 0b00, 139 ADCL367_ACT_REF_ENABLED = 0b11, 140 }; 141 142 enum adxl367_activity_type { 143 ADXL367_ACTIVITY, 144 ADXL367_INACTIVITY, 145 }; 146 147 enum adxl367_odr { 148 ADXL367_ODR_12P5HZ, 149 ADXL367_ODR_25HZ, 150 ADXL367_ODR_50HZ, 151 ADXL367_ODR_100HZ, 152 ADXL367_ODR_200HZ, 153 ADXL367_ODR_400HZ, 154 }; 155 156 struct adxl367_state { 157 const struct adxl367_ops *ops; 158 void *context; 159 160 struct device *dev; 161 struct regmap *regmap; 162 163 /* 164 * Synchronize access to members of driver state, and ensure atomicity 165 * of consecutive regmap operations. 166 */ 167 struct mutex lock; 168 169 enum adxl367_odr odr; 170 enum adxl367_range range; 171 172 unsigned int act_threshold; 173 unsigned int act_time_ms; 174 unsigned int inact_threshold; 175 unsigned int inact_time_ms; 176 177 unsigned int fifo_set_size; 178 unsigned int fifo_watermark; 179 180 __be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN); 181 __be16 sample_buf; 182 u8 act_threshold_buf[2]; 183 u8 inact_time_buf[2]; 184 u8 status_buf[3]; 185 }; 186 187 static const unsigned int adxl367_threshold_h_reg_tbl[] = { 188 [ADXL367_ACTIVITY] = ADXL367_REG_THRESH_ACT_H, 189 [ADXL367_INACTIVITY] = ADXL367_REG_THRESH_INACT_H, 190 }; 191 192 static const unsigned int adxl367_act_en_shift_tbl[] = { 193 [ADXL367_ACTIVITY] = 0, 194 [ADXL367_INACTIVITY] = 2, 195 }; 196 197 static const unsigned int adxl367_act_int_mask_tbl[] = { 198 [ADXL367_ACTIVITY] = ADXL367_INT_ACT_MASK, 199 [ADXL367_INACTIVITY] = ADXL367_INT_INACT_MASK, 200 }; 201 202 static const int adxl367_samp_freq_tbl[][2] = { 203 [ADXL367_ODR_12P5HZ] = {12, 500000}, 204 [ADXL367_ODR_25HZ] = {25, 0}, 205 [ADXL367_ODR_50HZ] = {50, 0}, 206 [ADXL367_ODR_100HZ] = {100, 0}, 207 [ADXL367_ODR_200HZ] = {200, 0}, 208 [ADXL367_ODR_400HZ] = {400, 0}, 209 }; 210 211 /* (g * 2) * 9.80665 * 1000000 / (2^14 - 1) */ 212 static const int adxl367_range_scale_tbl[][2] = { 213 [ADXL367_2G_RANGE] = {0, 2394347}, 214 [ADXL367_4G_RANGE] = {0, 4788695}, 215 [ADXL367_8G_RANGE] = {0, 9577391}, 216 }; 217 218 static const int adxl367_range_scale_factor_tbl[] = { 219 [ADXL367_2G_RANGE] = 1, 220 [ADXL367_4G_RANGE] = 2, 221 [ADXL367_8G_RANGE] = 4, 222 }; 223 224 enum { 225 ADXL367_X_CHANNEL_INDEX, 226 ADXL367_Y_CHANNEL_INDEX, 227 ADXL367_Z_CHANNEL_INDEX, 228 ADXL367_TEMP_CHANNEL_INDEX, 229 ADXL367_EX_ADC_CHANNEL_INDEX 230 }; 231 232 #define ADXL367_X_CHANNEL_MASK BIT(ADXL367_X_CHANNEL_INDEX) 233 #define ADXL367_Y_CHANNEL_MASK BIT(ADXL367_Y_CHANNEL_INDEX) 234 #define ADXL367_Z_CHANNEL_MASK BIT(ADXL367_Z_CHANNEL_INDEX) 235 #define ADXL367_TEMP_CHANNEL_MASK BIT(ADXL367_TEMP_CHANNEL_INDEX) 236 #define ADXL367_EX_ADC_CHANNEL_MASK BIT(ADXL367_EX_ADC_CHANNEL_INDEX) 237 238 static const enum adxl367_fifo_format adxl367_fifo_formats[] = { 239 ADXL367_FIFO_FORMAT_X, 240 ADXL367_FIFO_FORMAT_Y, 241 ADXL367_FIFO_FORMAT_Z, 242 ADXL367_FIFO_FORMAT_XT, 243 ADXL367_FIFO_FORMAT_YT, 244 ADXL367_FIFO_FORMAT_ZT, 245 ADXL367_FIFO_FORMAT_XA, 246 ADXL367_FIFO_FORMAT_YA, 247 ADXL367_FIFO_FORMAT_ZA, 248 ADXL367_FIFO_FORMAT_XYZ, 249 ADXL367_FIFO_FORMAT_XYZT, 250 ADXL367_FIFO_FORMAT_XYZA, 251 }; 252 253 static const unsigned long adxl367_channel_masks[] = { 254 ADXL367_X_CHANNEL_MASK, 255 ADXL367_Y_CHANNEL_MASK, 256 ADXL367_Z_CHANNEL_MASK, 257 ADXL367_X_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK, 258 ADXL367_Y_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK, 259 ADXL367_Z_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK, 260 ADXL367_X_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK, 261 ADXL367_Y_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK, 262 ADXL367_Z_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK, 263 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK, 264 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK | 265 ADXL367_TEMP_CHANNEL_MASK, 266 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK | 267 ADXL367_EX_ADC_CHANNEL_MASK, 268 0, 269 }; 270 271 static int adxl367_set_measure_en(struct adxl367_state *st, bool en) 272 { 273 enum adxl367_op_mode op_mode = en ? ADXL367_OP_MEASURE 274 : ADXL367_OP_STANDBY; 275 int ret; 276 277 ret = regmap_update_bits(st->regmap, ADXL367_REG_POWER_CTL, 278 ADXL367_POWER_CTL_MODE_MASK, 279 FIELD_PREP(ADXL367_POWER_CTL_MODE_MASK, 280 op_mode)); 281 if (ret) 282 return ret; 283 284 /* 285 * Wait for acceleration output to settle after entering 286 * measure mode. 287 */ 288 if (en) 289 msleep(100); 290 291 return 0; 292 } 293 294 static void adxl367_scale_act_thresholds(struct adxl367_state *st, 295 enum adxl367_range old_range, 296 enum adxl367_range new_range) 297 { 298 st->act_threshold = st->act_threshold 299 * adxl367_range_scale_factor_tbl[old_range] 300 / adxl367_range_scale_factor_tbl[new_range]; 301 st->inact_threshold = st->inact_threshold 302 * adxl367_range_scale_factor_tbl[old_range] 303 / adxl367_range_scale_factor_tbl[new_range]; 304 } 305 306 static int _adxl367_set_act_threshold(struct adxl367_state *st, 307 enum adxl367_activity_type act, 308 unsigned int threshold) 309 { 310 u8 reg = adxl367_threshold_h_reg_tbl[act]; 311 int ret; 312 313 if (threshold > ADXL367_THRESH_MAX) 314 return -EINVAL; 315 316 st->act_threshold_buf[0] = FIELD_PREP(ADXL367_THRESH_H_MASK, 317 FIELD_GET(ADXL367_THRESH_VAL_H_MASK, 318 threshold)); 319 st->act_threshold_buf[1] = FIELD_PREP(ADXL367_THRESH_L_MASK, 320 FIELD_GET(ADXL367_THRESH_VAL_L_MASK, 321 threshold)); 322 323 ret = regmap_bulk_write(st->regmap, reg, st->act_threshold_buf, 324 sizeof(st->act_threshold_buf)); 325 if (ret) 326 return ret; 327 328 if (act == ADXL367_ACTIVITY) 329 st->act_threshold = threshold; 330 else 331 st->inact_threshold = threshold; 332 333 return 0; 334 } 335 336 static int adxl367_set_act_threshold(struct adxl367_state *st, 337 enum adxl367_activity_type act, 338 unsigned int threshold) 339 { 340 int ret; 341 342 mutex_lock(&st->lock); 343 344 ret = adxl367_set_measure_en(st, false); 345 if (ret) 346 goto out; 347 348 ret = _adxl367_set_act_threshold(st, act, threshold); 349 if (ret) 350 goto out; 351 352 ret = adxl367_set_measure_en(st, true); 353 354 out: 355 mutex_unlock(&st->lock); 356 357 return ret; 358 } 359 360 static int adxl367_set_act_proc_mode(struct adxl367_state *st, 361 enum adxl367_act_proc_mode mode) 362 { 363 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL, 364 ADXL367_ACT_LINKLOOP_MASK, 365 FIELD_PREP(ADXL367_ACT_LINKLOOP_MASK, 366 mode)); 367 } 368 369 static int adxl367_set_act_interrupt_en(struct adxl367_state *st, 370 enum adxl367_activity_type act, 371 bool en) 372 { 373 unsigned int mask = adxl367_act_int_mask_tbl[act]; 374 375 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP, 376 mask, en ? mask : 0); 377 } 378 379 static int adxl367_get_act_interrupt_en(struct adxl367_state *st, 380 enum adxl367_activity_type act, 381 bool *en) 382 { 383 unsigned int mask = adxl367_act_int_mask_tbl[act]; 384 unsigned int val; 385 int ret; 386 387 ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val); 388 if (ret) 389 return ret; 390 391 *en = !!(val & mask); 392 393 return 0; 394 } 395 396 static int adxl367_set_act_en(struct adxl367_state *st, 397 enum adxl367_activity_type act, 398 enum adxl367_act_en_mode en) 399 { 400 unsigned int ctl_shift = adxl367_act_en_shift_tbl[act]; 401 402 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL, 403 ADXL367_ACT_EN_MASK << ctl_shift, 404 en << ctl_shift); 405 } 406 407 static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st, 408 bool en) 409 { 410 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP, 411 ADXL367_INT_FIFO_WATERMARK_MASK, 412 en ? ADXL367_INT_FIFO_WATERMARK_MASK : 0); 413 } 414 415 static int adxl367_get_fifo_mode(struct adxl367_state *st, 416 enum adxl367_fifo_mode *fifo_mode) 417 { 418 unsigned int val; 419 int ret; 420 421 ret = regmap_read(st->regmap, ADXL367_REG_FIFO_CTL, &val); 422 if (ret) 423 return ret; 424 425 *fifo_mode = FIELD_GET(ADXL367_FIFO_CTL_MODE_MASK, val); 426 427 return 0; 428 } 429 430 static int adxl367_set_fifo_mode(struct adxl367_state *st, 431 enum adxl367_fifo_mode fifo_mode) 432 { 433 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL, 434 ADXL367_FIFO_CTL_MODE_MASK, 435 FIELD_PREP(ADXL367_FIFO_CTL_MODE_MASK, 436 fifo_mode)); 437 } 438 439 static int adxl367_set_fifo_format(struct adxl367_state *st, 440 enum adxl367_fifo_format fifo_format) 441 { 442 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL, 443 ADXL367_FIFO_CTL_FORMAT_MASK, 444 FIELD_PREP(ADXL367_FIFO_CTL_FORMAT_MASK, 445 fifo_format)); 446 } 447 448 static int adxl367_set_fifo_watermark(struct adxl367_state *st, 449 unsigned int fifo_watermark) 450 { 451 unsigned int fifo_samples = fifo_watermark * st->fifo_set_size; 452 unsigned int fifo_samples_h, fifo_samples_l; 453 int ret; 454 455 if (fifo_samples > ADXL367_FIFO_MAX_WATERMARK) 456 fifo_samples = ADXL367_FIFO_MAX_WATERMARK; 457 458 fifo_samples /= st->fifo_set_size; 459 460 fifo_samples_h = FIELD_PREP(ADXL367_SAMPLES_H_MASK, 461 FIELD_GET(ADXL367_SAMPLES_VAL_H_MASK, 462 fifo_samples)); 463 fifo_samples_l = FIELD_PREP(ADXL367_SAMPLES_L_MASK, 464 FIELD_GET(ADXL367_SAMPLES_VAL_L_MASK, 465 fifo_samples)); 466 467 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL, 468 ADXL367_SAMPLES_H_MASK, fifo_samples_h); 469 if (ret) 470 return ret; 471 472 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_SAMPLES, 473 ADXL367_SAMPLES_L_MASK, fifo_samples_l); 474 if (ret) 475 return ret; 476 477 st->fifo_watermark = fifo_watermark; 478 479 return 0; 480 } 481 482 static int adxl367_set_range(struct iio_dev *indio_dev, 483 enum adxl367_range range) 484 { 485 struct adxl367_state *st = iio_priv(indio_dev); 486 int ret; 487 488 ret = iio_device_claim_direct_mode(indio_dev); 489 if (ret) 490 return ret; 491 492 mutex_lock(&st->lock); 493 494 ret = adxl367_set_measure_en(st, false); 495 if (ret) 496 goto out; 497 498 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL, 499 ADXL367_FILTER_CTL_RANGE_MASK, 500 FIELD_PREP(ADXL367_FILTER_CTL_RANGE_MASK, 501 range)); 502 if (ret) 503 goto out; 504 505 adxl367_scale_act_thresholds(st, st->range, range); 506 507 /* Activity thresholds depend on range */ 508 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY, 509 st->act_threshold); 510 if (ret) 511 goto out; 512 513 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY, 514 st->inact_threshold); 515 if (ret) 516 goto out; 517 518 ret = adxl367_set_measure_en(st, true); 519 if (ret) 520 goto out; 521 522 st->range = range; 523 524 out: 525 mutex_unlock(&st->lock); 526 527 iio_device_release_direct_mode(indio_dev); 528 529 return ret; 530 } 531 532 static int adxl367_time_ms_to_samples(struct adxl367_state *st, unsigned int ms) 533 { 534 int freq_hz = adxl367_samp_freq_tbl[st->odr][0]; 535 int freq_microhz = adxl367_samp_freq_tbl[st->odr][1]; 536 /* Scale to decihertz to prevent precision loss in 12.5Hz case. */ 537 int freq_dhz = freq_hz * 10 + freq_microhz / 100000; 538 539 return DIV_ROUND_CLOSEST(ms * freq_dhz, 10000); 540 } 541 542 static int _adxl367_set_act_time_ms(struct adxl367_state *st, unsigned int ms) 543 { 544 unsigned int val = adxl367_time_ms_to_samples(st, ms); 545 int ret; 546 547 if (val > ADXL367_TIME_ACT_MAX) 548 val = ADXL367_TIME_ACT_MAX; 549 550 ret = regmap_write(st->regmap, ADXL367_REG_TIME_ACT, val); 551 if (ret) 552 return ret; 553 554 st->act_time_ms = ms; 555 556 return 0; 557 } 558 559 static int _adxl367_set_inact_time_ms(struct adxl367_state *st, unsigned int ms) 560 { 561 unsigned int val = adxl367_time_ms_to_samples(st, ms); 562 int ret; 563 564 if (val > ADXL367_TIME_INACT_MAX) 565 val = ADXL367_TIME_INACT_MAX; 566 567 st->inact_time_buf[0] = FIELD_PREP(ADXL367_TIME_INACT_H_MASK, 568 FIELD_GET(ADXL367_TIME_INACT_VAL_H_MASK, 569 val)); 570 st->inact_time_buf[1] = FIELD_PREP(ADXL367_TIME_INACT_L_MASK, 571 FIELD_GET(ADXL367_TIME_INACT_VAL_L_MASK, 572 val)); 573 574 ret = regmap_bulk_write(st->regmap, ADXL367_REG_TIME_INACT_H, 575 st->inact_time_buf, sizeof(st->inact_time_buf)); 576 if (ret) 577 return ret; 578 579 st->inact_time_ms = ms; 580 581 return 0; 582 } 583 584 static int adxl367_set_act_time_ms(struct adxl367_state *st, 585 enum adxl367_activity_type act, 586 unsigned int ms) 587 { 588 int ret; 589 590 mutex_lock(&st->lock); 591 592 ret = adxl367_set_measure_en(st, false); 593 if (ret) 594 goto out; 595 596 if (act == ADXL367_ACTIVITY) 597 ret = _adxl367_set_act_time_ms(st, ms); 598 else 599 ret = _adxl367_set_inact_time_ms(st, ms); 600 601 if (ret) 602 goto out; 603 604 ret = adxl367_set_measure_en(st, true); 605 606 out: 607 mutex_unlock(&st->lock); 608 609 return ret; 610 } 611 612 static int _adxl367_set_odr(struct adxl367_state *st, enum adxl367_odr odr) 613 { 614 int ret; 615 616 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL, 617 ADXL367_FILTER_CTL_ODR_MASK, 618 FIELD_PREP(ADXL367_FILTER_CTL_ODR_MASK, 619 odr)); 620 if (ret) 621 return ret; 622 623 /* Activity timers depend on ODR */ 624 ret = _adxl367_set_act_time_ms(st, st->act_time_ms); 625 if (ret) 626 return ret; 627 628 ret = _adxl367_set_inact_time_ms(st, st->inact_time_ms); 629 if (ret) 630 return ret; 631 632 st->odr = odr; 633 634 return 0; 635 } 636 637 static int adxl367_set_odr(struct iio_dev *indio_dev, enum adxl367_odr odr) 638 { 639 struct adxl367_state *st = iio_priv(indio_dev); 640 int ret; 641 642 ret = iio_device_claim_direct_mode(indio_dev); 643 if (ret) 644 return ret; 645 646 mutex_lock(&st->lock); 647 648 ret = adxl367_set_measure_en(st, false); 649 if (ret) 650 goto out; 651 652 ret = _adxl367_set_odr(st, odr); 653 if (ret) 654 goto out; 655 656 ret = adxl367_set_measure_en(st, true); 657 658 out: 659 mutex_unlock(&st->lock); 660 661 iio_device_release_direct_mode(indio_dev); 662 663 return ret; 664 } 665 666 static int adxl367_set_temp_adc_en(struct adxl367_state *st, unsigned int reg, 667 bool en) 668 { 669 return regmap_update_bits(st->regmap, reg, ADXL367_ADC_EN_MASK, 670 en ? ADXL367_ADC_EN_MASK : 0); 671 } 672 673 static int adxl367_set_temp_adc_reg_en(struct adxl367_state *st, 674 unsigned int reg, bool en) 675 { 676 int ret; 677 678 switch (reg) { 679 case ADXL367_REG_TEMP_DATA_H: 680 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en); 681 break; 682 case ADXL367_REG_EX_ADC_DATA_H: 683 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en); 684 break; 685 default: 686 return 0; 687 } 688 689 if (ret) 690 return ret; 691 692 if (en) 693 msleep(100); 694 695 return 0; 696 } 697 698 static int adxl367_set_temp_adc_mask_en(struct adxl367_state *st, 699 const unsigned long *active_scan_mask, 700 bool en) 701 { 702 if (*active_scan_mask & ADXL367_TEMP_CHANNEL_MASK) 703 return adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en); 704 else if (*active_scan_mask & ADXL367_EX_ADC_CHANNEL_MASK) 705 return adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en); 706 707 return 0; 708 } 709 710 static int adxl367_find_odr(struct adxl367_state *st, int val, int val2, 711 enum adxl367_odr *odr) 712 { 713 size_t size = ARRAY_SIZE(adxl367_samp_freq_tbl); 714 int i; 715 716 for (i = 0; i < size; i++) 717 if (val == adxl367_samp_freq_tbl[i][0] && 718 val2 == adxl367_samp_freq_tbl[i][1]) 719 break; 720 721 if (i == size) 722 return -EINVAL; 723 724 *odr = i; 725 726 return 0; 727 } 728 729 static int adxl367_find_range(struct adxl367_state *st, int val, int val2, 730 enum adxl367_range *range) 731 { 732 size_t size = ARRAY_SIZE(adxl367_range_scale_tbl); 733 int i; 734 735 for (i = 0; i < size; i++) 736 if (val == adxl367_range_scale_tbl[i][0] && 737 val2 == adxl367_range_scale_tbl[i][1]) 738 break; 739 740 if (i == size) 741 return -EINVAL; 742 743 *range = i; 744 745 return 0; 746 } 747 748 static int adxl367_read_sample(struct iio_dev *indio_dev, 749 struct iio_chan_spec const *chan, 750 int *val) 751 { 752 struct adxl367_state *st = iio_priv(indio_dev); 753 u16 sample; 754 int ret; 755 756 ret = iio_device_claim_direct_mode(indio_dev); 757 if (ret) 758 return ret; 759 760 mutex_lock(&st->lock); 761 762 ret = adxl367_set_temp_adc_reg_en(st, chan->address, true); 763 if (ret) 764 goto out; 765 766 ret = regmap_bulk_read(st->regmap, chan->address, &st->sample_buf, 767 sizeof(st->sample_buf)); 768 if (ret) 769 goto out; 770 771 sample = FIELD_GET(ADXL367_DATA_MASK, be16_to_cpu(st->sample_buf)); 772 *val = sign_extend32(sample, chan->scan_type.realbits - 1); 773 774 ret = adxl367_set_temp_adc_reg_en(st, chan->address, false); 775 776 out: 777 mutex_unlock(&st->lock); 778 779 iio_device_release_direct_mode(indio_dev); 780 781 return ret ?: IIO_VAL_INT; 782 } 783 784 static int adxl367_get_status(struct adxl367_state *st, u8 *status, 785 u16 *fifo_entries) 786 { 787 int ret; 788 789 /* Read STATUS, FIFO_ENT_L and FIFO_ENT_H */ 790 ret = regmap_bulk_read(st->regmap, ADXL367_REG_STATUS, 791 st->status_buf, sizeof(st->status_buf)); 792 if (ret) 793 return ret; 794 795 st->status_buf[2] &= ADXL367_FIFO_ENT_H_MASK; 796 797 *status = st->status_buf[0]; 798 *fifo_entries = get_unaligned_le16(&st->status_buf[1]); 799 800 return 0; 801 } 802 803 static bool adxl367_push_event(struct iio_dev *indio_dev, u8 status) 804 { 805 unsigned int ev_dir; 806 807 if (FIELD_GET(ADXL367_STATUS_ACT_MASK, status)) 808 ev_dir = IIO_EV_DIR_RISING; 809 else if (FIELD_GET(ADXL367_STATUS_INACT_MASK, status)) 810 ev_dir = IIO_EV_DIR_FALLING; 811 else 812 return false; 813 814 iio_push_event(indio_dev, 815 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z, 816 IIO_EV_TYPE_THRESH, ev_dir), 817 iio_get_time_ns(indio_dev)); 818 819 return true; 820 } 821 822 static bool adxl367_push_fifo_data(struct iio_dev *indio_dev, u8 status, 823 u16 fifo_entries) 824 { 825 struct adxl367_state *st = iio_priv(indio_dev); 826 int ret; 827 int i; 828 829 if (!FIELD_GET(ADXL367_STATUS_FIFO_FULL_MASK, status)) 830 return false; 831 832 fifo_entries -= fifo_entries % st->fifo_set_size; 833 834 ret = st->ops->read_fifo(st->context, st->fifo_buf, fifo_entries); 835 if (ret) { 836 dev_err(st->dev, "Failed to read FIFO: %d\n", ret); 837 return true; 838 } 839 840 for (i = 0; i < fifo_entries; i += st->fifo_set_size) 841 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]); 842 843 return true; 844 } 845 846 static irqreturn_t adxl367_irq_handler(int irq, void *private) 847 { 848 struct iio_dev *indio_dev = private; 849 struct adxl367_state *st = iio_priv(indio_dev); 850 u16 fifo_entries; 851 bool handled; 852 u8 status; 853 int ret; 854 855 ret = adxl367_get_status(st, &status, &fifo_entries); 856 if (ret) 857 return IRQ_NONE; 858 859 handled = adxl367_push_event(indio_dev, status); 860 handled |= adxl367_push_fifo_data(indio_dev, status, fifo_entries); 861 862 return handled ? IRQ_HANDLED : IRQ_NONE; 863 } 864 865 static int adxl367_reg_access(struct iio_dev *indio_dev, 866 unsigned int reg, 867 unsigned int writeval, 868 unsigned int *readval) 869 { 870 struct adxl367_state *st = iio_priv(indio_dev); 871 872 if (readval) 873 return regmap_read(st->regmap, reg, readval); 874 else 875 return regmap_write(st->regmap, reg, writeval); 876 } 877 878 static int adxl367_read_raw(struct iio_dev *indio_dev, 879 struct iio_chan_spec const *chan, 880 int *val, int *val2, long info) 881 { 882 struct adxl367_state *st = iio_priv(indio_dev); 883 884 switch (info) { 885 case IIO_CHAN_INFO_RAW: 886 return adxl367_read_sample(indio_dev, chan, val); 887 case IIO_CHAN_INFO_SCALE: 888 switch (chan->type) { 889 case IIO_ACCEL: 890 mutex_lock(&st->lock); 891 *val = adxl367_range_scale_tbl[st->range][0]; 892 *val2 = adxl367_range_scale_tbl[st->range][1]; 893 mutex_unlock(&st->lock); 894 return IIO_VAL_INT_PLUS_NANO; 895 case IIO_TEMP: 896 *val = 1000; 897 *val2 = ADXL367_TEMP_PER_C; 898 return IIO_VAL_FRACTIONAL; 899 case IIO_VOLTAGE: 900 *val = ADXL367_VOLTAGE_MAX_MV; 901 *val2 = ADXL367_VOLTAGE_MAX_RAW; 902 return IIO_VAL_FRACTIONAL; 903 default: 904 return -EINVAL; 905 } 906 case IIO_CHAN_INFO_OFFSET: 907 switch (chan->type) { 908 case IIO_TEMP: 909 *val = 25 * ADXL367_TEMP_PER_C - ADXL367_TEMP_25C; 910 return IIO_VAL_INT; 911 case IIO_VOLTAGE: 912 *val = ADXL367_VOLTAGE_OFFSET; 913 return IIO_VAL_INT; 914 default: 915 return -EINVAL; 916 } 917 case IIO_CHAN_INFO_SAMP_FREQ: 918 mutex_lock(&st->lock); 919 *val = adxl367_samp_freq_tbl[st->odr][0]; 920 *val2 = adxl367_samp_freq_tbl[st->odr][1]; 921 mutex_unlock(&st->lock); 922 return IIO_VAL_INT_PLUS_MICRO; 923 default: 924 return -EINVAL; 925 } 926 } 927 928 static int adxl367_write_raw(struct iio_dev *indio_dev, 929 struct iio_chan_spec const *chan, 930 int val, int val2, long info) 931 { 932 struct adxl367_state *st = iio_priv(indio_dev); 933 int ret; 934 935 switch (info) { 936 case IIO_CHAN_INFO_SAMP_FREQ: { 937 enum adxl367_odr odr; 938 939 ret = adxl367_find_odr(st, val, val2, &odr); 940 if (ret) 941 return ret; 942 943 return adxl367_set_odr(indio_dev, odr); 944 } 945 case IIO_CHAN_INFO_SCALE: { 946 enum adxl367_range range; 947 948 ret = adxl367_find_range(st, val, val2, &range); 949 if (ret) 950 return ret; 951 952 return adxl367_set_range(indio_dev, range); 953 } 954 default: 955 return -EINVAL; 956 } 957 } 958 959 static int adxl367_write_raw_get_fmt(struct iio_dev *indio_dev, 960 struct iio_chan_spec const *chan, 961 long info) 962 { 963 switch (info) { 964 case IIO_CHAN_INFO_SCALE: 965 if (chan->type != IIO_ACCEL) 966 return -EINVAL; 967 968 return IIO_VAL_INT_PLUS_NANO; 969 default: 970 return IIO_VAL_INT_PLUS_MICRO; 971 } 972 } 973 974 static int adxl367_read_avail(struct iio_dev *indio_dev, 975 struct iio_chan_spec const *chan, 976 const int **vals, int *type, int *length, 977 long info) 978 { 979 switch (info) { 980 case IIO_CHAN_INFO_SCALE: 981 if (chan->type != IIO_ACCEL) 982 return -EINVAL; 983 984 *vals = (int *)adxl367_range_scale_tbl; 985 *type = IIO_VAL_INT_PLUS_NANO; 986 *length = ARRAY_SIZE(adxl367_range_scale_tbl) * 2; 987 return IIO_AVAIL_LIST; 988 case IIO_CHAN_INFO_SAMP_FREQ: 989 *vals = (int *)adxl367_samp_freq_tbl; 990 *type = IIO_VAL_INT_PLUS_MICRO; 991 *length = ARRAY_SIZE(adxl367_samp_freq_tbl) * 2; 992 return IIO_AVAIL_LIST; 993 default: 994 return -EINVAL; 995 } 996 } 997 998 static int adxl367_read_event_value(struct iio_dev *indio_dev, 999 const struct iio_chan_spec *chan, 1000 enum iio_event_type type, 1001 enum iio_event_direction dir, 1002 enum iio_event_info info, 1003 int *val, int *val2) 1004 { 1005 struct adxl367_state *st = iio_priv(indio_dev); 1006 1007 switch (info) { 1008 case IIO_EV_INFO_VALUE: { 1009 switch (dir) { 1010 case IIO_EV_DIR_RISING: 1011 mutex_lock(&st->lock); 1012 *val = st->act_threshold; 1013 mutex_unlock(&st->lock); 1014 return IIO_VAL_INT; 1015 case IIO_EV_DIR_FALLING: 1016 mutex_lock(&st->lock); 1017 *val = st->inact_threshold; 1018 mutex_unlock(&st->lock); 1019 return IIO_VAL_INT; 1020 default: 1021 return -EINVAL; 1022 } 1023 } 1024 case IIO_EV_INFO_PERIOD: 1025 switch (dir) { 1026 case IIO_EV_DIR_RISING: 1027 mutex_lock(&st->lock); 1028 *val = st->act_time_ms; 1029 mutex_unlock(&st->lock); 1030 *val2 = 1000; 1031 return IIO_VAL_FRACTIONAL; 1032 case IIO_EV_DIR_FALLING: 1033 mutex_lock(&st->lock); 1034 *val = st->inact_time_ms; 1035 mutex_unlock(&st->lock); 1036 *val2 = 1000; 1037 return IIO_VAL_FRACTIONAL; 1038 default: 1039 return -EINVAL; 1040 } 1041 default: 1042 return -EINVAL; 1043 } 1044 } 1045 1046 static int adxl367_write_event_value(struct iio_dev *indio_dev, 1047 const struct iio_chan_spec *chan, 1048 enum iio_event_type type, 1049 enum iio_event_direction dir, 1050 enum iio_event_info info, 1051 int val, int val2) 1052 { 1053 struct adxl367_state *st = iio_priv(indio_dev); 1054 1055 switch (info) { 1056 case IIO_EV_INFO_VALUE: 1057 if (val < 0) 1058 return -EINVAL; 1059 1060 switch (dir) { 1061 case IIO_EV_DIR_RISING: 1062 return adxl367_set_act_threshold(st, ADXL367_ACTIVITY, val); 1063 case IIO_EV_DIR_FALLING: 1064 return adxl367_set_act_threshold(st, ADXL367_INACTIVITY, val); 1065 default: 1066 return -EINVAL; 1067 } 1068 case IIO_EV_INFO_PERIOD: 1069 if (val < 0) 1070 return -EINVAL; 1071 1072 val = val * 1000 + DIV_ROUND_UP(val2, 1000); 1073 switch (dir) { 1074 case IIO_EV_DIR_RISING: 1075 return adxl367_set_act_time_ms(st, ADXL367_ACTIVITY, val); 1076 case IIO_EV_DIR_FALLING: 1077 return adxl367_set_act_time_ms(st, ADXL367_INACTIVITY, val); 1078 default: 1079 return -EINVAL; 1080 } 1081 default: 1082 return -EINVAL; 1083 } 1084 } 1085 1086 static int adxl367_read_event_config(struct iio_dev *indio_dev, 1087 const struct iio_chan_spec *chan, 1088 enum iio_event_type type, 1089 enum iio_event_direction dir) 1090 { 1091 struct adxl367_state *st = iio_priv(indio_dev); 1092 bool en; 1093 int ret; 1094 1095 switch (dir) { 1096 case IIO_EV_DIR_RISING: 1097 ret = adxl367_get_act_interrupt_en(st, ADXL367_ACTIVITY, &en); 1098 return ret ?: en; 1099 case IIO_EV_DIR_FALLING: 1100 ret = adxl367_get_act_interrupt_en(st, ADXL367_INACTIVITY, &en); 1101 return ret ?: en; 1102 default: 1103 return -EINVAL; 1104 } 1105 } 1106 1107 static int adxl367_write_event_config(struct iio_dev *indio_dev, 1108 const struct iio_chan_spec *chan, 1109 enum iio_event_type type, 1110 enum iio_event_direction dir, 1111 int state) 1112 { 1113 struct adxl367_state *st = iio_priv(indio_dev); 1114 enum adxl367_activity_type act; 1115 int ret; 1116 1117 switch (dir) { 1118 case IIO_EV_DIR_RISING: 1119 act = ADXL367_ACTIVITY; 1120 break; 1121 case IIO_EV_DIR_FALLING: 1122 act = ADXL367_INACTIVITY; 1123 break; 1124 default: 1125 return -EINVAL; 1126 } 1127 1128 ret = iio_device_claim_direct_mode(indio_dev); 1129 if (ret) 1130 return ret; 1131 1132 mutex_lock(&st->lock); 1133 1134 ret = adxl367_set_measure_en(st, false); 1135 if (ret) 1136 goto out; 1137 1138 ret = adxl367_set_act_interrupt_en(st, act, state); 1139 if (ret) 1140 goto out; 1141 1142 ret = adxl367_set_act_en(st, act, state ? ADCL367_ACT_REF_ENABLED 1143 : ADXL367_ACT_DISABLED); 1144 if (ret) 1145 goto out; 1146 1147 ret = adxl367_set_measure_en(st, true); 1148 1149 out: 1150 mutex_unlock(&st->lock); 1151 1152 iio_device_release_direct_mode(indio_dev); 1153 1154 return ret; 1155 } 1156 1157 static ssize_t adxl367_get_fifo_enabled(struct device *dev, 1158 struct device_attribute *attr, 1159 char *buf) 1160 { 1161 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev)); 1162 enum adxl367_fifo_mode fifo_mode; 1163 int ret; 1164 1165 ret = adxl367_get_fifo_mode(st, &fifo_mode); 1166 if (ret) 1167 return ret; 1168 1169 return sysfs_emit(buf, "%d\n", fifo_mode != ADXL367_FIFO_MODE_DISABLED); 1170 } 1171 1172 static ssize_t adxl367_get_fifo_watermark(struct device *dev, 1173 struct device_attribute *attr, 1174 char *buf) 1175 { 1176 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev)); 1177 unsigned int fifo_watermark; 1178 1179 mutex_lock(&st->lock); 1180 fifo_watermark = st->fifo_watermark; 1181 mutex_unlock(&st->lock); 1182 1183 return sysfs_emit(buf, "%d\n", fifo_watermark); 1184 } 1185 1186 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "1"); 1187 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max, 1188 __stringify(ADXL367_FIFO_MAX_WATERMARK)); 1189 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 1190 adxl367_get_fifo_watermark, NULL, 0); 1191 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 1192 adxl367_get_fifo_enabled, NULL, 0); 1193 1194 static const struct iio_dev_attr *adxl367_fifo_attributes[] = { 1195 &iio_dev_attr_hwfifo_watermark_min, 1196 &iio_dev_attr_hwfifo_watermark_max, 1197 &iio_dev_attr_hwfifo_watermark, 1198 &iio_dev_attr_hwfifo_enabled, 1199 NULL, 1200 }; 1201 1202 static int adxl367_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1203 { 1204 struct adxl367_state *st = iio_priv(indio_dev); 1205 int ret; 1206 1207 if (val > ADXL367_FIFO_MAX_WATERMARK) 1208 return -EINVAL; 1209 1210 mutex_lock(&st->lock); 1211 1212 ret = adxl367_set_measure_en(st, false); 1213 if (ret) 1214 goto out; 1215 1216 ret = adxl367_set_fifo_watermark(st, val); 1217 if (ret) 1218 goto out; 1219 1220 ret = adxl367_set_measure_en(st, true); 1221 1222 out: 1223 mutex_unlock(&st->lock); 1224 1225 return ret; 1226 } 1227 1228 static bool adxl367_find_mask_fifo_format(const unsigned long *scan_mask, 1229 enum adxl367_fifo_format *fifo_format) 1230 { 1231 size_t size = ARRAY_SIZE(adxl367_fifo_formats); 1232 int i; 1233 1234 for (i = 0; i < size; i++) 1235 if (*scan_mask == adxl367_channel_masks[i]) 1236 break; 1237 1238 if (i == size) 1239 return false; 1240 1241 *fifo_format = adxl367_fifo_formats[i]; 1242 1243 return true; 1244 } 1245 1246 static int adxl367_update_scan_mode(struct iio_dev *indio_dev, 1247 const unsigned long *active_scan_mask) 1248 { 1249 struct adxl367_state *st = iio_priv(indio_dev); 1250 enum adxl367_fifo_format fifo_format; 1251 int ret; 1252 1253 if (!adxl367_find_mask_fifo_format(active_scan_mask, &fifo_format)) 1254 return -EINVAL; 1255 1256 mutex_lock(&st->lock); 1257 1258 ret = adxl367_set_measure_en(st, false); 1259 if (ret) 1260 goto out; 1261 1262 ret = adxl367_set_fifo_format(st, fifo_format); 1263 if (ret) 1264 goto out; 1265 1266 ret = adxl367_set_measure_en(st, true); 1267 if (ret) 1268 goto out; 1269 1270 st->fifo_set_size = bitmap_weight(active_scan_mask, 1271 indio_dev->masklength); 1272 1273 out: 1274 mutex_unlock(&st->lock); 1275 1276 return ret; 1277 } 1278 1279 static int adxl367_buffer_postenable(struct iio_dev *indio_dev) 1280 { 1281 struct adxl367_state *st = iio_priv(indio_dev); 1282 int ret; 1283 1284 mutex_lock(&st->lock); 1285 1286 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask, 1287 true); 1288 if (ret) 1289 goto out; 1290 1291 ret = adxl367_set_measure_en(st, false); 1292 if (ret) 1293 goto out; 1294 1295 ret = adxl367_set_fifo_watermark_interrupt_en(st, true); 1296 if (ret) 1297 goto out; 1298 1299 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_STREAM); 1300 if (ret) 1301 goto out; 1302 1303 ret = adxl367_set_measure_en(st, true); 1304 1305 out: 1306 mutex_unlock(&st->lock); 1307 1308 return ret; 1309 } 1310 1311 static int adxl367_buffer_predisable(struct iio_dev *indio_dev) 1312 { 1313 struct adxl367_state *st = iio_priv(indio_dev); 1314 int ret; 1315 1316 mutex_lock(&st->lock); 1317 1318 ret = adxl367_set_measure_en(st, false); 1319 if (ret) 1320 goto out; 1321 1322 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_DISABLED); 1323 if (ret) 1324 goto out; 1325 1326 ret = adxl367_set_fifo_watermark_interrupt_en(st, false); 1327 if (ret) 1328 goto out; 1329 1330 ret = adxl367_set_measure_en(st, true); 1331 if (ret) 1332 goto out; 1333 1334 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask, 1335 false); 1336 1337 out: 1338 mutex_unlock(&st->lock); 1339 1340 return ret; 1341 } 1342 1343 static const struct iio_buffer_setup_ops adxl367_buffer_ops = { 1344 .postenable = adxl367_buffer_postenable, 1345 .predisable = adxl367_buffer_predisable, 1346 }; 1347 1348 static const struct iio_info adxl367_info = { 1349 .read_raw = adxl367_read_raw, 1350 .write_raw = adxl367_write_raw, 1351 .write_raw_get_fmt = adxl367_write_raw_get_fmt, 1352 .read_avail = adxl367_read_avail, 1353 .read_event_config = adxl367_read_event_config, 1354 .write_event_config = adxl367_write_event_config, 1355 .read_event_value = adxl367_read_event_value, 1356 .write_event_value = adxl367_write_event_value, 1357 .debugfs_reg_access = adxl367_reg_access, 1358 .hwfifo_set_watermark = adxl367_set_watermark, 1359 .update_scan_mode = adxl367_update_scan_mode, 1360 }; 1361 1362 static const struct iio_event_spec adxl367_events[] = { 1363 { 1364 .type = IIO_EV_TYPE_MAG_REFERENCED, 1365 .dir = IIO_EV_DIR_RISING, 1366 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) | 1367 BIT(IIO_EV_INFO_PERIOD) | 1368 BIT(IIO_EV_INFO_VALUE), 1369 }, 1370 { 1371 .type = IIO_EV_TYPE_MAG_REFERENCED, 1372 .dir = IIO_EV_DIR_FALLING, 1373 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) | 1374 BIT(IIO_EV_INFO_PERIOD) | 1375 BIT(IIO_EV_INFO_VALUE), 1376 }, 1377 }; 1378 1379 #define ADXL367_ACCEL_CHANNEL(index, reg, axis) { \ 1380 .type = IIO_ACCEL, \ 1381 .address = (reg), \ 1382 .modified = 1, \ 1383 .channel2 = IIO_MOD_##axis, \ 1384 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 1385 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 1386 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ 1387 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1388 .info_mask_shared_by_all_available = \ 1389 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1390 .event_spec = adxl367_events, \ 1391 .num_event_specs = ARRAY_SIZE(adxl367_events), \ 1392 .scan_index = (index), \ 1393 .scan_type = { \ 1394 .sign = 's', \ 1395 .realbits = 14, \ 1396 .storagebits = 16, \ 1397 .endianness = IIO_BE, \ 1398 }, \ 1399 } 1400 1401 #define ADXL367_CHANNEL(index, reg, _type) { \ 1402 .type = (_type), \ 1403 .address = (reg), \ 1404 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1405 BIT(IIO_CHAN_INFO_OFFSET) | \ 1406 BIT(IIO_CHAN_INFO_SCALE), \ 1407 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1408 .scan_index = (index), \ 1409 .scan_type = { \ 1410 .sign = 's', \ 1411 .realbits = 14, \ 1412 .storagebits = 16, \ 1413 .endianness = IIO_BE, \ 1414 }, \ 1415 } 1416 1417 static const struct iio_chan_spec adxl367_channels[] = { 1418 ADXL367_ACCEL_CHANNEL(ADXL367_X_CHANNEL_INDEX, ADXL367_REG_X_DATA_H, X), 1419 ADXL367_ACCEL_CHANNEL(ADXL367_Y_CHANNEL_INDEX, ADXL367_REG_Y_DATA_H, Y), 1420 ADXL367_ACCEL_CHANNEL(ADXL367_Z_CHANNEL_INDEX, ADXL367_REG_Z_DATA_H, Z), 1421 ADXL367_CHANNEL(ADXL367_TEMP_CHANNEL_INDEX, ADXL367_REG_TEMP_DATA_H, 1422 IIO_TEMP), 1423 ADXL367_CHANNEL(ADXL367_EX_ADC_CHANNEL_INDEX, ADXL367_REG_EX_ADC_DATA_H, 1424 IIO_VOLTAGE), 1425 }; 1426 1427 static int adxl367_verify_devid(struct adxl367_state *st) 1428 { 1429 unsigned int val; 1430 int ret; 1431 1432 ret = regmap_read_poll_timeout(st->regmap, ADXL367_REG_DEVID, val, 1433 val == ADXL367_DEVID_AD, 1000, 10000); 1434 if (ret) 1435 return dev_err_probe(st->dev, -ENODEV, 1436 "Invalid dev id 0x%02X, expected 0x%02X\n", 1437 val, ADXL367_DEVID_AD); 1438 1439 return 0; 1440 } 1441 1442 static int adxl367_setup(struct adxl367_state *st) 1443 { 1444 int ret; 1445 1446 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY, 1447 ADXL367_2G_RANGE_1G); 1448 if (ret) 1449 return ret; 1450 1451 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY, 1452 ADXL367_2G_RANGE_100MG); 1453 if (ret) 1454 return ret; 1455 1456 ret = adxl367_set_act_proc_mode(st, ADXL367_LOOPED); 1457 if (ret) 1458 return ret; 1459 1460 ret = _adxl367_set_odr(st, ADXL367_ODR_400HZ); 1461 if (ret) 1462 return ret; 1463 1464 ret = _adxl367_set_act_time_ms(st, 10); 1465 if (ret) 1466 return ret; 1467 1468 ret = _adxl367_set_inact_time_ms(st, 10000); 1469 if (ret) 1470 return ret; 1471 1472 return adxl367_set_measure_en(st, true); 1473 } 1474 1475 int adxl367_probe(struct device *dev, const struct adxl367_ops *ops, 1476 void *context, struct regmap *regmap, int irq) 1477 { 1478 static const char * const regulator_names[] = { "vdd", "vddio" }; 1479 struct iio_dev *indio_dev; 1480 struct adxl367_state *st; 1481 int ret; 1482 1483 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1484 if (!indio_dev) 1485 return -ENOMEM; 1486 1487 st = iio_priv(indio_dev); 1488 st->dev = dev; 1489 st->regmap = regmap; 1490 st->context = context; 1491 st->ops = ops; 1492 1493 mutex_init(&st->lock); 1494 1495 indio_dev->channels = adxl367_channels; 1496 indio_dev->num_channels = ARRAY_SIZE(adxl367_channels); 1497 indio_dev->available_scan_masks = adxl367_channel_masks; 1498 indio_dev->name = "adxl367"; 1499 indio_dev->info = &adxl367_info; 1500 indio_dev->modes = INDIO_DIRECT_MODE; 1501 1502 ret = devm_regulator_bulk_get_enable(st->dev, 1503 ARRAY_SIZE(regulator_names), 1504 regulator_names); 1505 if (ret) 1506 return dev_err_probe(st->dev, ret, 1507 "Failed to get regulators\n"); 1508 1509 ret = regmap_write(st->regmap, ADXL367_REG_RESET, ADXL367_RESET_CODE); 1510 if (ret) 1511 return ret; 1512 1513 ret = adxl367_verify_devid(st); 1514 if (ret) 1515 return ret; 1516 1517 ret = adxl367_setup(st); 1518 if (ret) 1519 return ret; 1520 1521 ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev, 1522 &adxl367_buffer_ops, 1523 adxl367_fifo_attributes); 1524 if (ret) 1525 return ret; 1526 1527 ret = devm_request_threaded_irq(st->dev, irq, NULL, 1528 adxl367_irq_handler, IRQF_ONESHOT, 1529 indio_dev->name, indio_dev); 1530 if (ret) 1531 return dev_err_probe(st->dev, ret, "Failed to request irq\n"); 1532 1533 return devm_iio_device_register(dev, indio_dev); 1534 } 1535 EXPORT_SYMBOL_NS_GPL(adxl367_probe, IIO_ADXL367); 1536 1537 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>"); 1538 MODULE_DESCRIPTION("Analog Devices ADXL367 3-axis accelerometer driver"); 1539 MODULE_LICENSE("GPL"); 1540