1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2021 Analog Devices, Inc. 4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/iio/buffer.h> 10 #include <linux/iio/events.h> 11 #include <linux/iio/iio.h> 12 #include <linux/iio/kfifo_buf.h> 13 #include <linux/iio/sysfs.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/unaligned.h> 20 21 #include "adxl367.h" 22 23 #define ADXL367_REG_DEVID 0x00 24 #define ADXL367_DEVID_AD 0xAD 25 26 #define ADXL367_REG_STATUS 0x0B 27 #define ADXL367_STATUS_INACT_MASK BIT(5) 28 #define ADXL367_STATUS_ACT_MASK BIT(4) 29 #define ADXL367_STATUS_FIFO_FULL_MASK BIT(2) 30 31 #define ADXL367_FIFO_ENT_H_MASK GENMASK(1, 0) 32 33 #define ADXL367_REG_X_DATA_H 0x0E 34 #define ADXL367_REG_Y_DATA_H 0x10 35 #define ADXL367_REG_Z_DATA_H 0x12 36 #define ADXL367_REG_TEMP_DATA_H 0x14 37 #define ADXL367_REG_EX_ADC_DATA_H 0x16 38 #define ADXL367_DATA_MASK GENMASK(15, 2) 39 40 #define ADXL367_TEMP_25C 165 41 #define ADXL367_TEMP_PER_C 54 42 43 #define ADXL367_VOLTAGE_OFFSET 8192 44 #define ADXL367_VOLTAGE_MAX_MV 1000 45 #define ADXL367_VOLTAGE_MAX_RAW GENMASK(13, 0) 46 47 #define ADXL367_REG_RESET 0x1F 48 #define ADXL367_RESET_CODE 0x52 49 50 #define ADXL367_REG_THRESH_ACT_H 0x20 51 #define ADXL367_REG_THRESH_INACT_H 0x23 52 #define ADXL367_THRESH_MAX GENMASK(12, 0) 53 #define ADXL367_THRESH_VAL_H_MASK GENMASK(12, 6) 54 #define ADXL367_THRESH_H_MASK GENMASK(6, 0) 55 #define ADXL367_THRESH_VAL_L_MASK GENMASK(5, 0) 56 #define ADXL367_THRESH_L_MASK GENMASK(7, 2) 57 58 #define ADXL367_REG_TIME_ACT 0x22 59 #define ADXL367_REG_TIME_INACT_H 0x25 60 #define ADXL367_TIME_ACT_MAX GENMASK(7, 0) 61 #define ADXL367_TIME_INACT_MAX GENMASK(15, 0) 62 #define ADXL367_TIME_INACT_VAL_H_MASK GENMASK(15, 8) 63 #define ADXL367_TIME_INACT_H_MASK GENMASK(7, 0) 64 #define ADXL367_TIME_INACT_VAL_L_MASK GENMASK(7, 0) 65 #define ADXL367_TIME_INACT_L_MASK GENMASK(7, 0) 66 67 #define ADXL367_REG_ACT_INACT_CTL 0x27 68 #define ADXL367_ACT_EN_MASK GENMASK(1, 0) 69 #define ADXL367_ACT_LINKLOOP_MASK GENMASK(5, 4) 70 71 #define ADXL367_REG_FIFO_CTL 0x28 72 #define ADXL367_FIFO_CTL_FORMAT_MASK GENMASK(6, 3) 73 #define ADXL367_FIFO_CTL_MODE_MASK GENMASK(1, 0) 74 75 #define ADXL367_REG_FIFO_SAMPLES 0x29 76 #define ADXL367_FIFO_SIZE 512 77 #define ADXL367_FIFO_MAX_WATERMARK 511 78 79 #define ADXL367_SAMPLES_VAL_H_MASK BIT(8) 80 #define ADXL367_SAMPLES_H_MASK BIT(2) 81 #define ADXL367_SAMPLES_VAL_L_MASK GENMASK(7, 0) 82 #define ADXL367_SAMPLES_L_MASK GENMASK(7, 0) 83 84 #define ADXL367_REG_INT1_MAP 0x2A 85 #define ADXL367_INT_INACT_MASK BIT(5) 86 #define ADXL367_INT_ACT_MASK BIT(4) 87 #define ADXL367_INT_FIFO_WATERMARK_MASK BIT(2) 88 89 #define ADXL367_REG_FILTER_CTL 0x2C 90 #define ADXL367_FILTER_CTL_RANGE_MASK GENMASK(7, 6) 91 #define ADXL367_2G_RANGE_1G 4095 92 #define ADXL367_2G_RANGE_100MG 409 93 #define ADXL367_FILTER_CTL_ODR_MASK GENMASK(2, 0) 94 95 #define ADXL367_REG_POWER_CTL 0x2D 96 #define ADXL367_POWER_CTL_MODE_MASK GENMASK(1, 0) 97 98 #define ADXL367_REG_ADC_CTL 0x3C 99 #define ADXL367_REG_TEMP_CTL 0x3D 100 #define ADXL367_ADC_EN_MASK BIT(0) 101 102 enum adxl367_range { 103 ADXL367_2G_RANGE, 104 ADXL367_4G_RANGE, 105 ADXL367_8G_RANGE, 106 }; 107 108 enum adxl367_fifo_mode { 109 ADXL367_FIFO_MODE_DISABLED = 0b00, 110 ADXL367_FIFO_MODE_STREAM = 0b10, 111 }; 112 113 enum adxl367_fifo_format { 114 ADXL367_FIFO_FORMAT_XYZ, 115 ADXL367_FIFO_FORMAT_X, 116 ADXL367_FIFO_FORMAT_Y, 117 ADXL367_FIFO_FORMAT_Z, 118 ADXL367_FIFO_FORMAT_XYZT, 119 ADXL367_FIFO_FORMAT_XT, 120 ADXL367_FIFO_FORMAT_YT, 121 ADXL367_FIFO_FORMAT_ZT, 122 ADXL367_FIFO_FORMAT_XYZA, 123 ADXL367_FIFO_FORMAT_XA, 124 ADXL367_FIFO_FORMAT_YA, 125 ADXL367_FIFO_FORMAT_ZA, 126 }; 127 128 enum adxl367_op_mode { 129 ADXL367_OP_STANDBY = 0b00, 130 ADXL367_OP_MEASURE = 0b10, 131 }; 132 133 enum adxl367_act_proc_mode { 134 ADXL367_LOOPED = 0b11, 135 }; 136 137 enum adxl367_act_en_mode { 138 ADXL367_ACT_DISABLED = 0b00, 139 ADCL367_ACT_REF_ENABLED = 0b11, 140 }; 141 142 enum adxl367_activity_type { 143 ADXL367_ACTIVITY, 144 ADXL367_INACTIVITY, 145 }; 146 147 enum adxl367_odr { 148 ADXL367_ODR_12P5HZ, 149 ADXL367_ODR_25HZ, 150 ADXL367_ODR_50HZ, 151 ADXL367_ODR_100HZ, 152 ADXL367_ODR_200HZ, 153 ADXL367_ODR_400HZ, 154 }; 155 156 struct adxl367_state { 157 const struct adxl367_ops *ops; 158 void *context; 159 160 struct device *dev; 161 struct regmap *regmap; 162 163 /* 164 * Synchronize access to members of driver state, and ensure atomicity 165 * of consecutive regmap operations. 166 */ 167 struct mutex lock; 168 169 enum adxl367_odr odr; 170 enum adxl367_range range; 171 172 unsigned int act_threshold; 173 unsigned int act_time_ms; 174 unsigned int inact_threshold; 175 unsigned int inact_time_ms; 176 177 unsigned int fifo_set_size; 178 unsigned int fifo_watermark; 179 180 __be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN); 181 __be16 sample_buf; 182 u8 act_threshold_buf[2]; 183 u8 inact_time_buf[2]; 184 u8 status_buf[3]; 185 }; 186 187 static const unsigned int adxl367_threshold_h_reg_tbl[] = { 188 [ADXL367_ACTIVITY] = ADXL367_REG_THRESH_ACT_H, 189 [ADXL367_INACTIVITY] = ADXL367_REG_THRESH_INACT_H, 190 }; 191 192 static const unsigned int adxl367_act_en_shift_tbl[] = { 193 [ADXL367_ACTIVITY] = 0, 194 [ADXL367_INACTIVITY] = 2, 195 }; 196 197 static const unsigned int adxl367_act_int_mask_tbl[] = { 198 [ADXL367_ACTIVITY] = ADXL367_INT_ACT_MASK, 199 [ADXL367_INACTIVITY] = ADXL367_INT_INACT_MASK, 200 }; 201 202 static const int adxl367_samp_freq_tbl[][2] = { 203 [ADXL367_ODR_12P5HZ] = {12, 500000}, 204 [ADXL367_ODR_25HZ] = {25, 0}, 205 [ADXL367_ODR_50HZ] = {50, 0}, 206 [ADXL367_ODR_100HZ] = {100, 0}, 207 [ADXL367_ODR_200HZ] = {200, 0}, 208 [ADXL367_ODR_400HZ] = {400, 0}, 209 }; 210 211 /* (g * 2) * 9.80665 * 1000000 / (2^14 - 1) */ 212 static const int adxl367_range_scale_tbl[][2] = { 213 [ADXL367_2G_RANGE] = {0, 2394347}, 214 [ADXL367_4G_RANGE] = {0, 4788695}, 215 [ADXL367_8G_RANGE] = {0, 9577391}, 216 }; 217 218 static const int adxl367_range_scale_factor_tbl[] = { 219 [ADXL367_2G_RANGE] = 1, 220 [ADXL367_4G_RANGE] = 2, 221 [ADXL367_8G_RANGE] = 4, 222 }; 223 224 enum { 225 ADXL367_X_CHANNEL_INDEX, 226 ADXL367_Y_CHANNEL_INDEX, 227 ADXL367_Z_CHANNEL_INDEX, 228 ADXL367_TEMP_CHANNEL_INDEX, 229 ADXL367_EX_ADC_CHANNEL_INDEX 230 }; 231 232 #define ADXL367_X_CHANNEL_MASK BIT(ADXL367_X_CHANNEL_INDEX) 233 #define ADXL367_Y_CHANNEL_MASK BIT(ADXL367_Y_CHANNEL_INDEX) 234 #define ADXL367_Z_CHANNEL_MASK BIT(ADXL367_Z_CHANNEL_INDEX) 235 #define ADXL367_TEMP_CHANNEL_MASK BIT(ADXL367_TEMP_CHANNEL_INDEX) 236 #define ADXL367_EX_ADC_CHANNEL_MASK BIT(ADXL367_EX_ADC_CHANNEL_INDEX) 237 238 static const enum adxl367_fifo_format adxl367_fifo_formats[] = { 239 ADXL367_FIFO_FORMAT_X, 240 ADXL367_FIFO_FORMAT_Y, 241 ADXL367_FIFO_FORMAT_Z, 242 ADXL367_FIFO_FORMAT_XT, 243 ADXL367_FIFO_FORMAT_YT, 244 ADXL367_FIFO_FORMAT_ZT, 245 ADXL367_FIFO_FORMAT_XA, 246 ADXL367_FIFO_FORMAT_YA, 247 ADXL367_FIFO_FORMAT_ZA, 248 ADXL367_FIFO_FORMAT_XYZ, 249 ADXL367_FIFO_FORMAT_XYZT, 250 ADXL367_FIFO_FORMAT_XYZA, 251 }; 252 253 static const unsigned long adxl367_channel_masks[] = { 254 ADXL367_X_CHANNEL_MASK, 255 ADXL367_Y_CHANNEL_MASK, 256 ADXL367_Z_CHANNEL_MASK, 257 ADXL367_X_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK, 258 ADXL367_Y_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK, 259 ADXL367_Z_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK, 260 ADXL367_X_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK, 261 ADXL367_Y_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK, 262 ADXL367_Z_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK, 263 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK, 264 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK | 265 ADXL367_TEMP_CHANNEL_MASK, 266 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK | 267 ADXL367_EX_ADC_CHANNEL_MASK, 268 0, 269 }; 270 271 static int adxl367_set_measure_en(struct adxl367_state *st, bool en) 272 { 273 enum adxl367_op_mode op_mode = en ? ADXL367_OP_MEASURE 274 : ADXL367_OP_STANDBY; 275 int ret; 276 277 ret = regmap_update_bits(st->regmap, ADXL367_REG_POWER_CTL, 278 ADXL367_POWER_CTL_MODE_MASK, 279 FIELD_PREP(ADXL367_POWER_CTL_MODE_MASK, 280 op_mode)); 281 if (ret) 282 return ret; 283 284 /* 285 * Wait for acceleration output to settle after entering 286 * measure mode. 287 */ 288 if (en) 289 msleep(100); 290 291 return 0; 292 } 293 294 static void adxl367_scale_act_thresholds(struct adxl367_state *st, 295 enum adxl367_range old_range, 296 enum adxl367_range new_range) 297 { 298 st->act_threshold = st->act_threshold 299 * adxl367_range_scale_factor_tbl[old_range] 300 / adxl367_range_scale_factor_tbl[new_range]; 301 st->inact_threshold = st->inact_threshold 302 * adxl367_range_scale_factor_tbl[old_range] 303 / adxl367_range_scale_factor_tbl[new_range]; 304 } 305 306 static int _adxl367_set_act_threshold(struct adxl367_state *st, 307 enum adxl367_activity_type act, 308 unsigned int threshold) 309 { 310 u8 reg = adxl367_threshold_h_reg_tbl[act]; 311 int ret; 312 313 if (threshold > ADXL367_THRESH_MAX) 314 return -EINVAL; 315 316 st->act_threshold_buf[0] = FIELD_PREP(ADXL367_THRESH_H_MASK, 317 FIELD_GET(ADXL367_THRESH_VAL_H_MASK, 318 threshold)); 319 st->act_threshold_buf[1] = FIELD_PREP(ADXL367_THRESH_L_MASK, 320 FIELD_GET(ADXL367_THRESH_VAL_L_MASK, 321 threshold)); 322 323 ret = regmap_bulk_write(st->regmap, reg, st->act_threshold_buf, 324 sizeof(st->act_threshold_buf)); 325 if (ret) 326 return ret; 327 328 if (act == ADXL367_ACTIVITY) 329 st->act_threshold = threshold; 330 else 331 st->inact_threshold = threshold; 332 333 return 0; 334 } 335 336 static int adxl367_set_act_threshold(struct adxl367_state *st, 337 enum adxl367_activity_type act, 338 unsigned int threshold) 339 { 340 int ret; 341 342 guard(mutex)(&st->lock); 343 344 ret = adxl367_set_measure_en(st, false); 345 if (ret) 346 return ret; 347 348 ret = _adxl367_set_act_threshold(st, act, threshold); 349 if (ret) 350 return ret; 351 352 return adxl367_set_measure_en(st, true); 353 } 354 355 static int adxl367_set_act_proc_mode(struct adxl367_state *st, 356 enum adxl367_act_proc_mode mode) 357 { 358 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL, 359 ADXL367_ACT_LINKLOOP_MASK, 360 FIELD_PREP(ADXL367_ACT_LINKLOOP_MASK, 361 mode)); 362 } 363 364 static int adxl367_set_act_interrupt_en(struct adxl367_state *st, 365 enum adxl367_activity_type act, 366 bool en) 367 { 368 unsigned int mask = adxl367_act_int_mask_tbl[act]; 369 370 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP, 371 mask, en ? mask : 0); 372 } 373 374 static int adxl367_get_act_interrupt_en(struct adxl367_state *st, 375 enum adxl367_activity_type act, 376 bool *en) 377 { 378 unsigned int mask = adxl367_act_int_mask_tbl[act]; 379 unsigned int val; 380 int ret; 381 382 ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val); 383 if (ret) 384 return ret; 385 386 *en = !!(val & mask); 387 388 return 0; 389 } 390 391 static int adxl367_set_act_en(struct adxl367_state *st, 392 enum adxl367_activity_type act, 393 enum adxl367_act_en_mode en) 394 { 395 unsigned int ctl_shift = adxl367_act_en_shift_tbl[act]; 396 397 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL, 398 ADXL367_ACT_EN_MASK << ctl_shift, 399 en << ctl_shift); 400 } 401 402 static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st, 403 bool en) 404 { 405 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP, 406 ADXL367_INT_FIFO_WATERMARK_MASK, 407 en ? ADXL367_INT_FIFO_WATERMARK_MASK : 0); 408 } 409 410 static int adxl367_get_fifo_mode(struct adxl367_state *st, 411 enum adxl367_fifo_mode *fifo_mode) 412 { 413 unsigned int val; 414 int ret; 415 416 ret = regmap_read(st->regmap, ADXL367_REG_FIFO_CTL, &val); 417 if (ret) 418 return ret; 419 420 *fifo_mode = FIELD_GET(ADXL367_FIFO_CTL_MODE_MASK, val); 421 422 return 0; 423 } 424 425 static int adxl367_set_fifo_mode(struct adxl367_state *st, 426 enum adxl367_fifo_mode fifo_mode) 427 { 428 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL, 429 ADXL367_FIFO_CTL_MODE_MASK, 430 FIELD_PREP(ADXL367_FIFO_CTL_MODE_MASK, 431 fifo_mode)); 432 } 433 434 static int adxl367_set_fifo_format(struct adxl367_state *st, 435 enum adxl367_fifo_format fifo_format) 436 { 437 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL, 438 ADXL367_FIFO_CTL_FORMAT_MASK, 439 FIELD_PREP(ADXL367_FIFO_CTL_FORMAT_MASK, 440 fifo_format)); 441 } 442 443 static int adxl367_set_fifo_watermark(struct adxl367_state *st, 444 unsigned int fifo_watermark) 445 { 446 unsigned int fifo_samples = fifo_watermark * st->fifo_set_size; 447 unsigned int fifo_samples_h, fifo_samples_l; 448 int ret; 449 450 if (fifo_samples > ADXL367_FIFO_MAX_WATERMARK) 451 fifo_samples = ADXL367_FIFO_MAX_WATERMARK; 452 453 fifo_samples /= st->fifo_set_size; 454 455 fifo_samples_h = FIELD_PREP(ADXL367_SAMPLES_H_MASK, 456 FIELD_GET(ADXL367_SAMPLES_VAL_H_MASK, 457 fifo_samples)); 458 fifo_samples_l = FIELD_PREP(ADXL367_SAMPLES_L_MASK, 459 FIELD_GET(ADXL367_SAMPLES_VAL_L_MASK, 460 fifo_samples)); 461 462 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL, 463 ADXL367_SAMPLES_H_MASK, fifo_samples_h); 464 if (ret) 465 return ret; 466 467 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_SAMPLES, 468 ADXL367_SAMPLES_L_MASK, fifo_samples_l); 469 if (ret) 470 return ret; 471 472 st->fifo_watermark = fifo_watermark; 473 474 return 0; 475 } 476 477 static int adxl367_set_range(struct iio_dev *indio_dev, 478 enum adxl367_range range) 479 { 480 struct adxl367_state *st = iio_priv(indio_dev); 481 int ret; 482 483 guard(mutex)(&st->lock); 484 485 ret = adxl367_set_measure_en(st, false); 486 if (ret) 487 return ret; 488 489 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL, 490 ADXL367_FILTER_CTL_RANGE_MASK, 491 FIELD_PREP(ADXL367_FILTER_CTL_RANGE_MASK, 492 range)); 493 if (ret) 494 return ret; 495 496 adxl367_scale_act_thresholds(st, st->range, range); 497 498 /* Activity thresholds depend on range */ 499 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY, 500 st->act_threshold); 501 if (ret) 502 return ret; 503 504 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY, 505 st->inact_threshold); 506 if (ret) 507 return ret; 508 509 ret = adxl367_set_measure_en(st, true); 510 if (ret) 511 return ret; 512 513 st->range = range; 514 515 return 0; 516 } 517 518 static int adxl367_time_ms_to_samples(struct adxl367_state *st, unsigned int ms) 519 { 520 int freq_hz = adxl367_samp_freq_tbl[st->odr][0]; 521 int freq_microhz = adxl367_samp_freq_tbl[st->odr][1]; 522 /* Scale to decihertz to prevent precision loss in 12.5Hz case. */ 523 int freq_dhz = freq_hz * 10 + freq_microhz / 100000; 524 525 return DIV_ROUND_CLOSEST(ms * freq_dhz, 10000); 526 } 527 528 static int _adxl367_set_act_time_ms(struct adxl367_state *st, unsigned int ms) 529 { 530 unsigned int val = adxl367_time_ms_to_samples(st, ms); 531 int ret; 532 533 if (val > ADXL367_TIME_ACT_MAX) 534 val = ADXL367_TIME_ACT_MAX; 535 536 ret = regmap_write(st->regmap, ADXL367_REG_TIME_ACT, val); 537 if (ret) 538 return ret; 539 540 st->act_time_ms = ms; 541 542 return 0; 543 } 544 545 static int _adxl367_set_inact_time_ms(struct adxl367_state *st, unsigned int ms) 546 { 547 unsigned int val = adxl367_time_ms_to_samples(st, ms); 548 int ret; 549 550 if (val > ADXL367_TIME_INACT_MAX) 551 val = ADXL367_TIME_INACT_MAX; 552 553 st->inact_time_buf[0] = FIELD_PREP(ADXL367_TIME_INACT_H_MASK, 554 FIELD_GET(ADXL367_TIME_INACT_VAL_H_MASK, 555 val)); 556 st->inact_time_buf[1] = FIELD_PREP(ADXL367_TIME_INACT_L_MASK, 557 FIELD_GET(ADXL367_TIME_INACT_VAL_L_MASK, 558 val)); 559 560 ret = regmap_bulk_write(st->regmap, ADXL367_REG_TIME_INACT_H, 561 st->inact_time_buf, sizeof(st->inact_time_buf)); 562 if (ret) 563 return ret; 564 565 st->inact_time_ms = ms; 566 567 return 0; 568 } 569 570 static int adxl367_set_act_time_ms(struct adxl367_state *st, 571 enum adxl367_activity_type act, 572 unsigned int ms) 573 { 574 int ret; 575 576 guard(mutex)(&st->lock); 577 578 ret = adxl367_set_measure_en(st, false); 579 if (ret) 580 return ret; 581 582 if (act == ADXL367_ACTIVITY) 583 ret = _adxl367_set_act_time_ms(st, ms); 584 else 585 ret = _adxl367_set_inact_time_ms(st, ms); 586 587 if (ret) 588 return ret; 589 590 return adxl367_set_measure_en(st, true); 591 } 592 593 static int _adxl367_set_odr(struct adxl367_state *st, enum adxl367_odr odr) 594 { 595 int ret; 596 597 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL, 598 ADXL367_FILTER_CTL_ODR_MASK, 599 FIELD_PREP(ADXL367_FILTER_CTL_ODR_MASK, 600 odr)); 601 if (ret) 602 return ret; 603 604 /* Activity timers depend on ODR */ 605 ret = _adxl367_set_act_time_ms(st, st->act_time_ms); 606 if (ret) 607 return ret; 608 609 ret = _adxl367_set_inact_time_ms(st, st->inact_time_ms); 610 if (ret) 611 return ret; 612 613 st->odr = odr; 614 615 return 0; 616 } 617 618 static int adxl367_set_odr(struct iio_dev *indio_dev, enum adxl367_odr odr) 619 { 620 struct adxl367_state *st = iio_priv(indio_dev); 621 int ret; 622 623 guard(mutex)(&st->lock); 624 625 ret = adxl367_set_measure_en(st, false); 626 if (ret) 627 return ret; 628 629 ret = _adxl367_set_odr(st, odr); 630 if (ret) 631 return ret; 632 633 return adxl367_set_measure_en(st, true); 634 } 635 636 static int adxl367_set_temp_adc_en(struct adxl367_state *st, unsigned int reg, 637 bool en) 638 { 639 return regmap_update_bits(st->regmap, reg, ADXL367_ADC_EN_MASK, 640 en ? ADXL367_ADC_EN_MASK : 0); 641 } 642 643 static int adxl367_set_temp_adc_reg_en(struct adxl367_state *st, 644 unsigned int reg, bool en) 645 { 646 int ret; 647 648 switch (reg) { 649 case ADXL367_REG_TEMP_DATA_H: 650 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en); 651 break; 652 case ADXL367_REG_EX_ADC_DATA_H: 653 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en); 654 break; 655 default: 656 return 0; 657 } 658 659 if (ret) 660 return ret; 661 662 if (en) 663 msleep(100); 664 665 return 0; 666 } 667 668 static int adxl367_set_temp_adc_mask_en(struct adxl367_state *st, 669 const unsigned long *active_scan_mask, 670 bool en) 671 { 672 if (*active_scan_mask & ADXL367_TEMP_CHANNEL_MASK) 673 return adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en); 674 else if (*active_scan_mask & ADXL367_EX_ADC_CHANNEL_MASK) 675 return adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en); 676 677 return 0; 678 } 679 680 static int adxl367_find_odr(struct adxl367_state *st, int val, int val2, 681 enum adxl367_odr *odr) 682 { 683 size_t size = ARRAY_SIZE(adxl367_samp_freq_tbl); 684 int i; 685 686 for (i = 0; i < size; i++) 687 if (val == adxl367_samp_freq_tbl[i][0] && 688 val2 == adxl367_samp_freq_tbl[i][1]) 689 break; 690 691 if (i == size) 692 return -EINVAL; 693 694 *odr = i; 695 696 return 0; 697 } 698 699 static int adxl367_find_range(struct adxl367_state *st, int val, int val2, 700 enum adxl367_range *range) 701 { 702 size_t size = ARRAY_SIZE(adxl367_range_scale_tbl); 703 int i; 704 705 for (i = 0; i < size; i++) 706 if (val == adxl367_range_scale_tbl[i][0] && 707 val2 == adxl367_range_scale_tbl[i][1]) 708 break; 709 710 if (i == size) 711 return -EINVAL; 712 713 *range = i; 714 715 return 0; 716 } 717 718 static int adxl367_read_sample(struct iio_dev *indio_dev, 719 struct iio_chan_spec const *chan, 720 int *val) 721 { 722 struct adxl367_state *st = iio_priv(indio_dev); 723 u16 sample; 724 int ret; 725 726 guard(mutex)(&st->lock); 727 728 ret = adxl367_set_temp_adc_reg_en(st, chan->address, true); 729 if (ret) 730 return ret; 731 732 ret = regmap_bulk_read(st->regmap, chan->address, &st->sample_buf, 733 sizeof(st->sample_buf)); 734 if (ret) 735 return ret; 736 737 sample = FIELD_GET(ADXL367_DATA_MASK, be16_to_cpu(st->sample_buf)); 738 *val = sign_extend32(sample, chan->scan_type.realbits - 1); 739 740 ret = adxl367_set_temp_adc_reg_en(st, chan->address, false); 741 if (ret) 742 return ret; 743 744 return IIO_VAL_INT; 745 } 746 747 static int adxl367_get_status(struct adxl367_state *st, u8 *status, 748 u16 *fifo_entries) 749 { 750 int ret; 751 752 /* Read STATUS, FIFO_ENT_L and FIFO_ENT_H */ 753 ret = regmap_bulk_read(st->regmap, ADXL367_REG_STATUS, 754 st->status_buf, sizeof(st->status_buf)); 755 if (ret) 756 return ret; 757 758 st->status_buf[2] &= ADXL367_FIFO_ENT_H_MASK; 759 760 *status = st->status_buf[0]; 761 *fifo_entries = get_unaligned_le16(&st->status_buf[1]); 762 763 return 0; 764 } 765 766 static bool adxl367_push_event(struct iio_dev *indio_dev, u8 status) 767 { 768 unsigned int ev_dir; 769 770 if (FIELD_GET(ADXL367_STATUS_ACT_MASK, status)) 771 ev_dir = IIO_EV_DIR_RISING; 772 else if (FIELD_GET(ADXL367_STATUS_INACT_MASK, status)) 773 ev_dir = IIO_EV_DIR_FALLING; 774 else 775 return false; 776 777 iio_push_event(indio_dev, 778 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z, 779 IIO_EV_TYPE_THRESH, ev_dir), 780 iio_get_time_ns(indio_dev)); 781 782 return true; 783 } 784 785 static bool adxl367_push_fifo_data(struct iio_dev *indio_dev, u8 status, 786 u16 fifo_entries) 787 { 788 struct adxl367_state *st = iio_priv(indio_dev); 789 int ret; 790 int i; 791 792 if (!FIELD_GET(ADXL367_STATUS_FIFO_FULL_MASK, status)) 793 return false; 794 795 fifo_entries -= fifo_entries % st->fifo_set_size; 796 797 ret = st->ops->read_fifo(st->context, st->fifo_buf, fifo_entries); 798 if (ret) { 799 dev_err(st->dev, "Failed to read FIFO: %d\n", ret); 800 return true; 801 } 802 803 for (i = 0; i < fifo_entries; i += st->fifo_set_size) 804 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]); 805 806 return true; 807 } 808 809 static irqreturn_t adxl367_irq_handler(int irq, void *private) 810 { 811 struct iio_dev *indio_dev = private; 812 struct adxl367_state *st = iio_priv(indio_dev); 813 u16 fifo_entries; 814 bool handled; 815 u8 status; 816 int ret; 817 818 ret = adxl367_get_status(st, &status, &fifo_entries); 819 if (ret) 820 return IRQ_NONE; 821 822 handled = adxl367_push_event(indio_dev, status); 823 handled |= adxl367_push_fifo_data(indio_dev, status, fifo_entries); 824 825 return handled ? IRQ_HANDLED : IRQ_NONE; 826 } 827 828 static int adxl367_reg_access(struct iio_dev *indio_dev, 829 unsigned int reg, 830 unsigned int writeval, 831 unsigned int *readval) 832 { 833 struct adxl367_state *st = iio_priv(indio_dev); 834 835 if (readval) 836 return regmap_read(st->regmap, reg, readval); 837 else 838 return regmap_write(st->regmap, reg, writeval); 839 } 840 841 static int adxl367_read_raw(struct iio_dev *indio_dev, 842 struct iio_chan_spec const *chan, 843 int *val, int *val2, long info) 844 { 845 struct adxl367_state *st = iio_priv(indio_dev); 846 int ret; 847 848 switch (info) { 849 case IIO_CHAN_INFO_RAW: 850 if (!iio_device_claim_direct(indio_dev)) 851 return -EBUSY; 852 ret = adxl367_read_sample(indio_dev, chan, val); 853 iio_device_release_direct(indio_dev); 854 return ret; 855 case IIO_CHAN_INFO_SCALE: 856 switch (chan->type) { 857 case IIO_ACCEL: { 858 guard(mutex)(&st->lock); 859 *val = adxl367_range_scale_tbl[st->range][0]; 860 *val2 = adxl367_range_scale_tbl[st->range][1]; 861 return IIO_VAL_INT_PLUS_NANO; 862 } 863 case IIO_TEMP: 864 *val = 1000; 865 *val2 = ADXL367_TEMP_PER_C; 866 return IIO_VAL_FRACTIONAL; 867 case IIO_VOLTAGE: 868 *val = ADXL367_VOLTAGE_MAX_MV; 869 *val2 = ADXL367_VOLTAGE_MAX_RAW; 870 return IIO_VAL_FRACTIONAL; 871 default: 872 return -EINVAL; 873 } 874 case IIO_CHAN_INFO_OFFSET: 875 switch (chan->type) { 876 case IIO_TEMP: 877 *val = 25 * ADXL367_TEMP_PER_C - ADXL367_TEMP_25C; 878 return IIO_VAL_INT; 879 case IIO_VOLTAGE: 880 *val = ADXL367_VOLTAGE_OFFSET; 881 return IIO_VAL_INT; 882 default: 883 return -EINVAL; 884 } 885 case IIO_CHAN_INFO_SAMP_FREQ: { 886 guard(mutex)(&st->lock); 887 *val = adxl367_samp_freq_tbl[st->odr][0]; 888 *val2 = adxl367_samp_freq_tbl[st->odr][1]; 889 return IIO_VAL_INT_PLUS_MICRO; 890 } 891 default: 892 return -EINVAL; 893 } 894 } 895 896 static int adxl367_write_raw(struct iio_dev *indio_dev, 897 struct iio_chan_spec const *chan, 898 int val, int val2, long info) 899 { 900 struct adxl367_state *st = iio_priv(indio_dev); 901 int ret; 902 903 switch (info) { 904 case IIO_CHAN_INFO_SAMP_FREQ: { 905 enum adxl367_odr odr; 906 907 ret = adxl367_find_odr(st, val, val2, &odr); 908 if (ret) 909 return ret; 910 911 if (!iio_device_claim_direct(indio_dev)) 912 return -EBUSY; 913 914 ret = adxl367_set_odr(indio_dev, odr); 915 iio_device_release_direct(indio_dev); 916 return ret; 917 } 918 case IIO_CHAN_INFO_SCALE: { 919 enum adxl367_range range; 920 921 ret = adxl367_find_range(st, val, val2, &range); 922 if (ret) 923 return ret; 924 925 if (!iio_device_claim_direct(indio_dev)) 926 return -EBUSY; 927 928 ret = adxl367_set_range(indio_dev, range); 929 iio_device_release_direct(indio_dev); 930 return ret; 931 } 932 default: 933 return -EINVAL; 934 } 935 } 936 937 static int adxl367_write_raw_get_fmt(struct iio_dev *indio_dev, 938 struct iio_chan_spec const *chan, 939 long info) 940 { 941 switch (info) { 942 case IIO_CHAN_INFO_SCALE: 943 if (chan->type != IIO_ACCEL) 944 return -EINVAL; 945 946 return IIO_VAL_INT_PLUS_NANO; 947 default: 948 return IIO_VAL_INT_PLUS_MICRO; 949 } 950 } 951 952 static int adxl367_read_avail(struct iio_dev *indio_dev, 953 struct iio_chan_spec const *chan, 954 const int **vals, int *type, int *length, 955 long info) 956 { 957 switch (info) { 958 case IIO_CHAN_INFO_SCALE: 959 if (chan->type != IIO_ACCEL) 960 return -EINVAL; 961 962 *vals = (int *)adxl367_range_scale_tbl; 963 *type = IIO_VAL_INT_PLUS_NANO; 964 *length = ARRAY_SIZE(adxl367_range_scale_tbl) * 2; 965 return IIO_AVAIL_LIST; 966 case IIO_CHAN_INFO_SAMP_FREQ: 967 *vals = (int *)adxl367_samp_freq_tbl; 968 *type = IIO_VAL_INT_PLUS_MICRO; 969 *length = ARRAY_SIZE(adxl367_samp_freq_tbl) * 2; 970 return IIO_AVAIL_LIST; 971 default: 972 return -EINVAL; 973 } 974 } 975 976 static int adxl367_read_event_value(struct iio_dev *indio_dev, 977 const struct iio_chan_spec *chan, 978 enum iio_event_type type, 979 enum iio_event_direction dir, 980 enum iio_event_info info, 981 int *val, int *val2) 982 { 983 struct adxl367_state *st = iio_priv(indio_dev); 984 985 guard(mutex)(&st->lock); 986 switch (info) { 987 case IIO_EV_INFO_VALUE: { 988 switch (dir) { 989 case IIO_EV_DIR_RISING: 990 *val = st->act_threshold; 991 return IIO_VAL_INT; 992 case IIO_EV_DIR_FALLING: 993 *val = st->inact_threshold; 994 return IIO_VAL_INT; 995 default: 996 return -EINVAL; 997 } 998 } 999 case IIO_EV_INFO_PERIOD: 1000 switch (dir) { 1001 case IIO_EV_DIR_RISING: 1002 *val = st->act_time_ms; 1003 *val2 = 1000; 1004 return IIO_VAL_FRACTIONAL; 1005 case IIO_EV_DIR_FALLING: 1006 *val = st->inact_time_ms; 1007 *val2 = 1000; 1008 return IIO_VAL_FRACTIONAL; 1009 default: 1010 return -EINVAL; 1011 } 1012 default: 1013 return -EINVAL; 1014 } 1015 } 1016 1017 static int adxl367_write_event_value(struct iio_dev *indio_dev, 1018 const struct iio_chan_spec *chan, 1019 enum iio_event_type type, 1020 enum iio_event_direction dir, 1021 enum iio_event_info info, 1022 int val, int val2) 1023 { 1024 struct adxl367_state *st = iio_priv(indio_dev); 1025 1026 switch (info) { 1027 case IIO_EV_INFO_VALUE: 1028 if (val < 0) 1029 return -EINVAL; 1030 1031 switch (dir) { 1032 case IIO_EV_DIR_RISING: 1033 return adxl367_set_act_threshold(st, ADXL367_ACTIVITY, val); 1034 case IIO_EV_DIR_FALLING: 1035 return adxl367_set_act_threshold(st, ADXL367_INACTIVITY, val); 1036 default: 1037 return -EINVAL; 1038 } 1039 case IIO_EV_INFO_PERIOD: 1040 if (val < 0) 1041 return -EINVAL; 1042 1043 val = val * 1000 + DIV_ROUND_UP(val2, 1000); 1044 switch (dir) { 1045 case IIO_EV_DIR_RISING: 1046 return adxl367_set_act_time_ms(st, ADXL367_ACTIVITY, val); 1047 case IIO_EV_DIR_FALLING: 1048 return adxl367_set_act_time_ms(st, ADXL367_INACTIVITY, val); 1049 default: 1050 return -EINVAL; 1051 } 1052 default: 1053 return -EINVAL; 1054 } 1055 } 1056 1057 static int adxl367_read_event_config(struct iio_dev *indio_dev, 1058 const struct iio_chan_spec *chan, 1059 enum iio_event_type type, 1060 enum iio_event_direction dir) 1061 { 1062 struct adxl367_state *st = iio_priv(indio_dev); 1063 bool en; 1064 int ret; 1065 1066 switch (dir) { 1067 case IIO_EV_DIR_RISING: 1068 ret = adxl367_get_act_interrupt_en(st, ADXL367_ACTIVITY, &en); 1069 return ret ?: en; 1070 case IIO_EV_DIR_FALLING: 1071 ret = adxl367_get_act_interrupt_en(st, ADXL367_INACTIVITY, &en); 1072 return ret ?: en; 1073 default: 1074 return -EINVAL; 1075 } 1076 } 1077 1078 static int __adxl367_write_event_config(struct iio_dev *indio_dev, 1079 const struct iio_chan_spec *chan, 1080 enum iio_event_type type, 1081 enum iio_event_direction dir, 1082 bool state) 1083 { 1084 struct adxl367_state *st = iio_priv(indio_dev); 1085 enum adxl367_activity_type act; 1086 int ret; 1087 1088 switch (dir) { 1089 case IIO_EV_DIR_RISING: 1090 act = ADXL367_ACTIVITY; 1091 break; 1092 case IIO_EV_DIR_FALLING: 1093 act = ADXL367_INACTIVITY; 1094 break; 1095 default: 1096 return -EINVAL; 1097 } 1098 1099 guard(mutex)(&st->lock); 1100 1101 ret = adxl367_set_measure_en(st, false); 1102 if (ret) 1103 return ret; 1104 1105 ret = adxl367_set_act_interrupt_en(st, act, state); 1106 if (ret) 1107 return ret; 1108 1109 ret = adxl367_set_act_en(st, act, state ? ADCL367_ACT_REF_ENABLED 1110 : ADXL367_ACT_DISABLED); 1111 if (ret) 1112 return ret; 1113 1114 return adxl367_set_measure_en(st, true); 1115 } 1116 1117 static int adxl367_write_event_config(struct iio_dev *indio_dev, 1118 const struct iio_chan_spec *chan, 1119 enum iio_event_type type, 1120 enum iio_event_direction dir, 1121 bool state) 1122 { 1123 int ret; 1124 1125 if (!iio_device_claim_direct(indio_dev)) 1126 return -EBUSY; 1127 1128 ret = __adxl367_write_event_config(indio_dev, chan, type, dir, state); 1129 iio_device_release_direct(indio_dev); 1130 return ret; 1131 } 1132 1133 static ssize_t adxl367_get_fifo_enabled(struct device *dev, 1134 struct device_attribute *attr, 1135 char *buf) 1136 { 1137 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev)); 1138 enum adxl367_fifo_mode fifo_mode; 1139 int ret; 1140 1141 ret = adxl367_get_fifo_mode(st, &fifo_mode); 1142 if (ret) 1143 return ret; 1144 1145 return sysfs_emit(buf, "%d\n", fifo_mode != ADXL367_FIFO_MODE_DISABLED); 1146 } 1147 1148 static ssize_t adxl367_get_fifo_watermark(struct device *dev, 1149 struct device_attribute *attr, 1150 char *buf) 1151 { 1152 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev)); 1153 unsigned int fifo_watermark; 1154 1155 guard(mutex)(&st->lock); 1156 fifo_watermark = st->fifo_watermark; 1157 1158 return sysfs_emit(buf, "%d\n", fifo_watermark); 1159 } 1160 1161 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "1"); 1162 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max, 1163 __stringify(ADXL367_FIFO_MAX_WATERMARK)); 1164 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 1165 adxl367_get_fifo_watermark, NULL, 0); 1166 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 1167 adxl367_get_fifo_enabled, NULL, 0); 1168 1169 static const struct iio_dev_attr *adxl367_fifo_attributes[] = { 1170 &iio_dev_attr_hwfifo_watermark_min, 1171 &iio_dev_attr_hwfifo_watermark_max, 1172 &iio_dev_attr_hwfifo_watermark, 1173 &iio_dev_attr_hwfifo_enabled, 1174 NULL, 1175 }; 1176 1177 static int adxl367_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1178 { 1179 struct adxl367_state *st = iio_priv(indio_dev); 1180 int ret; 1181 1182 if (val > ADXL367_FIFO_MAX_WATERMARK) 1183 return -EINVAL; 1184 1185 guard(mutex)(&st->lock); 1186 1187 ret = adxl367_set_measure_en(st, false); 1188 if (ret) 1189 return ret; 1190 1191 ret = adxl367_set_fifo_watermark(st, val); 1192 if (ret) 1193 return ret; 1194 1195 return adxl367_set_measure_en(st, true); 1196 } 1197 1198 static bool adxl367_find_mask_fifo_format(const unsigned long *scan_mask, 1199 enum adxl367_fifo_format *fifo_format) 1200 { 1201 size_t size = ARRAY_SIZE(adxl367_fifo_formats); 1202 int i; 1203 1204 for (i = 0; i < size; i++) 1205 if (*scan_mask == adxl367_channel_masks[i]) 1206 break; 1207 1208 if (i == size) 1209 return false; 1210 1211 *fifo_format = adxl367_fifo_formats[i]; 1212 1213 return true; 1214 } 1215 1216 static int adxl367_update_scan_mode(struct iio_dev *indio_dev, 1217 const unsigned long *active_scan_mask) 1218 { 1219 struct adxl367_state *st = iio_priv(indio_dev); 1220 enum adxl367_fifo_format fifo_format; 1221 int ret; 1222 1223 if (!adxl367_find_mask_fifo_format(active_scan_mask, &fifo_format)) 1224 return -EINVAL; 1225 1226 guard(mutex)(&st->lock); 1227 1228 ret = adxl367_set_measure_en(st, false); 1229 if (ret) 1230 return ret; 1231 1232 ret = adxl367_set_fifo_format(st, fifo_format); 1233 if (ret) 1234 return ret; 1235 1236 ret = adxl367_set_measure_en(st, true); 1237 if (ret) 1238 return ret; 1239 1240 st->fifo_set_size = bitmap_weight(active_scan_mask, 1241 iio_get_masklength(indio_dev)); 1242 1243 return 0; 1244 } 1245 1246 static int adxl367_buffer_postenable(struct iio_dev *indio_dev) 1247 { 1248 struct adxl367_state *st = iio_priv(indio_dev); 1249 int ret; 1250 1251 guard(mutex)(&st->lock); 1252 1253 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask, 1254 true); 1255 if (ret) 1256 return ret; 1257 1258 ret = adxl367_set_measure_en(st, false); 1259 if (ret) 1260 return ret; 1261 1262 ret = adxl367_set_fifo_watermark_interrupt_en(st, true); 1263 if (ret) 1264 return ret; 1265 1266 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_STREAM); 1267 if (ret) 1268 return ret; 1269 1270 return adxl367_set_measure_en(st, true); 1271 } 1272 1273 static int adxl367_buffer_predisable(struct iio_dev *indio_dev) 1274 { 1275 struct adxl367_state *st = iio_priv(indio_dev); 1276 int ret; 1277 1278 guard(mutex)(&st->lock); 1279 1280 ret = adxl367_set_measure_en(st, false); 1281 if (ret) 1282 return ret; 1283 1284 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_DISABLED); 1285 if (ret) 1286 return ret; 1287 1288 ret = adxl367_set_fifo_watermark_interrupt_en(st, false); 1289 if (ret) 1290 return ret; 1291 1292 ret = adxl367_set_measure_en(st, true); 1293 if (ret) 1294 return ret; 1295 1296 return adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask, 1297 false); 1298 } 1299 1300 static const struct iio_buffer_setup_ops adxl367_buffer_ops = { 1301 .postenable = adxl367_buffer_postenable, 1302 .predisable = adxl367_buffer_predisable, 1303 }; 1304 1305 static const struct iio_info adxl367_info = { 1306 .read_raw = adxl367_read_raw, 1307 .write_raw = adxl367_write_raw, 1308 .write_raw_get_fmt = adxl367_write_raw_get_fmt, 1309 .read_avail = adxl367_read_avail, 1310 .read_event_config = adxl367_read_event_config, 1311 .write_event_config = adxl367_write_event_config, 1312 .read_event_value = adxl367_read_event_value, 1313 .write_event_value = adxl367_write_event_value, 1314 .debugfs_reg_access = adxl367_reg_access, 1315 .hwfifo_set_watermark = adxl367_set_watermark, 1316 .update_scan_mode = adxl367_update_scan_mode, 1317 }; 1318 1319 static const struct iio_event_spec adxl367_events[] = { 1320 { 1321 .type = IIO_EV_TYPE_MAG_REFERENCED, 1322 .dir = IIO_EV_DIR_RISING, 1323 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) | 1324 BIT(IIO_EV_INFO_PERIOD) | 1325 BIT(IIO_EV_INFO_VALUE), 1326 }, 1327 { 1328 .type = IIO_EV_TYPE_MAG_REFERENCED, 1329 .dir = IIO_EV_DIR_FALLING, 1330 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) | 1331 BIT(IIO_EV_INFO_PERIOD) | 1332 BIT(IIO_EV_INFO_VALUE), 1333 }, 1334 }; 1335 1336 #define ADXL367_ACCEL_CHANNEL(index, reg, axis) { \ 1337 .type = IIO_ACCEL, \ 1338 .address = (reg), \ 1339 .modified = 1, \ 1340 .channel2 = IIO_MOD_##axis, \ 1341 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 1342 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 1343 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ 1344 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1345 .info_mask_shared_by_all_available = \ 1346 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1347 .event_spec = adxl367_events, \ 1348 .num_event_specs = ARRAY_SIZE(adxl367_events), \ 1349 .scan_index = (index), \ 1350 .scan_type = { \ 1351 .sign = 's', \ 1352 .realbits = 14, \ 1353 .storagebits = 16, \ 1354 .endianness = IIO_BE, \ 1355 }, \ 1356 } 1357 1358 #define ADXL367_CHANNEL(index, reg, _type) { \ 1359 .type = (_type), \ 1360 .address = (reg), \ 1361 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1362 BIT(IIO_CHAN_INFO_OFFSET) | \ 1363 BIT(IIO_CHAN_INFO_SCALE), \ 1364 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1365 .scan_index = (index), \ 1366 .scan_type = { \ 1367 .sign = 's', \ 1368 .realbits = 14, \ 1369 .storagebits = 16, \ 1370 .endianness = IIO_BE, \ 1371 }, \ 1372 } 1373 1374 static const struct iio_chan_spec adxl367_channels[] = { 1375 ADXL367_ACCEL_CHANNEL(ADXL367_X_CHANNEL_INDEX, ADXL367_REG_X_DATA_H, X), 1376 ADXL367_ACCEL_CHANNEL(ADXL367_Y_CHANNEL_INDEX, ADXL367_REG_Y_DATA_H, Y), 1377 ADXL367_ACCEL_CHANNEL(ADXL367_Z_CHANNEL_INDEX, ADXL367_REG_Z_DATA_H, Z), 1378 ADXL367_CHANNEL(ADXL367_TEMP_CHANNEL_INDEX, ADXL367_REG_TEMP_DATA_H, 1379 IIO_TEMP), 1380 ADXL367_CHANNEL(ADXL367_EX_ADC_CHANNEL_INDEX, ADXL367_REG_EX_ADC_DATA_H, 1381 IIO_VOLTAGE), 1382 }; 1383 1384 static int adxl367_verify_devid(struct adxl367_state *st) 1385 { 1386 unsigned int val; 1387 int ret; 1388 1389 ret = regmap_read(st->regmap, ADXL367_REG_DEVID, &val); 1390 if (ret) 1391 return dev_err_probe(st->dev, ret, "Failed to read dev id\n"); 1392 1393 if (val != ADXL367_DEVID_AD) 1394 return dev_err_probe(st->dev, -ENODEV, 1395 "Invalid dev id 0x%02X, expected 0x%02X\n", 1396 val, ADXL367_DEVID_AD); 1397 1398 return 0; 1399 } 1400 1401 static int adxl367_setup(struct adxl367_state *st) 1402 { 1403 int ret; 1404 1405 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY, 1406 ADXL367_2G_RANGE_1G); 1407 if (ret) 1408 return ret; 1409 1410 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY, 1411 ADXL367_2G_RANGE_100MG); 1412 if (ret) 1413 return ret; 1414 1415 ret = adxl367_set_act_proc_mode(st, ADXL367_LOOPED); 1416 if (ret) 1417 return ret; 1418 1419 ret = _adxl367_set_odr(st, ADXL367_ODR_400HZ); 1420 if (ret) 1421 return ret; 1422 1423 ret = _adxl367_set_act_time_ms(st, 10); 1424 if (ret) 1425 return ret; 1426 1427 ret = _adxl367_set_inact_time_ms(st, 10000); 1428 if (ret) 1429 return ret; 1430 1431 return adxl367_set_measure_en(st, true); 1432 } 1433 1434 int adxl367_probe(struct device *dev, const struct adxl367_ops *ops, 1435 void *context, struct regmap *regmap, int irq) 1436 { 1437 static const char * const regulator_names[] = { "vdd", "vddio" }; 1438 struct iio_dev *indio_dev; 1439 struct adxl367_state *st; 1440 int ret; 1441 1442 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1443 if (!indio_dev) 1444 return -ENOMEM; 1445 1446 st = iio_priv(indio_dev); 1447 st->dev = dev; 1448 st->regmap = regmap; 1449 st->context = context; 1450 st->ops = ops; 1451 1452 mutex_init(&st->lock); 1453 1454 indio_dev->channels = adxl367_channels; 1455 indio_dev->num_channels = ARRAY_SIZE(adxl367_channels); 1456 indio_dev->available_scan_masks = adxl367_channel_masks; 1457 indio_dev->name = "adxl367"; 1458 indio_dev->info = &adxl367_info; 1459 indio_dev->modes = INDIO_DIRECT_MODE; 1460 1461 ret = devm_regulator_bulk_get_enable(st->dev, 1462 ARRAY_SIZE(regulator_names), 1463 regulator_names); 1464 if (ret) 1465 return dev_err_probe(st->dev, ret, 1466 "Failed to get regulators\n"); 1467 1468 ret = regmap_write(st->regmap, ADXL367_REG_RESET, ADXL367_RESET_CODE); 1469 if (ret) 1470 return ret; 1471 1472 fsleep(15000); 1473 1474 ret = adxl367_verify_devid(st); 1475 if (ret) 1476 return ret; 1477 1478 ret = adxl367_setup(st); 1479 if (ret) 1480 return ret; 1481 1482 ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev, 1483 &adxl367_buffer_ops, 1484 adxl367_fifo_attributes); 1485 if (ret) 1486 return ret; 1487 1488 ret = devm_request_threaded_irq(st->dev, irq, NULL, 1489 adxl367_irq_handler, IRQF_ONESHOT, 1490 indio_dev->name, indio_dev); 1491 if (ret) 1492 return dev_err_probe(st->dev, ret, "Failed to request irq\n"); 1493 1494 return devm_iio_device_register(dev, indio_dev); 1495 } 1496 EXPORT_SYMBOL_NS_GPL(adxl367_probe, "IIO_ADXL367"); 1497 1498 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>"); 1499 MODULE_DESCRIPTION("Analog Devices ADXL367 3-axis accelerometer driver"); 1500 MODULE_LICENSE("GPL"); 1501