1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADXL355 3-Axis Digital Accelerometer IIO core driver 4 * 5 * Copyright (c) 2021 Puranjay Mohan <puranjay12@gmail.com> 6 * 7 * Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/adxl354_adxl355.pdf 8 */ 9 10 #include <linux/bits.h> 11 #include <linux/bitfield.h> 12 #include <linux/iio/buffer.h> 13 #include <linux/iio/iio.h> 14 #include <linux/iio/trigger.h> 15 #include <linux/iio/triggered_buffer.h> 16 #include <linux/iio/trigger_consumer.h> 17 #include <linux/limits.h> 18 #include <linux/math64.h> 19 #include <linux/module.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/property.h> 22 #include <linux/regmap.h> 23 #include <linux/units.h> 24 25 #include <linux/unaligned.h> 26 27 #include "adxl355.h" 28 29 /* ADXL355 Register Definitions */ 30 #define ADXL355_DEVID_AD_REG 0x00 31 #define ADXL355_DEVID_MST_REG 0x01 32 #define ADXL355_PARTID_REG 0x02 33 #define ADXL355_STATUS_REG 0x04 34 #define ADXL355_FIFO_ENTRIES_REG 0x05 35 #define ADXL355_TEMP2_REG 0x06 36 #define ADXL355_XDATA3_REG 0x08 37 #define ADXL355_YDATA3_REG 0x0B 38 #define ADXL355_ZDATA3_REG 0x0E 39 #define ADXL355_FIFO_DATA_REG 0x11 40 #define ADXL355_OFFSET_X_H_REG 0x1E 41 #define ADXL355_OFFSET_Y_H_REG 0x20 42 #define ADXL355_OFFSET_Z_H_REG 0x22 43 #define ADXL355_ACT_EN_REG 0x24 44 #define ADXL355_ACT_THRESH_H_REG 0x25 45 #define ADXL355_ACT_THRESH_L_REG 0x26 46 #define ADXL355_ACT_COUNT_REG 0x27 47 #define ADXL355_FILTER_REG 0x28 48 #define ADXL355_FILTER_ODR_MSK GENMASK(3, 0) 49 #define ADXL355_FILTER_HPF_MSK GENMASK(6, 4) 50 #define ADXL355_FIFO_SAMPLES_REG 0x29 51 #define ADXL355_INT_MAP_REG 0x2A 52 #define ADXL355_SYNC_REG 0x2B 53 #define ADXL355_RANGE_REG 0x2C 54 #define ADXL355_POWER_CTL_REG 0x2D 55 #define ADXL355_POWER_CTL_MODE_MSK GENMASK(1, 0) 56 #define ADXL355_POWER_CTL_DRDY_MSK BIT(2) 57 #define ADXL355_SELF_TEST_REG 0x2E 58 #define ADXL355_RESET_REG 0x2F 59 #define ADXL355_BASE_ADDR_SHADOW_REG 0x50 60 #define ADXL355_SHADOW_REG_COUNT 5 61 62 #define ADXL355_DEVID_AD_VAL 0xAD 63 #define ADXL355_DEVID_MST_VAL 0x1D 64 #define ADXL355_PARTID_VAL 0xED 65 #define ADXL359_PARTID_VAL 0xE9 66 #define ADXL355_RESET_CODE 0x52 67 68 static const struct regmap_range adxl355_read_reg_range[] = { 69 regmap_reg_range(ADXL355_DEVID_AD_REG, ADXL355_FIFO_DATA_REG), 70 regmap_reg_range(ADXL355_OFFSET_X_H_REG, ADXL355_SELF_TEST_REG), 71 }; 72 73 const struct regmap_access_table adxl355_readable_regs_tbl = { 74 .yes_ranges = adxl355_read_reg_range, 75 .n_yes_ranges = ARRAY_SIZE(adxl355_read_reg_range), 76 }; 77 EXPORT_SYMBOL_NS_GPL(adxl355_readable_regs_tbl, "IIO_ADXL355"); 78 79 static const struct regmap_range adxl355_write_reg_range[] = { 80 regmap_reg_range(ADXL355_OFFSET_X_H_REG, ADXL355_RESET_REG), 81 }; 82 83 const struct regmap_access_table adxl355_writeable_regs_tbl = { 84 .yes_ranges = adxl355_write_reg_range, 85 .n_yes_ranges = ARRAY_SIZE(adxl355_write_reg_range), 86 }; 87 EXPORT_SYMBOL_NS_GPL(adxl355_writeable_regs_tbl, "IIO_ADXL355"); 88 89 const struct adxl355_chip_info adxl35x_chip_info[] = { 90 [ADXL355] = { 91 .name = "adxl355", 92 .part_id = ADXL355_PARTID_VAL, 93 /* 94 * At +/- 2g with 20-bit resolution, scale is given in datasheet 95 * as 3.9ug/LSB = 0.0000039 * 9.80665 = 0.00003824593 m/s^2. 96 */ 97 .accel_scale = { 98 .integer = 0, 99 .decimal = 38245, 100 }, 101 /* 102 * The datasheet defines an intercept of 1885 LSB at 25 degC 103 * and a slope of -9.05 LSB/C. The following formula can be used 104 * to find the temperature: 105 * Temp = ((RAW - 1885)/(-9.05)) + 25 but this doesn't follow 106 * the format of the IIO which is Temp = (RAW + OFFSET) * SCALE. 107 * Hence using some rearranging we get the scale as -110.497238 108 * and offset as -2111.25. 109 */ 110 .temp_offset = { 111 .integer = -2111, 112 .decimal = 250000, 113 }, 114 }, 115 [ADXL359] = { 116 .name = "adxl359", 117 .part_id = ADXL359_PARTID_VAL, 118 /* 119 * At +/- 10g with 20-bit resolution, scale is given in datasheet 120 * as 19.5ug/LSB = 0.0000195 * 9.80665 = 0.0.00019122967 m/s^2. 121 */ 122 .accel_scale = { 123 .integer = 0, 124 .decimal = 191229, 125 }, 126 /* 127 * The datasheet defines an intercept of 1852 LSB at 25 degC 128 * and a slope of -9.05 LSB/C. The following formula can be used 129 * to find the temperature: 130 * Temp = ((RAW - 1852)/(-9.05)) + 25 but this doesn't follow 131 * the format of the IIO which is Temp = (RAW + OFFSET) * SCALE. 132 * Hence using some rearranging we get the scale as -110.497238 133 * and offset as -2079.25. 134 */ 135 .temp_offset = { 136 .integer = -2079, 137 .decimal = 250000, 138 }, 139 }, 140 }; 141 EXPORT_SYMBOL_NS_GPL(adxl35x_chip_info, "IIO_ADXL355"); 142 143 enum adxl355_op_mode { 144 ADXL355_MEASUREMENT, 145 ADXL355_STANDBY, 146 ADXL355_TEMP_OFF, 147 }; 148 149 enum adxl355_odr { 150 ADXL355_ODR_4000HZ, 151 ADXL355_ODR_2000HZ, 152 ADXL355_ODR_1000HZ, 153 ADXL355_ODR_500HZ, 154 ADXL355_ODR_250HZ, 155 ADXL355_ODR_125HZ, 156 ADXL355_ODR_62_5HZ, 157 ADXL355_ODR_31_25HZ, 158 ADXL355_ODR_15_625HZ, 159 ADXL355_ODR_7_813HZ, 160 ADXL355_ODR_3_906HZ, 161 }; 162 163 enum adxl355_hpf_3db { 164 ADXL355_HPF_OFF, 165 ADXL355_HPF_24_7, 166 ADXL355_HPF_6_2084, 167 ADXL355_HPF_1_5545, 168 ADXL355_HPF_0_3862, 169 ADXL355_HPF_0_0954, 170 ADXL355_HPF_0_0238, 171 }; 172 173 static const int adxl355_odr_table[][2] = { 174 [0] = {4000, 0}, 175 [1] = {2000, 0}, 176 [2] = {1000, 0}, 177 [3] = {500, 0}, 178 [4] = {250, 0}, 179 [5] = {125, 0}, 180 [6] = {62, 500000}, 181 [7] = {31, 250000}, 182 [8] = {15, 625000}, 183 [9] = {7, 813000}, 184 [10] = {3, 906000}, 185 }; 186 187 static const int adxl355_hpf_3db_multipliers[] = { 188 0, 189 247000, 190 62084, 191 15545, 192 3862, 193 954, 194 238, 195 }; 196 197 enum adxl355_chans { 198 chan_x, chan_y, chan_z, 199 }; 200 201 struct adxl355_chan_info { 202 u8 data_reg; 203 u8 offset_reg; 204 }; 205 206 static const struct adxl355_chan_info adxl355_chans[] = { 207 [chan_x] = { 208 .data_reg = ADXL355_XDATA3_REG, 209 .offset_reg = ADXL355_OFFSET_X_H_REG 210 }, 211 [chan_y] = { 212 .data_reg = ADXL355_YDATA3_REG, 213 .offset_reg = ADXL355_OFFSET_Y_H_REG 214 }, 215 [chan_z] = { 216 .data_reg = ADXL355_ZDATA3_REG, 217 .offset_reg = ADXL355_OFFSET_Z_H_REG 218 }, 219 }; 220 221 struct adxl355_data { 222 const struct adxl355_chip_info *chip_info; 223 struct regmap *regmap; 224 struct device *dev; 225 struct mutex lock; /* lock to protect op_mode */ 226 enum adxl355_op_mode op_mode; 227 enum adxl355_odr odr; 228 enum adxl355_hpf_3db hpf_3db; 229 int calibbias[3]; 230 int adxl355_hpf_3db_table[7][2]; 231 struct iio_trigger *dready_trig; 232 union { 233 u8 transf_buf[3]; 234 struct { 235 u8 buf[14]; 236 aligned_s64 ts; 237 } buffer; 238 } __aligned(IIO_DMA_MINALIGN); 239 }; 240 241 static int adxl355_set_op_mode(struct adxl355_data *data, 242 enum adxl355_op_mode op_mode) 243 { 244 int ret; 245 246 if (data->op_mode == op_mode) 247 return 0; 248 249 ret = regmap_update_bits(data->regmap, ADXL355_POWER_CTL_REG, 250 ADXL355_POWER_CTL_MODE_MSK, op_mode); 251 if (ret) 252 return ret; 253 254 data->op_mode = op_mode; 255 256 return ret; 257 } 258 259 static int adxl355_data_rdy_trigger_set_state(struct iio_trigger *trig, 260 bool state) 261 { 262 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 263 struct adxl355_data *data = iio_priv(indio_dev); 264 int ret; 265 266 mutex_lock(&data->lock); 267 ret = regmap_update_bits(data->regmap, ADXL355_POWER_CTL_REG, 268 ADXL355_POWER_CTL_DRDY_MSK, 269 FIELD_PREP(ADXL355_POWER_CTL_DRDY_MSK, 270 state ? 0 : 1)); 271 mutex_unlock(&data->lock); 272 273 return ret; 274 } 275 276 static void adxl355_fill_3db_frequency_table(struct adxl355_data *data) 277 { 278 u32 multiplier; 279 u64 div, rem; 280 u64 odr; 281 int i; 282 283 odr = mul_u64_u32_shr(adxl355_odr_table[data->odr][0], MEGA, 0) + 284 adxl355_odr_table[data->odr][1]; 285 286 for (i = 0; i < ARRAY_SIZE(adxl355_hpf_3db_multipliers); i++) { 287 multiplier = adxl355_hpf_3db_multipliers[i]; 288 div = div64_u64_rem(mul_u64_u32_shr(odr, multiplier, 0), 289 TERA * 100, &rem); 290 291 data->adxl355_hpf_3db_table[i][0] = div; 292 data->adxl355_hpf_3db_table[i][1] = div_u64(rem, MEGA * 100); 293 } 294 } 295 296 static int adxl355_setup(struct adxl355_data *data) 297 { 298 unsigned int regval; 299 int retries = 5; /* the number is chosen based on empirical reasons */ 300 int ret; 301 u8 *shadow_regs __free(kfree) = kzalloc(ADXL355_SHADOW_REG_COUNT, GFP_KERNEL); 302 303 if (!shadow_regs) 304 return -ENOMEM; 305 306 ret = regmap_read(data->regmap, ADXL355_DEVID_AD_REG, ®val); 307 if (ret) 308 return ret; 309 310 if (regval != ADXL355_DEVID_AD_VAL) { 311 dev_err(data->dev, "Invalid ADI ID 0x%02x\n", regval); 312 return -ENODEV; 313 } 314 315 ret = regmap_read(data->regmap, ADXL355_DEVID_MST_REG, ®val); 316 if (ret) 317 return ret; 318 319 if (regval != ADXL355_DEVID_MST_VAL) { 320 dev_err(data->dev, "Invalid MEMS ID 0x%02x\n", regval); 321 return -ENODEV; 322 } 323 324 ret = regmap_read(data->regmap, ADXL355_PARTID_REG, ®val); 325 if (ret) 326 return ret; 327 328 if (regval != ADXL355_PARTID_VAL) 329 dev_warn(data->dev, "Invalid DEV ID 0x%02x\n", regval); 330 331 /* Read shadow registers to be compared after reset */ 332 ret = regmap_bulk_read(data->regmap, 333 ADXL355_BASE_ADDR_SHADOW_REG, 334 shadow_regs, ADXL355_SHADOW_REG_COUNT); 335 if (ret) 336 return ret; 337 338 do { 339 if (--retries == 0) { 340 dev_err(data->dev, "Shadow registers mismatch\n"); 341 return -EIO; 342 } 343 344 /* 345 * Perform a software reset to make sure the device is in a consistent 346 * state after start-up. 347 */ 348 ret = regmap_write(data->regmap, ADXL355_RESET_REG, 349 ADXL355_RESET_CODE); 350 if (ret) 351 return ret; 352 353 /* Wait at least 5ms after software reset */ 354 usleep_range(5000, 10000); 355 356 /* Read shadow registers for comparison */ 357 ret = regmap_bulk_read(data->regmap, 358 ADXL355_BASE_ADDR_SHADOW_REG, 359 data->buffer.buf, 360 ADXL355_SHADOW_REG_COUNT); 361 if (ret) 362 return ret; 363 } while (memcmp(shadow_regs, data->buffer.buf, 364 ADXL355_SHADOW_REG_COUNT)); 365 366 ret = regmap_update_bits(data->regmap, ADXL355_POWER_CTL_REG, 367 ADXL355_POWER_CTL_DRDY_MSK, 368 FIELD_PREP(ADXL355_POWER_CTL_DRDY_MSK, 1)); 369 if (ret) 370 return ret; 371 372 adxl355_fill_3db_frequency_table(data); 373 374 return adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 375 } 376 377 static int adxl355_get_temp_data(struct adxl355_data *data, u8 addr) 378 { 379 return regmap_bulk_read(data->regmap, addr, data->transf_buf, 2); 380 } 381 382 static int adxl355_read_axis(struct adxl355_data *data, u8 addr) 383 { 384 int ret; 385 386 ret = regmap_bulk_read(data->regmap, addr, data->transf_buf, 387 ARRAY_SIZE(data->transf_buf)); 388 if (ret) 389 return ret; 390 391 return get_unaligned_be24(data->transf_buf); 392 } 393 394 static int adxl355_find_match(const int (*freq_tbl)[2], const int n, 395 const int val, const int val2) 396 { 397 int i; 398 399 for (i = 0; i < n; i++) { 400 if (freq_tbl[i][0] == val && freq_tbl[i][1] == val2) 401 return i; 402 } 403 404 return -EINVAL; 405 } 406 407 static int adxl355_set_odr(struct adxl355_data *data, 408 enum adxl355_odr odr) 409 { 410 int ret; 411 412 mutex_lock(&data->lock); 413 414 if (data->odr == odr) { 415 mutex_unlock(&data->lock); 416 return 0; 417 } 418 419 ret = adxl355_set_op_mode(data, ADXL355_STANDBY); 420 if (ret) 421 goto err_unlock; 422 423 ret = regmap_update_bits(data->regmap, ADXL355_FILTER_REG, 424 ADXL355_FILTER_ODR_MSK, 425 FIELD_PREP(ADXL355_FILTER_ODR_MSK, odr)); 426 if (ret) 427 goto err_set_opmode; 428 429 data->odr = odr; 430 adxl355_fill_3db_frequency_table(data); 431 432 ret = adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 433 if (ret) 434 goto err_set_opmode; 435 436 mutex_unlock(&data->lock); 437 return 0; 438 439 err_set_opmode: 440 adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 441 err_unlock: 442 mutex_unlock(&data->lock); 443 return ret; 444 } 445 446 static int adxl355_set_hpf_3db(struct adxl355_data *data, 447 enum adxl355_hpf_3db hpf) 448 { 449 int ret; 450 451 mutex_lock(&data->lock); 452 453 if (data->hpf_3db == hpf) { 454 mutex_unlock(&data->lock); 455 return 0; 456 } 457 458 ret = adxl355_set_op_mode(data, ADXL355_STANDBY); 459 if (ret) 460 goto err_unlock; 461 462 ret = regmap_update_bits(data->regmap, ADXL355_FILTER_REG, 463 ADXL355_FILTER_HPF_MSK, 464 FIELD_PREP(ADXL355_FILTER_HPF_MSK, hpf)); 465 if (ret) 466 goto err_set_opmode; 467 468 data->hpf_3db = hpf; 469 470 ret = adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 471 if (ret) 472 goto err_set_opmode; 473 474 mutex_unlock(&data->lock); 475 return 0; 476 477 err_set_opmode: 478 adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 479 err_unlock: 480 mutex_unlock(&data->lock); 481 return ret; 482 } 483 484 static int adxl355_set_calibbias(struct adxl355_data *data, 485 enum adxl355_chans chan, int calibbias) 486 { 487 int ret; 488 489 mutex_lock(&data->lock); 490 491 ret = adxl355_set_op_mode(data, ADXL355_STANDBY); 492 if (ret) 493 goto err_unlock; 494 495 put_unaligned_be16(calibbias, data->transf_buf); 496 ret = regmap_bulk_write(data->regmap, 497 adxl355_chans[chan].offset_reg, 498 data->transf_buf, 2); 499 if (ret) 500 goto err_set_opmode; 501 502 data->calibbias[chan] = calibbias; 503 504 ret = adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 505 if (ret) 506 goto err_set_opmode; 507 508 mutex_unlock(&data->lock); 509 return 0; 510 511 err_set_opmode: 512 adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 513 err_unlock: 514 mutex_unlock(&data->lock); 515 return ret; 516 } 517 518 static int adxl355_read_raw(struct iio_dev *indio_dev, 519 struct iio_chan_spec const *chan, 520 int *val, int *val2, long mask) 521 { 522 struct adxl355_data *data = iio_priv(indio_dev); 523 int ret; 524 525 switch (mask) { 526 case IIO_CHAN_INFO_RAW: 527 switch (chan->type) { 528 case IIO_TEMP: 529 ret = adxl355_get_temp_data(data, chan->address); 530 if (ret < 0) 531 return ret; 532 *val = get_unaligned_be16(data->transf_buf); 533 534 return IIO_VAL_INT; 535 case IIO_ACCEL: 536 ret = adxl355_read_axis(data, adxl355_chans[ 537 chan->address].data_reg); 538 if (ret < 0) 539 return ret; 540 *val = sign_extend32(ret >> chan->scan_type.shift, 541 chan->scan_type.realbits - 1); 542 return IIO_VAL_INT; 543 default: 544 return -EINVAL; 545 } 546 547 case IIO_CHAN_INFO_SCALE: 548 switch (chan->type) { 549 case IIO_TEMP: 550 /* 551 * Temperature scale is -110.497238. 552 * See the detailed explanation in adxl35x_chip_info 553 * definition above. 554 */ 555 *val = -110; 556 *val2 = 497238; 557 return IIO_VAL_INT_PLUS_MICRO; 558 case IIO_ACCEL: 559 *val = data->chip_info->accel_scale.integer; 560 *val2 = data->chip_info->accel_scale.decimal; 561 return IIO_VAL_INT_PLUS_NANO; 562 default: 563 return -EINVAL; 564 } 565 case IIO_CHAN_INFO_OFFSET: 566 *val = data->chip_info->temp_offset.integer; 567 *val2 = data->chip_info->temp_offset.decimal; 568 return IIO_VAL_INT_PLUS_MICRO; 569 case IIO_CHAN_INFO_CALIBBIAS: 570 *val = sign_extend32(data->calibbias[chan->address], 15); 571 return IIO_VAL_INT; 572 case IIO_CHAN_INFO_SAMP_FREQ: 573 *val = adxl355_odr_table[data->odr][0]; 574 *val2 = adxl355_odr_table[data->odr][1]; 575 return IIO_VAL_INT_PLUS_MICRO; 576 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 577 *val = data->adxl355_hpf_3db_table[data->hpf_3db][0]; 578 *val2 = data->adxl355_hpf_3db_table[data->hpf_3db][1]; 579 return IIO_VAL_INT_PLUS_MICRO; 580 default: 581 return -EINVAL; 582 } 583 } 584 585 static int adxl355_write_raw(struct iio_dev *indio_dev, 586 struct iio_chan_spec const *chan, 587 int val, int val2, long mask) 588 { 589 struct adxl355_data *data = iio_priv(indio_dev); 590 int odr_idx, hpf_idx, calibbias; 591 592 switch (mask) { 593 case IIO_CHAN_INFO_SAMP_FREQ: 594 odr_idx = adxl355_find_match(adxl355_odr_table, 595 ARRAY_SIZE(adxl355_odr_table), 596 val, val2); 597 if (odr_idx < 0) 598 return odr_idx; 599 600 return adxl355_set_odr(data, odr_idx); 601 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 602 hpf_idx = adxl355_find_match(data->adxl355_hpf_3db_table, 603 ARRAY_SIZE(data->adxl355_hpf_3db_table), 604 val, val2); 605 if (hpf_idx < 0) 606 return hpf_idx; 607 608 return adxl355_set_hpf_3db(data, hpf_idx); 609 case IIO_CHAN_INFO_CALIBBIAS: 610 calibbias = clamp_t(int, val, S16_MIN, S16_MAX); 611 612 return adxl355_set_calibbias(data, chan->address, calibbias); 613 default: 614 return -EINVAL; 615 } 616 } 617 618 static int adxl355_read_avail(struct iio_dev *indio_dev, 619 struct iio_chan_spec const *chan, 620 const int **vals, int *type, int *length, 621 long mask) 622 { 623 struct adxl355_data *data = iio_priv(indio_dev); 624 625 switch (mask) { 626 case IIO_CHAN_INFO_SAMP_FREQ: 627 *vals = (const int *)adxl355_odr_table; 628 *type = IIO_VAL_INT_PLUS_MICRO; 629 /* Values are stored in a 2D matrix */ 630 *length = ARRAY_SIZE(adxl355_odr_table) * 2; 631 632 return IIO_AVAIL_LIST; 633 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 634 *vals = (const int *)data->adxl355_hpf_3db_table; 635 *type = IIO_VAL_INT_PLUS_MICRO; 636 /* Values are stored in a 2D matrix */ 637 *length = ARRAY_SIZE(data->adxl355_hpf_3db_table) * 2; 638 639 return IIO_AVAIL_LIST; 640 default: 641 return -EINVAL; 642 } 643 } 644 645 static const unsigned long adxl355_avail_scan_masks[] = { 646 GENMASK(3, 0), 647 0 648 }; 649 650 static const struct iio_info adxl355_info = { 651 .read_raw = adxl355_read_raw, 652 .write_raw = adxl355_write_raw, 653 .read_avail = &adxl355_read_avail, 654 }; 655 656 static const struct iio_trigger_ops adxl355_trigger_ops = { 657 .set_trigger_state = &adxl355_data_rdy_trigger_set_state, 658 .validate_device = &iio_trigger_validate_own_device, 659 }; 660 661 static irqreturn_t adxl355_trigger_handler(int irq, void *p) 662 { 663 struct iio_poll_func *pf = p; 664 struct iio_dev *indio_dev = pf->indio_dev; 665 struct adxl355_data *data = iio_priv(indio_dev); 666 int ret; 667 668 mutex_lock(&data->lock); 669 670 /* 671 * data->buffer is used both for triggered buffer support 672 * and read/write_raw(), hence, it has to be zeroed here before usage. 673 */ 674 data->buffer.buf[0] = 0; 675 676 /* 677 * The acceleration data is 24 bits and big endian. It has to be saved 678 * in 32 bits, hence, it is saved in the 2nd byte of the 4 byte buffer. 679 * The buf array is 14 bytes as it includes 3x4=12 bytes for 680 * acceleration data of x, y, and z axis. It also includes 2 bytes for 681 * temperature data. 682 */ 683 ret = regmap_bulk_read(data->regmap, ADXL355_XDATA3_REG, 684 &data->buffer.buf[1], 3); 685 if (ret) 686 goto out_unlock_notify; 687 688 ret = regmap_bulk_read(data->regmap, ADXL355_YDATA3_REG, 689 &data->buffer.buf[5], 3); 690 if (ret) 691 goto out_unlock_notify; 692 693 ret = regmap_bulk_read(data->regmap, ADXL355_ZDATA3_REG, 694 &data->buffer.buf[9], 3); 695 if (ret) 696 goto out_unlock_notify; 697 698 ret = regmap_bulk_read(data->regmap, ADXL355_TEMP2_REG, 699 &data->buffer.buf[12], 2); 700 if (ret) 701 goto out_unlock_notify; 702 703 iio_push_to_buffers_with_ts(indio_dev, &data->buffer, 704 sizeof(data->buffer), pf->timestamp); 705 706 out_unlock_notify: 707 mutex_unlock(&data->lock); 708 iio_trigger_notify_done(indio_dev->trig); 709 710 return IRQ_HANDLED; 711 } 712 713 #define ADXL355_ACCEL_CHANNEL(index, reg, axis) { \ 714 .type = IIO_ACCEL, \ 715 .address = reg, \ 716 .modified = 1, \ 717 .channel2 = IIO_MOD_##axis, \ 718 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 719 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 720 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 721 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 722 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \ 723 .info_mask_shared_by_type_available = \ 724 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 725 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \ 726 .scan_index = index, \ 727 .scan_type = { \ 728 .sign = 's', \ 729 .realbits = 20, \ 730 .storagebits = 32, \ 731 .shift = 4, \ 732 .endianness = IIO_BE, \ 733 } \ 734 } 735 736 static const struct iio_chan_spec adxl355_channels[] = { 737 ADXL355_ACCEL_CHANNEL(0, chan_x, X), 738 ADXL355_ACCEL_CHANNEL(1, chan_y, Y), 739 ADXL355_ACCEL_CHANNEL(2, chan_z, Z), 740 { 741 .type = IIO_TEMP, 742 .address = ADXL355_TEMP2_REG, 743 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 744 BIT(IIO_CHAN_INFO_SCALE) | 745 BIT(IIO_CHAN_INFO_OFFSET), 746 .scan_index = 3, 747 .scan_type = { 748 .sign = 's', 749 .realbits = 12, 750 .storagebits = 16, 751 .endianness = IIO_BE, 752 }, 753 }, 754 IIO_CHAN_SOFT_TIMESTAMP(4), 755 }; 756 757 static int adxl355_probe_trigger(struct iio_dev *indio_dev, int irq) 758 { 759 struct adxl355_data *data = iio_priv(indio_dev); 760 int ret; 761 762 data->dready_trig = devm_iio_trigger_alloc(data->dev, "%s-dev%d", 763 indio_dev->name, 764 iio_device_id(indio_dev)); 765 if (!data->dready_trig) 766 return -ENOMEM; 767 768 data->dready_trig->ops = &adxl355_trigger_ops; 769 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 770 771 ret = devm_request_irq(data->dev, irq, 772 &iio_trigger_generic_data_rdy_poll, 773 IRQF_ONESHOT, "adxl355_irq", data->dready_trig); 774 if (ret) 775 return dev_err_probe(data->dev, ret, "request irq %d failed\n", 776 irq); 777 778 ret = devm_iio_trigger_register(data->dev, data->dready_trig); 779 if (ret) { 780 dev_err(data->dev, "iio trigger register failed\n"); 781 return ret; 782 } 783 784 indio_dev->trig = iio_trigger_get(data->dready_trig); 785 786 return 0; 787 } 788 789 int adxl355_core_probe(struct device *dev, struct regmap *regmap, 790 const struct adxl355_chip_info *chip_info) 791 { 792 struct adxl355_data *data; 793 struct iio_dev *indio_dev; 794 int ret; 795 int irq; 796 797 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 798 if (!indio_dev) 799 return -ENOMEM; 800 801 data = iio_priv(indio_dev); 802 data->regmap = regmap; 803 data->dev = dev; 804 data->op_mode = ADXL355_STANDBY; 805 data->chip_info = chip_info; 806 mutex_init(&data->lock); 807 808 indio_dev->name = chip_info->name; 809 indio_dev->info = &adxl355_info; 810 indio_dev->modes = INDIO_DIRECT_MODE; 811 indio_dev->channels = adxl355_channels; 812 indio_dev->num_channels = ARRAY_SIZE(adxl355_channels); 813 indio_dev->available_scan_masks = adxl355_avail_scan_masks; 814 815 ret = adxl355_setup(data); 816 if (ret) { 817 dev_err(dev, "ADXL355 setup failed\n"); 818 return ret; 819 } 820 821 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 822 &iio_pollfunc_store_time, 823 &adxl355_trigger_handler, NULL); 824 if (ret) { 825 dev_err(dev, "iio triggered buffer setup failed\n"); 826 return ret; 827 } 828 829 irq = fwnode_irq_get_byname(dev_fwnode(dev), "DRDY"); 830 if (irq > 0) { 831 ret = adxl355_probe_trigger(indio_dev, irq); 832 if (ret) 833 return ret; 834 } 835 836 return devm_iio_device_register(dev, indio_dev); 837 } 838 EXPORT_SYMBOL_NS_GPL(adxl355_core_probe, "IIO_ADXL355"); 839 840 MODULE_AUTHOR("Puranjay Mohan <puranjay12@gmail.com>"); 841 MODULE_DESCRIPTION("ADXL355 3-Axis Digital Accelerometer core driver"); 842 MODULE_LICENSE("GPL v2"); 843