1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADXL355 3-Axis Digital Accelerometer IIO core driver 4 * 5 * Copyright (c) 2021 Puranjay Mohan <puranjay12@gmail.com> 6 * 7 * Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/adxl354_adxl355.pdf 8 */ 9 10 #include <linux/bits.h> 11 #include <linux/bitfield.h> 12 #include <linux/iio/buffer.h> 13 #include <linux/iio/iio.h> 14 #include <linux/iio/trigger.h> 15 #include <linux/iio/triggered_buffer.h> 16 #include <linux/iio/trigger_consumer.h> 17 #include <linux/limits.h> 18 #include <linux/math64.h> 19 #include <linux/module.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/units.h> 23 24 #include <linux/unaligned.h> 25 26 #include "adxl355.h" 27 28 /* ADXL355 Register Definitions */ 29 #define ADXL355_DEVID_AD_REG 0x00 30 #define ADXL355_DEVID_MST_REG 0x01 31 #define ADXL355_PARTID_REG 0x02 32 #define ADXL355_STATUS_REG 0x04 33 #define ADXL355_FIFO_ENTRIES_REG 0x05 34 #define ADXL355_TEMP2_REG 0x06 35 #define ADXL355_XDATA3_REG 0x08 36 #define ADXL355_YDATA3_REG 0x0B 37 #define ADXL355_ZDATA3_REG 0x0E 38 #define ADXL355_FIFO_DATA_REG 0x11 39 #define ADXL355_OFFSET_X_H_REG 0x1E 40 #define ADXL355_OFFSET_Y_H_REG 0x20 41 #define ADXL355_OFFSET_Z_H_REG 0x22 42 #define ADXL355_ACT_EN_REG 0x24 43 #define ADXL355_ACT_THRESH_H_REG 0x25 44 #define ADXL355_ACT_THRESH_L_REG 0x26 45 #define ADXL355_ACT_COUNT_REG 0x27 46 #define ADXL355_FILTER_REG 0x28 47 #define ADXL355_FILTER_ODR_MSK GENMASK(3, 0) 48 #define ADXL355_FILTER_HPF_MSK GENMASK(6, 4) 49 #define ADXL355_FIFO_SAMPLES_REG 0x29 50 #define ADXL355_INT_MAP_REG 0x2A 51 #define ADXL355_SYNC_REG 0x2B 52 #define ADXL355_RANGE_REG 0x2C 53 #define ADXL355_POWER_CTL_REG 0x2D 54 #define ADXL355_POWER_CTL_MODE_MSK GENMASK(1, 0) 55 #define ADXL355_POWER_CTL_DRDY_MSK BIT(2) 56 #define ADXL355_SELF_TEST_REG 0x2E 57 #define ADXL355_RESET_REG 0x2F 58 #define ADXL355_BASE_ADDR_SHADOW_REG 0x50 59 #define ADXL355_SHADOW_REG_COUNT 5 60 61 #define ADXL355_DEVID_AD_VAL 0xAD 62 #define ADXL355_DEVID_MST_VAL 0x1D 63 #define ADXL355_PARTID_VAL 0xED 64 #define ADXL359_PARTID_VAL 0xE9 65 #define ADXL355_RESET_CODE 0x52 66 67 static const struct regmap_range adxl355_read_reg_range[] = { 68 regmap_reg_range(ADXL355_DEVID_AD_REG, ADXL355_FIFO_DATA_REG), 69 regmap_reg_range(ADXL355_OFFSET_X_H_REG, ADXL355_SELF_TEST_REG), 70 }; 71 72 const struct regmap_access_table adxl355_readable_regs_tbl = { 73 .yes_ranges = adxl355_read_reg_range, 74 .n_yes_ranges = ARRAY_SIZE(adxl355_read_reg_range), 75 }; 76 EXPORT_SYMBOL_NS_GPL(adxl355_readable_regs_tbl, "IIO_ADXL355"); 77 78 static const struct regmap_range adxl355_write_reg_range[] = { 79 regmap_reg_range(ADXL355_OFFSET_X_H_REG, ADXL355_RESET_REG), 80 }; 81 82 const struct regmap_access_table adxl355_writeable_regs_tbl = { 83 .yes_ranges = adxl355_write_reg_range, 84 .n_yes_ranges = ARRAY_SIZE(adxl355_write_reg_range), 85 }; 86 EXPORT_SYMBOL_NS_GPL(adxl355_writeable_regs_tbl, "IIO_ADXL355"); 87 88 const struct adxl355_chip_info adxl35x_chip_info[] = { 89 [ADXL355] = { 90 .name = "adxl355", 91 .part_id = ADXL355_PARTID_VAL, 92 /* 93 * At +/- 2g with 20-bit resolution, scale is given in datasheet 94 * as 3.9ug/LSB = 0.0000039 * 9.80665 = 0.00003824593 m/s^2. 95 */ 96 .accel_scale = { 97 .integer = 0, 98 .decimal = 38245, 99 }, 100 /* 101 * The datasheet defines an intercept of 1885 LSB at 25 degC 102 * and a slope of -9.05 LSB/C. The following formula can be used 103 * to find the temperature: 104 * Temp = ((RAW - 1885)/(-9.05)) + 25 but this doesn't follow 105 * the format of the IIO which is Temp = (RAW + OFFSET) * SCALE. 106 * Hence using some rearranging we get the scale as -110.497238 107 * and offset as -2111.25. 108 */ 109 .temp_offset = { 110 .integer = -2111, 111 .decimal = 250000, 112 }, 113 }, 114 [ADXL359] = { 115 .name = "adxl359", 116 .part_id = ADXL359_PARTID_VAL, 117 /* 118 * At +/- 10g with 20-bit resolution, scale is given in datasheet 119 * as 19.5ug/LSB = 0.0000195 * 9.80665 = 0.0.00019122967 m/s^2. 120 */ 121 .accel_scale = { 122 .integer = 0, 123 .decimal = 191229, 124 }, 125 /* 126 * The datasheet defines an intercept of 1852 LSB at 25 degC 127 * and a slope of -9.05 LSB/C. The following formula can be used 128 * to find the temperature: 129 * Temp = ((RAW - 1852)/(-9.05)) + 25 but this doesn't follow 130 * the format of the IIO which is Temp = (RAW + OFFSET) * SCALE. 131 * Hence using some rearranging we get the scale as -110.497238 132 * and offset as -2079.25. 133 */ 134 .temp_offset = { 135 .integer = -2079, 136 .decimal = 250000, 137 }, 138 }, 139 }; 140 EXPORT_SYMBOL_NS_GPL(adxl35x_chip_info, "IIO_ADXL355"); 141 142 enum adxl355_op_mode { 143 ADXL355_MEASUREMENT, 144 ADXL355_STANDBY, 145 ADXL355_TEMP_OFF, 146 }; 147 148 enum adxl355_odr { 149 ADXL355_ODR_4000HZ, 150 ADXL355_ODR_2000HZ, 151 ADXL355_ODR_1000HZ, 152 ADXL355_ODR_500HZ, 153 ADXL355_ODR_250HZ, 154 ADXL355_ODR_125HZ, 155 ADXL355_ODR_62_5HZ, 156 ADXL355_ODR_31_25HZ, 157 ADXL355_ODR_15_625HZ, 158 ADXL355_ODR_7_813HZ, 159 ADXL355_ODR_3_906HZ, 160 }; 161 162 enum adxl355_hpf_3db { 163 ADXL355_HPF_OFF, 164 ADXL355_HPF_24_7, 165 ADXL355_HPF_6_2084, 166 ADXL355_HPF_1_5545, 167 ADXL355_HPF_0_3862, 168 ADXL355_HPF_0_0954, 169 ADXL355_HPF_0_0238, 170 }; 171 172 static const int adxl355_odr_table[][2] = { 173 [0] = {4000, 0}, 174 [1] = {2000, 0}, 175 [2] = {1000, 0}, 176 [3] = {500, 0}, 177 [4] = {250, 0}, 178 [5] = {125, 0}, 179 [6] = {62, 500000}, 180 [7] = {31, 250000}, 181 [8] = {15, 625000}, 182 [9] = {7, 813000}, 183 [10] = {3, 906000}, 184 }; 185 186 static const int adxl355_hpf_3db_multipliers[] = { 187 0, 188 247000, 189 62084, 190 15545, 191 3862, 192 954, 193 238, 194 }; 195 196 enum adxl355_chans { 197 chan_x, chan_y, chan_z, 198 }; 199 200 struct adxl355_chan_info { 201 u8 data_reg; 202 u8 offset_reg; 203 }; 204 205 static const struct adxl355_chan_info adxl355_chans[] = { 206 [chan_x] = { 207 .data_reg = ADXL355_XDATA3_REG, 208 .offset_reg = ADXL355_OFFSET_X_H_REG 209 }, 210 [chan_y] = { 211 .data_reg = ADXL355_YDATA3_REG, 212 .offset_reg = ADXL355_OFFSET_Y_H_REG 213 }, 214 [chan_z] = { 215 .data_reg = ADXL355_ZDATA3_REG, 216 .offset_reg = ADXL355_OFFSET_Z_H_REG 217 }, 218 }; 219 220 struct adxl355_data { 221 const struct adxl355_chip_info *chip_info; 222 struct regmap *regmap; 223 struct device *dev; 224 struct mutex lock; /* lock to protect op_mode */ 225 enum adxl355_op_mode op_mode; 226 enum adxl355_odr odr; 227 enum adxl355_hpf_3db hpf_3db; 228 int calibbias[3]; 229 int adxl355_hpf_3db_table[7][2]; 230 struct iio_trigger *dready_trig; 231 union { 232 u8 transf_buf[3]; 233 struct { 234 u8 buf[14]; 235 aligned_s64 ts; 236 } buffer; 237 } __aligned(IIO_DMA_MINALIGN); 238 }; 239 240 static int adxl355_set_op_mode(struct adxl355_data *data, 241 enum adxl355_op_mode op_mode) 242 { 243 int ret; 244 245 if (data->op_mode == op_mode) 246 return 0; 247 248 ret = regmap_update_bits(data->regmap, ADXL355_POWER_CTL_REG, 249 ADXL355_POWER_CTL_MODE_MSK, op_mode); 250 if (ret) 251 return ret; 252 253 data->op_mode = op_mode; 254 255 return ret; 256 } 257 258 static int adxl355_data_rdy_trigger_set_state(struct iio_trigger *trig, 259 bool state) 260 { 261 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 262 struct adxl355_data *data = iio_priv(indio_dev); 263 int ret; 264 265 mutex_lock(&data->lock); 266 ret = regmap_update_bits(data->regmap, ADXL355_POWER_CTL_REG, 267 ADXL355_POWER_CTL_DRDY_MSK, 268 FIELD_PREP(ADXL355_POWER_CTL_DRDY_MSK, 269 state ? 0 : 1)); 270 mutex_unlock(&data->lock); 271 272 return ret; 273 } 274 275 static void adxl355_fill_3db_frequency_table(struct adxl355_data *data) 276 { 277 u32 multiplier; 278 u64 div, rem; 279 u64 odr; 280 int i; 281 282 odr = mul_u64_u32_shr(adxl355_odr_table[data->odr][0], MEGA, 0) + 283 adxl355_odr_table[data->odr][1]; 284 285 for (i = 0; i < ARRAY_SIZE(adxl355_hpf_3db_multipliers); i++) { 286 multiplier = adxl355_hpf_3db_multipliers[i]; 287 div = div64_u64_rem(mul_u64_u32_shr(odr, multiplier, 0), 288 TERA * 100, &rem); 289 290 data->adxl355_hpf_3db_table[i][0] = div; 291 data->adxl355_hpf_3db_table[i][1] = div_u64(rem, MEGA * 100); 292 } 293 } 294 295 static int adxl355_setup(struct adxl355_data *data) 296 { 297 unsigned int regval; 298 int retries = 5; /* the number is chosen based on empirical reasons */ 299 int ret; 300 u8 *shadow_regs __free(kfree) = kzalloc(ADXL355_SHADOW_REG_COUNT, GFP_KERNEL); 301 302 if (!shadow_regs) 303 return -ENOMEM; 304 305 ret = regmap_read(data->regmap, ADXL355_DEVID_AD_REG, ®val); 306 if (ret) 307 return ret; 308 309 if (regval != ADXL355_DEVID_AD_VAL) { 310 dev_err(data->dev, "Invalid ADI ID 0x%02x\n", regval); 311 return -ENODEV; 312 } 313 314 ret = regmap_read(data->regmap, ADXL355_DEVID_MST_REG, ®val); 315 if (ret) 316 return ret; 317 318 if (regval != ADXL355_DEVID_MST_VAL) { 319 dev_err(data->dev, "Invalid MEMS ID 0x%02x\n", regval); 320 return -ENODEV; 321 } 322 323 ret = regmap_read(data->regmap, ADXL355_PARTID_REG, ®val); 324 if (ret) 325 return ret; 326 327 if (regval != ADXL355_PARTID_VAL) 328 dev_warn(data->dev, "Invalid DEV ID 0x%02x\n", regval); 329 330 /* Read shadow registers to be compared after reset */ 331 ret = regmap_bulk_read(data->regmap, 332 ADXL355_BASE_ADDR_SHADOW_REG, 333 shadow_regs, ADXL355_SHADOW_REG_COUNT); 334 if (ret) 335 return ret; 336 337 do { 338 if (--retries == 0) 339 return dev_err_probe(data->dev, -EIO, "Shadow registers mismatch\n"); 340 341 /* 342 * Perform a software reset to make sure the device is in a consistent 343 * state after start-up. 344 */ 345 ret = regmap_write(data->regmap, ADXL355_RESET_REG, 346 ADXL355_RESET_CODE); 347 if (ret) 348 return ret; 349 350 /* Wait at least 5ms after software reset */ 351 fsleep(5 * USEC_PER_MSEC); 352 353 /* Read shadow registers for comparison */ 354 ret = regmap_bulk_read(data->regmap, 355 ADXL355_BASE_ADDR_SHADOW_REG, 356 data->buffer.buf, 357 ADXL355_SHADOW_REG_COUNT); 358 if (ret) 359 return ret; 360 } while (memcmp(shadow_regs, data->buffer.buf, 361 ADXL355_SHADOW_REG_COUNT)); 362 363 ret = regmap_update_bits(data->regmap, ADXL355_POWER_CTL_REG, 364 ADXL355_POWER_CTL_DRDY_MSK, 365 FIELD_PREP(ADXL355_POWER_CTL_DRDY_MSK, 1)); 366 if (ret) 367 return ret; 368 369 adxl355_fill_3db_frequency_table(data); 370 371 return adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 372 } 373 374 static int adxl355_get_temp_data(struct adxl355_data *data, u8 addr) 375 { 376 return regmap_bulk_read(data->regmap, addr, data->transf_buf, 2); 377 } 378 379 static int adxl355_read_axis(struct adxl355_data *data, u8 addr) 380 { 381 int ret; 382 383 ret = regmap_bulk_read(data->regmap, addr, data->transf_buf, 384 ARRAY_SIZE(data->transf_buf)); 385 if (ret) 386 return ret; 387 388 return get_unaligned_be24(data->transf_buf); 389 } 390 391 static int adxl355_find_match(const int (*freq_tbl)[2], const int n, 392 const int val, const int val2) 393 { 394 int i; 395 396 for (i = 0; i < n; i++) { 397 if (freq_tbl[i][0] == val && freq_tbl[i][1] == val2) 398 return i; 399 } 400 401 return -EINVAL; 402 } 403 404 static int adxl355_set_odr(struct adxl355_data *data, 405 enum adxl355_odr odr) 406 { 407 int ret; 408 409 mutex_lock(&data->lock); 410 411 if (data->odr == odr) { 412 mutex_unlock(&data->lock); 413 return 0; 414 } 415 416 ret = adxl355_set_op_mode(data, ADXL355_STANDBY); 417 if (ret) 418 goto err_unlock; 419 420 ret = regmap_update_bits(data->regmap, ADXL355_FILTER_REG, 421 ADXL355_FILTER_ODR_MSK, 422 FIELD_PREP(ADXL355_FILTER_ODR_MSK, odr)); 423 if (ret) 424 goto err_set_opmode; 425 426 data->odr = odr; 427 adxl355_fill_3db_frequency_table(data); 428 429 ret = adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 430 if (ret) 431 goto err_set_opmode; 432 433 mutex_unlock(&data->lock); 434 return 0; 435 436 err_set_opmode: 437 adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 438 err_unlock: 439 mutex_unlock(&data->lock); 440 return ret; 441 } 442 443 static int adxl355_set_hpf_3db(struct adxl355_data *data, 444 enum adxl355_hpf_3db hpf) 445 { 446 int ret; 447 448 mutex_lock(&data->lock); 449 450 if (data->hpf_3db == hpf) { 451 mutex_unlock(&data->lock); 452 return 0; 453 } 454 455 ret = adxl355_set_op_mode(data, ADXL355_STANDBY); 456 if (ret) 457 goto err_unlock; 458 459 ret = regmap_update_bits(data->regmap, ADXL355_FILTER_REG, 460 ADXL355_FILTER_HPF_MSK, 461 FIELD_PREP(ADXL355_FILTER_HPF_MSK, hpf)); 462 if (ret) 463 goto err_set_opmode; 464 465 data->hpf_3db = hpf; 466 467 ret = adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 468 if (ret) 469 goto err_set_opmode; 470 471 mutex_unlock(&data->lock); 472 return 0; 473 474 err_set_opmode: 475 adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 476 err_unlock: 477 mutex_unlock(&data->lock); 478 return ret; 479 } 480 481 static int adxl355_set_calibbias(struct adxl355_data *data, 482 enum adxl355_chans chan, int calibbias) 483 { 484 int ret; 485 486 mutex_lock(&data->lock); 487 488 ret = adxl355_set_op_mode(data, ADXL355_STANDBY); 489 if (ret) 490 goto err_unlock; 491 492 put_unaligned_be16(calibbias, data->transf_buf); 493 ret = regmap_bulk_write(data->regmap, 494 adxl355_chans[chan].offset_reg, 495 data->transf_buf, 2); 496 if (ret) 497 goto err_set_opmode; 498 499 data->calibbias[chan] = calibbias; 500 501 ret = adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 502 if (ret) 503 goto err_set_opmode; 504 505 mutex_unlock(&data->lock); 506 return 0; 507 508 err_set_opmode: 509 adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 510 err_unlock: 511 mutex_unlock(&data->lock); 512 return ret; 513 } 514 515 static int adxl355_read_raw(struct iio_dev *indio_dev, 516 struct iio_chan_spec const *chan, 517 int *val, int *val2, long mask) 518 { 519 struct adxl355_data *data = iio_priv(indio_dev); 520 int ret; 521 522 switch (mask) { 523 case IIO_CHAN_INFO_RAW: 524 switch (chan->type) { 525 case IIO_TEMP: 526 ret = adxl355_get_temp_data(data, chan->address); 527 if (ret < 0) 528 return ret; 529 *val = get_unaligned_be16(data->transf_buf); 530 531 return IIO_VAL_INT; 532 case IIO_ACCEL: 533 ret = adxl355_read_axis(data, adxl355_chans[ 534 chan->address].data_reg); 535 if (ret < 0) 536 return ret; 537 *val = sign_extend32(ret >> chan->scan_type.shift, 538 chan->scan_type.realbits - 1); 539 return IIO_VAL_INT; 540 default: 541 return -EINVAL; 542 } 543 544 case IIO_CHAN_INFO_SCALE: 545 switch (chan->type) { 546 case IIO_TEMP: 547 /* 548 * Temperature scale is -110.497238. 549 * See the detailed explanation in adxl35x_chip_info 550 * definition above. 551 */ 552 *val = -110; 553 *val2 = 497238; 554 return IIO_VAL_INT_PLUS_MICRO; 555 case IIO_ACCEL: 556 *val = data->chip_info->accel_scale.integer; 557 *val2 = data->chip_info->accel_scale.decimal; 558 return IIO_VAL_INT_PLUS_NANO; 559 default: 560 return -EINVAL; 561 } 562 case IIO_CHAN_INFO_OFFSET: 563 *val = data->chip_info->temp_offset.integer; 564 *val2 = data->chip_info->temp_offset.decimal; 565 return IIO_VAL_INT_PLUS_MICRO; 566 case IIO_CHAN_INFO_CALIBBIAS: 567 *val = sign_extend32(data->calibbias[chan->address], 15); 568 return IIO_VAL_INT; 569 case IIO_CHAN_INFO_SAMP_FREQ: 570 *val = adxl355_odr_table[data->odr][0]; 571 *val2 = adxl355_odr_table[data->odr][1]; 572 return IIO_VAL_INT_PLUS_MICRO; 573 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 574 *val = data->adxl355_hpf_3db_table[data->hpf_3db][0]; 575 *val2 = data->adxl355_hpf_3db_table[data->hpf_3db][1]; 576 return IIO_VAL_INT_PLUS_MICRO; 577 default: 578 return -EINVAL; 579 } 580 } 581 582 static int adxl355_write_raw(struct iio_dev *indio_dev, 583 struct iio_chan_spec const *chan, 584 int val, int val2, long mask) 585 { 586 struct adxl355_data *data = iio_priv(indio_dev); 587 int odr_idx, hpf_idx, calibbias; 588 589 switch (mask) { 590 case IIO_CHAN_INFO_SAMP_FREQ: 591 odr_idx = adxl355_find_match(adxl355_odr_table, 592 ARRAY_SIZE(adxl355_odr_table), 593 val, val2); 594 if (odr_idx < 0) 595 return odr_idx; 596 597 return adxl355_set_odr(data, odr_idx); 598 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 599 hpf_idx = adxl355_find_match(data->adxl355_hpf_3db_table, 600 ARRAY_SIZE(data->adxl355_hpf_3db_table), 601 val, val2); 602 if (hpf_idx < 0) 603 return hpf_idx; 604 605 return adxl355_set_hpf_3db(data, hpf_idx); 606 case IIO_CHAN_INFO_CALIBBIAS: 607 calibbias = clamp_t(int, val, S16_MIN, S16_MAX); 608 609 return adxl355_set_calibbias(data, chan->address, calibbias); 610 default: 611 return -EINVAL; 612 } 613 } 614 615 static int adxl355_read_avail(struct iio_dev *indio_dev, 616 struct iio_chan_spec const *chan, 617 const int **vals, int *type, int *length, 618 long mask) 619 { 620 struct adxl355_data *data = iio_priv(indio_dev); 621 622 switch (mask) { 623 case IIO_CHAN_INFO_SAMP_FREQ: 624 *vals = (const int *)adxl355_odr_table; 625 *type = IIO_VAL_INT_PLUS_MICRO; 626 /* Values are stored in a 2D matrix */ 627 *length = ARRAY_SIZE(adxl355_odr_table) * 2; 628 629 return IIO_AVAIL_LIST; 630 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 631 *vals = (const int *)data->adxl355_hpf_3db_table; 632 *type = IIO_VAL_INT_PLUS_MICRO; 633 /* Values are stored in a 2D matrix */ 634 *length = ARRAY_SIZE(data->adxl355_hpf_3db_table) * 2; 635 636 return IIO_AVAIL_LIST; 637 default: 638 return -EINVAL; 639 } 640 } 641 642 static const unsigned long adxl355_avail_scan_masks[] = { 643 GENMASK(3, 0), 644 0 645 }; 646 647 static const struct iio_info adxl355_info = { 648 .read_raw = adxl355_read_raw, 649 .write_raw = adxl355_write_raw, 650 .read_avail = &adxl355_read_avail, 651 }; 652 653 static const struct iio_trigger_ops adxl355_trigger_ops = { 654 .set_trigger_state = &adxl355_data_rdy_trigger_set_state, 655 .validate_device = &iio_trigger_validate_own_device, 656 }; 657 658 static irqreturn_t adxl355_trigger_handler(int irq, void *p) 659 { 660 struct iio_poll_func *pf = p; 661 struct iio_dev *indio_dev = pf->indio_dev; 662 struct adxl355_data *data = iio_priv(indio_dev); 663 int ret; 664 665 mutex_lock(&data->lock); 666 667 /* 668 * data->buffer is used both for triggered buffer support 669 * and read/write_raw(), hence, it has to be zeroed here before usage. 670 */ 671 data->buffer.buf[0] = 0; 672 673 /* 674 * The acceleration data is 24 bits and big endian. It has to be saved 675 * in 32 bits, hence, it is saved in the 2nd byte of the 4 byte buffer. 676 * The buf array is 14 bytes as it includes 3x4=12 bytes for 677 * acceleration data of x, y, and z axis. It also includes 2 bytes for 678 * temperature data. 679 */ 680 ret = regmap_bulk_read(data->regmap, ADXL355_XDATA3_REG, 681 &data->buffer.buf[1], 3); 682 if (ret) 683 goto out_unlock_notify; 684 685 ret = regmap_bulk_read(data->regmap, ADXL355_YDATA3_REG, 686 &data->buffer.buf[5], 3); 687 if (ret) 688 goto out_unlock_notify; 689 690 ret = regmap_bulk_read(data->regmap, ADXL355_ZDATA3_REG, 691 &data->buffer.buf[9], 3); 692 if (ret) 693 goto out_unlock_notify; 694 695 ret = regmap_bulk_read(data->regmap, ADXL355_TEMP2_REG, 696 &data->buffer.buf[12], 2); 697 if (ret) 698 goto out_unlock_notify; 699 700 iio_push_to_buffers_with_ts(indio_dev, &data->buffer, 701 sizeof(data->buffer), pf->timestamp); 702 703 out_unlock_notify: 704 mutex_unlock(&data->lock); 705 iio_trigger_notify_done(indio_dev->trig); 706 707 return IRQ_HANDLED; 708 } 709 710 #define ADXL355_ACCEL_CHANNEL(index, reg, axis) { \ 711 .type = IIO_ACCEL, \ 712 .address = reg, \ 713 .modified = 1, \ 714 .channel2 = IIO_MOD_##axis, \ 715 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 716 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 717 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 718 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 719 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \ 720 .info_mask_shared_by_type_available = \ 721 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 722 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \ 723 .scan_index = index, \ 724 .scan_type = { \ 725 .sign = 's', \ 726 .realbits = 20, \ 727 .storagebits = 32, \ 728 .shift = 4, \ 729 .endianness = IIO_BE, \ 730 } \ 731 } 732 733 static const struct iio_chan_spec adxl355_channels[] = { 734 ADXL355_ACCEL_CHANNEL(0, chan_x, X), 735 ADXL355_ACCEL_CHANNEL(1, chan_y, Y), 736 ADXL355_ACCEL_CHANNEL(2, chan_z, Z), 737 { 738 .type = IIO_TEMP, 739 .address = ADXL355_TEMP2_REG, 740 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 741 BIT(IIO_CHAN_INFO_SCALE) | 742 BIT(IIO_CHAN_INFO_OFFSET), 743 .scan_index = 3, 744 .scan_type = { 745 .sign = 'u', 746 .realbits = 12, 747 .storagebits = 16, 748 .endianness = IIO_BE, 749 }, 750 }, 751 IIO_CHAN_SOFT_TIMESTAMP(4), 752 }; 753 754 static int adxl355_probe_trigger(struct iio_dev *indio_dev, int irq) 755 { 756 struct adxl355_data *data = iio_priv(indio_dev); 757 int ret; 758 759 data->dready_trig = devm_iio_trigger_alloc(data->dev, "%s-dev%d", 760 indio_dev->name, 761 iio_device_id(indio_dev)); 762 if (!data->dready_trig) 763 return -ENOMEM; 764 765 data->dready_trig->ops = &adxl355_trigger_ops; 766 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 767 768 ret = devm_request_irq(data->dev, irq, &iio_trigger_generic_data_rdy_poll, 769 IRQF_NO_THREAD, "adxl355_irq", data->dready_trig); 770 if (ret) 771 return ret; 772 773 ret = devm_iio_trigger_register(data->dev, data->dready_trig); 774 if (ret) 775 return dev_err_probe(data->dev, ret, "iio trigger register failed\n"); 776 777 indio_dev->trig = iio_trigger_get(data->dready_trig); 778 779 return 0; 780 } 781 782 int adxl355_core_probe(struct device *dev, struct regmap *regmap, 783 const struct adxl355_chip_info *chip_info) 784 { 785 struct adxl355_data *data; 786 struct iio_dev *indio_dev; 787 int ret; 788 int irq; 789 790 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 791 if (!indio_dev) 792 return -ENOMEM; 793 794 data = iio_priv(indio_dev); 795 data->regmap = regmap; 796 data->dev = dev; 797 data->op_mode = ADXL355_STANDBY; 798 data->chip_info = chip_info; 799 ret = devm_mutex_init(dev, &data->lock); 800 if (ret) 801 return ret; 802 803 indio_dev->name = chip_info->name; 804 indio_dev->info = &adxl355_info; 805 indio_dev->modes = INDIO_DIRECT_MODE; 806 indio_dev->channels = adxl355_channels; 807 indio_dev->num_channels = ARRAY_SIZE(adxl355_channels); 808 indio_dev->available_scan_masks = adxl355_avail_scan_masks; 809 810 ret = adxl355_setup(data); 811 if (ret) 812 return dev_err_probe(dev, ret, "ADXL355 setup failed\n"); 813 814 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 815 &iio_pollfunc_store_time, 816 &adxl355_trigger_handler, NULL); 817 if (ret) 818 return dev_err_probe(dev, ret, "iio triggered buffer setup failed\n"); 819 820 irq = fwnode_irq_get_byname(dev_fwnode(dev), "DRDY"); 821 if (irq > 0) { 822 ret = adxl355_probe_trigger(indio_dev, irq); 823 if (ret) 824 return ret; 825 } 826 827 return devm_iio_device_register(dev, indio_dev); 828 } 829 EXPORT_SYMBOL_NS_GPL(adxl355_core_probe, "IIO_ADXL355"); 830 831 MODULE_AUTHOR("Puranjay Mohan <puranjay12@gmail.com>"); 832 MODULE_DESCRIPTION("ADXL355 3-Axis Digital Accelerometer core driver"); 833 MODULE_LICENSE("GPL v2"); 834