1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADXL345 3-Axis Digital Accelerometer IIO core driver 4 * 5 * Copyright (c) 2017 Eva Rachel Retuya <eraretuya@gmail.com> 6 * 7 * Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/ADXL345.pdf 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bitops.h> 12 #include <linux/interrupt.h> 13 #include <linux/module.h> 14 #include <linux/property.h> 15 #include <linux/regmap.h> 16 #include <linux/units.h> 17 18 #include <linux/iio/iio.h> 19 #include <linux/iio/sysfs.h> 20 #include <linux/iio/buffer.h> 21 #include <linux/iio/events.h> 22 #include <linux/iio/kfifo_buf.h> 23 24 #include "adxl345.h" 25 26 #define ADXL345_FIFO_BYPASS 0 27 #define ADXL345_FIFO_FIFO 1 28 #define ADXL345_FIFO_STREAM 2 29 30 #define ADXL345_DIRS 3 31 32 #define ADXL345_INT_NONE 0xff 33 #define ADXL345_INT1 0 34 #define ADXL345_INT2 1 35 36 #define ADXL345_REG_TAP_AXIS_MSK GENMASK(2, 0) 37 #define ADXL345_REG_TAP_SUPPRESS_MSK BIT(3) 38 #define ADXL345_REG_TAP_SUPPRESS BIT(3) 39 40 #define ADXL345_TAP_Z_EN BIT(0) 41 #define ADXL345_TAP_Y_EN BIT(1) 42 #define ADXL345_TAP_X_EN BIT(2) 43 44 /* single/double tap */ 45 enum adxl345_tap_type { 46 ADXL345_SINGLE_TAP, 47 ADXL345_DOUBLE_TAP, 48 }; 49 50 static const unsigned int adxl345_tap_int_reg[] = { 51 [ADXL345_SINGLE_TAP] = ADXL345_INT_SINGLE_TAP, 52 [ADXL345_DOUBLE_TAP] = ADXL345_INT_DOUBLE_TAP, 53 }; 54 55 enum adxl345_tap_time_type { 56 ADXL345_TAP_TIME_LATENT, 57 ADXL345_TAP_TIME_WINDOW, 58 ADXL345_TAP_TIME_DUR, 59 }; 60 61 static const unsigned int adxl345_tap_time_reg[] = { 62 [ADXL345_TAP_TIME_LATENT] = ADXL345_REG_LATENT, 63 [ADXL345_TAP_TIME_WINDOW] = ADXL345_REG_WINDOW, 64 [ADXL345_TAP_TIME_DUR] = ADXL345_REG_DUR, 65 }; 66 67 enum adxl345_odr { 68 ADXL345_ODR_0P10HZ = 0, 69 ADXL345_ODR_0P20HZ, 70 ADXL345_ODR_0P39HZ, 71 ADXL345_ODR_0P78HZ, 72 ADXL345_ODR_1P56HZ, 73 ADXL345_ODR_3P13HZ, 74 ADXL345_ODR_6P25HZ, 75 ADXL345_ODR_12P50HZ, 76 ADXL345_ODR_25HZ, 77 ADXL345_ODR_50HZ, 78 ADXL345_ODR_100HZ, 79 ADXL345_ODR_200HZ, 80 ADXL345_ODR_400HZ, 81 ADXL345_ODR_800HZ, 82 ADXL345_ODR_1600HZ, 83 ADXL345_ODR_3200HZ, 84 }; 85 86 enum adxl345_range { 87 ADXL345_2G_RANGE = 0, 88 ADXL345_4G_RANGE, 89 ADXL345_8G_RANGE, 90 ADXL345_16G_RANGE, 91 }; 92 93 /* Certain features recommend 12.5 Hz - 400 Hz ODR */ 94 static const int adxl345_odr_tbl[][2] = { 95 [ADXL345_ODR_0P10HZ] = { 0, 97000 }, 96 [ADXL345_ODR_0P20HZ] = { 0, 195000 }, 97 [ADXL345_ODR_0P39HZ] = { 0, 390000 }, 98 [ADXL345_ODR_0P78HZ] = { 0, 781000 }, 99 [ADXL345_ODR_1P56HZ] = { 1, 562000 }, 100 [ADXL345_ODR_3P13HZ] = { 3, 125000 }, 101 [ADXL345_ODR_6P25HZ] = { 6, 250000 }, 102 [ADXL345_ODR_12P50HZ] = { 12, 500000 }, 103 [ADXL345_ODR_25HZ] = { 25, 0 }, 104 [ADXL345_ODR_50HZ] = { 50, 0 }, 105 [ADXL345_ODR_100HZ] = { 100, 0 }, 106 [ADXL345_ODR_200HZ] = { 200, 0 }, 107 [ADXL345_ODR_400HZ] = { 400, 0 }, 108 [ADXL345_ODR_800HZ] = { 800, 0 }, 109 [ADXL345_ODR_1600HZ] = { 1600, 0 }, 110 [ADXL345_ODR_3200HZ] = { 3200, 0 }, 111 }; 112 113 /* 114 * Full resolution frequency table: 115 * (g * 2 * 9.80665) / (2^(resolution) - 1) 116 * 117 * resolution := 13 (full) 118 * g := 2|4|8|16 119 * 120 * 2g at 13bit: 0.004789 121 * 4g at 13bit: 0.009578 122 * 8g at 13bit: 0.019156 123 * 16g at 16bit: 0.038312 124 */ 125 static const int adxl345_fullres_range_tbl[][2] = { 126 [ADXL345_2G_RANGE] = { 0, 4789 }, 127 [ADXL345_4G_RANGE] = { 0, 9578 }, 128 [ADXL345_8G_RANGE] = { 0, 19156 }, 129 [ADXL345_16G_RANGE] = { 0, 38312 }, 130 }; 131 132 struct adxl345_state { 133 const struct adxl345_chip_info *info; 134 struct regmap *regmap; 135 bool fifo_delay; /* delay: delay is needed for SPI */ 136 u8 watermark; 137 u8 fifo_mode; 138 139 u32 tap_duration_us; 140 u32 tap_latent_us; 141 u32 tap_window_us; 142 143 __le16 fifo_buf[ADXL345_DIRS * ADXL345_FIFO_SIZE + 1] __aligned(IIO_DMA_MINALIGN); 144 }; 145 146 static const struct iio_event_spec adxl345_events[] = { 147 { 148 /* single tap */ 149 .type = IIO_EV_TYPE_GESTURE, 150 .dir = IIO_EV_DIR_SINGLETAP, 151 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 152 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 153 BIT(IIO_EV_INFO_TIMEOUT), 154 }, 155 { 156 /* double tap */ 157 .type = IIO_EV_TYPE_GESTURE, 158 .dir = IIO_EV_DIR_DOUBLETAP, 159 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) | 160 BIT(IIO_EV_INFO_RESET_TIMEOUT) | 161 BIT(IIO_EV_INFO_TAP2_MIN_DELAY), 162 }, 163 }; 164 165 #define ADXL345_CHANNEL(index, reg, axis) { \ 166 .type = IIO_ACCEL, \ 167 .modified = 1, \ 168 .channel2 = IIO_MOD_##axis, \ 169 .address = (reg), \ 170 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 171 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 172 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 173 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 174 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \ 175 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 176 .scan_index = (index), \ 177 .scan_type = { \ 178 .sign = 's', \ 179 .realbits = 13, \ 180 .storagebits = 16, \ 181 .endianness = IIO_LE, \ 182 }, \ 183 .event_spec = adxl345_events, \ 184 .num_event_specs = ARRAY_SIZE(adxl345_events), \ 185 } 186 187 enum adxl345_chans { 188 chan_x, chan_y, chan_z, 189 }; 190 191 static const struct iio_chan_spec adxl345_channels[] = { 192 ADXL345_CHANNEL(0, chan_x, X), 193 ADXL345_CHANNEL(1, chan_y, Y), 194 ADXL345_CHANNEL(2, chan_z, Z), 195 }; 196 197 static const unsigned long adxl345_scan_masks[] = { 198 BIT(chan_x) | BIT(chan_y) | BIT(chan_z), 199 0 200 }; 201 202 bool adxl345_is_volatile_reg(struct device *dev, unsigned int reg) 203 { 204 switch (reg) { 205 case ADXL345_REG_DATA_AXIS(0): 206 case ADXL345_REG_DATA_AXIS(1): 207 case ADXL345_REG_DATA_AXIS(2): 208 case ADXL345_REG_DATA_AXIS(3): 209 case ADXL345_REG_DATA_AXIS(4): 210 case ADXL345_REG_DATA_AXIS(5): 211 case ADXL345_REG_ACT_TAP_STATUS: 212 case ADXL345_REG_FIFO_STATUS: 213 case ADXL345_REG_INT_SOURCE: 214 return true; 215 default: 216 return false; 217 } 218 } 219 EXPORT_SYMBOL_NS_GPL(adxl345_is_volatile_reg, "IIO_ADXL345"); 220 221 /** 222 * adxl345_set_measure_en() - Enable and disable measuring. 223 * 224 * @st: The device data. 225 * @en: Enable measurements, else standby mode. 226 * 227 * For lowest power operation, standby mode can be used. In standby mode, 228 * current consumption is supposed to be reduced to 0.1uA (typical). In this 229 * mode no measurements are made. Placing the device into standby mode 230 * preserves the contents of FIFO. 231 * 232 * Return: Returns 0 if successful, or a negative error value. 233 */ 234 static int adxl345_set_measure_en(struct adxl345_state *st, bool en) 235 { 236 return regmap_assign_bits(st->regmap, ADXL345_REG_POWER_CTL, 237 ADXL345_POWER_CTL_MEASURE, en); 238 } 239 240 /* tap */ 241 242 static int _adxl345_set_tap_int(struct adxl345_state *st, 243 enum adxl345_tap_type type, bool state) 244 { 245 unsigned int int_map = 0x00; 246 unsigned int tap_threshold; 247 bool axis_valid; 248 bool singletap_args_valid = false; 249 bool doubletap_args_valid = false; 250 bool en = false; 251 u32 axis_ctrl; 252 int ret; 253 254 ret = regmap_read(st->regmap, ADXL345_REG_TAP_AXIS, &axis_ctrl); 255 if (ret) 256 return ret; 257 258 axis_valid = FIELD_GET(ADXL345_REG_TAP_AXIS_MSK, axis_ctrl) > 0; 259 260 ret = regmap_read(st->regmap, ADXL345_REG_THRESH_TAP, &tap_threshold); 261 if (ret) 262 return ret; 263 264 /* 265 * Note: A value of 0 for threshold and/or dur may result in undesirable 266 * behavior if single tap/double tap interrupts are enabled. 267 */ 268 singletap_args_valid = tap_threshold > 0 && st->tap_duration_us > 0; 269 270 if (type == ADXL345_SINGLE_TAP) { 271 en = axis_valid && singletap_args_valid; 272 } else { 273 /* doubletap: Window must be equal or greater than latent! */ 274 doubletap_args_valid = st->tap_latent_us > 0 && 275 st->tap_window_us > 0 && 276 st->tap_window_us >= st->tap_latent_us; 277 278 en = axis_valid && singletap_args_valid && doubletap_args_valid; 279 } 280 281 if (state && en) 282 int_map |= adxl345_tap_int_reg[type]; 283 284 return regmap_update_bits(st->regmap, ADXL345_REG_INT_ENABLE, 285 adxl345_tap_int_reg[type], int_map); 286 } 287 288 static int adxl345_is_tap_en(struct adxl345_state *st, 289 enum iio_modifier axis, 290 enum adxl345_tap_type type, bool *en) 291 { 292 unsigned int regval; 293 u32 axis_ctrl; 294 int ret; 295 296 ret = regmap_read(st->regmap, ADXL345_REG_TAP_AXIS, &axis_ctrl); 297 if (ret) 298 return ret; 299 300 /* Verify if axis is enabled for the tap detection. */ 301 switch (axis) { 302 case IIO_MOD_X: 303 *en = FIELD_GET(ADXL345_TAP_X_EN, axis_ctrl); 304 break; 305 case IIO_MOD_Y: 306 *en = FIELD_GET(ADXL345_TAP_Y_EN, axis_ctrl); 307 break; 308 case IIO_MOD_Z: 309 *en = FIELD_GET(ADXL345_TAP_Z_EN, axis_ctrl); 310 break; 311 default: 312 *en = false; 313 return -EINVAL; 314 } 315 316 if (*en) { 317 /* 318 * If axis allow for tap detection, verify if the interrupt is 319 * enabled for tap detection. 320 */ 321 ret = regmap_read(st->regmap, ADXL345_REG_INT_ENABLE, ®val); 322 if (ret) 323 return ret; 324 325 *en = adxl345_tap_int_reg[type] & regval; 326 } 327 328 return 0; 329 } 330 331 static int adxl345_set_singletap_en(struct adxl345_state *st, 332 enum iio_modifier axis, bool en) 333 { 334 int ret; 335 u32 axis_ctrl; 336 337 switch (axis) { 338 case IIO_MOD_X: 339 axis_ctrl = ADXL345_TAP_X_EN; 340 break; 341 case IIO_MOD_Y: 342 axis_ctrl = ADXL345_TAP_Y_EN; 343 break; 344 case IIO_MOD_Z: 345 axis_ctrl = ADXL345_TAP_Z_EN; 346 break; 347 default: 348 return -EINVAL; 349 } 350 351 if (en) 352 ret = regmap_set_bits(st->regmap, ADXL345_REG_TAP_AXIS, 353 axis_ctrl); 354 else 355 ret = regmap_clear_bits(st->regmap, ADXL345_REG_TAP_AXIS, 356 axis_ctrl); 357 if (ret) 358 return ret; 359 360 return _adxl345_set_tap_int(st, ADXL345_SINGLE_TAP, en); 361 } 362 363 static int adxl345_set_doubletap_en(struct adxl345_state *st, bool en) 364 { 365 int ret; 366 367 /* 368 * Generally suppress detection of spikes during the latency period as 369 * double taps here, this is fully optional for double tap detection 370 */ 371 ret = regmap_update_bits(st->regmap, ADXL345_REG_TAP_AXIS, 372 ADXL345_REG_TAP_SUPPRESS_MSK, 373 en ? ADXL345_REG_TAP_SUPPRESS : 0x00); 374 if (ret) 375 return ret; 376 377 return _adxl345_set_tap_int(st, ADXL345_DOUBLE_TAP, en); 378 } 379 380 static int _adxl345_set_tap_time(struct adxl345_state *st, 381 enum adxl345_tap_time_type type, u32 val_us) 382 { 383 unsigned int regval; 384 385 switch (type) { 386 case ADXL345_TAP_TIME_WINDOW: 387 st->tap_window_us = val_us; 388 break; 389 case ADXL345_TAP_TIME_LATENT: 390 st->tap_latent_us = val_us; 391 break; 392 case ADXL345_TAP_TIME_DUR: 393 st->tap_duration_us = val_us; 394 break; 395 } 396 397 /* 398 * The scale factor is 1250us / LSB for tap_window_us and tap_latent_us. 399 * For tap_duration_us the scale factor is 625us / LSB. 400 */ 401 if (type == ADXL345_TAP_TIME_DUR) 402 regval = DIV_ROUND_CLOSEST(val_us, 625); 403 else 404 regval = DIV_ROUND_CLOSEST(val_us, 1250); 405 406 return regmap_write(st->regmap, adxl345_tap_time_reg[type], regval); 407 } 408 409 static int adxl345_set_tap_duration(struct adxl345_state *st, u32 val_int, 410 u32 val_fract_us) 411 { 412 /* 413 * Max value is 255 * 625 us = 0.159375 seconds 414 * 415 * Note: the scaling is similar to the scaling in the ADXL380 416 */ 417 if (val_int || val_fract_us > 159375) 418 return -EINVAL; 419 420 return _adxl345_set_tap_time(st, ADXL345_TAP_TIME_DUR, val_fract_us); 421 } 422 423 static int adxl345_set_tap_window(struct adxl345_state *st, u32 val_int, 424 u32 val_fract_us) 425 { 426 /* 427 * Max value is 255 * 1250 us = 0.318750 seconds 428 * 429 * Note: the scaling is similar to the scaling in the ADXL380 430 */ 431 if (val_int || val_fract_us > 318750) 432 return -EINVAL; 433 434 return _adxl345_set_tap_time(st, ADXL345_TAP_TIME_WINDOW, val_fract_us); 435 } 436 437 static int adxl345_set_tap_latent(struct adxl345_state *st, u32 val_int, 438 u32 val_fract_us) 439 { 440 /* 441 * Max value is 255 * 1250 us = 0.318750 seconds 442 * 443 * Note: the scaling is similar to the scaling in the ADXL380 444 */ 445 if (val_int || val_fract_us > 318750) 446 return -EINVAL; 447 448 return _adxl345_set_tap_time(st, ADXL345_TAP_TIME_LATENT, val_fract_us); 449 } 450 451 static int adxl345_find_odr(struct adxl345_state *st, int val, 452 int val2, enum adxl345_odr *odr) 453 { 454 int i; 455 456 for (i = 0; i < ARRAY_SIZE(adxl345_odr_tbl); i++) { 457 if (val == adxl345_odr_tbl[i][0] && 458 val2 == adxl345_odr_tbl[i][1]) { 459 *odr = i; 460 return 0; 461 } 462 } 463 464 return -EINVAL; 465 } 466 467 static int adxl345_set_odr(struct adxl345_state *st, enum adxl345_odr odr) 468 { 469 return regmap_update_bits(st->regmap, ADXL345_REG_BW_RATE, 470 ADXL345_BW_RATE_MSK, 471 FIELD_PREP(ADXL345_BW_RATE_MSK, odr)); 472 } 473 474 static int adxl345_find_range(struct adxl345_state *st, int val, int val2, 475 enum adxl345_range *range) 476 { 477 int i; 478 479 for (i = 0; i < ARRAY_SIZE(adxl345_fullres_range_tbl); i++) { 480 if (val == adxl345_fullres_range_tbl[i][0] && 481 val2 == adxl345_fullres_range_tbl[i][1]) { 482 *range = i; 483 return 0; 484 } 485 } 486 487 return -EINVAL; 488 } 489 490 static int adxl345_set_range(struct adxl345_state *st, enum adxl345_range range) 491 { 492 return regmap_update_bits(st->regmap, ADXL345_REG_DATA_FORMAT, 493 ADXL345_DATA_FORMAT_RANGE, 494 FIELD_PREP(ADXL345_DATA_FORMAT_RANGE, range)); 495 } 496 497 static int adxl345_read_avail(struct iio_dev *indio_dev, 498 struct iio_chan_spec const *chan, 499 const int **vals, int *type, 500 int *length, long mask) 501 { 502 switch (mask) { 503 case IIO_CHAN_INFO_SCALE: 504 *vals = (int *)adxl345_fullres_range_tbl; 505 *type = IIO_VAL_INT_PLUS_MICRO; 506 *length = ARRAY_SIZE(adxl345_fullres_range_tbl) * 2; 507 return IIO_AVAIL_LIST; 508 case IIO_CHAN_INFO_SAMP_FREQ: 509 *vals = (int *)adxl345_odr_tbl; 510 *type = IIO_VAL_INT_PLUS_MICRO; 511 *length = ARRAY_SIZE(adxl345_odr_tbl) * 2; 512 return IIO_AVAIL_LIST; 513 } 514 515 return -EINVAL; 516 } 517 518 static int adxl345_read_raw(struct iio_dev *indio_dev, 519 struct iio_chan_spec const *chan, 520 int *val, int *val2, long mask) 521 { 522 struct adxl345_state *st = iio_priv(indio_dev); 523 __le16 accel; 524 unsigned int regval; 525 enum adxl345_odr odr; 526 enum adxl345_range range; 527 int ret; 528 529 switch (mask) { 530 case IIO_CHAN_INFO_RAW: 531 /* 532 * Data is stored in adjacent registers: 533 * ADXL345_REG_DATA(X0/Y0/Z0) contain the least significant byte 534 * and ADXL345_REG_DATA(X0/Y0/Z0) + 1 the most significant byte 535 */ 536 ret = regmap_bulk_read(st->regmap, 537 ADXL345_REG_DATA_AXIS(chan->address), 538 &accel, sizeof(accel)); 539 if (ret) 540 return ret; 541 542 *val = sign_extend32(le16_to_cpu(accel), 12); 543 return IIO_VAL_INT; 544 case IIO_CHAN_INFO_SCALE: 545 ret = regmap_read(st->regmap, ADXL345_REG_DATA_FORMAT, ®val); 546 if (ret) 547 return ret; 548 range = FIELD_GET(ADXL345_DATA_FORMAT_RANGE, regval); 549 *val = adxl345_fullres_range_tbl[range][0]; 550 *val2 = adxl345_fullres_range_tbl[range][1]; 551 return IIO_VAL_INT_PLUS_MICRO; 552 case IIO_CHAN_INFO_CALIBBIAS: 553 ret = regmap_read(st->regmap, 554 ADXL345_REG_OFS_AXIS(chan->address), ®val); 555 if (ret) 556 return ret; 557 /* 558 * 8-bit resolution at +/- 2g, that is 4x accel data scale 559 * factor 560 */ 561 *val = sign_extend32(regval, 7) * 4; 562 563 return IIO_VAL_INT; 564 case IIO_CHAN_INFO_SAMP_FREQ: 565 ret = regmap_read(st->regmap, ADXL345_REG_BW_RATE, ®val); 566 if (ret) 567 return ret; 568 odr = FIELD_GET(ADXL345_BW_RATE_MSK, regval); 569 *val = adxl345_odr_tbl[odr][0]; 570 *val2 = adxl345_odr_tbl[odr][1]; 571 return IIO_VAL_INT_PLUS_MICRO; 572 } 573 574 return -EINVAL; 575 } 576 577 static int adxl345_write_raw(struct iio_dev *indio_dev, 578 struct iio_chan_spec const *chan, 579 int val, int val2, long mask) 580 { 581 struct adxl345_state *st = iio_priv(indio_dev); 582 enum adxl345_range range; 583 enum adxl345_odr odr; 584 int ret; 585 586 ret = adxl345_set_measure_en(st, false); 587 if (ret) 588 return ret; 589 590 switch (mask) { 591 case IIO_CHAN_INFO_CALIBBIAS: 592 /* 593 * 8-bit resolution at +/- 2g, that is 4x accel data scale 594 * factor 595 */ 596 ret = regmap_write(st->regmap, 597 ADXL345_REG_OFS_AXIS(chan->address), 598 val / 4); 599 if (ret) 600 return ret; 601 break; 602 case IIO_CHAN_INFO_SAMP_FREQ: 603 ret = adxl345_find_odr(st, val, val2, &odr); 604 if (ret) 605 return ret; 606 607 ret = adxl345_set_odr(st, odr); 608 if (ret) 609 return ret; 610 break; 611 case IIO_CHAN_INFO_SCALE: 612 ret = adxl345_find_range(st, val, val2, &range); 613 if (ret) 614 return ret; 615 616 ret = adxl345_set_range(st, range); 617 if (ret) 618 return ret; 619 break; 620 default: 621 return -EINVAL; 622 } 623 624 return adxl345_set_measure_en(st, true); 625 } 626 627 static int adxl345_read_event_config(struct iio_dev *indio_dev, 628 const struct iio_chan_spec *chan, 629 enum iio_event_type type, 630 enum iio_event_direction dir) 631 { 632 struct adxl345_state *st = iio_priv(indio_dev); 633 bool int_en; 634 int ret; 635 636 switch (type) { 637 case IIO_EV_TYPE_GESTURE: 638 switch (dir) { 639 case IIO_EV_DIR_SINGLETAP: 640 ret = adxl345_is_tap_en(st, chan->channel2, 641 ADXL345_SINGLE_TAP, &int_en); 642 if (ret) 643 return ret; 644 return int_en; 645 case IIO_EV_DIR_DOUBLETAP: 646 ret = adxl345_is_tap_en(st, chan->channel2, 647 ADXL345_DOUBLE_TAP, &int_en); 648 if (ret) 649 return ret; 650 return int_en; 651 default: 652 return -EINVAL; 653 } 654 default: 655 return -EINVAL; 656 } 657 } 658 659 static int adxl345_write_event_config(struct iio_dev *indio_dev, 660 const struct iio_chan_spec *chan, 661 enum iio_event_type type, 662 enum iio_event_direction dir, 663 bool state) 664 { 665 struct adxl345_state *st = iio_priv(indio_dev); 666 667 switch (type) { 668 case IIO_EV_TYPE_GESTURE: 669 switch (dir) { 670 case IIO_EV_DIR_SINGLETAP: 671 return adxl345_set_singletap_en(st, chan->channel2, state); 672 case IIO_EV_DIR_DOUBLETAP: 673 return adxl345_set_doubletap_en(st, state); 674 default: 675 return -EINVAL; 676 } 677 default: 678 return -EINVAL; 679 } 680 } 681 682 static int adxl345_read_event_value(struct iio_dev *indio_dev, 683 const struct iio_chan_spec *chan, 684 enum iio_event_type type, 685 enum iio_event_direction dir, 686 enum iio_event_info info, 687 int *val, int *val2) 688 { 689 struct adxl345_state *st = iio_priv(indio_dev); 690 unsigned int tap_threshold; 691 int ret; 692 693 switch (type) { 694 case IIO_EV_TYPE_GESTURE: 695 switch (info) { 696 case IIO_EV_INFO_VALUE: 697 /* 698 * The scale factor would be 62.5mg/LSB (i.e. 0xFF = 16g) but 699 * not applied here. In context of this general purpose sensor, 700 * what imports is rather signal intensity than the absolute 701 * measured g value. 702 */ 703 ret = regmap_read(st->regmap, ADXL345_REG_THRESH_TAP, 704 &tap_threshold); 705 if (ret) 706 return ret; 707 *val = sign_extend32(tap_threshold, 7); 708 return IIO_VAL_INT; 709 case IIO_EV_INFO_TIMEOUT: 710 *val = st->tap_duration_us; 711 *val2 = MICRO; 712 return IIO_VAL_FRACTIONAL; 713 case IIO_EV_INFO_RESET_TIMEOUT: 714 *val = st->tap_window_us; 715 *val2 = MICRO; 716 return IIO_VAL_FRACTIONAL; 717 case IIO_EV_INFO_TAP2_MIN_DELAY: 718 *val = st->tap_latent_us; 719 *val2 = MICRO; 720 return IIO_VAL_FRACTIONAL; 721 default: 722 return -EINVAL; 723 } 724 default: 725 return -EINVAL; 726 } 727 } 728 729 static int adxl345_write_event_value(struct iio_dev *indio_dev, 730 const struct iio_chan_spec *chan, 731 enum iio_event_type type, 732 enum iio_event_direction dir, 733 enum iio_event_info info, 734 int val, int val2) 735 { 736 struct adxl345_state *st = iio_priv(indio_dev); 737 int ret; 738 739 ret = adxl345_set_measure_en(st, false); 740 if (ret) 741 return ret; 742 743 switch (type) { 744 case IIO_EV_TYPE_GESTURE: 745 switch (info) { 746 case IIO_EV_INFO_VALUE: 747 ret = regmap_write(st->regmap, ADXL345_REG_THRESH_TAP, 748 min(val, 0xFF)); 749 if (ret) 750 return ret; 751 break; 752 case IIO_EV_INFO_TIMEOUT: 753 ret = adxl345_set_tap_duration(st, val, val2); 754 if (ret) 755 return ret; 756 break; 757 case IIO_EV_INFO_RESET_TIMEOUT: 758 ret = adxl345_set_tap_window(st, val, val2); 759 if (ret) 760 return ret; 761 break; 762 case IIO_EV_INFO_TAP2_MIN_DELAY: 763 ret = adxl345_set_tap_latent(st, val, val2); 764 if (ret) 765 return ret; 766 break; 767 default: 768 return -EINVAL; 769 } 770 break; 771 default: 772 return -EINVAL; 773 } 774 775 return adxl345_set_measure_en(st, true); 776 } 777 778 static int adxl345_reg_access(struct iio_dev *indio_dev, unsigned int reg, 779 unsigned int writeval, unsigned int *readval) 780 { 781 struct adxl345_state *st = iio_priv(indio_dev); 782 783 if (readval) 784 return regmap_read(st->regmap, reg, readval); 785 return regmap_write(st->regmap, reg, writeval); 786 } 787 788 static int adxl345_set_watermark(struct iio_dev *indio_dev, unsigned int value) 789 { 790 struct adxl345_state *st = iio_priv(indio_dev); 791 const unsigned int fifo_mask = 0x1F, watermark_mask = 0x02; 792 int ret; 793 794 value = min(value, ADXL345_FIFO_SIZE - 1); 795 796 ret = regmap_update_bits(st->regmap, ADXL345_REG_FIFO_CTL, fifo_mask, value); 797 if (ret) 798 return ret; 799 800 st->watermark = value; 801 return regmap_update_bits(st->regmap, ADXL345_REG_INT_ENABLE, 802 watermark_mask, ADXL345_INT_WATERMARK); 803 } 804 805 static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev, 806 struct iio_chan_spec const *chan, 807 long mask) 808 { 809 switch (mask) { 810 case IIO_CHAN_INFO_CALIBBIAS: 811 return IIO_VAL_INT; 812 case IIO_CHAN_INFO_SCALE: 813 return IIO_VAL_INT_PLUS_MICRO; 814 case IIO_CHAN_INFO_SAMP_FREQ: 815 return IIO_VAL_INT_PLUS_MICRO; 816 default: 817 return -EINVAL; 818 } 819 } 820 821 static void adxl345_powerdown(void *ptr) 822 { 823 struct adxl345_state *st = ptr; 824 825 adxl345_set_measure_en(st, false); 826 } 827 828 static int adxl345_set_fifo(struct adxl345_state *st) 829 { 830 unsigned int intio; 831 int ret; 832 833 /* FIFO should only be configured while in standby mode */ 834 ret = adxl345_set_measure_en(st, false); 835 if (ret) 836 return ret; 837 838 ret = regmap_read(st->regmap, ADXL345_REG_INT_MAP, &intio); 839 if (ret) 840 return ret; 841 842 ret = regmap_write(st->regmap, ADXL345_REG_FIFO_CTL, 843 FIELD_PREP(ADXL345_FIFO_CTL_SAMPLES_MSK, 844 st->watermark) | 845 FIELD_PREP(ADXL345_FIFO_CTL_TRIGGER_MSK, intio) | 846 FIELD_PREP(ADXL345_FIFO_CTL_MODE_MSK, 847 st->fifo_mode)); 848 if (ret) 849 return ret; 850 851 return adxl345_set_measure_en(st, true); 852 } 853 854 /** 855 * adxl345_get_samples() - Read number of FIFO entries. 856 * @st: The initialized state instance of this driver. 857 * 858 * The sensor does not support treating any axis individually, or exclude them 859 * from measuring. 860 * 861 * Return: negative error, or value. 862 */ 863 static int adxl345_get_samples(struct adxl345_state *st) 864 { 865 unsigned int regval = 0; 866 int ret; 867 868 ret = regmap_read(st->regmap, ADXL345_REG_FIFO_STATUS, ®val); 869 if (ret) 870 return ret; 871 872 return FIELD_GET(ADXL345_REG_FIFO_STATUS_MSK, regval); 873 } 874 875 /** 876 * adxl345_fifo_transfer() - Read samples number of elements. 877 * @st: The instance of the state object of this sensor. 878 * @samples: The number of lines in the FIFO referred to as fifo_entry. 879 * 880 * It is recommended that a multiple-byte read of all registers be performed to 881 * prevent a change in data between reads of sequential registers. That is to 882 * read out the data registers X0, X1, Y0, Y1, Z0, Z1, i.e. 6 bytes at once. 883 * 884 * Return: 0 or error value. 885 */ 886 static int adxl345_fifo_transfer(struct adxl345_state *st, int samples) 887 { 888 int i, ret = 0; 889 890 for (i = 0; i < samples; i++) { 891 ret = regmap_bulk_read(st->regmap, ADXL345_REG_XYZ_BASE, 892 st->fifo_buf + (i * ADXL345_DIRS), 893 sizeof(st->fifo_buf[0]) * ADXL345_DIRS); 894 if (ret) 895 return ret; 896 897 /* 898 * To ensure that the FIFO has completely popped, there must be at least 5 899 * us between the end of reading the data registers, signified by the 900 * transition to register 0x38 from 0x37 or the CS pin going high, and the 901 * start of new reads of the FIFO or reading the FIFO_STATUS register. For 902 * SPI operation at 1.5 MHz or lower, the register addressing portion of the 903 * transmission is sufficient delay to ensure the FIFO has completely 904 * popped. It is necessary for SPI operation greater than 1.5 MHz to 905 * de-assert the CS pin to ensure a total of 5 us, which is at most 3.4 us 906 * at 5 MHz operation. 907 */ 908 if (st->fifo_delay && samples > 1) 909 udelay(3); 910 } 911 return ret; 912 } 913 914 /** 915 * adxl345_fifo_reset() - Empty the FIFO in error condition. 916 * @st: The instance to the state object of the sensor. 917 * 918 * Read all elements of the FIFO. Reading the interrupt source register 919 * resets the sensor. 920 */ 921 static void adxl345_fifo_reset(struct adxl345_state *st) 922 { 923 int regval; 924 int samples; 925 926 adxl345_set_measure_en(st, false); 927 928 samples = adxl345_get_samples(st); 929 if (samples > 0) 930 adxl345_fifo_transfer(st, samples); 931 932 regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, ®val); 933 934 adxl345_set_measure_en(st, true); 935 } 936 937 static int adxl345_buffer_postenable(struct iio_dev *indio_dev) 938 { 939 struct adxl345_state *st = iio_priv(indio_dev); 940 941 st->fifo_mode = ADXL345_FIFO_STREAM; 942 return adxl345_set_fifo(st); 943 } 944 945 static int adxl345_buffer_predisable(struct iio_dev *indio_dev) 946 { 947 struct adxl345_state *st = iio_priv(indio_dev); 948 int ret; 949 950 st->fifo_mode = ADXL345_FIFO_BYPASS; 951 ret = adxl345_set_fifo(st); 952 if (ret) 953 return ret; 954 955 return regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, 0x00); 956 } 957 958 static const struct iio_buffer_setup_ops adxl345_buffer_ops = { 959 .postenable = adxl345_buffer_postenable, 960 .predisable = adxl345_buffer_predisable, 961 }; 962 963 static int adxl345_fifo_push(struct iio_dev *indio_dev, 964 int samples) 965 { 966 struct adxl345_state *st = iio_priv(indio_dev); 967 int i, ret; 968 969 if (samples <= 0) 970 return -EINVAL; 971 972 ret = adxl345_fifo_transfer(st, samples); 973 if (ret) 974 return ret; 975 976 for (i = 0; i < ADXL345_DIRS * samples; i += ADXL345_DIRS) 977 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]); 978 979 return 0; 980 } 981 982 static int adxl345_push_event(struct iio_dev *indio_dev, int int_stat, 983 enum iio_modifier tap_dir) 984 { 985 s64 ts = iio_get_time_ns(indio_dev); 986 struct adxl345_state *st = iio_priv(indio_dev); 987 int samples; 988 int ret = -ENOENT; 989 990 if (FIELD_GET(ADXL345_INT_SINGLE_TAP, int_stat)) { 991 ret = iio_push_event(indio_dev, 992 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, tap_dir, 993 IIO_EV_TYPE_GESTURE, 994 IIO_EV_DIR_SINGLETAP), 995 ts); 996 if (ret) 997 return ret; 998 } 999 1000 if (FIELD_GET(ADXL345_INT_DOUBLE_TAP, int_stat)) { 1001 ret = iio_push_event(indio_dev, 1002 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, tap_dir, 1003 IIO_EV_TYPE_GESTURE, 1004 IIO_EV_DIR_DOUBLETAP), 1005 ts); 1006 if (ret) 1007 return ret; 1008 } 1009 1010 if (FIELD_GET(ADXL345_INT_WATERMARK, int_stat)) { 1011 samples = adxl345_get_samples(st); 1012 if (samples < 0) 1013 return -EINVAL; 1014 1015 if (adxl345_fifo_push(indio_dev, samples) < 0) 1016 return -EINVAL; 1017 1018 ret = 0; 1019 } 1020 1021 return ret; 1022 } 1023 1024 /** 1025 * adxl345_irq_handler() - Handle irqs of the ADXL345. 1026 * @irq: The irq being handled. 1027 * @p: The struct iio_device pointer for the device. 1028 * 1029 * Return: The interrupt was handled. 1030 */ 1031 static irqreturn_t adxl345_irq_handler(int irq, void *p) 1032 { 1033 struct iio_dev *indio_dev = p; 1034 struct adxl345_state *st = iio_priv(indio_dev); 1035 unsigned int regval; 1036 enum iio_modifier tap_dir = IIO_NO_MOD; 1037 u32 axis_ctrl; 1038 int int_stat; 1039 int ret; 1040 1041 ret = regmap_read(st->regmap, ADXL345_REG_TAP_AXIS, &axis_ctrl); 1042 if (ret) 1043 return IRQ_NONE; 1044 1045 if (FIELD_GET(ADXL345_REG_TAP_AXIS_MSK, axis_ctrl)) { 1046 ret = regmap_read(st->regmap, ADXL345_REG_ACT_TAP_STATUS, ®val); 1047 if (ret) 1048 return IRQ_NONE; 1049 1050 if (FIELD_GET(ADXL345_TAP_Z_EN, regval)) 1051 tap_dir = IIO_MOD_Z; 1052 else if (FIELD_GET(ADXL345_TAP_Y_EN, regval)) 1053 tap_dir = IIO_MOD_Y; 1054 else if (FIELD_GET(ADXL345_TAP_X_EN, regval)) 1055 tap_dir = IIO_MOD_X; 1056 } 1057 1058 if (regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, &int_stat)) 1059 return IRQ_NONE; 1060 1061 if (adxl345_push_event(indio_dev, int_stat, tap_dir)) 1062 goto err; 1063 1064 if (FIELD_GET(ADXL345_INT_OVERRUN, int_stat)) 1065 goto err; 1066 1067 return IRQ_HANDLED; 1068 1069 err: 1070 adxl345_fifo_reset(st); 1071 1072 return IRQ_HANDLED; 1073 } 1074 1075 static const struct iio_info adxl345_info = { 1076 .read_raw = adxl345_read_raw, 1077 .write_raw = adxl345_write_raw, 1078 .read_avail = adxl345_read_avail, 1079 .write_raw_get_fmt = adxl345_write_raw_get_fmt, 1080 .read_event_config = adxl345_read_event_config, 1081 .write_event_config = adxl345_write_event_config, 1082 .read_event_value = adxl345_read_event_value, 1083 .write_event_value = adxl345_write_event_value, 1084 .debugfs_reg_access = &adxl345_reg_access, 1085 .hwfifo_set_watermark = adxl345_set_watermark, 1086 }; 1087 1088 static int adxl345_get_int_line(struct device *dev, int *irq) 1089 { 1090 *irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT1"); 1091 if (*irq > 0) 1092 return ADXL345_INT1; 1093 1094 *irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT2"); 1095 if (*irq > 0) 1096 return ADXL345_INT2; 1097 1098 return ADXL345_INT_NONE; 1099 } 1100 1101 /** 1102 * adxl345_core_probe() - Probe and setup for the accelerometer. 1103 * @dev: Driver model representation of the device 1104 * @regmap: Regmap instance for the device 1105 * @fifo_delay_default: Using FIFO with SPI needs delay 1106 * @setup: Setup routine to be executed right before the standard device 1107 * setup 1108 * 1109 * For SPI operation greater than 1.6 MHz, it is necessary to deassert the CS 1110 * pin to ensure a total delay of 5 us; otherwise, the delay is not sufficient. 1111 * The total delay necessary for 5 MHz operation is at most 3.4 us. This is not 1112 * a concern when using I2C mode because the communication rate is low enough 1113 * to ensure a sufficient delay between FIFO reads. 1114 * Ref: "Retrieving Data from FIFO", p. 21 of 36, Data Sheet ADXL345 Rev. G 1115 * 1116 * Return: 0 on success, negative errno on error 1117 */ 1118 int adxl345_core_probe(struct device *dev, struct regmap *regmap, 1119 bool fifo_delay_default, 1120 int (*setup)(struct device*, struct regmap*)) 1121 { 1122 struct adxl345_state *st; 1123 struct iio_dev *indio_dev; 1124 u32 regval; 1125 u8 intio = ADXL345_INT1; 1126 unsigned int data_format_mask = (ADXL345_DATA_FORMAT_RANGE | 1127 ADXL345_DATA_FORMAT_JUSTIFY | 1128 ADXL345_DATA_FORMAT_FULL_RES | 1129 ADXL345_DATA_FORMAT_SELF_TEST); 1130 unsigned int tap_threshold; 1131 int irq; 1132 int ret; 1133 1134 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1135 if (!indio_dev) 1136 return -ENOMEM; 1137 1138 st = iio_priv(indio_dev); 1139 st->regmap = regmap; 1140 st->info = device_get_match_data(dev); 1141 if (!st->info) 1142 return -ENODEV; 1143 st->fifo_delay = fifo_delay_default; 1144 1145 /* Init with reasonable values */ 1146 tap_threshold = 48; /* 48 [0x30] -> ~3g */ 1147 st->tap_duration_us = 16; /* 16 [0x10] -> .010 */ 1148 st->tap_window_us = 64; /* 64 [0x40] -> .080 */ 1149 st->tap_latent_us = 16; /* 16 [0x10] -> .020 */ 1150 1151 indio_dev->name = st->info->name; 1152 indio_dev->info = &adxl345_info; 1153 indio_dev->modes = INDIO_DIRECT_MODE; 1154 indio_dev->channels = adxl345_channels; 1155 indio_dev->num_channels = ARRAY_SIZE(adxl345_channels); 1156 indio_dev->available_scan_masks = adxl345_scan_masks; 1157 1158 /* 1159 * Using I2C at 100kHz would limit the maximum ODR to 200Hz, operation 1160 * at an output rate above the recommended maximum may result in 1161 * undesired behavior. 1162 */ 1163 ret = adxl345_set_odr(st, ADXL345_ODR_200HZ); 1164 if (ret) 1165 return ret; 1166 1167 ret = adxl345_set_range(st, ADXL345_16G_RANGE); 1168 if (ret) 1169 return ret; 1170 1171 /* Reset interrupts at start up */ 1172 ret = regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, 0x00); 1173 if (ret) 1174 return ret; 1175 1176 if (setup) { 1177 /* Perform optional initial bus specific configuration */ 1178 ret = setup(dev, st->regmap); 1179 if (ret) 1180 return ret; 1181 1182 /* Enable full-resolution mode */ 1183 ret = regmap_update_bits(st->regmap, ADXL345_REG_DATA_FORMAT, 1184 data_format_mask, 1185 ADXL345_DATA_FORMAT_FULL_RES); 1186 if (ret) 1187 return dev_err_probe(dev, ret, 1188 "Failed to set data range\n"); 1189 1190 } else { 1191 /* Enable full-resolution mode (init all data_format bits) */ 1192 ret = regmap_write(st->regmap, ADXL345_REG_DATA_FORMAT, 1193 ADXL345_DATA_FORMAT_FULL_RES); 1194 if (ret) 1195 return dev_err_probe(dev, ret, 1196 "Failed to set data range\n"); 1197 } 1198 1199 ret = regmap_read(st->regmap, ADXL345_REG_DEVID, ®val); 1200 if (ret) 1201 return dev_err_probe(dev, ret, "Error reading device ID\n"); 1202 1203 if (regval != ADXL345_DEVID) 1204 return dev_err_probe(dev, -ENODEV, "Invalid device ID: %x, expected %x\n", 1205 regval, ADXL345_DEVID); 1206 1207 /* Enable measurement mode */ 1208 ret = adxl345_set_measure_en(st, true); 1209 if (ret) 1210 return dev_err_probe(dev, ret, "Failed to enable measurement mode\n"); 1211 1212 ret = devm_add_action_or_reset(dev, adxl345_powerdown, st); 1213 if (ret) 1214 return ret; 1215 1216 intio = adxl345_get_int_line(dev, &irq); 1217 if (intio != ADXL345_INT_NONE) { 1218 /* 1219 * In the INT map register, bits set to 0 route their 1220 * corresponding interrupts to the INT1 pin, while bits set to 1 1221 * route them to the INT2 pin. The intio should handle this 1222 * mapping accordingly. 1223 */ 1224 ret = regmap_assign_bits(st->regmap, ADXL345_REG_INT_MAP, 1225 U8_MAX, intio); 1226 if (ret) 1227 return ret; 1228 1229 ret = regmap_write(st->regmap, ADXL345_REG_THRESH_TAP, tap_threshold); 1230 if (ret) 1231 return ret; 1232 1233 /* FIFO_STREAM mode is going to be activated later */ 1234 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, &adxl345_buffer_ops); 1235 if (ret) 1236 return ret; 1237 1238 ret = devm_request_threaded_irq(dev, irq, NULL, 1239 &adxl345_irq_handler, 1240 IRQF_SHARED | IRQF_ONESHOT, 1241 indio_dev->name, indio_dev); 1242 if (ret) 1243 return ret; 1244 } else { 1245 ret = regmap_write(st->regmap, ADXL345_REG_FIFO_CTL, 1246 FIELD_PREP(ADXL345_FIFO_CTL_MODE_MSK, 1247 ADXL345_FIFO_BYPASS)); 1248 if (ret) 1249 return ret; 1250 } 1251 1252 return devm_iio_device_register(dev, indio_dev); 1253 } 1254 EXPORT_SYMBOL_NS_GPL(adxl345_core_probe, "IIO_ADXL345"); 1255 1256 MODULE_AUTHOR("Eva Rachel Retuya <eraretuya@gmail.com>"); 1257 MODULE_DESCRIPTION("ADXL345 3-Axis Digital Accelerometer core driver"); 1258 MODULE_LICENSE("GPL v2"); 1259