1 /* 2 * intel_idle.c - native hardware idle loop for modern Intel processors 3 * 4 * Copyright (c) 2010, Intel Corporation. 5 * Len Brown <len.brown@intel.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 21 /* 22 * intel_idle is a cpuidle driver that loads on specific Intel processors 23 * in lieu of the legacy ACPI processor_idle driver. The intent is to 24 * make Linux more efficient on these processors, as intel_idle knows 25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs. 26 */ 27 28 /* 29 * Design Assumptions 30 * 31 * All CPUs have same idle states as boot CPU 32 * 33 * Chipset BM_STS (bus master status) bit is a NOP 34 * for preventing entry into deep C-stats 35 */ 36 37 /* 38 * Known limitations 39 * 40 * The driver currently initializes for_each_online_cpu() upon modprobe. 41 * It it unaware of subsequent processors hot-added to the system. 42 * This means that if you boot with maxcpus=n and later online 43 * processors above n, those processors will use C1 only. 44 * 45 * ACPI has a .suspend hack to turn off deep c-statees during suspend 46 * to avoid complications with the lapic timer workaround. 47 * Have not seen issues with suspend, but may need same workaround here. 48 * 49 * There is currently no kernel-based automatic probing/loading mechanism 50 * if the driver is built as a module. 51 */ 52 53 /* un-comment DEBUG to enable pr_debug() statements */ 54 #define DEBUG 55 56 #include <linux/kernel.h> 57 #include <linux/cpuidle.h> 58 #include <linux/clockchips.h> 59 #include <linux/hrtimer.h> /* ktime_get_real() */ 60 #include <trace/events/power.h> 61 #include <linux/sched.h> 62 #include <linux/notifier.h> 63 #include <linux/cpu.h> 64 #include <asm/mwait.h> 65 #include <asm/msr.h> 66 67 #define INTEL_IDLE_VERSION "0.4" 68 #define PREFIX "intel_idle: " 69 70 static struct cpuidle_driver intel_idle_driver = { 71 .name = "intel_idle", 72 .owner = THIS_MODULE, 73 }; 74 /* intel_idle.max_cstate=0 disables driver */ 75 static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1; 76 77 static unsigned int mwait_substates; 78 79 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF 80 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */ 81 static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */ 82 83 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices; 84 static int intel_idle(struct cpuidle_device *dev, int index); 85 86 static struct cpuidle_state *cpuidle_state_table; 87 88 /* 89 * Hardware C-state auto-demotion may not always be optimal. 90 * Indicate which enable bits to clear here. 91 */ 92 static unsigned long long auto_demotion_disable_flags; 93 94 /* 95 * Set this flag for states where the HW flushes the TLB for us 96 * and so we don't need cross-calls to keep it consistent. 97 * If this flag is set, SW flushes the TLB, so even if the 98 * HW doesn't do the flushing, this flag is safe to use. 99 */ 100 #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000 101 102 /* 103 * States are indexed by the cstate number, 104 * which is also the index into the MWAIT hint array. 105 * Thus C0 is a dummy. 106 */ 107 static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = { 108 { /* MWAIT C0 */ }, 109 { /* MWAIT C1 */ 110 .name = "C1-NHM", 111 .desc = "MWAIT 0x00", 112 .driver_data = (void *) 0x00, 113 .flags = CPUIDLE_FLAG_TIME_VALID, 114 .exit_latency = 3, 115 .target_residency = 6, 116 .enter = &intel_idle }, 117 { /* MWAIT C2 */ 118 .name = "C3-NHM", 119 .desc = "MWAIT 0x10", 120 .driver_data = (void *) 0x10, 121 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 122 .exit_latency = 20, 123 .target_residency = 80, 124 .enter = &intel_idle }, 125 { /* MWAIT C3 */ 126 .name = "C6-NHM", 127 .desc = "MWAIT 0x20", 128 .driver_data = (void *) 0x20, 129 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 130 .exit_latency = 200, 131 .target_residency = 800, 132 .enter = &intel_idle }, 133 }; 134 135 static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = { 136 { /* MWAIT C0 */ }, 137 { /* MWAIT C1 */ 138 .name = "C1-SNB", 139 .desc = "MWAIT 0x00", 140 .driver_data = (void *) 0x00, 141 .flags = CPUIDLE_FLAG_TIME_VALID, 142 .exit_latency = 1, 143 .target_residency = 1, 144 .enter = &intel_idle }, 145 { /* MWAIT C2 */ 146 .name = "C3-SNB", 147 .desc = "MWAIT 0x10", 148 .driver_data = (void *) 0x10, 149 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 150 .exit_latency = 80, 151 .target_residency = 211, 152 .enter = &intel_idle }, 153 { /* MWAIT C3 */ 154 .name = "C6-SNB", 155 .desc = "MWAIT 0x20", 156 .driver_data = (void *) 0x20, 157 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 158 .exit_latency = 104, 159 .target_residency = 345, 160 .enter = &intel_idle }, 161 { /* MWAIT C4 */ 162 .name = "C7-SNB", 163 .desc = "MWAIT 0x30", 164 .driver_data = (void *) 0x30, 165 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 166 .exit_latency = 109, 167 .target_residency = 345, 168 .enter = &intel_idle }, 169 }; 170 171 static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = { 172 { /* MWAIT C0 */ }, 173 { /* MWAIT C1 */ 174 .name = "C1-ATM", 175 .desc = "MWAIT 0x00", 176 .driver_data = (void *) 0x00, 177 .flags = CPUIDLE_FLAG_TIME_VALID, 178 .exit_latency = 1, 179 .target_residency = 4, 180 .enter = &intel_idle }, 181 { /* MWAIT C2 */ 182 .name = "C2-ATM", 183 .desc = "MWAIT 0x10", 184 .driver_data = (void *) 0x10, 185 .flags = CPUIDLE_FLAG_TIME_VALID, 186 .exit_latency = 20, 187 .target_residency = 80, 188 .enter = &intel_idle }, 189 { /* MWAIT C3 */ }, 190 { /* MWAIT C4 */ 191 .name = "C4-ATM", 192 .desc = "MWAIT 0x30", 193 .driver_data = (void *) 0x30, 194 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 195 .exit_latency = 100, 196 .target_residency = 400, 197 .enter = &intel_idle }, 198 { /* MWAIT C5 */ }, 199 { /* MWAIT C6 */ 200 .name = "C6-ATM", 201 .desc = "MWAIT 0x52", 202 .driver_data = (void *) 0x52, 203 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 204 .exit_latency = 140, 205 .target_residency = 560, 206 .enter = &intel_idle }, 207 }; 208 209 /** 210 * intel_idle 211 * @dev: cpuidle_device 212 * @index: index of cpuidle state 213 * 214 */ 215 static int intel_idle(struct cpuidle_device *dev, int index) 216 { 217 unsigned long ecx = 1; /* break on interrupt flag */ 218 struct cpuidle_state *state = &dev->states[index]; 219 unsigned long eax = (unsigned long)cpuidle_get_statedata(state); 220 unsigned int cstate; 221 ktime_t kt_before, kt_after; 222 s64 usec_delta; 223 int cpu = smp_processor_id(); 224 225 cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1; 226 227 local_irq_disable(); 228 229 /* 230 * leave_mm() to avoid costly and often unnecessary wakeups 231 * for flushing the user TLB's associated with the active mm. 232 */ 233 if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED) 234 leave_mm(cpu); 235 236 if (!(lapic_timer_reliable_states & (1 << (cstate)))) 237 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); 238 239 kt_before = ktime_get_real(); 240 241 stop_critical_timings(); 242 if (!need_resched()) { 243 244 __monitor((void *)¤t_thread_info()->flags, 0, 0); 245 smp_mb(); 246 if (!need_resched()) 247 __mwait(eax, ecx); 248 } 249 250 start_critical_timings(); 251 252 kt_after = ktime_get_real(); 253 usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before)); 254 255 local_irq_enable(); 256 257 if (!(lapic_timer_reliable_states & (1 << (cstate)))) 258 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); 259 260 /* Update cpuidle counters */ 261 dev->last_residency = (int)usec_delta; 262 263 return index; 264 } 265 266 static void __setup_broadcast_timer(void *arg) 267 { 268 unsigned long reason = (unsigned long)arg; 269 int cpu = smp_processor_id(); 270 271 reason = reason ? 272 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; 273 274 clockevents_notify(reason, &cpu); 275 } 276 277 static int setup_broadcast_cpuhp_notify(struct notifier_block *n, 278 unsigned long action, void *hcpu) 279 { 280 int hotcpu = (unsigned long)hcpu; 281 282 switch (action & 0xf) { 283 case CPU_ONLINE: 284 smp_call_function_single(hotcpu, __setup_broadcast_timer, 285 (void *)true, 1); 286 break; 287 } 288 return NOTIFY_OK; 289 } 290 291 static struct notifier_block setup_broadcast_notifier = { 292 .notifier_call = setup_broadcast_cpuhp_notify, 293 }; 294 295 static void auto_demotion_disable(void *dummy) 296 { 297 unsigned long long msr_bits; 298 299 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); 300 msr_bits &= ~auto_demotion_disable_flags; 301 wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); 302 } 303 304 /* 305 * intel_idle_probe() 306 */ 307 static int intel_idle_probe(void) 308 { 309 unsigned int eax, ebx, ecx; 310 311 if (max_cstate == 0) { 312 pr_debug(PREFIX "disabled\n"); 313 return -EPERM; 314 } 315 316 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 317 return -ENODEV; 318 319 if (!boot_cpu_has(X86_FEATURE_MWAIT)) 320 return -ENODEV; 321 322 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) 323 return -ENODEV; 324 325 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates); 326 327 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || 328 !(ecx & CPUID5_ECX_INTERRUPT_BREAK)) 329 return -ENODEV; 330 331 pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates); 332 333 334 if (boot_cpu_data.x86 != 6) /* family 6 */ 335 return -ENODEV; 336 337 switch (boot_cpu_data.x86_model) { 338 339 case 0x1A: /* Core i7, Xeon 5500 series */ 340 case 0x1E: /* Core i7 and i5 Processor - Lynnfield Jasper Forest */ 341 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 342 case 0x2E: /* Nehalem-EX Xeon */ 343 case 0x2F: /* Westmere-EX Xeon */ 344 case 0x25: /* Westmere */ 345 case 0x2C: /* Westmere */ 346 cpuidle_state_table = nehalem_cstates; 347 auto_demotion_disable_flags = 348 (NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE); 349 break; 350 351 case 0x1C: /* 28 - Atom Processor */ 352 cpuidle_state_table = atom_cstates; 353 break; 354 355 case 0x26: /* 38 - Lincroft Atom Processor */ 356 cpuidle_state_table = atom_cstates; 357 auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE; 358 break; 359 360 case 0x2A: /* SNB */ 361 case 0x2D: /* SNB Xeon */ 362 cpuidle_state_table = snb_cstates; 363 break; 364 365 default: 366 pr_debug(PREFIX "does not run on family %d model %d\n", 367 boot_cpu_data.x86, boot_cpu_data.x86_model); 368 return -ENODEV; 369 } 370 371 if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */ 372 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE; 373 else { 374 smp_call_function(__setup_broadcast_timer, (void *)true, 1); 375 register_cpu_notifier(&setup_broadcast_notifier); 376 } 377 378 pr_debug(PREFIX "v" INTEL_IDLE_VERSION 379 " model 0x%X\n", boot_cpu_data.x86_model); 380 381 pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n", 382 lapic_timer_reliable_states); 383 return 0; 384 } 385 386 /* 387 * intel_idle_cpuidle_devices_uninit() 388 * unregister, free cpuidle_devices 389 */ 390 static void intel_idle_cpuidle_devices_uninit(void) 391 { 392 int i; 393 struct cpuidle_device *dev; 394 395 for_each_online_cpu(i) { 396 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i); 397 cpuidle_unregister_device(dev); 398 } 399 400 free_percpu(intel_idle_cpuidle_devices); 401 return; 402 } 403 /* 404 * intel_idle_cpuidle_devices_init() 405 * allocate, initialize, register cpuidle_devices 406 */ 407 static int intel_idle_cpuidle_devices_init(void) 408 { 409 int i, cstate; 410 struct cpuidle_device *dev; 411 412 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device); 413 if (intel_idle_cpuidle_devices == NULL) 414 return -ENOMEM; 415 416 for_each_online_cpu(i) { 417 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i); 418 419 dev->state_count = 1; 420 421 for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) { 422 int num_substates; 423 424 if (cstate > max_cstate) { 425 printk(PREFIX "max_cstate %d reached\n", 426 max_cstate); 427 break; 428 } 429 430 /* does the state exist in CPUID.MWAIT? */ 431 num_substates = (mwait_substates >> ((cstate) * 4)) 432 & MWAIT_SUBSTATE_MASK; 433 if (num_substates == 0) 434 continue; 435 /* is the state not enabled? */ 436 if (cpuidle_state_table[cstate].enter == NULL) { 437 /* does the driver not know about the state? */ 438 if (*cpuidle_state_table[cstate].name == '\0') 439 pr_debug(PREFIX "unaware of model 0x%x" 440 " MWAIT %d please" 441 " contact lenb@kernel.org", 442 boot_cpu_data.x86_model, cstate); 443 continue; 444 } 445 446 if ((cstate > 2) && 447 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) 448 mark_tsc_unstable("TSC halts in idle" 449 " states deeper than C2"); 450 451 dev->states[dev->state_count] = /* structure copy */ 452 cpuidle_state_table[cstate]; 453 454 dev->state_count += 1; 455 } 456 457 dev->cpu = i; 458 if (cpuidle_register_device(dev)) { 459 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", 460 i); 461 intel_idle_cpuidle_devices_uninit(); 462 return -EIO; 463 } 464 } 465 if (auto_demotion_disable_flags) 466 smp_call_function(auto_demotion_disable, NULL, 1); 467 468 return 0; 469 } 470 471 472 static int __init intel_idle_init(void) 473 { 474 int retval; 475 476 /* Do not load intel_idle at all for now if idle= is passed */ 477 if (boot_option_idle_override != IDLE_NO_OVERRIDE) 478 return -ENODEV; 479 480 retval = intel_idle_probe(); 481 if (retval) 482 return retval; 483 484 retval = cpuidle_register_driver(&intel_idle_driver); 485 if (retval) { 486 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s", 487 cpuidle_get_driver()->name); 488 return retval; 489 } 490 491 retval = intel_idle_cpuidle_devices_init(); 492 if (retval) { 493 cpuidle_unregister_driver(&intel_idle_driver); 494 return retval; 495 } 496 497 return 0; 498 } 499 500 static void __exit intel_idle_exit(void) 501 { 502 intel_idle_cpuidle_devices_uninit(); 503 cpuidle_unregister_driver(&intel_idle_driver); 504 505 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) { 506 smp_call_function(__setup_broadcast_timer, (void *)false, 1); 507 unregister_cpu_notifier(&setup_broadcast_notifier); 508 } 509 510 return; 511 } 512 513 module_init(intel_idle_init); 514 module_exit(intel_idle_exit); 515 516 module_param(max_cstate, int, 0444); 517 518 MODULE_AUTHOR("Len Brown <len.brown@intel.com>"); 519 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION); 520 MODULE_LICENSE("GPL"); 521