1 /* 2 * intel_idle.c - native hardware idle loop for modern Intel processors 3 * 4 * Copyright (c) 2013, Intel Corporation. 5 * Len Brown <len.brown@intel.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 21 /* 22 * intel_idle is a cpuidle driver that loads on specific Intel processors 23 * in lieu of the legacy ACPI processor_idle driver. The intent is to 24 * make Linux more efficient on these processors, as intel_idle knows 25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs. 26 */ 27 28 /* 29 * Design Assumptions 30 * 31 * All CPUs have same idle states as boot CPU 32 * 33 * Chipset BM_STS (bus master status) bit is a NOP 34 * for preventing entry into deep C-stats 35 */ 36 37 /* 38 * Known limitations 39 * 40 * The driver currently initializes for_each_online_cpu() upon modprobe. 41 * It it unaware of subsequent processors hot-added to the system. 42 * This means that if you boot with maxcpus=n and later online 43 * processors above n, those processors will use C1 only. 44 * 45 * ACPI has a .suspend hack to turn off deep c-statees during suspend 46 * to avoid complications with the lapic timer workaround. 47 * Have not seen issues with suspend, but may need same workaround here. 48 * 49 * There is currently no kernel-based automatic probing/loading mechanism 50 * if the driver is built as a module. 51 */ 52 53 /* un-comment DEBUG to enable pr_debug() statements */ 54 #define DEBUG 55 56 #include <linux/kernel.h> 57 #include <linux/cpuidle.h> 58 #include <linux/clockchips.h> 59 #include <trace/events/power.h> 60 #include <linux/sched.h> 61 #include <linux/notifier.h> 62 #include <linux/cpu.h> 63 #include <linux/module.h> 64 #include <asm/cpu_device_id.h> 65 #include <asm/mwait.h> 66 #include <asm/msr.h> 67 68 #define INTEL_IDLE_VERSION "0.4" 69 #define PREFIX "intel_idle: " 70 71 static struct cpuidle_driver intel_idle_driver = { 72 .name = "intel_idle", 73 .owner = THIS_MODULE, 74 }; 75 /* intel_idle.max_cstate=0 disables driver */ 76 static int max_cstate = CPUIDLE_STATE_MAX - 1; 77 78 static unsigned int mwait_substates; 79 80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF 81 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */ 82 static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */ 83 84 struct idle_cpu { 85 struct cpuidle_state *state_table; 86 87 /* 88 * Hardware C-state auto-demotion may not always be optimal. 89 * Indicate which enable bits to clear here. 90 */ 91 unsigned long auto_demotion_disable_flags; 92 bool byt_auto_demotion_disable_flag; 93 bool disable_promotion_to_c1e; 94 }; 95 96 static const struct idle_cpu *icpu; 97 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices; 98 static int intel_idle(struct cpuidle_device *dev, 99 struct cpuidle_driver *drv, int index); 100 static void intel_idle_freeze(struct cpuidle_device *dev, 101 struct cpuidle_driver *drv, int index); 102 static int intel_idle_cpu_init(int cpu); 103 104 static struct cpuidle_state *cpuidle_state_table; 105 106 /* 107 * Set this flag for states where the HW flushes the TLB for us 108 * and so we don't need cross-calls to keep it consistent. 109 * If this flag is set, SW flushes the TLB, so even if the 110 * HW doesn't do the flushing, this flag is safe to use. 111 */ 112 #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000 113 114 /* 115 * MWAIT takes an 8-bit "hint" in EAX "suggesting" 116 * the C-state (top nibble) and sub-state (bottom nibble) 117 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc. 118 * 119 * We store the hint at the top of our "flags" for each state. 120 */ 121 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF) 122 #define MWAIT2flg(eax) ((eax & 0xFF) << 24) 123 124 /* 125 * States are indexed by the cstate number, 126 * which is also the index into the MWAIT hint array. 127 * Thus C0 is a dummy. 128 */ 129 static struct cpuidle_state nehalem_cstates[] = { 130 { 131 .name = "C1-NHM", 132 .desc = "MWAIT 0x00", 133 .flags = MWAIT2flg(0x00), 134 .exit_latency = 3, 135 .target_residency = 6, 136 .enter = &intel_idle, 137 .enter_freeze = intel_idle_freeze, }, 138 { 139 .name = "C1E-NHM", 140 .desc = "MWAIT 0x01", 141 .flags = MWAIT2flg(0x01), 142 .exit_latency = 10, 143 .target_residency = 20, 144 .enter = &intel_idle, 145 .enter_freeze = intel_idle_freeze, }, 146 { 147 .name = "C3-NHM", 148 .desc = "MWAIT 0x10", 149 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 150 .exit_latency = 20, 151 .target_residency = 80, 152 .enter = &intel_idle, 153 .enter_freeze = intel_idle_freeze, }, 154 { 155 .name = "C6-NHM", 156 .desc = "MWAIT 0x20", 157 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 158 .exit_latency = 200, 159 .target_residency = 800, 160 .enter = &intel_idle, 161 .enter_freeze = intel_idle_freeze, }, 162 { 163 .enter = NULL } 164 }; 165 166 static struct cpuidle_state snb_cstates[] = { 167 { 168 .name = "C1-SNB", 169 .desc = "MWAIT 0x00", 170 .flags = MWAIT2flg(0x00), 171 .exit_latency = 2, 172 .target_residency = 2, 173 .enter = &intel_idle, 174 .enter_freeze = intel_idle_freeze, }, 175 { 176 .name = "C1E-SNB", 177 .desc = "MWAIT 0x01", 178 .flags = MWAIT2flg(0x01), 179 .exit_latency = 10, 180 .target_residency = 20, 181 .enter = &intel_idle, 182 .enter_freeze = intel_idle_freeze, }, 183 { 184 .name = "C3-SNB", 185 .desc = "MWAIT 0x10", 186 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 187 .exit_latency = 80, 188 .target_residency = 211, 189 .enter = &intel_idle, 190 .enter_freeze = intel_idle_freeze, }, 191 { 192 .name = "C6-SNB", 193 .desc = "MWAIT 0x20", 194 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 195 .exit_latency = 104, 196 .target_residency = 345, 197 .enter = &intel_idle, 198 .enter_freeze = intel_idle_freeze, }, 199 { 200 .name = "C7-SNB", 201 .desc = "MWAIT 0x30", 202 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, 203 .exit_latency = 109, 204 .target_residency = 345, 205 .enter = &intel_idle, 206 .enter_freeze = intel_idle_freeze, }, 207 { 208 .enter = NULL } 209 }; 210 211 static struct cpuidle_state byt_cstates[] = { 212 { 213 .name = "C1-BYT", 214 .desc = "MWAIT 0x00", 215 .flags = MWAIT2flg(0x00), 216 .exit_latency = 1, 217 .target_residency = 1, 218 .enter = &intel_idle, 219 .enter_freeze = intel_idle_freeze, }, 220 { 221 .name = "C1E-BYT", 222 .desc = "MWAIT 0x01", 223 .flags = MWAIT2flg(0x01), 224 .exit_latency = 15, 225 .target_residency = 30, 226 .enter = &intel_idle, 227 .enter_freeze = intel_idle_freeze, }, 228 { 229 .name = "C6N-BYT", 230 .desc = "MWAIT 0x58", 231 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, 232 .exit_latency = 40, 233 .target_residency = 275, 234 .enter = &intel_idle, 235 .enter_freeze = intel_idle_freeze, }, 236 { 237 .name = "C6S-BYT", 238 .desc = "MWAIT 0x52", 239 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, 240 .exit_latency = 140, 241 .target_residency = 560, 242 .enter = &intel_idle, 243 .enter_freeze = intel_idle_freeze, }, 244 { 245 .name = "C7-BYT", 246 .desc = "MWAIT 0x60", 247 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 248 .exit_latency = 1200, 249 .target_residency = 1500, 250 .enter = &intel_idle, 251 .enter_freeze = intel_idle_freeze, }, 252 { 253 .name = "C7S-BYT", 254 .desc = "MWAIT 0x64", 255 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, 256 .exit_latency = 10000, 257 .target_residency = 20000, 258 .enter = &intel_idle, 259 .enter_freeze = intel_idle_freeze, }, 260 { 261 .enter = NULL } 262 }; 263 264 static struct cpuidle_state ivb_cstates[] = { 265 { 266 .name = "C1-IVB", 267 .desc = "MWAIT 0x00", 268 .flags = MWAIT2flg(0x00), 269 .exit_latency = 1, 270 .target_residency = 1, 271 .enter = &intel_idle, 272 .enter_freeze = intel_idle_freeze, }, 273 { 274 .name = "C1E-IVB", 275 .desc = "MWAIT 0x01", 276 .flags = MWAIT2flg(0x01), 277 .exit_latency = 10, 278 .target_residency = 20, 279 .enter = &intel_idle, 280 .enter_freeze = intel_idle_freeze, }, 281 { 282 .name = "C3-IVB", 283 .desc = "MWAIT 0x10", 284 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 285 .exit_latency = 59, 286 .target_residency = 156, 287 .enter = &intel_idle, 288 .enter_freeze = intel_idle_freeze, }, 289 { 290 .name = "C6-IVB", 291 .desc = "MWAIT 0x20", 292 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 293 .exit_latency = 80, 294 .target_residency = 300, 295 .enter = &intel_idle, 296 .enter_freeze = intel_idle_freeze, }, 297 { 298 .name = "C7-IVB", 299 .desc = "MWAIT 0x30", 300 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, 301 .exit_latency = 87, 302 .target_residency = 300, 303 .enter = &intel_idle, 304 .enter_freeze = intel_idle_freeze, }, 305 { 306 .enter = NULL } 307 }; 308 309 static struct cpuidle_state ivt_cstates[] = { 310 { 311 .name = "C1-IVT", 312 .desc = "MWAIT 0x00", 313 .flags = MWAIT2flg(0x00), 314 .exit_latency = 1, 315 .target_residency = 1, 316 .enter = &intel_idle, 317 .enter_freeze = intel_idle_freeze, }, 318 { 319 .name = "C1E-IVT", 320 .desc = "MWAIT 0x01", 321 .flags = MWAIT2flg(0x01), 322 .exit_latency = 10, 323 .target_residency = 80, 324 .enter = &intel_idle, 325 .enter_freeze = intel_idle_freeze, }, 326 { 327 .name = "C3-IVT", 328 .desc = "MWAIT 0x10", 329 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 330 .exit_latency = 59, 331 .target_residency = 156, 332 .enter = &intel_idle, 333 .enter_freeze = intel_idle_freeze, }, 334 { 335 .name = "C6-IVT", 336 .desc = "MWAIT 0x20", 337 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 338 .exit_latency = 82, 339 .target_residency = 300, 340 .enter = &intel_idle, 341 .enter_freeze = intel_idle_freeze, }, 342 { 343 .enter = NULL } 344 }; 345 346 static struct cpuidle_state ivt_cstates_4s[] = { 347 { 348 .name = "C1-IVT-4S", 349 .desc = "MWAIT 0x00", 350 .flags = MWAIT2flg(0x00), 351 .exit_latency = 1, 352 .target_residency = 1, 353 .enter = &intel_idle, 354 .enter_freeze = intel_idle_freeze, }, 355 { 356 .name = "C1E-IVT-4S", 357 .desc = "MWAIT 0x01", 358 .flags = MWAIT2flg(0x01), 359 .exit_latency = 10, 360 .target_residency = 250, 361 .enter = &intel_idle, 362 .enter_freeze = intel_idle_freeze, }, 363 { 364 .name = "C3-IVT-4S", 365 .desc = "MWAIT 0x10", 366 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 367 .exit_latency = 59, 368 .target_residency = 300, 369 .enter = &intel_idle, 370 .enter_freeze = intel_idle_freeze, }, 371 { 372 .name = "C6-IVT-4S", 373 .desc = "MWAIT 0x20", 374 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 375 .exit_latency = 84, 376 .target_residency = 400, 377 .enter = &intel_idle, 378 .enter_freeze = intel_idle_freeze, }, 379 { 380 .enter = NULL } 381 }; 382 383 static struct cpuidle_state ivt_cstates_8s[] = { 384 { 385 .name = "C1-IVT-8S", 386 .desc = "MWAIT 0x00", 387 .flags = MWAIT2flg(0x00), 388 .exit_latency = 1, 389 .target_residency = 1, 390 .enter = &intel_idle, 391 .enter_freeze = intel_idle_freeze, }, 392 { 393 .name = "C1E-IVT-8S", 394 .desc = "MWAIT 0x01", 395 .flags = MWAIT2flg(0x01), 396 .exit_latency = 10, 397 .target_residency = 500, 398 .enter = &intel_idle, 399 .enter_freeze = intel_idle_freeze, }, 400 { 401 .name = "C3-IVT-8S", 402 .desc = "MWAIT 0x10", 403 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 404 .exit_latency = 59, 405 .target_residency = 600, 406 .enter = &intel_idle, 407 .enter_freeze = intel_idle_freeze, }, 408 { 409 .name = "C6-IVT-8S", 410 .desc = "MWAIT 0x20", 411 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 412 .exit_latency = 88, 413 .target_residency = 700, 414 .enter = &intel_idle, 415 .enter_freeze = intel_idle_freeze, }, 416 { 417 .enter = NULL } 418 }; 419 420 static struct cpuidle_state hsw_cstates[] = { 421 { 422 .name = "C1-HSW", 423 .desc = "MWAIT 0x00", 424 .flags = MWAIT2flg(0x00), 425 .exit_latency = 2, 426 .target_residency = 2, 427 .enter = &intel_idle, 428 .enter_freeze = intel_idle_freeze, }, 429 { 430 .name = "C1E-HSW", 431 .desc = "MWAIT 0x01", 432 .flags = MWAIT2flg(0x01), 433 .exit_latency = 10, 434 .target_residency = 20, 435 .enter = &intel_idle, 436 .enter_freeze = intel_idle_freeze, }, 437 { 438 .name = "C3-HSW", 439 .desc = "MWAIT 0x10", 440 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 441 .exit_latency = 33, 442 .target_residency = 100, 443 .enter = &intel_idle, 444 .enter_freeze = intel_idle_freeze, }, 445 { 446 .name = "C6-HSW", 447 .desc = "MWAIT 0x20", 448 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 449 .exit_latency = 133, 450 .target_residency = 400, 451 .enter = &intel_idle, 452 .enter_freeze = intel_idle_freeze, }, 453 { 454 .name = "C7s-HSW", 455 .desc = "MWAIT 0x32", 456 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, 457 .exit_latency = 166, 458 .target_residency = 500, 459 .enter = &intel_idle, 460 .enter_freeze = intel_idle_freeze, }, 461 { 462 .name = "C8-HSW", 463 .desc = "MWAIT 0x40", 464 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, 465 .exit_latency = 300, 466 .target_residency = 900, 467 .enter = &intel_idle, 468 .enter_freeze = intel_idle_freeze, }, 469 { 470 .name = "C9-HSW", 471 .desc = "MWAIT 0x50", 472 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, 473 .exit_latency = 600, 474 .target_residency = 1800, 475 .enter = &intel_idle, 476 .enter_freeze = intel_idle_freeze, }, 477 { 478 .name = "C10-HSW", 479 .desc = "MWAIT 0x60", 480 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 481 .exit_latency = 2600, 482 .target_residency = 7700, 483 .enter = &intel_idle, 484 .enter_freeze = intel_idle_freeze, }, 485 { 486 .enter = NULL } 487 }; 488 static struct cpuidle_state bdw_cstates[] = { 489 { 490 .name = "C1-BDW", 491 .desc = "MWAIT 0x00", 492 .flags = MWAIT2flg(0x00), 493 .exit_latency = 2, 494 .target_residency = 2, 495 .enter = &intel_idle, 496 .enter_freeze = intel_idle_freeze, }, 497 { 498 .name = "C1E-BDW", 499 .desc = "MWAIT 0x01", 500 .flags = MWAIT2flg(0x01), 501 .exit_latency = 10, 502 .target_residency = 20, 503 .enter = &intel_idle, 504 .enter_freeze = intel_idle_freeze, }, 505 { 506 .name = "C3-BDW", 507 .desc = "MWAIT 0x10", 508 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 509 .exit_latency = 40, 510 .target_residency = 100, 511 .enter = &intel_idle, 512 .enter_freeze = intel_idle_freeze, }, 513 { 514 .name = "C6-BDW", 515 .desc = "MWAIT 0x20", 516 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 517 .exit_latency = 133, 518 .target_residency = 400, 519 .enter = &intel_idle, 520 .enter_freeze = intel_idle_freeze, }, 521 { 522 .name = "C7s-BDW", 523 .desc = "MWAIT 0x32", 524 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, 525 .exit_latency = 166, 526 .target_residency = 500, 527 .enter = &intel_idle, 528 .enter_freeze = intel_idle_freeze, }, 529 { 530 .name = "C8-BDW", 531 .desc = "MWAIT 0x40", 532 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, 533 .exit_latency = 300, 534 .target_residency = 900, 535 .enter = &intel_idle, 536 .enter_freeze = intel_idle_freeze, }, 537 { 538 .name = "C9-BDW", 539 .desc = "MWAIT 0x50", 540 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, 541 .exit_latency = 600, 542 .target_residency = 1800, 543 .enter = &intel_idle, 544 .enter_freeze = intel_idle_freeze, }, 545 { 546 .name = "C10-BDW", 547 .desc = "MWAIT 0x60", 548 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 549 .exit_latency = 2600, 550 .target_residency = 7700, 551 .enter = &intel_idle, 552 .enter_freeze = intel_idle_freeze, }, 553 { 554 .enter = NULL } 555 }; 556 557 static struct cpuidle_state atom_cstates[] = { 558 { 559 .name = "C1E-ATM", 560 .desc = "MWAIT 0x00", 561 .flags = MWAIT2flg(0x00), 562 .exit_latency = 10, 563 .target_residency = 20, 564 .enter = &intel_idle, 565 .enter_freeze = intel_idle_freeze, }, 566 { 567 .name = "C2-ATM", 568 .desc = "MWAIT 0x10", 569 .flags = MWAIT2flg(0x10), 570 .exit_latency = 20, 571 .target_residency = 80, 572 .enter = &intel_idle, 573 .enter_freeze = intel_idle_freeze, }, 574 { 575 .name = "C4-ATM", 576 .desc = "MWAIT 0x30", 577 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, 578 .exit_latency = 100, 579 .target_residency = 400, 580 .enter = &intel_idle, 581 .enter_freeze = intel_idle_freeze, }, 582 { 583 .name = "C6-ATM", 584 .desc = "MWAIT 0x52", 585 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, 586 .exit_latency = 140, 587 .target_residency = 560, 588 .enter = &intel_idle, 589 .enter_freeze = intel_idle_freeze, }, 590 { 591 .enter = NULL } 592 }; 593 static struct cpuidle_state avn_cstates[] = { 594 { 595 .name = "C1-AVN", 596 .desc = "MWAIT 0x00", 597 .flags = MWAIT2flg(0x00), 598 .exit_latency = 2, 599 .target_residency = 2, 600 .enter = &intel_idle, 601 .enter_freeze = intel_idle_freeze, }, 602 { 603 .name = "C6-AVN", 604 .desc = "MWAIT 0x51", 605 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED, 606 .exit_latency = 15, 607 .target_residency = 45, 608 .enter = &intel_idle, 609 .enter_freeze = intel_idle_freeze, }, 610 { 611 .enter = NULL } 612 }; 613 614 /** 615 * intel_idle 616 * @dev: cpuidle_device 617 * @drv: cpuidle driver 618 * @index: index of cpuidle state 619 * 620 * Must be called under local_irq_disable(). 621 */ 622 static int intel_idle(struct cpuidle_device *dev, 623 struct cpuidle_driver *drv, int index) 624 { 625 unsigned long ecx = 1; /* break on interrupt flag */ 626 struct cpuidle_state *state = &drv->states[index]; 627 unsigned long eax = flg2MWAIT(state->flags); 628 unsigned int cstate; 629 int cpu = smp_processor_id(); 630 631 cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1; 632 633 /* 634 * leave_mm() to avoid costly and often unnecessary wakeups 635 * for flushing the user TLB's associated with the active mm. 636 */ 637 if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED) 638 leave_mm(cpu); 639 640 if (!(lapic_timer_reliable_states & (1 << (cstate)))) 641 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); 642 643 mwait_idle_with_hints(eax, ecx); 644 645 if (!(lapic_timer_reliable_states & (1 << (cstate)))) 646 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); 647 648 return index; 649 } 650 651 /** 652 * intel_idle_freeze - simplified "enter" callback routine for suspend-to-idle 653 * @dev: cpuidle_device 654 * @drv: cpuidle driver 655 * @index: state index 656 */ 657 static void intel_idle_freeze(struct cpuidle_device *dev, 658 struct cpuidle_driver *drv, int index) 659 { 660 unsigned long ecx = 1; /* break on interrupt flag */ 661 unsigned long eax = flg2MWAIT(drv->states[index].flags); 662 663 mwait_idle_with_hints(eax, ecx); 664 } 665 666 static void __setup_broadcast_timer(void *arg) 667 { 668 unsigned long reason = (unsigned long)arg; 669 int cpu = smp_processor_id(); 670 671 reason = reason ? 672 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; 673 674 clockevents_notify(reason, &cpu); 675 } 676 677 static int cpu_hotplug_notify(struct notifier_block *n, 678 unsigned long action, void *hcpu) 679 { 680 int hotcpu = (unsigned long)hcpu; 681 struct cpuidle_device *dev; 682 683 switch (action & ~CPU_TASKS_FROZEN) { 684 case CPU_ONLINE: 685 686 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) 687 smp_call_function_single(hotcpu, __setup_broadcast_timer, 688 (void *)true, 1); 689 690 /* 691 * Some systems can hotplug a cpu at runtime after 692 * the kernel has booted, we have to initialize the 693 * driver in this case 694 */ 695 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu); 696 if (!dev->registered) 697 intel_idle_cpu_init(hotcpu); 698 699 break; 700 } 701 return NOTIFY_OK; 702 } 703 704 static struct notifier_block cpu_hotplug_notifier = { 705 .notifier_call = cpu_hotplug_notify, 706 }; 707 708 static void auto_demotion_disable(void *dummy) 709 { 710 unsigned long long msr_bits; 711 712 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); 713 msr_bits &= ~(icpu->auto_demotion_disable_flags); 714 wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); 715 } 716 static void c1e_promotion_disable(void *dummy) 717 { 718 unsigned long long msr_bits; 719 720 rdmsrl(MSR_IA32_POWER_CTL, msr_bits); 721 msr_bits &= ~0x2; 722 wrmsrl(MSR_IA32_POWER_CTL, msr_bits); 723 } 724 725 static const struct idle_cpu idle_cpu_nehalem = { 726 .state_table = nehalem_cstates, 727 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE, 728 .disable_promotion_to_c1e = true, 729 }; 730 731 static const struct idle_cpu idle_cpu_atom = { 732 .state_table = atom_cstates, 733 }; 734 735 static const struct idle_cpu idle_cpu_lincroft = { 736 .state_table = atom_cstates, 737 .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE, 738 }; 739 740 static const struct idle_cpu idle_cpu_snb = { 741 .state_table = snb_cstates, 742 .disable_promotion_to_c1e = true, 743 }; 744 745 static const struct idle_cpu idle_cpu_byt = { 746 .state_table = byt_cstates, 747 .disable_promotion_to_c1e = true, 748 .byt_auto_demotion_disable_flag = true, 749 }; 750 751 static const struct idle_cpu idle_cpu_ivb = { 752 .state_table = ivb_cstates, 753 .disable_promotion_to_c1e = true, 754 }; 755 756 static const struct idle_cpu idle_cpu_ivt = { 757 .state_table = ivt_cstates, 758 .disable_promotion_to_c1e = true, 759 }; 760 761 static const struct idle_cpu idle_cpu_hsw = { 762 .state_table = hsw_cstates, 763 .disable_promotion_to_c1e = true, 764 }; 765 766 static const struct idle_cpu idle_cpu_bdw = { 767 .state_table = bdw_cstates, 768 .disable_promotion_to_c1e = true, 769 }; 770 771 static const struct idle_cpu idle_cpu_avn = { 772 .state_table = avn_cstates, 773 .disable_promotion_to_c1e = true, 774 }; 775 776 #define ICPU(model, cpu) \ 777 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu } 778 779 static const struct x86_cpu_id intel_idle_ids[] = { 780 ICPU(0x1a, idle_cpu_nehalem), 781 ICPU(0x1e, idle_cpu_nehalem), 782 ICPU(0x1f, idle_cpu_nehalem), 783 ICPU(0x25, idle_cpu_nehalem), 784 ICPU(0x2c, idle_cpu_nehalem), 785 ICPU(0x2e, idle_cpu_nehalem), 786 ICPU(0x1c, idle_cpu_atom), 787 ICPU(0x26, idle_cpu_lincroft), 788 ICPU(0x2f, idle_cpu_nehalem), 789 ICPU(0x2a, idle_cpu_snb), 790 ICPU(0x2d, idle_cpu_snb), 791 ICPU(0x36, idle_cpu_atom), 792 ICPU(0x37, idle_cpu_byt), 793 ICPU(0x3a, idle_cpu_ivb), 794 ICPU(0x3e, idle_cpu_ivt), 795 ICPU(0x3c, idle_cpu_hsw), 796 ICPU(0x3f, idle_cpu_hsw), 797 ICPU(0x45, idle_cpu_hsw), 798 ICPU(0x46, idle_cpu_hsw), 799 ICPU(0x4d, idle_cpu_avn), 800 ICPU(0x3d, idle_cpu_bdw), 801 ICPU(0x47, idle_cpu_bdw), 802 ICPU(0x4f, idle_cpu_bdw), 803 ICPU(0x56, idle_cpu_bdw), 804 {} 805 }; 806 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids); 807 808 /* 809 * intel_idle_probe() 810 */ 811 static int __init intel_idle_probe(void) 812 { 813 unsigned int eax, ebx, ecx; 814 const struct x86_cpu_id *id; 815 816 if (max_cstate == 0) { 817 pr_debug(PREFIX "disabled\n"); 818 return -EPERM; 819 } 820 821 id = x86_match_cpu(intel_idle_ids); 822 if (!id) { 823 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 824 boot_cpu_data.x86 == 6) 825 pr_debug(PREFIX "does not run on family %d model %d\n", 826 boot_cpu_data.x86, boot_cpu_data.x86_model); 827 return -ENODEV; 828 } 829 830 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) 831 return -ENODEV; 832 833 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates); 834 835 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || 836 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) || 837 !mwait_substates) 838 return -ENODEV; 839 840 pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates); 841 842 icpu = (const struct idle_cpu *)id->driver_data; 843 cpuidle_state_table = icpu->state_table; 844 845 if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */ 846 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE; 847 else 848 on_each_cpu(__setup_broadcast_timer, (void *)true, 1); 849 850 pr_debug(PREFIX "v" INTEL_IDLE_VERSION 851 " model 0x%X\n", boot_cpu_data.x86_model); 852 853 pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n", 854 lapic_timer_reliable_states); 855 return 0; 856 } 857 858 /* 859 * intel_idle_cpuidle_devices_uninit() 860 * unregister, free cpuidle_devices 861 */ 862 static void intel_idle_cpuidle_devices_uninit(void) 863 { 864 int i; 865 struct cpuidle_device *dev; 866 867 for_each_online_cpu(i) { 868 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i); 869 cpuidle_unregister_device(dev); 870 } 871 872 free_percpu(intel_idle_cpuidle_devices); 873 return; 874 } 875 876 /* 877 * intel_idle_state_table_update() 878 * 879 * Update the default state_table for this CPU-id 880 * 881 * Currently used to access tuned IVT multi-socket targets 882 * Assumption: num_sockets == (max_package_num + 1) 883 */ 884 void intel_idle_state_table_update(void) 885 { 886 /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */ 887 if (boot_cpu_data.x86_model == 0x3e) { /* IVT */ 888 int cpu, package_num, num_sockets = 1; 889 890 for_each_online_cpu(cpu) { 891 package_num = topology_physical_package_id(cpu); 892 if (package_num + 1 > num_sockets) { 893 num_sockets = package_num + 1; 894 895 if (num_sockets > 4) { 896 cpuidle_state_table = ivt_cstates_8s; 897 return; 898 } 899 } 900 } 901 902 if (num_sockets > 2) 903 cpuidle_state_table = ivt_cstates_4s; 904 /* else, 1 and 2 socket systems use default ivt_cstates */ 905 } 906 return; 907 } 908 909 /* 910 * intel_idle_cpuidle_driver_init() 911 * allocate, initialize cpuidle_states 912 */ 913 static int __init intel_idle_cpuidle_driver_init(void) 914 { 915 int cstate; 916 struct cpuidle_driver *drv = &intel_idle_driver; 917 918 intel_idle_state_table_update(); 919 920 drv->state_count = 1; 921 922 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { 923 int num_substates, mwait_hint, mwait_cstate; 924 925 if (cpuidle_state_table[cstate].enter == NULL) 926 break; 927 928 if (cstate + 1 > max_cstate) { 929 printk(PREFIX "max_cstate %d reached\n", 930 max_cstate); 931 break; 932 } 933 934 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags); 935 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint); 936 937 /* number of sub-states for this state in CPUID.MWAIT */ 938 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4)) 939 & MWAIT_SUBSTATE_MASK; 940 941 /* if NO sub-states for this state in CPUID, skip it */ 942 if (num_substates == 0) 943 continue; 944 945 if (((mwait_cstate + 1) > 2) && 946 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) 947 mark_tsc_unstable("TSC halts in idle" 948 " states deeper than C2"); 949 950 drv->states[drv->state_count] = /* structure copy */ 951 cpuidle_state_table[cstate]; 952 953 drv->state_count += 1; 954 } 955 956 if (icpu->auto_demotion_disable_flags) 957 on_each_cpu(auto_demotion_disable, NULL, 1); 958 959 if (icpu->byt_auto_demotion_disable_flag) { 960 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0); 961 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0); 962 } 963 964 if (icpu->disable_promotion_to_c1e) /* each-cpu is redundant */ 965 on_each_cpu(c1e_promotion_disable, NULL, 1); 966 967 return 0; 968 } 969 970 971 /* 972 * intel_idle_cpu_init() 973 * allocate, initialize, register cpuidle_devices 974 * @cpu: cpu/core to initialize 975 */ 976 static int intel_idle_cpu_init(int cpu) 977 { 978 struct cpuidle_device *dev; 979 980 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu); 981 982 dev->cpu = cpu; 983 984 if (cpuidle_register_device(dev)) { 985 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu); 986 intel_idle_cpuidle_devices_uninit(); 987 return -EIO; 988 } 989 990 if (icpu->auto_demotion_disable_flags) 991 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1); 992 993 if (icpu->disable_promotion_to_c1e) 994 smp_call_function_single(cpu, c1e_promotion_disable, NULL, 1); 995 996 return 0; 997 } 998 999 static int __init intel_idle_init(void) 1000 { 1001 int retval, i; 1002 1003 /* Do not load intel_idle at all for now if idle= is passed */ 1004 if (boot_option_idle_override != IDLE_NO_OVERRIDE) 1005 return -ENODEV; 1006 1007 retval = intel_idle_probe(); 1008 if (retval) 1009 return retval; 1010 1011 intel_idle_cpuidle_driver_init(); 1012 retval = cpuidle_register_driver(&intel_idle_driver); 1013 if (retval) { 1014 struct cpuidle_driver *drv = cpuidle_get_driver(); 1015 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s", 1016 drv ? drv->name : "none"); 1017 return retval; 1018 } 1019 1020 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device); 1021 if (intel_idle_cpuidle_devices == NULL) 1022 return -ENOMEM; 1023 1024 cpu_notifier_register_begin(); 1025 1026 for_each_online_cpu(i) { 1027 retval = intel_idle_cpu_init(i); 1028 if (retval) { 1029 cpu_notifier_register_done(); 1030 cpuidle_unregister_driver(&intel_idle_driver); 1031 return retval; 1032 } 1033 } 1034 __register_cpu_notifier(&cpu_hotplug_notifier); 1035 1036 cpu_notifier_register_done(); 1037 1038 return 0; 1039 } 1040 1041 static void __exit intel_idle_exit(void) 1042 { 1043 intel_idle_cpuidle_devices_uninit(); 1044 cpuidle_unregister_driver(&intel_idle_driver); 1045 1046 cpu_notifier_register_begin(); 1047 1048 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) 1049 on_each_cpu(__setup_broadcast_timer, (void *)false, 1); 1050 __unregister_cpu_notifier(&cpu_hotplug_notifier); 1051 1052 cpu_notifier_register_done(); 1053 1054 return; 1055 } 1056 1057 module_init(intel_idle_init); 1058 module_exit(intel_idle_exit); 1059 1060 module_param(max_cstate, int, 0444); 1061 1062 MODULE_AUTHOR("Len Brown <len.brown@intel.com>"); 1063 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION); 1064 MODULE_LICENSE("GPL"); 1065