1 /* 2 * intel_idle.c - native hardware idle loop for modern Intel processors 3 * 4 * Copyright (c) 2010, Intel Corporation. 5 * Len Brown <len.brown@intel.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 21 /* 22 * intel_idle is a cpuidle driver that loads on specific Intel processors 23 * in lieu of the legacy ACPI processor_idle driver. The intent is to 24 * make Linux more efficient on these processors, as intel_idle knows 25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs. 26 */ 27 28 /* 29 * Design Assumptions 30 * 31 * All CPUs have same idle states as boot CPU 32 * 33 * Chipset BM_STS (bus master status) bit is a NOP 34 * for preventing entry into deep C-stats 35 */ 36 37 /* 38 * Known limitations 39 * 40 * The driver currently initializes for_each_online_cpu() upon modprobe. 41 * It it unaware of subsequent processors hot-added to the system. 42 * This means that if you boot with maxcpus=n and later online 43 * processors above n, those processors will use C1 only. 44 * 45 * ACPI has a .suspend hack to turn off deep c-statees during suspend 46 * to avoid complications with the lapic timer workaround. 47 * Have not seen issues with suspend, but may need same workaround here. 48 * 49 * There is currently no kernel-based automatic probing/loading mechanism 50 * if the driver is built as a module. 51 */ 52 53 /* un-comment DEBUG to enable pr_debug() statements */ 54 #define DEBUG 55 56 #include <linux/kernel.h> 57 #include <linux/cpuidle.h> 58 #include <linux/clockchips.h> 59 #include <trace/events/power.h> 60 #include <linux/sched.h> 61 #include <linux/notifier.h> 62 #include <linux/cpu.h> 63 #include <linux/module.h> 64 #include <asm/cpu_device_id.h> 65 #include <asm/mwait.h> 66 #include <asm/msr.h> 67 68 #define INTEL_IDLE_VERSION "0.4" 69 #define PREFIX "intel_idle: " 70 71 static struct cpuidle_driver intel_idle_driver = { 72 .name = "intel_idle", 73 .owner = THIS_MODULE, 74 .en_core_tk_irqen = 1, 75 }; 76 /* intel_idle.max_cstate=0 disables driver */ 77 static int max_cstate = CPUIDLE_STATE_MAX - 1; 78 79 static unsigned int mwait_substates; 80 81 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF 82 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */ 83 static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */ 84 85 struct idle_cpu { 86 struct cpuidle_state *state_table; 87 88 /* 89 * Hardware C-state auto-demotion may not always be optimal. 90 * Indicate which enable bits to clear here. 91 */ 92 unsigned long auto_demotion_disable_flags; 93 bool disable_promotion_to_c1e; 94 }; 95 96 static const struct idle_cpu *icpu; 97 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices; 98 static int intel_idle(struct cpuidle_device *dev, 99 struct cpuidle_driver *drv, int index); 100 static int intel_idle_cpu_init(int cpu); 101 102 static struct cpuidle_state *cpuidle_state_table; 103 104 /* 105 * Set this flag for states where the HW flushes the TLB for us 106 * and so we don't need cross-calls to keep it consistent. 107 * If this flag is set, SW flushes the TLB, so even if the 108 * HW doesn't do the flushing, this flag is safe to use. 109 */ 110 #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000 111 112 /* 113 * MWAIT takes an 8-bit "hint" in EAX "suggesting" 114 * the C-state (top nibble) and sub-state (bottom nibble) 115 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc. 116 * 117 * We store the hint at the top of our "flags" for each state. 118 */ 119 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF) 120 #define MWAIT2flg(eax) ((eax & 0xFF) << 24) 121 122 /* 123 * States are indexed by the cstate number, 124 * which is also the index into the MWAIT hint array. 125 * Thus C0 is a dummy. 126 */ 127 static struct cpuidle_state nehalem_cstates[CPUIDLE_STATE_MAX] = { 128 { 129 .name = "C1-NHM", 130 .desc = "MWAIT 0x00", 131 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 132 .exit_latency = 3, 133 .target_residency = 6, 134 .enter = &intel_idle }, 135 { 136 .name = "C1E-NHM", 137 .desc = "MWAIT 0x01", 138 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 139 .exit_latency = 10, 140 .target_residency = 20, 141 .enter = &intel_idle }, 142 { 143 .name = "C3-NHM", 144 .desc = "MWAIT 0x10", 145 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 146 .exit_latency = 20, 147 .target_residency = 80, 148 .enter = &intel_idle }, 149 { 150 .name = "C6-NHM", 151 .desc = "MWAIT 0x20", 152 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 153 .exit_latency = 200, 154 .target_residency = 800, 155 .enter = &intel_idle }, 156 { 157 .enter = NULL } 158 }; 159 160 static struct cpuidle_state snb_cstates[CPUIDLE_STATE_MAX] = { 161 { 162 .name = "C1-SNB", 163 .desc = "MWAIT 0x00", 164 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 165 .exit_latency = 2, 166 .target_residency = 2, 167 .enter = &intel_idle }, 168 { 169 .name = "C1E-SNB", 170 .desc = "MWAIT 0x01", 171 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 172 .exit_latency = 10, 173 .target_residency = 20, 174 .enter = &intel_idle }, 175 { 176 .name = "C3-SNB", 177 .desc = "MWAIT 0x10", 178 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 179 .exit_latency = 80, 180 .target_residency = 211, 181 .enter = &intel_idle }, 182 { 183 .name = "C6-SNB", 184 .desc = "MWAIT 0x20", 185 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 186 .exit_latency = 104, 187 .target_residency = 345, 188 .enter = &intel_idle }, 189 { 190 .name = "C7-SNB", 191 .desc = "MWAIT 0x30", 192 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 193 .exit_latency = 109, 194 .target_residency = 345, 195 .enter = &intel_idle }, 196 { 197 .enter = NULL } 198 }; 199 200 static struct cpuidle_state ivb_cstates[CPUIDLE_STATE_MAX] = { 201 { 202 .name = "C1-IVB", 203 .desc = "MWAIT 0x00", 204 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 205 .exit_latency = 1, 206 .target_residency = 1, 207 .enter = &intel_idle }, 208 { 209 .name = "C1E-IVB", 210 .desc = "MWAIT 0x01", 211 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 212 .exit_latency = 10, 213 .target_residency = 20, 214 .enter = &intel_idle }, 215 { 216 .name = "C3-IVB", 217 .desc = "MWAIT 0x10", 218 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 219 .exit_latency = 59, 220 .target_residency = 156, 221 .enter = &intel_idle }, 222 { 223 .name = "C6-IVB", 224 .desc = "MWAIT 0x20", 225 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 226 .exit_latency = 80, 227 .target_residency = 300, 228 .enter = &intel_idle }, 229 { 230 .name = "C7-IVB", 231 .desc = "MWAIT 0x30", 232 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 233 .exit_latency = 87, 234 .target_residency = 300, 235 .enter = &intel_idle }, 236 { 237 .enter = NULL } 238 }; 239 240 static struct cpuidle_state hsw_cstates[CPUIDLE_STATE_MAX] = { 241 { 242 .name = "C1-HSW", 243 .desc = "MWAIT 0x00", 244 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 245 .exit_latency = 2, 246 .target_residency = 2, 247 .enter = &intel_idle }, 248 { 249 .name = "C1E-HSW", 250 .desc = "MWAIT 0x01", 251 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 252 .exit_latency = 10, 253 .target_residency = 20, 254 .enter = &intel_idle }, 255 { 256 .name = "C3-HSW", 257 .desc = "MWAIT 0x10", 258 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 259 .exit_latency = 33, 260 .target_residency = 100, 261 .enter = &intel_idle }, 262 { 263 .name = "C6-HSW", 264 .desc = "MWAIT 0x20", 265 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 266 .exit_latency = 133, 267 .target_residency = 400, 268 .enter = &intel_idle }, 269 { 270 .name = "C7s-HSW", 271 .desc = "MWAIT 0x32", 272 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 273 .exit_latency = 166, 274 .target_residency = 500, 275 .enter = &intel_idle }, 276 { 277 .enter = NULL } 278 }; 279 280 static struct cpuidle_state atom_cstates[CPUIDLE_STATE_MAX] = { 281 { 282 .name = "C1E-ATM", 283 .desc = "MWAIT 0x00", 284 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 285 .exit_latency = 10, 286 .target_residency = 20, 287 .enter = &intel_idle }, 288 { 289 .name = "C2-ATM", 290 .desc = "MWAIT 0x10", 291 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID, 292 .exit_latency = 20, 293 .target_residency = 80, 294 .enter = &intel_idle }, 295 { 296 .name = "C4-ATM", 297 .desc = "MWAIT 0x30", 298 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 299 .exit_latency = 100, 300 .target_residency = 400, 301 .enter = &intel_idle }, 302 { 303 .name = "C6-ATM", 304 .desc = "MWAIT 0x52", 305 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 306 .exit_latency = 140, 307 .target_residency = 560, 308 .enter = &intel_idle }, 309 { 310 .enter = NULL } 311 }; 312 313 /** 314 * intel_idle 315 * @dev: cpuidle_device 316 * @drv: cpuidle driver 317 * @index: index of cpuidle state 318 * 319 * Must be called under local_irq_disable(). 320 */ 321 static int intel_idle(struct cpuidle_device *dev, 322 struct cpuidle_driver *drv, int index) 323 { 324 unsigned long ecx = 1; /* break on interrupt flag */ 325 struct cpuidle_state *state = &drv->states[index]; 326 unsigned long eax = flg2MWAIT(state->flags); 327 unsigned int cstate; 328 int cpu = smp_processor_id(); 329 330 cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1; 331 332 /* 333 * leave_mm() to avoid costly and often unnecessary wakeups 334 * for flushing the user TLB's associated with the active mm. 335 */ 336 if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED) 337 leave_mm(cpu); 338 339 if (!(lapic_timer_reliable_states & (1 << (cstate)))) 340 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); 341 342 if (!need_resched()) { 343 344 __monitor((void *)¤t_thread_info()->flags, 0, 0); 345 smp_mb(); 346 if (!need_resched()) 347 __mwait(eax, ecx); 348 } 349 350 if (!(lapic_timer_reliable_states & (1 << (cstate)))) 351 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); 352 353 return index; 354 } 355 356 static void __setup_broadcast_timer(void *arg) 357 { 358 unsigned long reason = (unsigned long)arg; 359 int cpu = smp_processor_id(); 360 361 reason = reason ? 362 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; 363 364 clockevents_notify(reason, &cpu); 365 } 366 367 static int cpu_hotplug_notify(struct notifier_block *n, 368 unsigned long action, void *hcpu) 369 { 370 int hotcpu = (unsigned long)hcpu; 371 struct cpuidle_device *dev; 372 373 switch (action & 0xf) { 374 case CPU_ONLINE: 375 376 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) 377 smp_call_function_single(hotcpu, __setup_broadcast_timer, 378 (void *)true, 1); 379 380 /* 381 * Some systems can hotplug a cpu at runtime after 382 * the kernel has booted, we have to initialize the 383 * driver in this case 384 */ 385 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu); 386 if (!dev->registered) 387 intel_idle_cpu_init(hotcpu); 388 389 break; 390 } 391 return NOTIFY_OK; 392 } 393 394 static struct notifier_block cpu_hotplug_notifier = { 395 .notifier_call = cpu_hotplug_notify, 396 }; 397 398 static void auto_demotion_disable(void *dummy) 399 { 400 unsigned long long msr_bits; 401 402 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); 403 msr_bits &= ~(icpu->auto_demotion_disable_flags); 404 wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); 405 } 406 static void c1e_promotion_disable(void *dummy) 407 { 408 unsigned long long msr_bits; 409 410 rdmsrl(MSR_IA32_POWER_CTL, msr_bits); 411 msr_bits &= ~0x2; 412 wrmsrl(MSR_IA32_POWER_CTL, msr_bits); 413 } 414 415 static const struct idle_cpu idle_cpu_nehalem = { 416 .state_table = nehalem_cstates, 417 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE, 418 .disable_promotion_to_c1e = true, 419 }; 420 421 static const struct idle_cpu idle_cpu_atom = { 422 .state_table = atom_cstates, 423 }; 424 425 static const struct idle_cpu idle_cpu_lincroft = { 426 .state_table = atom_cstates, 427 .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE, 428 }; 429 430 static const struct idle_cpu idle_cpu_snb = { 431 .state_table = snb_cstates, 432 .disable_promotion_to_c1e = true, 433 }; 434 435 static const struct idle_cpu idle_cpu_ivb = { 436 .state_table = ivb_cstates, 437 .disable_promotion_to_c1e = true, 438 }; 439 440 static const struct idle_cpu idle_cpu_hsw = { 441 .state_table = hsw_cstates, 442 .disable_promotion_to_c1e = true, 443 }; 444 445 #define ICPU(model, cpu) \ 446 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu } 447 448 static const struct x86_cpu_id intel_idle_ids[] = { 449 ICPU(0x1a, idle_cpu_nehalem), 450 ICPU(0x1e, idle_cpu_nehalem), 451 ICPU(0x1f, idle_cpu_nehalem), 452 ICPU(0x25, idle_cpu_nehalem), 453 ICPU(0x2c, idle_cpu_nehalem), 454 ICPU(0x2e, idle_cpu_nehalem), 455 ICPU(0x1c, idle_cpu_atom), 456 ICPU(0x26, idle_cpu_lincroft), 457 ICPU(0x2f, idle_cpu_nehalem), 458 ICPU(0x2a, idle_cpu_snb), 459 ICPU(0x2d, idle_cpu_snb), 460 ICPU(0x3a, idle_cpu_ivb), 461 ICPU(0x3e, idle_cpu_ivb), 462 ICPU(0x3c, idle_cpu_hsw), 463 ICPU(0x3f, idle_cpu_hsw), 464 ICPU(0x45, idle_cpu_hsw), 465 {} 466 }; 467 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids); 468 469 /* 470 * intel_idle_probe() 471 */ 472 static int intel_idle_probe(void) 473 { 474 unsigned int eax, ebx, ecx; 475 const struct x86_cpu_id *id; 476 477 if (max_cstate == 0) { 478 pr_debug(PREFIX "disabled\n"); 479 return -EPERM; 480 } 481 482 id = x86_match_cpu(intel_idle_ids); 483 if (!id) { 484 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 485 boot_cpu_data.x86 == 6) 486 pr_debug(PREFIX "does not run on family %d model %d\n", 487 boot_cpu_data.x86, boot_cpu_data.x86_model); 488 return -ENODEV; 489 } 490 491 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) 492 return -ENODEV; 493 494 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates); 495 496 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || 497 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) || 498 !mwait_substates) 499 return -ENODEV; 500 501 pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates); 502 503 icpu = (const struct idle_cpu *)id->driver_data; 504 cpuidle_state_table = icpu->state_table; 505 506 if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */ 507 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE; 508 else 509 on_each_cpu(__setup_broadcast_timer, (void *)true, 1); 510 511 pr_debug(PREFIX "v" INTEL_IDLE_VERSION 512 " model 0x%X\n", boot_cpu_data.x86_model); 513 514 pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n", 515 lapic_timer_reliable_states); 516 return 0; 517 } 518 519 /* 520 * intel_idle_cpuidle_devices_uninit() 521 * unregister, free cpuidle_devices 522 */ 523 static void intel_idle_cpuidle_devices_uninit(void) 524 { 525 int i; 526 struct cpuidle_device *dev; 527 528 for_each_online_cpu(i) { 529 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i); 530 cpuidle_unregister_device(dev); 531 } 532 533 free_percpu(intel_idle_cpuidle_devices); 534 return; 535 } 536 /* 537 * intel_idle_cpuidle_driver_init() 538 * allocate, initialize cpuidle_states 539 */ 540 static int intel_idle_cpuidle_driver_init(void) 541 { 542 int cstate; 543 struct cpuidle_driver *drv = &intel_idle_driver; 544 545 drv->state_count = 1; 546 547 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { 548 int num_substates, mwait_hint, mwait_cstate, mwait_substate; 549 550 if (cpuidle_state_table[cstate].enter == NULL) 551 break; 552 553 if (cstate + 1 > max_cstate) { 554 printk(PREFIX "max_cstate %d reached\n", 555 max_cstate); 556 break; 557 } 558 559 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags); 560 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint); 561 mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint); 562 563 /* does the state exist in CPUID.MWAIT? */ 564 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4)) 565 & MWAIT_SUBSTATE_MASK; 566 567 /* if sub-state in table is not enumerated by CPUID */ 568 if ((mwait_substate + 1) > num_substates) 569 continue; 570 571 if (((mwait_cstate + 1) > 2) && 572 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) 573 mark_tsc_unstable("TSC halts in idle" 574 " states deeper than C2"); 575 576 drv->states[drv->state_count] = /* structure copy */ 577 cpuidle_state_table[cstate]; 578 579 drv->state_count += 1; 580 } 581 582 if (icpu->auto_demotion_disable_flags) 583 on_each_cpu(auto_demotion_disable, NULL, 1); 584 585 if (icpu->disable_promotion_to_c1e) /* each-cpu is redundant */ 586 on_each_cpu(c1e_promotion_disable, NULL, 1); 587 588 return 0; 589 } 590 591 592 /* 593 * intel_idle_cpu_init() 594 * allocate, initialize, register cpuidle_devices 595 * @cpu: cpu/core to initialize 596 */ 597 static int intel_idle_cpu_init(int cpu) 598 { 599 int cstate; 600 struct cpuidle_device *dev; 601 602 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu); 603 604 dev->state_count = 1; 605 606 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { 607 int num_substates, mwait_hint, mwait_cstate, mwait_substate; 608 609 if (cpuidle_state_table[cstate].enter == NULL) 610 continue; 611 612 if (cstate + 1 > max_cstate) { 613 printk(PREFIX "max_cstate %d reached\n", max_cstate); 614 break; 615 } 616 617 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags); 618 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint); 619 mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint); 620 621 /* does the state exist in CPUID.MWAIT? */ 622 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4)) 623 & MWAIT_SUBSTATE_MASK; 624 625 /* if sub-state in table is not enumerated by CPUID */ 626 if ((mwait_substate + 1) > num_substates) 627 continue; 628 629 dev->state_count += 1; 630 } 631 632 dev->cpu = cpu; 633 634 if (cpuidle_register_device(dev)) { 635 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu); 636 intel_idle_cpuidle_devices_uninit(); 637 return -EIO; 638 } 639 640 if (icpu->auto_demotion_disable_flags) 641 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1); 642 643 return 0; 644 } 645 646 static int __init intel_idle_init(void) 647 { 648 int retval, i; 649 650 /* Do not load intel_idle at all for now if idle= is passed */ 651 if (boot_option_idle_override != IDLE_NO_OVERRIDE) 652 return -ENODEV; 653 654 retval = intel_idle_probe(); 655 if (retval) 656 return retval; 657 658 intel_idle_cpuidle_driver_init(); 659 retval = cpuidle_register_driver(&intel_idle_driver); 660 if (retval) { 661 struct cpuidle_driver *drv = cpuidle_get_driver(); 662 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s", 663 drv ? drv->name : "none"); 664 return retval; 665 } 666 667 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device); 668 if (intel_idle_cpuidle_devices == NULL) 669 return -ENOMEM; 670 671 for_each_online_cpu(i) { 672 retval = intel_idle_cpu_init(i); 673 if (retval) { 674 cpuidle_unregister_driver(&intel_idle_driver); 675 return retval; 676 } 677 } 678 register_cpu_notifier(&cpu_hotplug_notifier); 679 680 return 0; 681 } 682 683 static void __exit intel_idle_exit(void) 684 { 685 intel_idle_cpuidle_devices_uninit(); 686 cpuidle_unregister_driver(&intel_idle_driver); 687 688 689 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) 690 on_each_cpu(__setup_broadcast_timer, (void *)false, 1); 691 unregister_cpu_notifier(&cpu_hotplug_notifier); 692 693 return; 694 } 695 696 module_init(intel_idle_init); 697 module_exit(intel_idle_exit); 698 699 module_param(max_cstate, int, 0444); 700 701 MODULE_AUTHOR("Len Brown <len.brown@intel.com>"); 702 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION); 703 MODULE_LICENSE("GPL"); 704