1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Silvaco dual-role I3C master driver 4 * 5 * Copyright (C) 2020 Silvaco 6 * Author: Miquel RAYNAL <miquel.raynal@bootlin.com> 7 * Based on a work from: Conor Culhane <conor.culhane@silvaco.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/completion.h> 13 #include <linux/errno.h> 14 #include <linux/i3c/master.h> 15 #include <linux/interrupt.h> 16 #include <linux/iopoll.h> 17 #include <linux/list.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 24 /* Master Mode Registers */ 25 #define SVC_I3C_MCONFIG 0x000 26 #define SVC_I3C_MCONFIG_MASTER_EN BIT(0) 27 #define SVC_I3C_MCONFIG_DISTO(x) FIELD_PREP(BIT(3), (x)) 28 #define SVC_I3C_MCONFIG_HKEEP(x) FIELD_PREP(GENMASK(5, 4), (x)) 29 #define SVC_I3C_MCONFIG_ODSTOP(x) FIELD_PREP(BIT(6), (x)) 30 #define SVC_I3C_MCONFIG_PPBAUD(x) FIELD_PREP(GENMASK(11, 8), (x)) 31 #define SVC_I3C_MCONFIG_PPLOW(x) FIELD_PREP(GENMASK(15, 12), (x)) 32 #define SVC_I3C_MCONFIG_ODBAUD(x) FIELD_PREP(GENMASK(23, 16), (x)) 33 #define SVC_I3C_MCONFIG_ODHPP(x) FIELD_PREP(BIT(24), (x)) 34 #define SVC_I3C_MCONFIG_SKEW(x) FIELD_PREP(GENMASK(27, 25), (x)) 35 #define SVC_I3C_MCONFIG_SKEW_MASK GENMASK(27, 25) 36 #define SVC_I3C_MCONFIG_I2CBAUD(x) FIELD_PREP(GENMASK(31, 28), (x)) 37 38 #define SVC_I3C_MCTRL 0x084 39 #define SVC_I3C_MCTRL_REQUEST_MASK GENMASK(2, 0) 40 #define SVC_I3C_MCTRL_REQUEST_NONE 0 41 #define SVC_I3C_MCTRL_REQUEST_START_ADDR 1 42 #define SVC_I3C_MCTRL_REQUEST_STOP 2 43 #define SVC_I3C_MCTRL_REQUEST_FORCE_EXIT 6 44 #define SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK 3 45 #define SVC_I3C_MCTRL_REQUEST_PROC_DAA 4 46 #define SVC_I3C_MCTRL_REQUEST_AUTO_IBI 7 47 #define SVC_I3C_MCTRL_TYPE_I3C 0 48 #define SVC_I3C_MCTRL_TYPE_I2C BIT(4) 49 #define SVC_I3C_MCTRL_TYPE_DDR BIT(5) 50 #define SVC_I3C_MCTRL_IBIRESP_AUTO 0 51 #define SVC_I3C_MCTRL_IBIRESP_ACK_WITHOUT_BYTE 0 52 #define SVC_I3C_MCTRL_IBIRESP_ACK_WITH_BYTE BIT(7) 53 #define SVC_I3C_MCTRL_IBIRESP_NACK BIT(6) 54 #define SVC_I3C_MCTRL_IBIRESP_MANUAL GENMASK(7, 6) 55 #define SVC_I3C_MCTRL_DIR(x) FIELD_PREP(BIT(8), (x)) 56 #define SVC_I3C_MCTRL_DIR_WRITE 0 57 #define SVC_I3C_MCTRL_DIR_READ 1 58 #define SVC_I3C_MCTRL_ADDR(x) FIELD_PREP(GENMASK(15, 9), (x)) 59 #define SVC_I3C_MCTRL_RDTERM(x) FIELD_PREP(GENMASK(23, 16), (x)) 60 61 #define SVC_I3C_MSTATUS 0x088 62 #define SVC_I3C_MSTATUS_STATE(x) FIELD_GET(GENMASK(2, 0), (x)) 63 #define SVC_I3C_MSTATUS_STATE_DAA(x) (SVC_I3C_MSTATUS_STATE(x) == 5) 64 #define SVC_I3C_MSTATUS_STATE_SLVREQ(x) (SVC_I3C_MSTATUS_STATE(x) == 1) 65 #define SVC_I3C_MSTATUS_STATE_IDLE(x) (SVC_I3C_MSTATUS_STATE(x) == 0) 66 #define SVC_I3C_MSTATUS_BETWEEN(x) FIELD_GET(BIT(4), (x)) 67 #define SVC_I3C_MSTATUS_NACKED(x) FIELD_GET(BIT(5), (x)) 68 #define SVC_I3C_MSTATUS_IBITYPE(x) FIELD_GET(GENMASK(7, 6), (x)) 69 #define SVC_I3C_MSTATUS_IBITYPE_IBI 1 70 #define SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST 2 71 #define SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN 3 72 #define SVC_I3C_MINT_SLVSTART BIT(8) 73 #define SVC_I3C_MINT_MCTRLDONE BIT(9) 74 #define SVC_I3C_MINT_COMPLETE BIT(10) 75 #define SVC_I3C_MINT_RXPEND BIT(11) 76 #define SVC_I3C_MINT_TXNOTFULL BIT(12) 77 #define SVC_I3C_MINT_IBIWON BIT(13) 78 #define SVC_I3C_MINT_ERRWARN BIT(15) 79 #define SVC_I3C_MSTATUS_SLVSTART(x) FIELD_GET(SVC_I3C_MINT_SLVSTART, (x)) 80 #define SVC_I3C_MSTATUS_MCTRLDONE(x) FIELD_GET(SVC_I3C_MINT_MCTRLDONE, (x)) 81 #define SVC_I3C_MSTATUS_COMPLETE(x) FIELD_GET(SVC_I3C_MINT_COMPLETE, (x)) 82 #define SVC_I3C_MSTATUS_RXPEND(x) FIELD_GET(SVC_I3C_MINT_RXPEND, (x)) 83 #define SVC_I3C_MSTATUS_TXNOTFULL(x) FIELD_GET(SVC_I3C_MINT_TXNOTFULL, (x)) 84 #define SVC_I3C_MSTATUS_IBIWON(x) FIELD_GET(SVC_I3C_MINT_IBIWON, (x)) 85 #define SVC_I3C_MSTATUS_ERRWARN(x) FIELD_GET(SVC_I3C_MINT_ERRWARN, (x)) 86 #define SVC_I3C_MSTATUS_IBIADDR(x) FIELD_GET(GENMASK(30, 24), (x)) 87 88 #define SVC_I3C_IBIRULES 0x08C 89 #define SVC_I3C_IBIRULES_ADDR(slot, addr) FIELD_PREP(GENMASK(29, 0), \ 90 ((addr) & 0x3F) << ((slot) * 6)) 91 #define SVC_I3C_IBIRULES_ADDRS 5 92 #define SVC_I3C_IBIRULES_MSB0 BIT(30) 93 #define SVC_I3C_IBIRULES_NOBYTE BIT(31) 94 #define SVC_I3C_IBIRULES_MANDBYTE 0 95 #define SVC_I3C_MINTSET 0x090 96 #define SVC_I3C_MINTCLR 0x094 97 #define SVC_I3C_MINTMASKED 0x098 98 #define SVC_I3C_MERRWARN 0x09C 99 #define SVC_I3C_MERRWARN_NACK BIT(2) 100 #define SVC_I3C_MERRWARN_CRC BIT(10) 101 #define SVC_I3C_MERRWARN_TIMEOUT BIT(20) 102 #define SVC_I3C_MDMACTRL 0x0A0 103 #define SVC_I3C_MDATACTRL 0x0AC 104 #define SVC_I3C_MDATACTRL_FLUSHTB BIT(0) 105 #define SVC_I3C_MDATACTRL_FLUSHRB BIT(1) 106 #define SVC_I3C_MDATACTRL_UNLOCK_TRIG BIT(3) 107 #define SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL GENMASK(5, 4) 108 #define SVC_I3C_MDATACTRL_RXTRIG_FIFO_NOT_EMPTY 0 109 #define SVC_I3C_MDATACTRL_RXCOUNT(x) FIELD_GET(GENMASK(28, 24), (x)) 110 #define SVC_I3C_MDATACTRL_TXCOUNT(x) FIELD_GET(GENMASK(20, 16), (x)) 111 #define SVC_I3C_MDATACTRL_TXFULL BIT(30) 112 #define SVC_I3C_MDATACTRL_RXEMPTY BIT(31) 113 114 #define SVC_I3C_MWDATAB 0x0B0 115 #define SVC_I3C_MWDATAB_END BIT(8) 116 117 #define SVC_I3C_MWDATABE 0x0B4 118 #define SVC_I3C_MWDATAH 0x0B8 119 #define SVC_I3C_MWDATAHE 0x0BC 120 #define SVC_I3C_MRDATAB 0x0C0 121 #define SVC_I3C_MRDATAH 0x0C8 122 #define SVC_I3C_MWDATAB1 0x0CC 123 #define SVC_I3C_MWMSG_SDR 0x0D0 124 #define SVC_I3C_MRMSG_SDR 0x0D4 125 #define SVC_I3C_MWMSG_DDR 0x0D8 126 #define SVC_I3C_MRMSG_DDR 0x0DC 127 128 #define SVC_I3C_MDYNADDR 0x0E4 129 #define SVC_MDYNADDR_VALID BIT(0) 130 #define SVC_MDYNADDR_ADDR(x) FIELD_PREP(GENMASK(7, 1), (x)) 131 132 #define SVC_I3C_MAX_DEVS 32 133 #define SVC_I3C_PM_TIMEOUT_MS 1000 134 135 /* This parameter depends on the implementation and may be tuned */ 136 #define SVC_I3C_FIFO_SIZE 16 137 #define SVC_I3C_PPBAUD_MAX 15 138 #define SVC_I3C_QUICK_I2C_CLK 4170000 139 140 #define SVC_I3C_EVENT_IBI GENMASK(7, 0) 141 #define SVC_I3C_EVENT_HOTJOIN BIT(31) 142 143 /* 144 * SVC_I3C_QUIRK_FIFO_EMPTY: 145 * I3C HW stalls the write transfer if the transmit FIFO becomes empty, 146 * when new data is written to FIFO, I3C HW resumes the transfer but 147 * the first transmitted data bit may have the wrong value. 148 * Workaround: 149 * Fill the FIFO in advance to prevent FIFO from becoming empty. 150 */ 151 #define SVC_I3C_QUIRK_FIFO_EMPTY BIT(0) 152 /* 153 * SVC_I3C_QUIRK_FLASE_SLVSTART: 154 * I3C HW may generate an invalid SlvStart event when emitting a STOP. 155 * If it is a true SlvStart, the MSTATUS state is SLVREQ. 156 */ 157 #define SVC_I3C_QUIRK_FALSE_SLVSTART BIT(1) 158 /* 159 * SVC_I3C_QUIRK_DAA_CORRUPT: 160 * When MCONFIG.SKEW=0 and MCONFIG.ODHPP=0, the ENTDAA transaction gets 161 * corrupted and results in a no repeated-start condition at the end of 162 * address assignment. 163 * Workaround: 164 * Set MCONFIG.SKEW to 1 before initiating the DAA process. After the DAA 165 * process is completed, return MCONFIG.SKEW to its previous value. 166 */ 167 #define SVC_I3C_QUIRK_DAA_CORRUPT BIT(2) 168 169 struct svc_i3c_cmd { 170 u8 addr; 171 union { 172 bool rnw; 173 u8 cmd; 174 u32 rnw_cmd; 175 }; 176 u8 *in; 177 const void *out; 178 unsigned int len; 179 unsigned int actual_len; 180 struct i3c_xfer *xfer; 181 bool continued; 182 }; 183 184 struct svc_i3c_xfer { 185 struct list_head node; 186 struct completion comp; 187 int ret; 188 unsigned int type; 189 unsigned int ncmds; 190 struct svc_i3c_cmd cmds[] __counted_by(ncmds); 191 }; 192 193 struct svc_i3c_regs_save { 194 u32 mconfig; 195 u32 mdynaddr; 196 }; 197 198 struct svc_i3c_drvdata { 199 u32 quirks; 200 }; 201 202 /** 203 * struct svc_i3c_master - Silvaco I3C Master structure 204 * @base: I3C master controller 205 * @dev: Corresponding device 206 * @regs: Memory mapping 207 * @saved_regs: Volatile values for PM operations 208 * @free_slots: Bit array of available slots 209 * @addrs: Array containing the dynamic addresses of each attached device 210 * @descs: Array of descriptors, one per attached device 211 * @irq: Main interrupt 212 * @num_clks: I3C clock number 213 * @fclk: Fast clock (bus) 214 * @clks: I3C clock array 215 * @xferqueue: Transfer queue structure 216 * @xferqueue.list: List member 217 * @xferqueue.cur: Current ongoing transfer 218 * @xferqueue.lock: Queue lock 219 * @ibi: IBI structure 220 * @ibi.num_slots: Number of slots available in @ibi.slots 221 * @ibi.slots: Available IBI slots 222 * @ibi.tbq_slot: To be queued IBI slot 223 * @ibi.lock: IBI lock 224 * @lock: Transfer lock, protect between IBI work thread and callbacks from master 225 * @drvdata: Driver data 226 * @enabled_events: Bit masks for enable events (IBI, HotJoin). 227 * @mctrl_config: Configuration value in SVC_I3C_MCTRL for setting speed back. 228 */ 229 struct svc_i3c_master { 230 struct i3c_master_controller base; 231 struct device *dev; 232 void __iomem *regs; 233 struct svc_i3c_regs_save saved_regs; 234 u32 free_slots; 235 u8 addrs[SVC_I3C_MAX_DEVS]; 236 struct i3c_dev_desc *descs[SVC_I3C_MAX_DEVS]; 237 int irq; 238 int num_clks; 239 struct clk *fclk; 240 struct clk_bulk_data *clks; 241 struct { 242 struct list_head list; 243 struct svc_i3c_xfer *cur; 244 /* Prevent races between transfers */ 245 spinlock_t lock; 246 } xferqueue; 247 struct { 248 unsigned int num_slots; 249 struct i3c_dev_desc **slots; 250 struct i3c_ibi_slot *tbq_slot; 251 /* Prevent races within IBI handlers */ 252 spinlock_t lock; 253 } ibi; 254 struct mutex lock; 255 const struct svc_i3c_drvdata *drvdata; 256 u32 enabled_events; 257 u32 mctrl_config; 258 }; 259 260 /** 261 * struct svc_i3c_i2c_dev_data - Device specific data 262 * @index: Index in the master tables corresponding to this device 263 * @ibi: IBI slot index in the master structure 264 * @ibi_pool: IBI pool associated to this device 265 */ 266 struct svc_i3c_i2c_dev_data { 267 u8 index; 268 int ibi; 269 struct i3c_generic_ibi_pool *ibi_pool; 270 }; 271 272 static inline bool svc_has_quirk(struct svc_i3c_master *master, u32 quirk) 273 { 274 return (master->drvdata->quirks & quirk); 275 } 276 277 static inline bool svc_has_daa_corrupt(struct svc_i3c_master *master) 278 { 279 return ((master->drvdata->quirks & SVC_I3C_QUIRK_DAA_CORRUPT) && 280 !(master->mctrl_config & 281 (SVC_I3C_MCONFIG_SKEW_MASK | SVC_I3C_MCONFIG_ODHPP(1)))); 282 } 283 284 static inline bool is_events_enabled(struct svc_i3c_master *master, u32 mask) 285 { 286 return !!(master->enabled_events & mask); 287 } 288 289 static bool svc_i3c_master_error(struct svc_i3c_master *master) 290 { 291 u32 mstatus, merrwarn; 292 293 mstatus = readl(master->regs + SVC_I3C_MSTATUS); 294 if (SVC_I3C_MSTATUS_ERRWARN(mstatus)) { 295 merrwarn = readl(master->regs + SVC_I3C_MERRWARN); 296 writel(merrwarn, master->regs + SVC_I3C_MERRWARN); 297 298 /* Ignore timeout error */ 299 if (merrwarn & SVC_I3C_MERRWARN_TIMEOUT) { 300 dev_dbg(master->dev, "Warning condition: MSTATUS 0x%08x, MERRWARN 0x%08x\n", 301 mstatus, merrwarn); 302 return false; 303 } 304 305 dev_err(master->dev, 306 "Error condition: MSTATUS 0x%08x, MERRWARN 0x%08x\n", 307 mstatus, merrwarn); 308 309 return true; 310 } 311 312 return false; 313 } 314 315 static void svc_i3c_master_enable_interrupts(struct svc_i3c_master *master, u32 mask) 316 { 317 writel(mask, master->regs + SVC_I3C_MINTSET); 318 } 319 320 static void svc_i3c_master_disable_interrupts(struct svc_i3c_master *master) 321 { 322 u32 mask = readl(master->regs + SVC_I3C_MINTSET); 323 324 writel(mask, master->regs + SVC_I3C_MINTCLR); 325 } 326 327 static void svc_i3c_master_clear_merrwarn(struct svc_i3c_master *master) 328 { 329 /* Clear pending warnings */ 330 writel(readl(master->regs + SVC_I3C_MERRWARN), 331 master->regs + SVC_I3C_MERRWARN); 332 } 333 334 static void svc_i3c_master_flush_fifo(struct svc_i3c_master *master) 335 { 336 /* Flush FIFOs */ 337 writel(SVC_I3C_MDATACTRL_FLUSHTB | SVC_I3C_MDATACTRL_FLUSHRB, 338 master->regs + SVC_I3C_MDATACTRL); 339 } 340 341 static void svc_i3c_master_reset_fifo_trigger(struct svc_i3c_master *master) 342 { 343 u32 reg; 344 345 /* Set RX and TX trigger levels, flush FIFOs */ 346 reg = SVC_I3C_MDATACTRL_FLUSHTB | 347 SVC_I3C_MDATACTRL_FLUSHRB | 348 SVC_I3C_MDATACTRL_UNLOCK_TRIG | 349 SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL | 350 SVC_I3C_MDATACTRL_RXTRIG_FIFO_NOT_EMPTY; 351 writel(reg, master->regs + SVC_I3C_MDATACTRL); 352 } 353 354 static void svc_i3c_master_reset(struct svc_i3c_master *master) 355 { 356 svc_i3c_master_clear_merrwarn(master); 357 svc_i3c_master_reset_fifo_trigger(master); 358 svc_i3c_master_disable_interrupts(master); 359 } 360 361 static inline struct svc_i3c_master * 362 to_svc_i3c_master(struct i3c_master_controller *master) 363 { 364 return container_of(master, struct svc_i3c_master, base); 365 } 366 367 static struct i3c_dev_desc * 368 svc_i3c_master_dev_from_addr(struct svc_i3c_master *master, 369 unsigned int ibiaddr) 370 { 371 int i; 372 373 for (i = 0; i < SVC_I3C_MAX_DEVS; i++) 374 if (master->addrs[i] == ibiaddr) 375 break; 376 377 if (i == SVC_I3C_MAX_DEVS) 378 return NULL; 379 380 return master->descs[i]; 381 } 382 383 static bool svc_cmd_is_read(u32 rnw_cmd, u32 type) 384 { 385 return (type == SVC_I3C_MCTRL_TYPE_DDR) ? (rnw_cmd & 0x80) : rnw_cmd; 386 } 387 388 static void svc_i3c_master_emit_force_exit(struct svc_i3c_master *master) 389 { 390 u32 reg; 391 392 writel(SVC_I3C_MCTRL_REQUEST_FORCE_EXIT, master->regs + SVC_I3C_MCTRL); 393 394 /* 395 * Not need check error here because it is never happen at hardware. 396 * IP just wait for few fclk cycle to complete DDR exit pattern. Even 397 * though fclk stop, timeout happen here, the whole data actually 398 * already finish transfer. The next command will be timeout because 399 * wrong hardware state. 400 */ 401 readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg, 402 SVC_I3C_MSTATUS_MCTRLDONE(reg), 0, 1000); 403 404 /* 405 * This delay is necessary after the emission of a stop, otherwise eg. 406 * repeating IBIs do not get detected. There is a note in the manual 407 * about it, stating that the stop condition might not be settled 408 * correctly if a start condition follows too rapidly. 409 */ 410 udelay(1); 411 } 412 413 static void svc_i3c_master_emit_stop(struct svc_i3c_master *master) 414 { 415 writel(SVC_I3C_MCTRL_REQUEST_STOP, master->regs + SVC_I3C_MCTRL); 416 417 /* 418 * This delay is necessary after the emission of a stop, otherwise eg. 419 * repeating IBIs do not get detected. There is a note in the manual 420 * about it, stating that the stop condition might not be settled 421 * correctly if a start condition follows too rapidly. 422 */ 423 udelay(1); 424 } 425 426 static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master, 427 struct i3c_dev_desc *dev) 428 { 429 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 430 struct i3c_ibi_slot *slot; 431 unsigned int count; 432 u32 mdatactrl; 433 int ret, val; 434 u8 *buf; 435 436 /* 437 * Wait for transfer to complete before returning. Otherwise, the EmitStop 438 * request might be sent when the transfer is not complete. 439 */ 440 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val, 441 SVC_I3C_MSTATUS_COMPLETE(val), 0, 1000); 442 if (ret) { 443 dev_err(master->dev, "Timeout when polling for COMPLETE\n"); 444 return ret; 445 } 446 447 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool); 448 if (!slot) { 449 dev_dbg(master->dev, "No free ibi slot, drop the data\n"); 450 writel(SVC_I3C_MDATACTRL_FLUSHRB, master->regs + SVC_I3C_MDATACTRL); 451 return -ENOSPC; 452 } 453 454 slot->len = 0; 455 buf = slot->data; 456 457 while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS)) && 458 slot->len < SVC_I3C_FIFO_SIZE) { 459 mdatactrl = readl(master->regs + SVC_I3C_MDATACTRL); 460 count = SVC_I3C_MDATACTRL_RXCOUNT(mdatactrl); 461 readsb(master->regs + SVC_I3C_MRDATAB, buf, count); 462 slot->len += count; 463 buf += count; 464 } 465 466 master->ibi.tbq_slot = slot; 467 468 return 0; 469 } 470 471 static int svc_i3c_master_ack_ibi(struct svc_i3c_master *master, 472 bool mandatory_byte) 473 { 474 unsigned int ibi_ack_nack; 475 u32 reg; 476 477 ibi_ack_nack = SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK; 478 if (mandatory_byte) 479 ibi_ack_nack |= SVC_I3C_MCTRL_IBIRESP_ACK_WITH_BYTE; 480 else 481 ibi_ack_nack |= SVC_I3C_MCTRL_IBIRESP_ACK_WITHOUT_BYTE; 482 483 writel(ibi_ack_nack, master->regs + SVC_I3C_MCTRL); 484 485 return readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg, 486 SVC_I3C_MSTATUS_MCTRLDONE(reg), 1, 1000); 487 488 } 489 490 static int svc_i3c_master_nack_ibi(struct svc_i3c_master *master) 491 { 492 int ret; 493 u32 reg; 494 495 writel(SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK | 496 SVC_I3C_MCTRL_IBIRESP_NACK, 497 master->regs + SVC_I3C_MCTRL); 498 499 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg, 500 SVC_I3C_MSTATUS_MCTRLDONE(reg), 1, 1000); 501 return ret; 502 } 503 504 static int svc_i3c_master_handle_ibi_won(struct svc_i3c_master *master, u32 mstatus) 505 { 506 u32 ibitype; 507 int ret = 0; 508 509 ibitype = SVC_I3C_MSTATUS_IBITYPE(mstatus); 510 511 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); 512 513 /* Hardware can't auto emit NACK for hot join and master request */ 514 switch (ibitype) { 515 case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN: 516 case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST: 517 ret = svc_i3c_master_nack_ibi(master); 518 } 519 520 return ret; 521 } 522 523 static void svc_i3c_master_ibi_isr(struct svc_i3c_master *master) 524 { 525 struct svc_i3c_i2c_dev_data *data; 526 struct i3c_dev_desc *dev = NULL; 527 unsigned int ibitype, ibiaddr; 528 u32 status, val; 529 int ret; 530 531 /* 532 * According to I3C spec ver 1.1, 09-Jun-2021, section 5.1.2.5: 533 * 534 * The I3C Controller shall hold SCL low while the Bus is in ACK/NACK Phase of I3C/I2C 535 * transfer. But maximum stall time is 100us. The IRQs have to be disabled to prevent 536 * schedule during the whole I3C transaction, otherwise, the I3C bus timeout may happen if 537 * any irq or schedule happen during transaction. 538 */ 539 guard(spinlock)(&master->xferqueue.lock); 540 541 /* 542 * IBIWON may be set before SVC_I3C_MCTRL_REQUEST_AUTO_IBI, causing 543 * readl_relaxed_poll_timeout() to return immediately. Consequently, 544 * ibitype will be 0 since it was last updated only after the 8th SCL 545 * cycle, leading to missed client IBI handlers. 546 * 547 * A typical scenario is when IBIWON occurs and bus arbitration is lost 548 * at svc_i3c_master_i3c_xfers(). 549 * 550 * Clear SVC_I3C_MINT_IBIWON before sending SVC_I3C_MCTRL_REQUEST_AUTO_IBI. 551 */ 552 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); 553 554 /* 555 * Write REQUEST_START_ADDR request to emit broadcast address for arbitration, 556 * instend of using AUTO_IBI. 557 * 558 * Using AutoIBI request may cause controller to remain in AutoIBI state when 559 * there is a glitch on SDA line (high->low->high). 560 * 1. SDA high->low, raising an interrupt to execute IBI isr. 561 * 2. SDA low->high. 562 * 3. IBI isr writes an AutoIBI request. 563 * 4. The controller will not start AutoIBI process because SDA is not low. 564 * 5. IBIWON polling times out. 565 * 6. Controller remains in AutoIBI state and doesn't accept EmitStop request. 566 */ 567 writel(SVC_I3C_MCTRL_REQUEST_START_ADDR | 568 SVC_I3C_MCTRL_TYPE_I3C | 569 SVC_I3C_MCTRL_IBIRESP_MANUAL | 570 SVC_I3C_MCTRL_DIR(SVC_I3C_MCTRL_DIR_WRITE) | 571 SVC_I3C_MCTRL_ADDR(I3C_BROADCAST_ADDR), 572 master->regs + SVC_I3C_MCTRL); 573 574 /* Wait for IBIWON, should take approximately 100us */ 575 ret = readl_relaxed_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, val, 576 SVC_I3C_MSTATUS_IBIWON(val), 0, 100); 577 if (ret) { 578 dev_err(master->dev, "Timeout when polling for IBIWON\n"); 579 svc_i3c_master_emit_stop(master); 580 return; 581 } 582 583 status = readl(master->regs + SVC_I3C_MSTATUS); 584 ibitype = SVC_I3C_MSTATUS_IBITYPE(status); 585 ibiaddr = SVC_I3C_MSTATUS_IBIADDR(status); 586 587 /* Handle the critical responses to IBI's */ 588 switch (ibitype) { 589 case SVC_I3C_MSTATUS_IBITYPE_IBI: 590 dev = svc_i3c_master_dev_from_addr(master, ibiaddr); 591 if (!dev || !is_events_enabled(master, SVC_I3C_EVENT_IBI)) { 592 svc_i3c_master_nack_ibi(master); 593 } else { 594 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) 595 svc_i3c_master_ack_ibi(master, true); 596 else 597 svc_i3c_master_ack_ibi(master, false); 598 svc_i3c_master_handle_ibi(master, dev); 599 } 600 break; 601 case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN: 602 if (is_events_enabled(master, SVC_I3C_EVENT_HOTJOIN)) 603 svc_i3c_master_ack_ibi(master, false); 604 else 605 svc_i3c_master_nack_ibi(master); 606 break; 607 case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST: 608 svc_i3c_master_nack_ibi(master); 609 break; 610 default: 611 break; 612 } 613 614 /* 615 * If an error happened, we probably got interrupted and the exchange 616 * timedout. In this case we just drop everything, emit a stop and wait 617 * for the slave to interrupt again. 618 */ 619 if (svc_i3c_master_error(master)) { 620 if (master->ibi.tbq_slot && dev) { 621 data = i3c_dev_get_master_data(dev); 622 i3c_generic_ibi_recycle_slot(data->ibi_pool, 623 master->ibi.tbq_slot); 624 master->ibi.tbq_slot = NULL; 625 } 626 627 svc_i3c_master_emit_stop(master); 628 629 return; 630 } 631 632 /* Handle the non critical tasks */ 633 switch (ibitype) { 634 case SVC_I3C_MSTATUS_IBITYPE_IBI: 635 svc_i3c_master_emit_stop(master); 636 if (dev) { 637 i3c_master_queue_ibi(dev, master->ibi.tbq_slot); 638 master->ibi.tbq_slot = NULL; 639 } 640 break; 641 case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN: 642 svc_i3c_master_emit_stop(master); 643 if (is_events_enabled(master, SVC_I3C_EVENT_HOTJOIN)) 644 i3c_master_queue_hotjoin(&master->base); 645 break; 646 case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST: 647 svc_i3c_master_emit_stop(master); 648 649 /* 650 * If a target gets stuck holding SDA low, the controller reports a MR. 651 * On NPCM845, emitting STOP may spuriously set SLVSTART, retriggering 652 * the interrupt and re-entering MR handling, leading to an IRQ storm. 653 * Clear SLVSTART after STOP to break the loop. 654 */ 655 if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART)) 656 writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS); 657 break; 658 default: 659 break; 660 } 661 } 662 663 static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id) 664 { 665 struct svc_i3c_master *master = (struct svc_i3c_master *)dev_id; 666 u32 active = readl(master->regs + SVC_I3C_MSTATUS); 667 668 if (!SVC_I3C_MSTATUS_SLVSTART(active)) 669 return IRQ_NONE; 670 671 /* Clear the interrupt status */ 672 writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS); 673 674 if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART)) { 675 /* 676 * Re-read MSTATUS to obtain the latest state and avoid 677 * missing an IBI that arrives after MSTATUS is latched 678 * but before SLVSTART is cleared. 679 */ 680 active = readl(master->regs + SVC_I3C_MSTATUS); 681 682 /* Ignore the false event */ 683 if (!SVC_I3C_MSTATUS_STATE_SLVREQ(active)) 684 return IRQ_HANDLED; 685 } 686 687 /* 688 * The SDA line remains low until the request is processed. 689 * Receive the request in the interrupt context to respond promptly 690 * and restore the bus to idle state. 691 */ 692 svc_i3c_master_ibi_isr(master); 693 694 return IRQ_HANDLED; 695 } 696 697 static int svc_i3c_master_set_speed(struct i3c_master_controller *m, 698 enum i3c_open_drain_speed speed) 699 { 700 struct svc_i3c_master *master = to_svc_i3c_master(m); 701 struct i3c_bus *bus = i3c_master_get_bus(&master->base); 702 u32 ppbaud, odbaud, odhpp, mconfig; 703 unsigned long fclk_rate; 704 int ret; 705 706 ret = pm_runtime_resume_and_get(master->dev); 707 if (ret < 0) { 708 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); 709 return ret; 710 } 711 712 switch (speed) { 713 case I3C_OPEN_DRAIN_SLOW_SPEED: 714 fclk_rate = clk_get_rate(master->fclk); 715 if (!fclk_rate) { 716 ret = -EINVAL; 717 goto rpm_out; 718 } 719 /* 720 * Set 50% duty-cycle I2C speed to I3C OPEN-DRAIN mode, so the first 721 * broadcast address is visible to all I2C/I3C devices on the I3C bus. 722 * I3C device working as a I2C device will turn off its 50ns Spike 723 * Filter to change to I3C mode. 724 */ 725 mconfig = master->mctrl_config; 726 ppbaud = FIELD_GET(GENMASK(11, 8), mconfig); 727 odhpp = 0; 728 odbaud = DIV_ROUND_UP(fclk_rate, bus->scl_rate.i2c * (2 + 2 * ppbaud)) - 1; 729 mconfig &= ~GENMASK(24, 16); 730 mconfig |= SVC_I3C_MCONFIG_ODBAUD(odbaud) | SVC_I3C_MCONFIG_ODHPP(odhpp); 731 writel(mconfig, master->regs + SVC_I3C_MCONFIG); 732 break; 733 case I3C_OPEN_DRAIN_NORMAL_SPEED: 734 writel(master->mctrl_config, master->regs + SVC_I3C_MCONFIG); 735 break; 736 } 737 738 rpm_out: 739 pm_runtime_put_autosuspend(master->dev); 740 741 return ret; 742 } 743 744 static int svc_i3c_master_bus_init(struct i3c_master_controller *m) 745 { 746 struct svc_i3c_master *master = to_svc_i3c_master(m); 747 struct i3c_bus *bus = i3c_master_get_bus(m); 748 struct i3c_device_info info = {}; 749 unsigned long fclk_rate, fclk_period_ns; 750 unsigned long i2c_period_ns, i2c_scl_rate, i3c_scl_rate; 751 unsigned int high_period_ns, od_low_period_ns; 752 u32 ppbaud, pplow, odhpp, odbaud, odstop, i2cbaud, reg; 753 int ret; 754 755 ret = pm_runtime_resume_and_get(master->dev); 756 if (ret < 0) { 757 dev_err(master->dev, 758 "<%s> cannot resume i3c bus master, err: %d\n", 759 __func__, ret); 760 return ret; 761 } 762 763 /* Timings derivation */ 764 fclk_rate = clk_get_rate(master->fclk); 765 if (!fclk_rate) { 766 ret = -EINVAL; 767 goto rpm_out; 768 } 769 770 fclk_period_ns = DIV_ROUND_UP(1000000000, fclk_rate); 771 i2c_period_ns = DIV_ROUND_UP(1000000000, bus->scl_rate.i2c); 772 i2c_scl_rate = bus->scl_rate.i2c; 773 i3c_scl_rate = bus->scl_rate.i3c; 774 775 /* 776 * Using I3C Push-Pull mode, target is 12.5MHz/80ns period. 777 * Simplest configuration is using a 50% duty-cycle of 40ns. 778 */ 779 ppbaud = DIV_ROUND_UP(fclk_rate / 2, i3c_scl_rate) - 1; 780 pplow = 0; 781 782 /* 783 * Using I3C Open-Drain mode, target is 4.17MHz/240ns with a 784 * duty-cycle tuned so that high levels are filtered out by 785 * the 50ns filter (target being 40ns). 786 */ 787 odhpp = 1; 788 high_period_ns = (ppbaud + 1) * fclk_period_ns; 789 odbaud = DIV_ROUND_UP(fclk_rate, SVC_I3C_QUICK_I2C_CLK * (1 + ppbaud)) - 2; 790 od_low_period_ns = (odbaud + 1) * high_period_ns; 791 792 switch (bus->mode) { 793 case I3C_BUS_MODE_PURE: 794 i2cbaud = 0; 795 odstop = 0; 796 break; 797 case I3C_BUS_MODE_MIXED_FAST: 798 /* 799 * Using I2C Fm+ mode, target is 1MHz/1000ns, the difference 800 * between the high and low period does not really matter. 801 */ 802 i2cbaud = DIV_ROUND_UP(i2c_period_ns, od_low_period_ns) - 2; 803 odstop = 1; 804 break; 805 case I3C_BUS_MODE_MIXED_LIMITED: 806 case I3C_BUS_MODE_MIXED_SLOW: 807 /* I3C PP + I3C OP + I2C OP both use i2c clk rate */ 808 if (ppbaud > SVC_I3C_PPBAUD_MAX) { 809 ppbaud = SVC_I3C_PPBAUD_MAX; 810 pplow = DIV_ROUND_UP(fclk_rate, i3c_scl_rate) - (2 + 2 * ppbaud); 811 } 812 813 high_period_ns = (ppbaud + 1) * fclk_period_ns; 814 odhpp = 0; 815 odbaud = DIV_ROUND_UP(fclk_rate, i2c_scl_rate * (2 + 2 * ppbaud)) - 1; 816 817 od_low_period_ns = (odbaud + 1) * high_period_ns; 818 i2cbaud = DIV_ROUND_UP(i2c_period_ns, od_low_period_ns) - 2; 819 odstop = 1; 820 break; 821 default: 822 goto rpm_out; 823 } 824 825 reg = SVC_I3C_MCONFIG_MASTER_EN | 826 SVC_I3C_MCONFIG_DISTO(0) | 827 SVC_I3C_MCONFIG_HKEEP(0) | 828 SVC_I3C_MCONFIG_ODSTOP(odstop) | 829 SVC_I3C_MCONFIG_PPBAUD(ppbaud) | 830 SVC_I3C_MCONFIG_PPLOW(pplow) | 831 SVC_I3C_MCONFIG_ODBAUD(odbaud) | 832 SVC_I3C_MCONFIG_ODHPP(odhpp) | 833 SVC_I3C_MCONFIG_SKEW(0) | 834 SVC_I3C_MCONFIG_I2CBAUD(i2cbaud); 835 writel(reg, master->regs + SVC_I3C_MCONFIG); 836 837 master->mctrl_config = reg; 838 /* Master core's registration */ 839 ret = i3c_master_get_free_addr(m, 0); 840 if (ret < 0) 841 goto rpm_out; 842 843 info.dyn_addr = ret; 844 845 info.hdr_cap = I3C_CCC_HDR_MODE(I3C_HDR_DDR); 846 847 writel(SVC_MDYNADDR_VALID | SVC_MDYNADDR_ADDR(info.dyn_addr), 848 master->regs + SVC_I3C_MDYNADDR); 849 850 ret = i3c_master_set_info(&master->base, &info); 851 if (ret) 852 goto rpm_out; 853 854 rpm_out: 855 pm_runtime_put_autosuspend(master->dev); 856 857 return ret; 858 } 859 860 static void svc_i3c_master_bus_cleanup(struct i3c_master_controller *m) 861 { 862 struct svc_i3c_master *master = to_svc_i3c_master(m); 863 int ret; 864 865 ret = pm_runtime_resume_and_get(master->dev); 866 if (ret < 0) { 867 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); 868 return; 869 } 870 871 svc_i3c_master_disable_interrupts(master); 872 873 /* Disable master */ 874 writel(0, master->regs + SVC_I3C_MCONFIG); 875 876 pm_runtime_put_autosuspend(master->dev); 877 } 878 879 static int svc_i3c_master_reserve_slot(struct svc_i3c_master *master) 880 { 881 unsigned int slot; 882 883 if (!(master->free_slots & GENMASK(SVC_I3C_MAX_DEVS - 1, 0))) 884 return -ENOSPC; 885 886 slot = ffs(master->free_slots) - 1; 887 888 master->free_slots &= ~BIT(slot); 889 890 return slot; 891 } 892 893 static void svc_i3c_master_release_slot(struct svc_i3c_master *master, 894 unsigned int slot) 895 { 896 master->free_slots |= BIT(slot); 897 } 898 899 static int svc_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev) 900 { 901 struct i3c_master_controller *m = i3c_dev_get_master(dev); 902 struct svc_i3c_master *master = to_svc_i3c_master(m); 903 struct svc_i3c_i2c_dev_data *data; 904 int slot; 905 906 slot = svc_i3c_master_reserve_slot(master); 907 if (slot < 0) 908 return slot; 909 910 data = kzalloc_obj(*data); 911 if (!data) { 912 svc_i3c_master_release_slot(master, slot); 913 return -ENOMEM; 914 } 915 916 data->ibi = -1; 917 data->index = slot; 918 master->addrs[slot] = dev->info.dyn_addr ? dev->info.dyn_addr : 919 dev->info.static_addr; 920 master->descs[slot] = dev; 921 922 i3c_dev_set_master_data(dev, data); 923 924 return 0; 925 } 926 927 static int svc_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, 928 u8 old_dyn_addr) 929 { 930 struct i3c_master_controller *m = i3c_dev_get_master(dev); 931 struct svc_i3c_master *master = to_svc_i3c_master(m); 932 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 933 934 master->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr : 935 dev->info.static_addr; 936 937 return 0; 938 } 939 940 static void svc_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) 941 { 942 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 943 struct i3c_master_controller *m = i3c_dev_get_master(dev); 944 struct svc_i3c_master *master = to_svc_i3c_master(m); 945 946 master->addrs[data->index] = 0; 947 svc_i3c_master_release_slot(master, data->index); 948 949 kfree(data); 950 } 951 952 static int svc_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) 953 { 954 struct i3c_master_controller *m = i2c_dev_get_master(dev); 955 struct svc_i3c_master *master = to_svc_i3c_master(m); 956 struct svc_i3c_i2c_dev_data *data; 957 int slot; 958 959 slot = svc_i3c_master_reserve_slot(master); 960 if (slot < 0) 961 return slot; 962 963 data = kzalloc_obj(*data); 964 if (!data) { 965 svc_i3c_master_release_slot(master, slot); 966 return -ENOMEM; 967 } 968 969 data->index = slot; 970 master->addrs[slot] = dev->addr; 971 972 i2c_dev_set_master_data(dev, data); 973 974 return 0; 975 } 976 977 static void svc_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) 978 { 979 struct svc_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 980 struct i3c_master_controller *m = i2c_dev_get_master(dev); 981 struct svc_i3c_master *master = to_svc_i3c_master(m); 982 983 svc_i3c_master_release_slot(master, data->index); 984 985 kfree(data); 986 } 987 988 static int svc_i3c_master_readb(struct svc_i3c_master *master, u8 *dst, 989 unsigned int len) 990 { 991 int ret, i; 992 u32 reg; 993 994 for (i = 0; i < len; i++) { 995 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, 996 reg, 997 SVC_I3C_MSTATUS_RXPEND(reg), 998 0, 1000); 999 if (ret) 1000 return ret; 1001 1002 dst[i] = readl(master->regs + SVC_I3C_MRDATAB); 1003 } 1004 1005 return 0; 1006 } 1007 1008 static int svc_i3c_master_do_daa_locked(struct svc_i3c_master *master, 1009 u8 *addrs, unsigned int *count) 1010 { 1011 u64 prov_id[SVC_I3C_MAX_DEVS] = {}, nacking_prov_id = 0; 1012 unsigned int dev_nb = 0, last_addr = 0, dyn_addr = 0; 1013 u32 reg; 1014 int ret, i; 1015 1016 svc_i3c_master_flush_fifo(master); 1017 1018 while (true) { 1019 /* clean SVC_I3C_MINT_IBIWON w1c bits */ 1020 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); 1021 1022 /* SVC_I3C_MCTRL_REQUEST_PROC_DAA have two mode, ENTER DAA or PROCESS DAA. 1023 * 1024 * ENTER DAA: 1025 * 1 will issue START, 7E, ENTDAA, and then emits 7E/R to process first target. 1026 * 2 Stops just before the new Dynamic Address (DA) is to be emitted. 1027 * 1028 * PROCESS DAA: 1029 * 1 The DA is written using MWDATAB or ADDR bits 6:0. 1030 * 2 ProcessDAA is requested again to write the new address, and then starts the 1031 * next (START, 7E, ENTDAA) unless marked to STOP; an MSTATUS indicating NACK 1032 * means DA was not accepted (e.g. parity error). If PROCESSDAA is NACKed on the 1033 * 7E/R, which means no more Slaves need a DA, then a COMPLETE will be signaled 1034 * (along with DONE), and a STOP issued automatically. 1035 */ 1036 writel(SVC_I3C_MCTRL_REQUEST_PROC_DAA | 1037 SVC_I3C_MCTRL_TYPE_I3C | 1038 SVC_I3C_MCTRL_IBIRESP_NACK | 1039 SVC_I3C_MCTRL_DIR(SVC_I3C_MCTRL_DIR_WRITE), 1040 master->regs + SVC_I3C_MCTRL); 1041 1042 /* 1043 * Either one slave will send its ID, or the assignment process 1044 * is done. 1045 */ 1046 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, 1047 reg, 1048 SVC_I3C_MSTATUS_RXPEND(reg) | 1049 SVC_I3C_MSTATUS_MCTRLDONE(reg), 1050 1, 1000); 1051 if (ret) 1052 break; 1053 1054 if (SVC_I3C_MSTATUS_RXPEND(reg)) { 1055 u8 data[6]; 1056 1057 /* 1058 * One slave sends its ID to request for address assignment, 1059 * prefilling the dynamic address can reduce SCL clock stalls 1060 * and also fix the SVC_I3C_QUIRK_FIFO_EMPTY quirk. 1061 * 1062 * Ideally, prefilling before the processDAA command is better. 1063 * However, it requires an additional check to write the dyn_addr 1064 * at the right time because the driver needs to write the processDAA 1065 * command twice for one assignment. 1066 * Prefilling here is safe and efficient because the FIFO starts 1067 * filling within a few hundred nanoseconds, which is significantly 1068 * faster compared to the 64 SCL clock cycles. 1069 */ 1070 ret = i3c_master_get_free_addr(&master->base, last_addr + 1); 1071 if (ret < 0) 1072 break; 1073 1074 dyn_addr = ret; 1075 writel(dyn_addr, master->regs + SVC_I3C_MWDATAB); 1076 1077 /* 1078 * We only care about the 48-bit provisioned ID yet to 1079 * be sure a device does not nack an address twice. 1080 * Otherwise, we would just need to flush the RX FIFO. 1081 */ 1082 ret = svc_i3c_master_readb(master, data, 6); 1083 if (ret) 1084 break; 1085 1086 for (i = 0; i < 6; i++) 1087 prov_id[dev_nb] |= (u64)(data[i]) << (8 * (5 - i)); 1088 1089 /* We do not care about the BCR and DCR yet */ 1090 ret = svc_i3c_master_readb(master, data, 2); 1091 if (ret) 1092 break; 1093 } else if (SVC_I3C_MSTATUS_IBIWON(reg)) { 1094 ret = svc_i3c_master_handle_ibi_won(master, reg); 1095 if (ret) 1096 break; 1097 continue; 1098 } else if (SVC_I3C_MSTATUS_MCTRLDONE(reg)) { 1099 if (SVC_I3C_MSTATUS_STATE_IDLE(reg) && 1100 SVC_I3C_MSTATUS_COMPLETE(reg)) { 1101 /* 1102 * All devices received and acked they dynamic 1103 * address, this is the natural end of the DAA 1104 * procedure. 1105 * 1106 * Hardware will auto emit STOP at this case. 1107 */ 1108 *count = dev_nb; 1109 return 0; 1110 1111 } else if (SVC_I3C_MSTATUS_NACKED(reg)) { 1112 /* No I3C devices attached */ 1113 if (dev_nb == 0) { 1114 /* 1115 * Hardware can't treat first NACK for ENTAA as normal 1116 * COMPLETE. So need manual emit STOP. 1117 */ 1118 ret = 0; 1119 *count = 0; 1120 break; 1121 } 1122 1123 /* 1124 * A slave device nacked the address, this is 1125 * allowed only once, DAA will be stopped and 1126 * then resumed. The same device is supposed to 1127 * answer again immediately and shall ack the 1128 * address this time. 1129 */ 1130 if (prov_id[dev_nb] == nacking_prov_id) { 1131 ret = -EIO; 1132 break; 1133 } 1134 1135 dev_nb--; 1136 nacking_prov_id = prov_id[dev_nb]; 1137 svc_i3c_master_emit_stop(master); 1138 1139 continue; 1140 } else { 1141 break; 1142 } 1143 } 1144 1145 /* Wait for the slave to be ready to receive its address */ 1146 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, 1147 reg, 1148 SVC_I3C_MSTATUS_MCTRLDONE(reg) && 1149 SVC_I3C_MSTATUS_STATE_DAA(reg) && 1150 SVC_I3C_MSTATUS_BETWEEN(reg), 1151 0, 1000); 1152 if (ret) 1153 break; 1154 1155 addrs[dev_nb] = dyn_addr; 1156 dev_dbg(master->dev, "DAA: device %d assigned to 0x%02x\n", 1157 dev_nb, addrs[dev_nb]); 1158 last_addr = addrs[dev_nb++]; 1159 } 1160 1161 /* Need manual issue STOP except for Complete condition */ 1162 svc_i3c_master_emit_stop(master); 1163 svc_i3c_master_flush_fifo(master); 1164 1165 return ret; 1166 } 1167 1168 static int svc_i3c_update_ibirules(struct svc_i3c_master *master) 1169 { 1170 struct i3c_dev_desc *dev; 1171 u32 reg_mbyte = 0, reg_nobyte = SVC_I3C_IBIRULES_NOBYTE; 1172 unsigned int mbyte_addr_ok = 0, mbyte_addr_ko = 0, nobyte_addr_ok = 0, 1173 nobyte_addr_ko = 0; 1174 bool list_mbyte = false, list_nobyte = false; 1175 1176 /* Create the IBIRULES register for both cases */ 1177 i3c_bus_for_each_i3cdev(&master->base.bus, dev) { 1178 if (!(dev->info.bcr & I3C_BCR_IBI_REQ_CAP)) 1179 continue; 1180 1181 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) { 1182 reg_mbyte |= SVC_I3C_IBIRULES_ADDR(mbyte_addr_ok, 1183 dev->info.dyn_addr); 1184 1185 /* IBI rules cannot be applied to devices with MSb=1 */ 1186 if (dev->info.dyn_addr & BIT(7)) 1187 mbyte_addr_ko++; 1188 else 1189 mbyte_addr_ok++; 1190 } else { 1191 reg_nobyte |= SVC_I3C_IBIRULES_ADDR(nobyte_addr_ok, 1192 dev->info.dyn_addr); 1193 1194 /* IBI rules cannot be applied to devices with MSb=1 */ 1195 if (dev->info.dyn_addr & BIT(7)) 1196 nobyte_addr_ko++; 1197 else 1198 nobyte_addr_ok++; 1199 } 1200 } 1201 1202 /* Device list cannot be handled by hardware */ 1203 if (!mbyte_addr_ko && mbyte_addr_ok <= SVC_I3C_IBIRULES_ADDRS) 1204 list_mbyte = true; 1205 1206 if (!nobyte_addr_ko && nobyte_addr_ok <= SVC_I3C_IBIRULES_ADDRS) 1207 list_nobyte = true; 1208 1209 /* No list can be properly handled, return an error */ 1210 if (!list_mbyte && !list_nobyte) 1211 return -ERANGE; 1212 1213 /* Pick the first list that can be handled by hardware, randomly */ 1214 if (list_mbyte) 1215 writel(reg_mbyte, master->regs + SVC_I3C_IBIRULES); 1216 else 1217 writel(reg_nobyte, master->regs + SVC_I3C_IBIRULES); 1218 1219 return 0; 1220 } 1221 1222 static int svc_i3c_master_do_daa(struct i3c_master_controller *m) 1223 { 1224 struct svc_i3c_master *master = to_svc_i3c_master(m); 1225 u8 addrs[SVC_I3C_MAX_DEVS]; 1226 unsigned long flags; 1227 unsigned int dev_nb; 1228 int ret, i; 1229 1230 ret = pm_runtime_resume_and_get(master->dev); 1231 if (ret < 0) { 1232 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); 1233 return ret; 1234 } 1235 1236 spin_lock_irqsave(&master->xferqueue.lock, flags); 1237 1238 if (svc_has_daa_corrupt(master)) 1239 writel(master->mctrl_config | SVC_I3C_MCONFIG_SKEW(1), 1240 master->regs + SVC_I3C_MCONFIG); 1241 1242 ret = svc_i3c_master_do_daa_locked(master, addrs, &dev_nb); 1243 1244 if (svc_has_daa_corrupt(master)) 1245 writel(master->mctrl_config, master->regs + SVC_I3C_MCONFIG); 1246 1247 spin_unlock_irqrestore(&master->xferqueue.lock, flags); 1248 1249 svc_i3c_master_clear_merrwarn(master); 1250 if (ret) 1251 goto rpm_out; 1252 1253 /* 1254 * Register all devices who participated to the core 1255 * 1256 * If two devices (A and B) are detected in DAA and address 0xa is assigned to 1257 * device A and 0xb to device B, a failure in i3c_master_add_i3c_dev_locked() 1258 * for device A (addr: 0xa) could prevent device B (addr: 0xb) from being 1259 * registered on the bus. The I3C stack might still consider 0xb a free 1260 * address. If a subsequent Hotjoin occurs, 0xb might be assigned to Device A, 1261 * causing both devices A and B to use the same address 0xb, violating the I3C 1262 * specification. 1263 * 1264 * The return value for i3c_master_add_i3c_dev_locked() should not be checked 1265 * because subsequent steps will scan the entire I3C bus, independent of 1266 * whether i3c_master_add_i3c_dev_locked() returns success. 1267 * 1268 * If device A registration fails, there is still a chance to register device 1269 * B. i3c_master_add_i3c_dev_locked() can reset DAA if a failure occurs while 1270 * retrieving device information. 1271 */ 1272 for (i = 0; i < dev_nb; i++) 1273 i3c_master_add_i3c_dev_locked(m, addrs[i]); 1274 1275 /* Configure IBI auto-rules */ 1276 ret = svc_i3c_update_ibirules(master); 1277 if (ret) 1278 dev_err(master->dev, "Cannot handle such a list of devices\n"); 1279 1280 rpm_out: 1281 pm_runtime_put_autosuspend(master->dev); 1282 1283 return ret; 1284 } 1285 1286 static int svc_i3c_master_read(struct svc_i3c_master *master, 1287 u8 *in, unsigned int len) 1288 { 1289 int offset = 0, i; 1290 u32 mdctrl, mstatus; 1291 bool completed = false; 1292 unsigned int count; 1293 unsigned long start = jiffies; 1294 1295 while (!completed) { 1296 mstatus = readl(master->regs + SVC_I3C_MSTATUS); 1297 if (SVC_I3C_MSTATUS_COMPLETE(mstatus) != 0) 1298 completed = true; 1299 1300 if (time_after(jiffies, start + msecs_to_jiffies(1000))) { 1301 dev_dbg(master->dev, "I3C read timeout\n"); 1302 return -ETIMEDOUT; 1303 } 1304 1305 mdctrl = readl(master->regs + SVC_I3C_MDATACTRL); 1306 count = SVC_I3C_MDATACTRL_RXCOUNT(mdctrl); 1307 if (offset + count > len) { 1308 dev_err(master->dev, "I3C receive length too long!\n"); 1309 return -EINVAL; 1310 } 1311 for (i = 0; i < count; i++) 1312 in[offset + i] = readl(master->regs + SVC_I3C_MRDATAB); 1313 1314 offset += count; 1315 } 1316 1317 return offset; 1318 } 1319 1320 static int svc_i3c_master_write(struct svc_i3c_master *master, 1321 const u8 *out, unsigned int len) 1322 { 1323 int offset = 0, ret; 1324 u32 mdctrl; 1325 1326 while (offset < len) { 1327 ret = readl_poll_timeout(master->regs + SVC_I3C_MDATACTRL, 1328 mdctrl, 1329 !(mdctrl & SVC_I3C_MDATACTRL_TXFULL), 1330 0, 1000); 1331 if (ret) 1332 return ret; 1333 1334 /* 1335 * The last byte to be sent over the bus must either have the 1336 * "end" bit set or be written in MWDATABE. 1337 */ 1338 if (likely(offset < (len - 1))) 1339 writel(out[offset++], master->regs + SVC_I3C_MWDATAB); 1340 else 1341 writel(out[offset++], master->regs + SVC_I3C_MWDATABE); 1342 } 1343 1344 return 0; 1345 } 1346 1347 static int svc_i3c_master_xfer(struct svc_i3c_master *master, 1348 u32 rnw_cmd, unsigned int xfer_type, u8 addr, 1349 u8 *in, const u8 *out, unsigned int xfer_len, 1350 unsigned int *actual_len, bool continued, bool repeat_start) 1351 { 1352 bool rnw = svc_cmd_is_read(rnw_cmd, xfer_type); 1353 int retry = repeat_start ? 1 : 2; 1354 u32 reg; 1355 int ret; 1356 1357 /* clean SVC_I3C_MINT_IBIWON w1c bits */ 1358 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); 1359 1360 if (xfer_type == SVC_I3C_MCTRL_TYPE_DDR) { 1361 /* DDR command need prefill into FIFO */ 1362 writel(rnw_cmd, master->regs + SVC_I3C_MWDATAB); 1363 if (!rnw) { 1364 /* write data also need prefill into FIFO */ 1365 ret = svc_i3c_master_write(master, out, xfer_len); 1366 if (ret) 1367 goto emit_stop; 1368 } 1369 } 1370 1371 while (retry--) { 1372 writel(SVC_I3C_MCTRL_REQUEST_START_ADDR | 1373 xfer_type | 1374 SVC_I3C_MCTRL_IBIRESP_NACK | 1375 SVC_I3C_MCTRL_DIR(rnw) | 1376 SVC_I3C_MCTRL_ADDR(addr) | 1377 SVC_I3C_MCTRL_RDTERM(*actual_len), 1378 master->regs + SVC_I3C_MCTRL); 1379 1380 /* 1381 * The entire transaction can consist of multiple write transfers. 1382 * Prefilling before EmitStartAddr causes the data to be emitted 1383 * immediately, becoming part of the previous transfer. 1384 * The only way to work around this hardware issue is to let the 1385 * FIFO start filling as soon as possible after EmitStartAddr. 1386 */ 1387 if (svc_has_quirk(master, SVC_I3C_QUIRK_FIFO_EMPTY) && !rnw && xfer_len) { 1388 u32 space, end, len; 1389 1390 reg = readl(master->regs + SVC_I3C_MDATACTRL); 1391 space = SVC_I3C_FIFO_SIZE - SVC_I3C_MDATACTRL_TXCOUNT(reg); 1392 if (space) { 1393 end = xfer_len > space ? 0 : SVC_I3C_MWDATAB_END; 1394 len = min_t(u32, xfer_len, space); 1395 writesb(master->regs + SVC_I3C_MWDATAB1, out, len - 1); 1396 /* Mark END bit if this is the last byte */ 1397 writel(out[len - 1] | end, master->regs + SVC_I3C_MWDATAB); 1398 xfer_len -= len; 1399 out += len; 1400 } 1401 } 1402 1403 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, 1404 SVC_I3C_MSTATUS_MCTRLDONE(reg), 0, 1000); 1405 if (ret) 1406 goto emit_stop; 1407 1408 /* 1409 * According to I3C spec ver 1.1.1, 5.1.2.2.3 Consequence of Controller Starting a 1410 * Frame with I3C Target Address. 1411 * 1412 * The I3C Controller normally should start a Frame, the Address may be arbitrated, 1413 * and so the Controller shall monitor to see whether an In-Band Interrupt request, 1414 * a Controller Role Request (i.e., Secondary Controller requests to become the 1415 * Active Controller), or a Hot-Join Request has been made. 1416 * 1417 * If missed IBIWON check, the wrong data will be return. When IBIWON happen, issue 1418 * repeat start. Address arbitrate only happen at START, never happen at REPEAT 1419 * start. 1420 */ 1421 if (SVC_I3C_MSTATUS_IBIWON(reg)) { 1422 ret = svc_i3c_master_handle_ibi_won(master, reg); 1423 if (ret) 1424 goto emit_stop; 1425 continue; 1426 } 1427 1428 if (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_NACK) { 1429 /* 1430 * According to I3C Spec 1.1.1, 11-Jun-2021, section: 5.1.2.2.3. 1431 * If the Controller chooses to start an I3C Message with an I3C Dynamic 1432 * Address, then special provisions shall be made because that same I3C 1433 * Target may be initiating an IBI or a Controller Role Request. So, one of 1434 * three things may happen: (skip 1, 2) 1435 * 1436 * 3. The Addresses match and the RnW bits also match, and so neither 1437 * Controller nor Target will ACK since both are expecting the other side to 1438 * provide ACK. As a result, each side might think it had "won" arbitration, 1439 * but neither side would continue, as each would subsequently see that the 1440 * other did not provide ACK. 1441 * ... 1442 * For either value of RnW: Due to the NACK, the Controller shall defer the 1443 * Private Write or Private Read, and should typically transmit the Target 1444 * Address again after a Repeated START (i.e., the next one or any one prior 1445 * to a STOP in the Frame). Since the Address Header following a Repeated 1446 * START is not arbitrated, the Controller will always win (see Section 1447 * 5.1.2.2.4). 1448 */ 1449 if (retry && addr != 0x7e) { 1450 writel(SVC_I3C_MERRWARN_NACK, master->regs + SVC_I3C_MERRWARN); 1451 } else { 1452 ret = -ENXIO; 1453 *actual_len = 0; 1454 goto emit_stop; 1455 } 1456 } else { 1457 break; 1458 } 1459 } 1460 1461 if (rnw) 1462 ret = svc_i3c_master_read(master, in, xfer_len); 1463 else if (xfer_type != SVC_I3C_MCTRL_TYPE_DDR) 1464 ret = svc_i3c_master_write(master, out, xfer_len); 1465 if (ret < 0) 1466 goto emit_stop; 1467 1468 if (rnw) 1469 *actual_len = ret; 1470 1471 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, 1472 SVC_I3C_MSTATUS_COMPLETE(reg), 0, 1000); 1473 if (ret) 1474 goto emit_stop; 1475 1476 if (xfer_type == SVC_I3C_MCTRL_TYPE_DDR && 1477 (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_CRC)) { 1478 ret = -ENXIO; 1479 goto emit_stop; 1480 } 1481 1482 writel(SVC_I3C_MINT_COMPLETE, master->regs + SVC_I3C_MSTATUS); 1483 1484 if (!continued) { 1485 if (xfer_type != SVC_I3C_MCTRL_TYPE_DDR) 1486 svc_i3c_master_emit_stop(master); 1487 else 1488 svc_i3c_master_emit_force_exit(master); 1489 1490 /* Wait idle if stop is sent. */ 1491 readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, 1492 SVC_I3C_MSTATUS_STATE_IDLE(reg), 0, 1000); 1493 } 1494 1495 return 0; 1496 1497 emit_stop: 1498 if (xfer_type != SVC_I3C_MCTRL_TYPE_DDR) 1499 svc_i3c_master_emit_stop(master); 1500 else 1501 svc_i3c_master_emit_force_exit(master); 1502 1503 svc_i3c_master_clear_merrwarn(master); 1504 svc_i3c_master_flush_fifo(master); 1505 1506 return ret; 1507 } 1508 1509 static struct svc_i3c_xfer * 1510 svc_i3c_master_alloc_xfer(struct svc_i3c_master *master, unsigned int ncmds) 1511 { 1512 struct svc_i3c_xfer *xfer; 1513 1514 xfer = kzalloc_flex(*xfer, cmds, ncmds); 1515 if (!xfer) 1516 return NULL; 1517 1518 INIT_LIST_HEAD(&xfer->node); 1519 xfer->ncmds = ncmds; 1520 xfer->ret = -ETIMEDOUT; 1521 1522 return xfer; 1523 } 1524 1525 static void svc_i3c_master_free_xfer(struct svc_i3c_xfer *xfer) 1526 { 1527 kfree(xfer); 1528 } 1529 1530 static void svc_i3c_master_dequeue_xfer_locked(struct svc_i3c_master *master, 1531 struct svc_i3c_xfer *xfer) 1532 { 1533 if (master->xferqueue.cur == xfer) 1534 master->xferqueue.cur = NULL; 1535 else 1536 list_del_init(&xfer->node); 1537 } 1538 1539 static void svc_i3c_master_dequeue_xfer(struct svc_i3c_master *master, 1540 struct svc_i3c_xfer *xfer) 1541 { 1542 unsigned long flags; 1543 1544 spin_lock_irqsave(&master->xferqueue.lock, flags); 1545 svc_i3c_master_dequeue_xfer_locked(master, xfer); 1546 spin_unlock_irqrestore(&master->xferqueue.lock, flags); 1547 } 1548 1549 static int i3c_mode_to_svc_type(enum i3c_xfer_mode mode) 1550 { 1551 return (mode == I3C_SDR) ? SVC_I3C_MCTRL_TYPE_I3C : SVC_I3C_MCTRL_TYPE_DDR; 1552 } 1553 1554 static void svc_i3c_master_start_xfer_locked(struct svc_i3c_master *master) 1555 { 1556 struct svc_i3c_xfer *xfer = master->xferqueue.cur; 1557 int ret, i; 1558 1559 if (!xfer) 1560 return; 1561 1562 svc_i3c_master_clear_merrwarn(master); 1563 svc_i3c_master_flush_fifo(master); 1564 1565 for (i = 0; i < xfer->ncmds; i++) { 1566 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; 1567 1568 ret = svc_i3c_master_xfer(master, cmd->rnw_cmd, xfer->type, 1569 cmd->addr, cmd->in, cmd->out, 1570 cmd->len, &cmd->actual_len, 1571 cmd->continued, i > 0); 1572 /* cmd->xfer is NULL if I2C or CCC transfer */ 1573 if (cmd->xfer) 1574 cmd->xfer->actual_len = cmd->actual_len; 1575 1576 if (ret) 1577 break; 1578 } 1579 1580 xfer->ret = ret; 1581 complete(&xfer->comp); 1582 1583 if (ret < 0) 1584 svc_i3c_master_dequeue_xfer_locked(master, xfer); 1585 1586 xfer = list_first_entry_or_null(&master->xferqueue.list, 1587 struct svc_i3c_xfer, 1588 node); 1589 if (xfer) 1590 list_del_init(&xfer->node); 1591 1592 master->xferqueue.cur = xfer; 1593 svc_i3c_master_start_xfer_locked(master); 1594 } 1595 1596 static void svc_i3c_master_enqueue_xfer(struct svc_i3c_master *master, 1597 struct svc_i3c_xfer *xfer) 1598 { 1599 unsigned long flags; 1600 int ret; 1601 1602 ret = pm_runtime_resume_and_get(master->dev); 1603 if (ret < 0) { 1604 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); 1605 return; 1606 } 1607 1608 init_completion(&xfer->comp); 1609 spin_lock_irqsave(&master->xferqueue.lock, flags); 1610 if (master->xferqueue.cur) { 1611 list_add_tail(&xfer->node, &master->xferqueue.list); 1612 } else { 1613 master->xferqueue.cur = xfer; 1614 svc_i3c_master_start_xfer_locked(master); 1615 } 1616 spin_unlock_irqrestore(&master->xferqueue.lock, flags); 1617 1618 pm_runtime_put_autosuspend(master->dev); 1619 } 1620 1621 static bool 1622 svc_i3c_master_supports_ccc_cmd(struct i3c_master_controller *master, 1623 const struct i3c_ccc_cmd *cmd) 1624 { 1625 /* No software support for CCC commands targeting more than one slave */ 1626 return (cmd->ndests == 1); 1627 } 1628 1629 static int svc_i3c_master_send_bdcast_ccc_cmd(struct svc_i3c_master *master, 1630 struct i3c_ccc_cmd *ccc) 1631 { 1632 unsigned int xfer_len = ccc->dests[0].payload.len + 1; 1633 struct svc_i3c_xfer *xfer; 1634 struct svc_i3c_cmd *cmd; 1635 u8 *buf; 1636 int ret; 1637 1638 xfer = svc_i3c_master_alloc_xfer(master, 1); 1639 if (!xfer) 1640 return -ENOMEM; 1641 1642 buf = kmalloc(xfer_len, GFP_KERNEL); 1643 if (!buf) { 1644 svc_i3c_master_free_xfer(xfer); 1645 return -ENOMEM; 1646 } 1647 1648 buf[0] = ccc->id; 1649 memcpy(&buf[1], ccc->dests[0].payload.data, ccc->dests[0].payload.len); 1650 1651 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; 1652 1653 cmd = &xfer->cmds[0]; 1654 cmd->addr = ccc->dests[0].addr; 1655 cmd->rnw = ccc->rnw; 1656 cmd->in = NULL; 1657 cmd->out = buf; 1658 cmd->len = xfer_len; 1659 cmd->actual_len = 0; 1660 cmd->continued = false; 1661 1662 mutex_lock(&master->lock); 1663 svc_i3c_master_enqueue_xfer(master, xfer); 1664 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) 1665 svc_i3c_master_dequeue_xfer(master, xfer); 1666 mutex_unlock(&master->lock); 1667 1668 ret = xfer->ret; 1669 kfree(buf); 1670 svc_i3c_master_free_xfer(xfer); 1671 1672 return ret; 1673 } 1674 1675 static int svc_i3c_master_send_direct_ccc_cmd(struct svc_i3c_master *master, 1676 struct i3c_ccc_cmd *ccc) 1677 { 1678 unsigned int xfer_len = ccc->dests[0].payload.len; 1679 unsigned int actual_len = ccc->rnw ? xfer_len : 0; 1680 struct svc_i3c_xfer *xfer; 1681 struct svc_i3c_cmd *cmd; 1682 int ret; 1683 1684 xfer = svc_i3c_master_alloc_xfer(master, 2); 1685 if (!xfer) 1686 return -ENOMEM; 1687 1688 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; 1689 1690 /* Broadcasted message */ 1691 cmd = &xfer->cmds[0]; 1692 cmd->addr = I3C_BROADCAST_ADDR; 1693 cmd->rnw = 0; 1694 cmd->in = NULL; 1695 cmd->out = &ccc->id; 1696 cmd->len = 1; 1697 cmd->actual_len = 0; 1698 cmd->continued = true; 1699 1700 /* Directed message */ 1701 cmd = &xfer->cmds[1]; 1702 cmd->addr = ccc->dests[0].addr; 1703 cmd->rnw = ccc->rnw; 1704 cmd->in = ccc->rnw ? ccc->dests[0].payload.data : NULL; 1705 cmd->out = ccc->rnw ? NULL : ccc->dests[0].payload.data; 1706 cmd->len = xfer_len; 1707 cmd->actual_len = actual_len; 1708 cmd->continued = false; 1709 1710 mutex_lock(&master->lock); 1711 svc_i3c_master_enqueue_xfer(master, xfer); 1712 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) 1713 svc_i3c_master_dequeue_xfer(master, xfer); 1714 mutex_unlock(&master->lock); 1715 1716 if (cmd->actual_len != xfer_len) 1717 ccc->dests[0].payload.len = cmd->actual_len; 1718 1719 ret = xfer->ret; 1720 svc_i3c_master_free_xfer(xfer); 1721 1722 return ret; 1723 } 1724 1725 static int svc_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, 1726 struct i3c_ccc_cmd *cmd) 1727 { 1728 struct svc_i3c_master *master = to_svc_i3c_master(m); 1729 bool broadcast = cmd->id < 0x80; 1730 int ret; 1731 1732 if (broadcast) 1733 ret = svc_i3c_master_send_bdcast_ccc_cmd(master, cmd); 1734 else 1735 ret = svc_i3c_master_send_direct_ccc_cmd(master, cmd); 1736 1737 if (ret) 1738 cmd->err = I3C_ERROR_M2; 1739 1740 return ret; 1741 } 1742 1743 static int svc_i3c_master_i3c_xfers(struct i3c_dev_desc *dev, struct i3c_xfer *xfers, 1744 int nxfers, enum i3c_xfer_mode mode) 1745 { 1746 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1747 struct svc_i3c_master *master = to_svc_i3c_master(m); 1748 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1749 struct svc_i3c_xfer *xfer; 1750 int ret, i; 1751 1752 if (mode != I3C_SDR) { 1753 /* 1754 * Only support data size less than FIFO SIZE when using DDR 1755 * mode. First entry is cmd in FIFO, so actual available FIFO 1756 * for data is SVC_I3C_FIFO_SIZE - 2 since DDR only supports 1757 * even length. 1758 */ 1759 for (i = 0; i < nxfers; i++) 1760 if (xfers[i].len > SVC_I3C_FIFO_SIZE - 2) 1761 return -EINVAL; 1762 } 1763 1764 xfer = svc_i3c_master_alloc_xfer(master, nxfers); 1765 if (!xfer) 1766 return -ENOMEM; 1767 1768 xfer->type = i3c_mode_to_svc_type(mode); 1769 1770 for (i = 0; i < nxfers; i++) { 1771 u32 rnw_cmd = (mode == I3C_SDR) ? xfers[i].rnw : xfers[i].cmd; 1772 bool rnw = svc_cmd_is_read(rnw_cmd, xfer->type); 1773 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; 1774 1775 cmd->xfer = &xfers[i]; 1776 cmd->addr = master->addrs[data->index]; 1777 cmd->rnw_cmd = rnw_cmd; 1778 cmd->in = rnw ? xfers[i].data.in : NULL; 1779 cmd->out = rnw ? NULL : xfers[i].data.out; 1780 cmd->len = xfers[i].len; 1781 cmd->actual_len = rnw ? xfers[i].len : 0; 1782 cmd->continued = (i + 1) < nxfers; 1783 } 1784 1785 mutex_lock(&master->lock); 1786 svc_i3c_master_enqueue_xfer(master, xfer); 1787 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) 1788 svc_i3c_master_dequeue_xfer(master, xfer); 1789 mutex_unlock(&master->lock); 1790 1791 ret = xfer->ret; 1792 svc_i3c_master_free_xfer(xfer); 1793 1794 return ret; 1795 } 1796 1797 static int svc_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, 1798 struct i2c_msg *xfers, 1799 int nxfers) 1800 { 1801 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1802 struct svc_i3c_master *master = to_svc_i3c_master(m); 1803 struct svc_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 1804 struct svc_i3c_xfer *xfer; 1805 int ret, i; 1806 1807 xfer = svc_i3c_master_alloc_xfer(master, nxfers); 1808 if (!xfer) 1809 return -ENOMEM; 1810 1811 xfer->type = SVC_I3C_MCTRL_TYPE_I2C; 1812 1813 for (i = 0; i < nxfers; i++) { 1814 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; 1815 1816 cmd->addr = master->addrs[data->index]; 1817 cmd->rnw = xfers[i].flags & I2C_M_RD; 1818 cmd->in = cmd->rnw ? xfers[i].buf : NULL; 1819 cmd->out = cmd->rnw ? NULL : xfers[i].buf; 1820 cmd->len = xfers[i].len; 1821 cmd->actual_len = cmd->rnw ? xfers[i].len : 0; 1822 cmd->continued = (i + 1 < nxfers); 1823 } 1824 1825 mutex_lock(&master->lock); 1826 svc_i3c_master_enqueue_xfer(master, xfer); 1827 if (!wait_for_completion_timeout(&xfer->comp, m->i2c.timeout)) 1828 svc_i3c_master_dequeue_xfer(master, xfer); 1829 mutex_unlock(&master->lock); 1830 1831 ret = xfer->ret; 1832 svc_i3c_master_free_xfer(xfer); 1833 1834 return ret; 1835 } 1836 1837 static int svc_i3c_master_request_ibi(struct i3c_dev_desc *dev, 1838 const struct i3c_ibi_setup *req) 1839 { 1840 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1841 struct svc_i3c_master *master = to_svc_i3c_master(m); 1842 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1843 unsigned long flags; 1844 unsigned int i; 1845 1846 if (dev->ibi->max_payload_len > SVC_I3C_FIFO_SIZE) { 1847 dev_err(master->dev, "IBI max payload %d should be < %d\n", 1848 dev->ibi->max_payload_len, SVC_I3C_FIFO_SIZE); 1849 return -ERANGE; 1850 } 1851 1852 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); 1853 if (IS_ERR(data->ibi_pool)) 1854 return PTR_ERR(data->ibi_pool); 1855 1856 spin_lock_irqsave(&master->ibi.lock, flags); 1857 for (i = 0; i < master->ibi.num_slots; i++) { 1858 if (!master->ibi.slots[i]) { 1859 data->ibi = i; 1860 master->ibi.slots[i] = dev; 1861 break; 1862 } 1863 } 1864 spin_unlock_irqrestore(&master->ibi.lock, flags); 1865 1866 if (i < master->ibi.num_slots) 1867 return 0; 1868 1869 i3c_generic_ibi_free_pool(data->ibi_pool); 1870 data->ibi_pool = NULL; 1871 1872 return -ENOSPC; 1873 } 1874 1875 static void svc_i3c_master_free_ibi(struct i3c_dev_desc *dev) 1876 { 1877 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1878 struct svc_i3c_master *master = to_svc_i3c_master(m); 1879 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1880 unsigned long flags; 1881 1882 spin_lock_irqsave(&master->ibi.lock, flags); 1883 master->ibi.slots[data->ibi] = NULL; 1884 data->ibi = -1; 1885 spin_unlock_irqrestore(&master->ibi.lock, flags); 1886 1887 i3c_generic_ibi_free_pool(data->ibi_pool); 1888 } 1889 1890 static int svc_i3c_master_enable_ibi(struct i3c_dev_desc *dev) 1891 { 1892 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1893 struct svc_i3c_master *master = to_svc_i3c_master(m); 1894 int ret; 1895 1896 ret = pm_runtime_resume_and_get(master->dev); 1897 if (ret < 0) { 1898 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); 1899 return ret; 1900 } 1901 1902 master->enabled_events++; 1903 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART); 1904 1905 return i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); 1906 } 1907 1908 static int svc_i3c_master_disable_ibi(struct i3c_dev_desc *dev) 1909 { 1910 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1911 struct svc_i3c_master *master = to_svc_i3c_master(m); 1912 int ret; 1913 1914 master->enabled_events--; 1915 if (!master->enabled_events) 1916 svc_i3c_master_disable_interrupts(master); 1917 1918 ret = i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); 1919 1920 pm_runtime_put_autosuspend(master->dev); 1921 1922 return ret; 1923 } 1924 1925 static int svc_i3c_master_enable_hotjoin(struct i3c_master_controller *m) 1926 { 1927 struct svc_i3c_master *master = to_svc_i3c_master(m); 1928 int ret; 1929 1930 ret = pm_runtime_resume_and_get(master->dev); 1931 if (ret < 0) { 1932 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); 1933 return ret; 1934 } 1935 1936 master->enabled_events |= SVC_I3C_EVENT_HOTJOIN; 1937 1938 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART); 1939 1940 return 0; 1941 } 1942 1943 static int svc_i3c_master_disable_hotjoin(struct i3c_master_controller *m) 1944 { 1945 struct svc_i3c_master *master = to_svc_i3c_master(m); 1946 1947 master->enabled_events &= ~SVC_I3C_EVENT_HOTJOIN; 1948 1949 if (!master->enabled_events) 1950 svc_i3c_master_disable_interrupts(master); 1951 1952 pm_runtime_put_autosuspend(master->dev); 1953 1954 return 0; 1955 } 1956 1957 static void svc_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev, 1958 struct i3c_ibi_slot *slot) 1959 { 1960 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1961 1962 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot); 1963 } 1964 1965 static const struct i3c_master_controller_ops svc_i3c_master_ops = { 1966 .bus_init = svc_i3c_master_bus_init, 1967 .bus_cleanup = svc_i3c_master_bus_cleanup, 1968 .attach_i3c_dev = svc_i3c_master_attach_i3c_dev, 1969 .detach_i3c_dev = svc_i3c_master_detach_i3c_dev, 1970 .reattach_i3c_dev = svc_i3c_master_reattach_i3c_dev, 1971 .attach_i2c_dev = svc_i3c_master_attach_i2c_dev, 1972 .detach_i2c_dev = svc_i3c_master_detach_i2c_dev, 1973 .do_daa = svc_i3c_master_do_daa, 1974 .supports_ccc_cmd = svc_i3c_master_supports_ccc_cmd, 1975 .send_ccc_cmd = svc_i3c_master_send_ccc_cmd, 1976 .i3c_xfers = svc_i3c_master_i3c_xfers, 1977 .i2c_xfers = svc_i3c_master_i2c_xfers, 1978 .request_ibi = svc_i3c_master_request_ibi, 1979 .free_ibi = svc_i3c_master_free_ibi, 1980 .recycle_ibi_slot = svc_i3c_master_recycle_ibi_slot, 1981 .enable_ibi = svc_i3c_master_enable_ibi, 1982 .disable_ibi = svc_i3c_master_disable_ibi, 1983 .enable_hotjoin = svc_i3c_master_enable_hotjoin, 1984 .disable_hotjoin = svc_i3c_master_disable_hotjoin, 1985 .set_speed = svc_i3c_master_set_speed, 1986 }; 1987 1988 static int svc_i3c_master_probe(struct platform_device *pdev) 1989 { 1990 struct device *dev = &pdev->dev; 1991 struct svc_i3c_master *master; 1992 int ret, i; 1993 1994 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); 1995 if (!master) 1996 return -ENOMEM; 1997 1998 master->drvdata = of_device_get_match_data(dev); 1999 if (!master->drvdata) 2000 return -EINVAL; 2001 2002 master->regs = devm_platform_ioremap_resource(pdev, 0); 2003 if (IS_ERR(master->regs)) 2004 return PTR_ERR(master->regs); 2005 2006 master->num_clks = devm_clk_bulk_get_all(dev, &master->clks); 2007 if (master->num_clks < 0) 2008 return dev_err_probe(dev, -EINVAL, "can't get I3C clocks\n"); 2009 2010 for (i = 0; i < master->num_clks; i++) { 2011 if (!strcmp(master->clks[i].id, "fast_clk")) 2012 break; 2013 } 2014 2015 if (i == master->num_clks) 2016 return dev_err_probe(dev, -EINVAL, 2017 "can't get I3C peripheral clock\n"); 2018 2019 master->fclk = master->clks[i].clk; 2020 if (IS_ERR(master->fclk)) 2021 return PTR_ERR(master->fclk); 2022 2023 master->irq = platform_get_irq(pdev, 0); 2024 if (master->irq < 0) 2025 return master->irq; 2026 2027 master->dev = dev; 2028 ret = clk_bulk_prepare_enable(master->num_clks, master->clks); 2029 if (ret) 2030 return dev_err_probe(dev, ret, "can't enable I3C clocks\n"); 2031 2032 mutex_init(&master->lock); 2033 2034 ret = devm_request_irq(dev, master->irq, svc_i3c_master_irq_handler, 2035 IRQF_NO_SUSPEND, "svc-i3c-irq", master); 2036 if (ret) 2037 goto err_disable_clks; 2038 2039 master->free_slots = GENMASK(SVC_I3C_MAX_DEVS - 1, 0); 2040 2041 spin_lock_init(&master->xferqueue.lock); 2042 INIT_LIST_HEAD(&master->xferqueue.list); 2043 2044 spin_lock_init(&master->ibi.lock); 2045 master->ibi.num_slots = SVC_I3C_MAX_DEVS; 2046 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots, 2047 sizeof(*master->ibi.slots), 2048 GFP_KERNEL); 2049 if (!master->ibi.slots) { 2050 ret = -ENOMEM; 2051 goto err_disable_clks; 2052 } 2053 2054 platform_set_drvdata(pdev, master); 2055 2056 pm_runtime_set_autosuspend_delay(&pdev->dev, SVC_I3C_PM_TIMEOUT_MS); 2057 pm_runtime_use_autosuspend(&pdev->dev); 2058 pm_runtime_get_noresume(&pdev->dev); 2059 pm_runtime_set_active(&pdev->dev); 2060 pm_runtime_enable(&pdev->dev); 2061 2062 svc_i3c_master_reset(master); 2063 2064 /* Register the master */ 2065 ret = i3c_master_register(&master->base, &pdev->dev, 2066 &svc_i3c_master_ops, false); 2067 if (ret) 2068 goto rpm_disable; 2069 2070 pm_runtime_put_autosuspend(&pdev->dev); 2071 2072 return 0; 2073 2074 rpm_disable: 2075 pm_runtime_dont_use_autosuspend(&pdev->dev); 2076 pm_runtime_put_noidle(&pdev->dev); 2077 pm_runtime_disable(&pdev->dev); 2078 pm_runtime_set_suspended(&pdev->dev); 2079 2080 err_disable_clks: 2081 clk_bulk_disable_unprepare(master->num_clks, master->clks); 2082 2083 return ret; 2084 } 2085 2086 static void svc_i3c_master_remove(struct platform_device *pdev) 2087 { 2088 struct svc_i3c_master *master = platform_get_drvdata(pdev); 2089 2090 i3c_master_unregister(&master->base); 2091 2092 pm_runtime_dont_use_autosuspend(&pdev->dev); 2093 pm_runtime_disable(&pdev->dev); 2094 } 2095 2096 static void svc_i3c_save_regs(struct svc_i3c_master *master) 2097 { 2098 master->saved_regs.mconfig = readl(master->regs + SVC_I3C_MCONFIG); 2099 master->saved_regs.mdynaddr = readl(master->regs + SVC_I3C_MDYNADDR); 2100 } 2101 2102 static void svc_i3c_restore_regs(struct svc_i3c_master *master) 2103 { 2104 if (readl(master->regs + SVC_I3C_MDYNADDR) != 2105 master->saved_regs.mdynaddr) { 2106 writel(master->saved_regs.mconfig, 2107 master->regs + SVC_I3C_MCONFIG); 2108 writel(master->saved_regs.mdynaddr, 2109 master->regs + SVC_I3C_MDYNADDR); 2110 } 2111 } 2112 2113 static int __maybe_unused svc_i3c_runtime_suspend(struct device *dev) 2114 { 2115 struct svc_i3c_master *master = dev_get_drvdata(dev); 2116 2117 svc_i3c_save_regs(master); 2118 clk_bulk_disable_unprepare(master->num_clks, master->clks); 2119 pinctrl_pm_select_sleep_state(dev); 2120 2121 return 0; 2122 } 2123 2124 static int __maybe_unused svc_i3c_runtime_resume(struct device *dev) 2125 { 2126 struct svc_i3c_master *master = dev_get_drvdata(dev); 2127 int ret; 2128 2129 pinctrl_pm_select_default_state(dev); 2130 ret = clk_bulk_prepare_enable(master->num_clks, master->clks); 2131 if (ret) 2132 return ret; 2133 2134 svc_i3c_restore_regs(master); 2135 2136 return 0; 2137 } 2138 2139 static const struct dev_pm_ops svc_i3c_pm_ops = { 2140 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2141 pm_runtime_force_resume) 2142 SET_RUNTIME_PM_OPS(svc_i3c_runtime_suspend, 2143 svc_i3c_runtime_resume, NULL) 2144 }; 2145 2146 static const struct svc_i3c_drvdata npcm845_drvdata = { 2147 .quirks = SVC_I3C_QUIRK_FIFO_EMPTY | 2148 SVC_I3C_QUIRK_FALSE_SLVSTART | 2149 SVC_I3C_QUIRK_DAA_CORRUPT, 2150 }; 2151 2152 static const struct svc_i3c_drvdata svc_default_drvdata = {}; 2153 2154 static const struct of_device_id svc_i3c_master_of_match_tbl[] = { 2155 { .compatible = "nuvoton,npcm845-i3c", .data = &npcm845_drvdata }, 2156 { .compatible = "silvaco,i3c-master-v1", .data = &svc_default_drvdata }, 2157 { /* sentinel */ }, 2158 }; 2159 MODULE_DEVICE_TABLE(of, svc_i3c_master_of_match_tbl); 2160 2161 static struct platform_driver svc_i3c_master = { 2162 .probe = svc_i3c_master_probe, 2163 .remove = svc_i3c_master_remove, 2164 .driver = { 2165 .name = "silvaco-i3c-master", 2166 .of_match_table = svc_i3c_master_of_match_tbl, 2167 .pm = &svc_i3c_pm_ops, 2168 }, 2169 }; 2170 module_platform_driver(svc_i3c_master); 2171 2172 MODULE_AUTHOR("Conor Culhane <conor.culhane@silvaco.com>"); 2173 MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>"); 2174 MODULE_DESCRIPTION("Silvaco dual-role I3C master driver"); 2175 MODULE_LICENSE("GPL v2"); 2176