1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Silvaco dual-role I3C master driver 4 * 5 * Copyright (C) 2020 Silvaco 6 * Author: Miquel RAYNAL <miquel.raynal@bootlin.com> 7 * Based on a work from: Conor Culhane <conor.culhane@silvaco.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/completion.h> 13 #include <linux/errno.h> 14 #include <linux/i3c/master.h> 15 #include <linux/interrupt.h> 16 #include <linux/iopoll.h> 17 #include <linux/list.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 24 /* Master Mode Registers */ 25 #define SVC_I3C_MCONFIG 0x000 26 #define SVC_I3C_MCONFIG_MASTER_EN BIT(0) 27 #define SVC_I3C_MCONFIG_DISTO(x) FIELD_PREP(BIT(3), (x)) 28 #define SVC_I3C_MCONFIG_HKEEP(x) FIELD_PREP(GENMASK(5, 4), (x)) 29 #define SVC_I3C_MCONFIG_ODSTOP(x) FIELD_PREP(BIT(6), (x)) 30 #define SVC_I3C_MCONFIG_PPBAUD(x) FIELD_PREP(GENMASK(11, 8), (x)) 31 #define SVC_I3C_MCONFIG_PPLOW(x) FIELD_PREP(GENMASK(15, 12), (x)) 32 #define SVC_I3C_MCONFIG_ODBAUD(x) FIELD_PREP(GENMASK(23, 16), (x)) 33 #define SVC_I3C_MCONFIG_ODHPP(x) FIELD_PREP(BIT(24), (x)) 34 #define SVC_I3C_MCONFIG_SKEW(x) FIELD_PREP(GENMASK(27, 25), (x)) 35 #define SVC_I3C_MCONFIG_I2CBAUD(x) FIELD_PREP(GENMASK(31, 28), (x)) 36 37 #define SVC_I3C_MCTRL 0x084 38 #define SVC_I3C_MCTRL_REQUEST_MASK GENMASK(2, 0) 39 #define SVC_I3C_MCTRL_REQUEST_NONE 0 40 #define SVC_I3C_MCTRL_REQUEST_START_ADDR 1 41 #define SVC_I3C_MCTRL_REQUEST_STOP 2 42 #define SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK 3 43 #define SVC_I3C_MCTRL_REQUEST_PROC_DAA 4 44 #define SVC_I3C_MCTRL_REQUEST_AUTO_IBI 7 45 #define SVC_I3C_MCTRL_TYPE_I3C 0 46 #define SVC_I3C_MCTRL_TYPE_I2C BIT(4) 47 #define SVC_I3C_MCTRL_IBIRESP_AUTO 0 48 #define SVC_I3C_MCTRL_IBIRESP_ACK_WITHOUT_BYTE 0 49 #define SVC_I3C_MCTRL_IBIRESP_ACK_WITH_BYTE BIT(7) 50 #define SVC_I3C_MCTRL_IBIRESP_NACK BIT(6) 51 #define SVC_I3C_MCTRL_IBIRESP_MANUAL GENMASK(7, 6) 52 #define SVC_I3C_MCTRL_DIR(x) FIELD_PREP(BIT(8), (x)) 53 #define SVC_I3C_MCTRL_DIR_WRITE 0 54 #define SVC_I3C_MCTRL_DIR_READ 1 55 #define SVC_I3C_MCTRL_ADDR(x) FIELD_PREP(GENMASK(15, 9), (x)) 56 #define SVC_I3C_MCTRL_RDTERM(x) FIELD_PREP(GENMASK(23, 16), (x)) 57 58 #define SVC_I3C_MSTATUS 0x088 59 #define SVC_I3C_MSTATUS_STATE(x) FIELD_GET(GENMASK(2, 0), (x)) 60 #define SVC_I3C_MSTATUS_STATE_DAA(x) (SVC_I3C_MSTATUS_STATE(x) == 5) 61 #define SVC_I3C_MSTATUS_STATE_IDLE(x) (SVC_I3C_MSTATUS_STATE(x) == 0) 62 #define SVC_I3C_MSTATUS_BETWEEN(x) FIELD_GET(BIT(4), (x)) 63 #define SVC_I3C_MSTATUS_NACKED(x) FIELD_GET(BIT(5), (x)) 64 #define SVC_I3C_MSTATUS_IBITYPE(x) FIELD_GET(GENMASK(7, 6), (x)) 65 #define SVC_I3C_MSTATUS_IBITYPE_IBI 1 66 #define SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST 2 67 #define SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN 3 68 #define SVC_I3C_MINT_SLVSTART BIT(8) 69 #define SVC_I3C_MINT_MCTRLDONE BIT(9) 70 #define SVC_I3C_MINT_COMPLETE BIT(10) 71 #define SVC_I3C_MINT_RXPEND BIT(11) 72 #define SVC_I3C_MINT_TXNOTFULL BIT(12) 73 #define SVC_I3C_MINT_IBIWON BIT(13) 74 #define SVC_I3C_MINT_ERRWARN BIT(15) 75 #define SVC_I3C_MSTATUS_SLVSTART(x) FIELD_GET(SVC_I3C_MINT_SLVSTART, (x)) 76 #define SVC_I3C_MSTATUS_MCTRLDONE(x) FIELD_GET(SVC_I3C_MINT_MCTRLDONE, (x)) 77 #define SVC_I3C_MSTATUS_COMPLETE(x) FIELD_GET(SVC_I3C_MINT_COMPLETE, (x)) 78 #define SVC_I3C_MSTATUS_RXPEND(x) FIELD_GET(SVC_I3C_MINT_RXPEND, (x)) 79 #define SVC_I3C_MSTATUS_TXNOTFULL(x) FIELD_GET(SVC_I3C_MINT_TXNOTFULL, (x)) 80 #define SVC_I3C_MSTATUS_IBIWON(x) FIELD_GET(SVC_I3C_MINT_IBIWON, (x)) 81 #define SVC_I3C_MSTATUS_ERRWARN(x) FIELD_GET(SVC_I3C_MINT_ERRWARN, (x)) 82 #define SVC_I3C_MSTATUS_IBIADDR(x) FIELD_GET(GENMASK(30, 24), (x)) 83 84 #define SVC_I3C_IBIRULES 0x08C 85 #define SVC_I3C_IBIRULES_ADDR(slot, addr) FIELD_PREP(GENMASK(29, 0), \ 86 ((addr) & 0x3F) << ((slot) * 6)) 87 #define SVC_I3C_IBIRULES_ADDRS 5 88 #define SVC_I3C_IBIRULES_MSB0 BIT(30) 89 #define SVC_I3C_IBIRULES_NOBYTE BIT(31) 90 #define SVC_I3C_IBIRULES_MANDBYTE 0 91 #define SVC_I3C_MINTSET 0x090 92 #define SVC_I3C_MINTCLR 0x094 93 #define SVC_I3C_MINTMASKED 0x098 94 #define SVC_I3C_MERRWARN 0x09C 95 #define SVC_I3C_MERRWARN_NACK BIT(2) 96 #define SVC_I3C_MERRWARN_TIMEOUT BIT(20) 97 #define SVC_I3C_MDMACTRL 0x0A0 98 #define SVC_I3C_MDATACTRL 0x0AC 99 #define SVC_I3C_MDATACTRL_FLUSHTB BIT(0) 100 #define SVC_I3C_MDATACTRL_FLUSHRB BIT(1) 101 #define SVC_I3C_MDATACTRL_UNLOCK_TRIG BIT(3) 102 #define SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL GENMASK(5, 4) 103 #define SVC_I3C_MDATACTRL_RXTRIG_FIFO_NOT_EMPTY 0 104 #define SVC_I3C_MDATACTRL_RXCOUNT(x) FIELD_GET(GENMASK(28, 24), (x)) 105 #define SVC_I3C_MDATACTRL_TXFULL BIT(30) 106 #define SVC_I3C_MDATACTRL_RXEMPTY BIT(31) 107 108 #define SVC_I3C_MWDATAB 0x0B0 109 #define SVC_I3C_MWDATAB_END BIT(8) 110 111 #define SVC_I3C_MWDATABE 0x0B4 112 #define SVC_I3C_MWDATAH 0x0B8 113 #define SVC_I3C_MWDATAHE 0x0BC 114 #define SVC_I3C_MRDATAB 0x0C0 115 #define SVC_I3C_MRDATAH 0x0C8 116 #define SVC_I3C_MWMSG_SDR 0x0D0 117 #define SVC_I3C_MRMSG_SDR 0x0D4 118 #define SVC_I3C_MWMSG_DDR 0x0D8 119 #define SVC_I3C_MRMSG_DDR 0x0DC 120 121 #define SVC_I3C_MDYNADDR 0x0E4 122 #define SVC_MDYNADDR_VALID BIT(0) 123 #define SVC_MDYNADDR_ADDR(x) FIELD_PREP(GENMASK(7, 1), (x)) 124 125 #define SVC_I3C_MAX_DEVS 32 126 #define SVC_I3C_PM_TIMEOUT_MS 1000 127 128 /* This parameter depends on the implementation and may be tuned */ 129 #define SVC_I3C_FIFO_SIZE 16 130 131 struct svc_i3c_cmd { 132 u8 addr; 133 bool rnw; 134 u8 *in; 135 const void *out; 136 unsigned int len; 137 unsigned int read_len; 138 bool continued; 139 }; 140 141 struct svc_i3c_xfer { 142 struct list_head node; 143 struct completion comp; 144 int ret; 145 unsigned int type; 146 unsigned int ncmds; 147 struct svc_i3c_cmd cmds[] __counted_by(ncmds); 148 }; 149 150 struct svc_i3c_regs_save { 151 u32 mconfig; 152 u32 mdynaddr; 153 }; 154 155 /** 156 * struct svc_i3c_master - Silvaco I3C Master structure 157 * @base: I3C master controller 158 * @dev: Corresponding device 159 * @regs: Memory mapping 160 * @saved_regs: Volatile values for PM operations 161 * @free_slots: Bit array of available slots 162 * @addrs: Array containing the dynamic addresses of each attached device 163 * @descs: Array of descriptors, one per attached device 164 * @hj_work: Hot-join work 165 * @ibi_work: IBI work 166 * @irq: Main interrupt 167 * @pclk: System clock 168 * @fclk: Fast clock (bus) 169 * @sclk: Slow clock (other events) 170 * @xferqueue: Transfer queue structure 171 * @xferqueue.list: List member 172 * @xferqueue.cur: Current ongoing transfer 173 * @xferqueue.lock: Queue lock 174 * @ibi: IBI structure 175 * @ibi.num_slots: Number of slots available in @ibi.slots 176 * @ibi.slots: Available IBI slots 177 * @ibi.tbq_slot: To be queued IBI slot 178 * @ibi.lock: IBI lock 179 * @lock: Transfer lock, protect between IBI work thread and callbacks from master 180 */ 181 struct svc_i3c_master { 182 struct i3c_master_controller base; 183 struct device *dev; 184 void __iomem *regs; 185 struct svc_i3c_regs_save saved_regs; 186 u32 free_slots; 187 u8 addrs[SVC_I3C_MAX_DEVS]; 188 struct i3c_dev_desc *descs[SVC_I3C_MAX_DEVS]; 189 struct work_struct hj_work; 190 struct work_struct ibi_work; 191 int irq; 192 struct clk *pclk; 193 struct clk *fclk; 194 struct clk *sclk; 195 struct { 196 struct list_head list; 197 struct svc_i3c_xfer *cur; 198 /* Prevent races between transfers */ 199 spinlock_t lock; 200 } xferqueue; 201 struct { 202 unsigned int num_slots; 203 struct i3c_dev_desc **slots; 204 struct i3c_ibi_slot *tbq_slot; 205 /* Prevent races within IBI handlers */ 206 spinlock_t lock; 207 } ibi; 208 struct mutex lock; 209 }; 210 211 /** 212 * struct svc_i3c_i2c_dev_data - Device specific data 213 * @index: Index in the master tables corresponding to this device 214 * @ibi: IBI slot index in the master structure 215 * @ibi_pool: IBI pool associated to this device 216 */ 217 struct svc_i3c_i2c_dev_data { 218 u8 index; 219 int ibi; 220 struct i3c_generic_ibi_pool *ibi_pool; 221 }; 222 223 static bool svc_i3c_master_error(struct svc_i3c_master *master) 224 { 225 u32 mstatus, merrwarn; 226 227 mstatus = readl(master->regs + SVC_I3C_MSTATUS); 228 if (SVC_I3C_MSTATUS_ERRWARN(mstatus)) { 229 merrwarn = readl(master->regs + SVC_I3C_MERRWARN); 230 writel(merrwarn, master->regs + SVC_I3C_MERRWARN); 231 232 /* Ignore timeout error */ 233 if (merrwarn & SVC_I3C_MERRWARN_TIMEOUT) { 234 dev_dbg(master->dev, "Warning condition: MSTATUS 0x%08x, MERRWARN 0x%08x\n", 235 mstatus, merrwarn); 236 return false; 237 } 238 239 dev_err(master->dev, 240 "Error condition: MSTATUS 0x%08x, MERRWARN 0x%08x\n", 241 mstatus, merrwarn); 242 243 return true; 244 } 245 246 return false; 247 } 248 249 static void svc_i3c_master_enable_interrupts(struct svc_i3c_master *master, u32 mask) 250 { 251 writel(mask, master->regs + SVC_I3C_MINTSET); 252 } 253 254 static void svc_i3c_master_disable_interrupts(struct svc_i3c_master *master) 255 { 256 u32 mask = readl(master->regs + SVC_I3C_MINTSET); 257 258 writel(mask, master->regs + SVC_I3C_MINTCLR); 259 } 260 261 static void svc_i3c_master_clear_merrwarn(struct svc_i3c_master *master) 262 { 263 /* Clear pending warnings */ 264 writel(readl(master->regs + SVC_I3C_MERRWARN), 265 master->regs + SVC_I3C_MERRWARN); 266 } 267 268 static void svc_i3c_master_flush_fifo(struct svc_i3c_master *master) 269 { 270 /* Flush FIFOs */ 271 writel(SVC_I3C_MDATACTRL_FLUSHTB | SVC_I3C_MDATACTRL_FLUSHRB, 272 master->regs + SVC_I3C_MDATACTRL); 273 } 274 275 static void svc_i3c_master_reset_fifo_trigger(struct svc_i3c_master *master) 276 { 277 u32 reg; 278 279 /* Set RX and TX tigger levels, flush FIFOs */ 280 reg = SVC_I3C_MDATACTRL_FLUSHTB | 281 SVC_I3C_MDATACTRL_FLUSHRB | 282 SVC_I3C_MDATACTRL_UNLOCK_TRIG | 283 SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL | 284 SVC_I3C_MDATACTRL_RXTRIG_FIFO_NOT_EMPTY; 285 writel(reg, master->regs + SVC_I3C_MDATACTRL); 286 } 287 288 static void svc_i3c_master_reset(struct svc_i3c_master *master) 289 { 290 svc_i3c_master_clear_merrwarn(master); 291 svc_i3c_master_reset_fifo_trigger(master); 292 svc_i3c_master_disable_interrupts(master); 293 } 294 295 static inline struct svc_i3c_master * 296 to_svc_i3c_master(struct i3c_master_controller *master) 297 { 298 return container_of(master, struct svc_i3c_master, base); 299 } 300 301 static void svc_i3c_master_hj_work(struct work_struct *work) 302 { 303 struct svc_i3c_master *master; 304 305 master = container_of(work, struct svc_i3c_master, hj_work); 306 i3c_master_do_daa(&master->base); 307 } 308 309 static struct i3c_dev_desc * 310 svc_i3c_master_dev_from_addr(struct svc_i3c_master *master, 311 unsigned int ibiaddr) 312 { 313 int i; 314 315 for (i = 0; i < SVC_I3C_MAX_DEVS; i++) 316 if (master->addrs[i] == ibiaddr) 317 break; 318 319 if (i == SVC_I3C_MAX_DEVS) 320 return NULL; 321 322 return master->descs[i]; 323 } 324 325 static void svc_i3c_master_emit_stop(struct svc_i3c_master *master) 326 { 327 writel(SVC_I3C_MCTRL_REQUEST_STOP, master->regs + SVC_I3C_MCTRL); 328 329 /* 330 * This delay is necessary after the emission of a stop, otherwise eg. 331 * repeating IBIs do not get detected. There is a note in the manual 332 * about it, stating that the stop condition might not be settled 333 * correctly if a start condition follows too rapidly. 334 */ 335 udelay(1); 336 } 337 338 static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master, 339 struct i3c_dev_desc *dev) 340 { 341 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 342 struct i3c_ibi_slot *slot; 343 unsigned int count; 344 u32 mdatactrl; 345 int ret, val; 346 u8 *buf; 347 348 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool); 349 if (!slot) 350 return -ENOSPC; 351 352 slot->len = 0; 353 buf = slot->data; 354 355 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val, 356 SVC_I3C_MSTATUS_COMPLETE(val), 0, 1000); 357 if (ret) { 358 dev_err(master->dev, "Timeout when polling for COMPLETE\n"); 359 return ret; 360 } 361 362 while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS)) && 363 slot->len < SVC_I3C_FIFO_SIZE) { 364 mdatactrl = readl(master->regs + SVC_I3C_MDATACTRL); 365 count = SVC_I3C_MDATACTRL_RXCOUNT(mdatactrl); 366 readsl(master->regs + SVC_I3C_MRDATAB, buf, count); 367 slot->len += count; 368 buf += count; 369 } 370 371 master->ibi.tbq_slot = slot; 372 373 return 0; 374 } 375 376 static void svc_i3c_master_ack_ibi(struct svc_i3c_master *master, 377 bool mandatory_byte) 378 { 379 unsigned int ibi_ack_nack; 380 381 ibi_ack_nack = SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK; 382 if (mandatory_byte) 383 ibi_ack_nack |= SVC_I3C_MCTRL_IBIRESP_ACK_WITH_BYTE; 384 else 385 ibi_ack_nack |= SVC_I3C_MCTRL_IBIRESP_ACK_WITHOUT_BYTE; 386 387 writel(ibi_ack_nack, master->regs + SVC_I3C_MCTRL); 388 } 389 390 static void svc_i3c_master_nack_ibi(struct svc_i3c_master *master) 391 { 392 writel(SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK | 393 SVC_I3C_MCTRL_IBIRESP_NACK, 394 master->regs + SVC_I3C_MCTRL); 395 } 396 397 static void svc_i3c_master_ibi_work(struct work_struct *work) 398 { 399 struct svc_i3c_master *master = container_of(work, struct svc_i3c_master, ibi_work); 400 struct svc_i3c_i2c_dev_data *data; 401 unsigned int ibitype, ibiaddr; 402 struct i3c_dev_desc *dev; 403 u32 status, val; 404 int ret; 405 406 mutex_lock(&master->lock); 407 /* Acknowledge the incoming interrupt with the AUTOIBI mechanism */ 408 writel(SVC_I3C_MCTRL_REQUEST_AUTO_IBI | 409 SVC_I3C_MCTRL_IBIRESP_AUTO, 410 master->regs + SVC_I3C_MCTRL); 411 412 /* Wait for IBIWON, should take approximately 100us */ 413 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val, 414 SVC_I3C_MSTATUS_IBIWON(val), 0, 1000); 415 if (ret) { 416 dev_err(master->dev, "Timeout when polling for IBIWON\n"); 417 svc_i3c_master_emit_stop(master); 418 goto reenable_ibis; 419 } 420 421 /* Clear the interrupt status */ 422 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); 423 424 status = readl(master->regs + SVC_I3C_MSTATUS); 425 ibitype = SVC_I3C_MSTATUS_IBITYPE(status); 426 ibiaddr = SVC_I3C_MSTATUS_IBIADDR(status); 427 428 /* Handle the critical responses to IBI's */ 429 switch (ibitype) { 430 case SVC_I3C_MSTATUS_IBITYPE_IBI: 431 dev = svc_i3c_master_dev_from_addr(master, ibiaddr); 432 if (!dev) 433 svc_i3c_master_nack_ibi(master); 434 else 435 svc_i3c_master_handle_ibi(master, dev); 436 break; 437 case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN: 438 svc_i3c_master_ack_ibi(master, false); 439 break; 440 case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST: 441 svc_i3c_master_nack_ibi(master); 442 break; 443 default: 444 break; 445 } 446 447 /* 448 * If an error happened, we probably got interrupted and the exchange 449 * timedout. In this case we just drop everything, emit a stop and wait 450 * for the slave to interrupt again. 451 */ 452 if (svc_i3c_master_error(master)) { 453 if (master->ibi.tbq_slot) { 454 data = i3c_dev_get_master_data(dev); 455 i3c_generic_ibi_recycle_slot(data->ibi_pool, 456 master->ibi.tbq_slot); 457 master->ibi.tbq_slot = NULL; 458 } 459 460 svc_i3c_master_emit_stop(master); 461 462 goto reenable_ibis; 463 } 464 465 /* Handle the non critical tasks */ 466 switch (ibitype) { 467 case SVC_I3C_MSTATUS_IBITYPE_IBI: 468 if (dev) { 469 i3c_master_queue_ibi(dev, master->ibi.tbq_slot); 470 master->ibi.tbq_slot = NULL; 471 } 472 svc_i3c_master_emit_stop(master); 473 break; 474 case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN: 475 queue_work(master->base.wq, &master->hj_work); 476 break; 477 case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST: 478 default: 479 break; 480 } 481 482 reenable_ibis: 483 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART); 484 mutex_unlock(&master->lock); 485 } 486 487 static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id) 488 { 489 struct svc_i3c_master *master = (struct svc_i3c_master *)dev_id; 490 u32 active = readl(master->regs + SVC_I3C_MSTATUS); 491 492 if (!SVC_I3C_MSTATUS_SLVSTART(active)) 493 return IRQ_NONE; 494 495 /* Clear the interrupt status */ 496 writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS); 497 498 svc_i3c_master_disable_interrupts(master); 499 500 /* Handle the interrupt in a non atomic context */ 501 queue_work(master->base.wq, &master->ibi_work); 502 503 return IRQ_HANDLED; 504 } 505 506 static int svc_i3c_master_bus_init(struct i3c_master_controller *m) 507 { 508 struct svc_i3c_master *master = to_svc_i3c_master(m); 509 struct i3c_bus *bus = i3c_master_get_bus(m); 510 struct i3c_device_info info = {}; 511 unsigned long fclk_rate, fclk_period_ns; 512 unsigned int high_period_ns, od_low_period_ns; 513 u32 ppbaud, pplow, odhpp, odbaud, odstop, i2cbaud, reg; 514 int ret; 515 516 ret = pm_runtime_resume_and_get(master->dev); 517 if (ret < 0) { 518 dev_err(master->dev, 519 "<%s> cannot resume i3c bus master, err: %d\n", 520 __func__, ret); 521 return ret; 522 } 523 524 /* Timings derivation */ 525 fclk_rate = clk_get_rate(master->fclk); 526 if (!fclk_rate) { 527 ret = -EINVAL; 528 goto rpm_out; 529 } 530 531 fclk_period_ns = DIV_ROUND_UP(1000000000, fclk_rate); 532 533 /* 534 * Using I3C Push-Pull mode, target is 12.5MHz/80ns period. 535 * Simplest configuration is using a 50% duty-cycle of 40ns. 536 */ 537 ppbaud = DIV_ROUND_UP(40, fclk_period_ns) - 1; 538 pplow = 0; 539 540 /* 541 * Using I3C Open-Drain mode, target is 4.17MHz/240ns with a 542 * duty-cycle tuned so that high levels are filetered out by 543 * the 50ns filter (target being 40ns). 544 */ 545 odhpp = 1; 546 high_period_ns = (ppbaud + 1) * fclk_period_ns; 547 odbaud = DIV_ROUND_UP(240 - high_period_ns, high_period_ns) - 1; 548 od_low_period_ns = (odbaud + 1) * high_period_ns; 549 550 switch (bus->mode) { 551 case I3C_BUS_MODE_PURE: 552 i2cbaud = 0; 553 odstop = 0; 554 break; 555 case I3C_BUS_MODE_MIXED_FAST: 556 case I3C_BUS_MODE_MIXED_LIMITED: 557 /* 558 * Using I2C Fm+ mode, target is 1MHz/1000ns, the difference 559 * between the high and low period does not really matter. 560 */ 561 i2cbaud = DIV_ROUND_UP(1000, od_low_period_ns) - 2; 562 odstop = 1; 563 break; 564 case I3C_BUS_MODE_MIXED_SLOW: 565 /* 566 * Using I2C Fm mode, target is 0.4MHz/2500ns, with the same 567 * constraints as the FM+ mode. 568 */ 569 i2cbaud = DIV_ROUND_UP(2500, od_low_period_ns) - 2; 570 odstop = 1; 571 break; 572 default: 573 goto rpm_out; 574 } 575 576 reg = SVC_I3C_MCONFIG_MASTER_EN | 577 SVC_I3C_MCONFIG_DISTO(0) | 578 SVC_I3C_MCONFIG_HKEEP(0) | 579 SVC_I3C_MCONFIG_ODSTOP(odstop) | 580 SVC_I3C_MCONFIG_PPBAUD(ppbaud) | 581 SVC_I3C_MCONFIG_PPLOW(pplow) | 582 SVC_I3C_MCONFIG_ODBAUD(odbaud) | 583 SVC_I3C_MCONFIG_ODHPP(odhpp) | 584 SVC_I3C_MCONFIG_SKEW(0) | 585 SVC_I3C_MCONFIG_I2CBAUD(i2cbaud); 586 writel(reg, master->regs + SVC_I3C_MCONFIG); 587 588 /* Master core's registration */ 589 ret = i3c_master_get_free_addr(m, 0); 590 if (ret < 0) 591 goto rpm_out; 592 593 info.dyn_addr = ret; 594 595 writel(SVC_MDYNADDR_VALID | SVC_MDYNADDR_ADDR(info.dyn_addr), 596 master->regs + SVC_I3C_MDYNADDR); 597 598 ret = i3c_master_set_info(&master->base, &info); 599 if (ret) 600 goto rpm_out; 601 602 rpm_out: 603 pm_runtime_mark_last_busy(master->dev); 604 pm_runtime_put_autosuspend(master->dev); 605 606 return ret; 607 } 608 609 static void svc_i3c_master_bus_cleanup(struct i3c_master_controller *m) 610 { 611 struct svc_i3c_master *master = to_svc_i3c_master(m); 612 int ret; 613 614 ret = pm_runtime_resume_and_get(master->dev); 615 if (ret < 0) { 616 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); 617 return; 618 } 619 620 svc_i3c_master_disable_interrupts(master); 621 622 /* Disable master */ 623 writel(0, master->regs + SVC_I3C_MCONFIG); 624 625 pm_runtime_mark_last_busy(master->dev); 626 pm_runtime_put_autosuspend(master->dev); 627 } 628 629 static int svc_i3c_master_reserve_slot(struct svc_i3c_master *master) 630 { 631 unsigned int slot; 632 633 if (!(master->free_slots & GENMASK(SVC_I3C_MAX_DEVS - 1, 0))) 634 return -ENOSPC; 635 636 slot = ffs(master->free_slots) - 1; 637 638 master->free_slots &= ~BIT(slot); 639 640 return slot; 641 } 642 643 static void svc_i3c_master_release_slot(struct svc_i3c_master *master, 644 unsigned int slot) 645 { 646 master->free_slots |= BIT(slot); 647 } 648 649 static int svc_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev) 650 { 651 struct i3c_master_controller *m = i3c_dev_get_master(dev); 652 struct svc_i3c_master *master = to_svc_i3c_master(m); 653 struct svc_i3c_i2c_dev_data *data; 654 int slot; 655 656 slot = svc_i3c_master_reserve_slot(master); 657 if (slot < 0) 658 return slot; 659 660 data = kzalloc(sizeof(*data), GFP_KERNEL); 661 if (!data) { 662 svc_i3c_master_release_slot(master, slot); 663 return -ENOMEM; 664 } 665 666 data->ibi = -1; 667 data->index = slot; 668 master->addrs[slot] = dev->info.dyn_addr ? dev->info.dyn_addr : 669 dev->info.static_addr; 670 master->descs[slot] = dev; 671 672 i3c_dev_set_master_data(dev, data); 673 674 return 0; 675 } 676 677 static int svc_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, 678 u8 old_dyn_addr) 679 { 680 struct i3c_master_controller *m = i3c_dev_get_master(dev); 681 struct svc_i3c_master *master = to_svc_i3c_master(m); 682 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 683 684 master->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr : 685 dev->info.static_addr; 686 687 return 0; 688 } 689 690 static void svc_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) 691 { 692 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 693 struct i3c_master_controller *m = i3c_dev_get_master(dev); 694 struct svc_i3c_master *master = to_svc_i3c_master(m); 695 696 master->addrs[data->index] = 0; 697 svc_i3c_master_release_slot(master, data->index); 698 699 kfree(data); 700 } 701 702 static int svc_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) 703 { 704 struct i3c_master_controller *m = i2c_dev_get_master(dev); 705 struct svc_i3c_master *master = to_svc_i3c_master(m); 706 struct svc_i3c_i2c_dev_data *data; 707 int slot; 708 709 slot = svc_i3c_master_reserve_slot(master); 710 if (slot < 0) 711 return slot; 712 713 data = kzalloc(sizeof(*data), GFP_KERNEL); 714 if (!data) { 715 svc_i3c_master_release_slot(master, slot); 716 return -ENOMEM; 717 } 718 719 data->index = slot; 720 master->addrs[slot] = dev->addr; 721 722 i2c_dev_set_master_data(dev, data); 723 724 return 0; 725 } 726 727 static void svc_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) 728 { 729 struct svc_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 730 struct i3c_master_controller *m = i2c_dev_get_master(dev); 731 struct svc_i3c_master *master = to_svc_i3c_master(m); 732 733 svc_i3c_master_release_slot(master, data->index); 734 735 kfree(data); 736 } 737 738 static int svc_i3c_master_readb(struct svc_i3c_master *master, u8 *dst, 739 unsigned int len) 740 { 741 int ret, i; 742 u32 reg; 743 744 for (i = 0; i < len; i++) { 745 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, 746 reg, 747 SVC_I3C_MSTATUS_RXPEND(reg), 748 0, 1000); 749 if (ret) 750 return ret; 751 752 dst[i] = readl(master->regs + SVC_I3C_MRDATAB); 753 } 754 755 return 0; 756 } 757 758 static int svc_i3c_master_do_daa_locked(struct svc_i3c_master *master, 759 u8 *addrs, unsigned int *count) 760 { 761 u64 prov_id[SVC_I3C_MAX_DEVS] = {}, nacking_prov_id = 0; 762 unsigned int dev_nb = 0, last_addr = 0; 763 u32 reg; 764 int ret, i; 765 766 while (true) { 767 /* Enter/proceed with DAA */ 768 writel(SVC_I3C_MCTRL_REQUEST_PROC_DAA | 769 SVC_I3C_MCTRL_TYPE_I3C | 770 SVC_I3C_MCTRL_IBIRESP_NACK | 771 SVC_I3C_MCTRL_DIR(SVC_I3C_MCTRL_DIR_WRITE), 772 master->regs + SVC_I3C_MCTRL); 773 774 /* 775 * Either one slave will send its ID, or the assignment process 776 * is done. 777 */ 778 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, 779 reg, 780 SVC_I3C_MSTATUS_RXPEND(reg) | 781 SVC_I3C_MSTATUS_MCTRLDONE(reg), 782 1, 1000); 783 if (ret) 784 return ret; 785 786 if (SVC_I3C_MSTATUS_RXPEND(reg)) { 787 u8 data[6]; 788 789 /* 790 * We only care about the 48-bit provisioned ID yet to 791 * be sure a device does not nack an address twice. 792 * Otherwise, we would just need to flush the RX FIFO. 793 */ 794 ret = svc_i3c_master_readb(master, data, 6); 795 if (ret) 796 return ret; 797 798 for (i = 0; i < 6; i++) 799 prov_id[dev_nb] |= (u64)(data[i]) << (8 * (5 - i)); 800 801 /* We do not care about the BCR and DCR yet */ 802 ret = svc_i3c_master_readb(master, data, 2); 803 if (ret) 804 return ret; 805 } else if (SVC_I3C_MSTATUS_MCTRLDONE(reg)) { 806 if (SVC_I3C_MSTATUS_STATE_IDLE(reg) && 807 SVC_I3C_MSTATUS_COMPLETE(reg)) { 808 /* 809 * All devices received and acked they dynamic 810 * address, this is the natural end of the DAA 811 * procedure. 812 */ 813 break; 814 } else if (SVC_I3C_MSTATUS_NACKED(reg)) { 815 /* No I3C devices attached */ 816 if (dev_nb == 0) 817 break; 818 819 /* 820 * A slave device nacked the address, this is 821 * allowed only once, DAA will be stopped and 822 * then resumed. The same device is supposed to 823 * answer again immediately and shall ack the 824 * address this time. 825 */ 826 if (prov_id[dev_nb] == nacking_prov_id) 827 return -EIO; 828 829 dev_nb--; 830 nacking_prov_id = prov_id[dev_nb]; 831 svc_i3c_master_emit_stop(master); 832 833 continue; 834 } else { 835 return -EIO; 836 } 837 } 838 839 /* Wait for the slave to be ready to receive its address */ 840 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, 841 reg, 842 SVC_I3C_MSTATUS_MCTRLDONE(reg) && 843 SVC_I3C_MSTATUS_STATE_DAA(reg) && 844 SVC_I3C_MSTATUS_BETWEEN(reg), 845 0, 1000); 846 if (ret) 847 return ret; 848 849 /* Give the slave device a suitable dynamic address */ 850 ret = i3c_master_get_free_addr(&master->base, last_addr + 1); 851 if (ret < 0) 852 return ret; 853 854 addrs[dev_nb] = ret; 855 dev_dbg(master->dev, "DAA: device %d assigned to 0x%02x\n", 856 dev_nb, addrs[dev_nb]); 857 858 writel(addrs[dev_nb], master->regs + SVC_I3C_MWDATAB); 859 last_addr = addrs[dev_nb++]; 860 } 861 862 *count = dev_nb; 863 864 return 0; 865 } 866 867 static int svc_i3c_update_ibirules(struct svc_i3c_master *master) 868 { 869 struct i3c_dev_desc *dev; 870 u32 reg_mbyte = 0, reg_nobyte = SVC_I3C_IBIRULES_NOBYTE; 871 unsigned int mbyte_addr_ok = 0, mbyte_addr_ko = 0, nobyte_addr_ok = 0, 872 nobyte_addr_ko = 0; 873 bool list_mbyte = false, list_nobyte = false; 874 875 /* Create the IBIRULES register for both cases */ 876 i3c_bus_for_each_i3cdev(&master->base.bus, dev) { 877 if (I3C_BCR_DEVICE_ROLE(dev->info.bcr) == I3C_BCR_I3C_MASTER) 878 continue; 879 880 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) { 881 reg_mbyte |= SVC_I3C_IBIRULES_ADDR(mbyte_addr_ok, 882 dev->info.dyn_addr); 883 884 /* IBI rules cannot be applied to devices with MSb=1 */ 885 if (dev->info.dyn_addr & BIT(7)) 886 mbyte_addr_ko++; 887 else 888 mbyte_addr_ok++; 889 } else { 890 reg_nobyte |= SVC_I3C_IBIRULES_ADDR(nobyte_addr_ok, 891 dev->info.dyn_addr); 892 893 /* IBI rules cannot be applied to devices with MSb=1 */ 894 if (dev->info.dyn_addr & BIT(7)) 895 nobyte_addr_ko++; 896 else 897 nobyte_addr_ok++; 898 } 899 } 900 901 /* Device list cannot be handled by hardware */ 902 if (!mbyte_addr_ko && mbyte_addr_ok <= SVC_I3C_IBIRULES_ADDRS) 903 list_mbyte = true; 904 905 if (!nobyte_addr_ko && nobyte_addr_ok <= SVC_I3C_IBIRULES_ADDRS) 906 list_nobyte = true; 907 908 /* No list can be properly handled, return an error */ 909 if (!list_mbyte && !list_nobyte) 910 return -ERANGE; 911 912 /* Pick the first list that can be handled by hardware, randomly */ 913 if (list_mbyte) 914 writel(reg_mbyte, master->regs + SVC_I3C_IBIRULES); 915 else 916 writel(reg_nobyte, master->regs + SVC_I3C_IBIRULES); 917 918 return 0; 919 } 920 921 static int svc_i3c_master_do_daa(struct i3c_master_controller *m) 922 { 923 struct svc_i3c_master *master = to_svc_i3c_master(m); 924 u8 addrs[SVC_I3C_MAX_DEVS]; 925 unsigned long flags; 926 unsigned int dev_nb; 927 int ret, i; 928 929 ret = pm_runtime_resume_and_get(master->dev); 930 if (ret < 0) { 931 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); 932 return ret; 933 } 934 935 spin_lock_irqsave(&master->xferqueue.lock, flags); 936 ret = svc_i3c_master_do_daa_locked(master, addrs, &dev_nb); 937 spin_unlock_irqrestore(&master->xferqueue.lock, flags); 938 if (ret) { 939 svc_i3c_master_emit_stop(master); 940 svc_i3c_master_clear_merrwarn(master); 941 goto rpm_out; 942 } 943 944 /* Register all devices who participated to the core */ 945 for (i = 0; i < dev_nb; i++) { 946 ret = i3c_master_add_i3c_dev_locked(m, addrs[i]); 947 if (ret) 948 goto rpm_out; 949 } 950 951 /* Configure IBI auto-rules */ 952 ret = svc_i3c_update_ibirules(master); 953 if (ret) 954 dev_err(master->dev, "Cannot handle such a list of devices"); 955 956 rpm_out: 957 pm_runtime_mark_last_busy(master->dev); 958 pm_runtime_put_autosuspend(master->dev); 959 960 return ret; 961 } 962 963 static int svc_i3c_master_read(struct svc_i3c_master *master, 964 u8 *in, unsigned int len) 965 { 966 int offset = 0, i; 967 u32 mdctrl, mstatus; 968 bool completed = false; 969 unsigned int count; 970 unsigned long start = jiffies; 971 972 while (!completed) { 973 mstatus = readl(master->regs + SVC_I3C_MSTATUS); 974 if (SVC_I3C_MSTATUS_COMPLETE(mstatus) != 0) 975 completed = true; 976 977 if (time_after(jiffies, start + msecs_to_jiffies(1000))) { 978 dev_dbg(master->dev, "I3C read timeout\n"); 979 return -ETIMEDOUT; 980 } 981 982 mdctrl = readl(master->regs + SVC_I3C_MDATACTRL); 983 count = SVC_I3C_MDATACTRL_RXCOUNT(mdctrl); 984 if (offset + count > len) { 985 dev_err(master->dev, "I3C receive length too long!\n"); 986 return -EINVAL; 987 } 988 for (i = 0; i < count; i++) 989 in[offset + i] = readl(master->regs + SVC_I3C_MRDATAB); 990 991 offset += count; 992 } 993 994 return offset; 995 } 996 997 static int svc_i3c_master_write(struct svc_i3c_master *master, 998 const u8 *out, unsigned int len) 999 { 1000 int offset = 0, ret; 1001 u32 mdctrl; 1002 1003 while (offset < len) { 1004 ret = readl_poll_timeout(master->regs + SVC_I3C_MDATACTRL, 1005 mdctrl, 1006 !(mdctrl & SVC_I3C_MDATACTRL_TXFULL), 1007 0, 1000); 1008 if (ret) 1009 return ret; 1010 1011 /* 1012 * The last byte to be sent over the bus must either have the 1013 * "end" bit set or be written in MWDATABE. 1014 */ 1015 if (likely(offset < (len - 1))) 1016 writel(out[offset++], master->regs + SVC_I3C_MWDATAB); 1017 else 1018 writel(out[offset++], master->regs + SVC_I3C_MWDATABE); 1019 } 1020 1021 return 0; 1022 } 1023 1024 static int svc_i3c_master_xfer(struct svc_i3c_master *master, 1025 bool rnw, unsigned int xfer_type, u8 addr, 1026 u8 *in, const u8 *out, unsigned int xfer_len, 1027 unsigned int *read_len, bool continued) 1028 { 1029 u32 reg; 1030 int ret; 1031 1032 /* clean SVC_I3C_MINT_IBIWON w1c bits */ 1033 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); 1034 1035 writel(SVC_I3C_MCTRL_REQUEST_START_ADDR | 1036 xfer_type | 1037 SVC_I3C_MCTRL_IBIRESP_NACK | 1038 SVC_I3C_MCTRL_DIR(rnw) | 1039 SVC_I3C_MCTRL_ADDR(addr) | 1040 SVC_I3C_MCTRL_RDTERM(*read_len), 1041 master->regs + SVC_I3C_MCTRL); 1042 1043 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, 1044 SVC_I3C_MSTATUS_MCTRLDONE(reg), 0, 1000); 1045 if (ret) 1046 goto emit_stop; 1047 1048 if (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_NACK) { 1049 ret = -ENXIO; 1050 goto emit_stop; 1051 } 1052 1053 /* 1054 * According to I3C spec ver 1.1.1, 5.1.2.2.3 Consequence of Controller Starting a Frame 1055 * with I3C Target Address. 1056 * 1057 * The I3C Controller normally should start a Frame, the Address may be arbitrated, and so 1058 * the Controller shall monitor to see whether an In-Band Interrupt request, a Controller 1059 * Role Request (i.e., Secondary Controller requests to become the Active Controller), or 1060 * a Hot-Join Request has been made. 1061 * 1062 * If missed IBIWON check, the wrong data will be return. When IBIWON happen, return failure 1063 * and yield the above events handler. 1064 */ 1065 if (SVC_I3C_MSTATUS_IBIWON(reg)) { 1066 ret = -ENXIO; 1067 goto emit_stop; 1068 } 1069 1070 if (rnw) 1071 ret = svc_i3c_master_read(master, in, xfer_len); 1072 else 1073 ret = svc_i3c_master_write(master, out, xfer_len); 1074 if (ret < 0) 1075 goto emit_stop; 1076 1077 if (rnw) 1078 *read_len = ret; 1079 1080 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, 1081 SVC_I3C_MSTATUS_COMPLETE(reg), 0, 1000); 1082 if (ret) 1083 goto emit_stop; 1084 1085 writel(SVC_I3C_MINT_COMPLETE, master->regs + SVC_I3C_MSTATUS); 1086 1087 if (!continued) { 1088 svc_i3c_master_emit_stop(master); 1089 1090 /* Wait idle if stop is sent. */ 1091 readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, 1092 SVC_I3C_MSTATUS_STATE_IDLE(reg), 0, 1000); 1093 } 1094 1095 return 0; 1096 1097 emit_stop: 1098 svc_i3c_master_emit_stop(master); 1099 svc_i3c_master_clear_merrwarn(master); 1100 1101 return ret; 1102 } 1103 1104 static struct svc_i3c_xfer * 1105 svc_i3c_master_alloc_xfer(struct svc_i3c_master *master, unsigned int ncmds) 1106 { 1107 struct svc_i3c_xfer *xfer; 1108 1109 xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL); 1110 if (!xfer) 1111 return NULL; 1112 1113 INIT_LIST_HEAD(&xfer->node); 1114 xfer->ncmds = ncmds; 1115 xfer->ret = -ETIMEDOUT; 1116 1117 return xfer; 1118 } 1119 1120 static void svc_i3c_master_free_xfer(struct svc_i3c_xfer *xfer) 1121 { 1122 kfree(xfer); 1123 } 1124 1125 static void svc_i3c_master_dequeue_xfer_locked(struct svc_i3c_master *master, 1126 struct svc_i3c_xfer *xfer) 1127 { 1128 if (master->xferqueue.cur == xfer) 1129 master->xferqueue.cur = NULL; 1130 else 1131 list_del_init(&xfer->node); 1132 } 1133 1134 static void svc_i3c_master_dequeue_xfer(struct svc_i3c_master *master, 1135 struct svc_i3c_xfer *xfer) 1136 { 1137 unsigned long flags; 1138 1139 spin_lock_irqsave(&master->xferqueue.lock, flags); 1140 svc_i3c_master_dequeue_xfer_locked(master, xfer); 1141 spin_unlock_irqrestore(&master->xferqueue.lock, flags); 1142 } 1143 1144 static void svc_i3c_master_start_xfer_locked(struct svc_i3c_master *master) 1145 { 1146 struct svc_i3c_xfer *xfer = master->xferqueue.cur; 1147 int ret, i; 1148 1149 if (!xfer) 1150 return; 1151 1152 svc_i3c_master_clear_merrwarn(master); 1153 svc_i3c_master_flush_fifo(master); 1154 1155 for (i = 0; i < xfer->ncmds; i++) { 1156 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; 1157 1158 ret = svc_i3c_master_xfer(master, cmd->rnw, xfer->type, 1159 cmd->addr, cmd->in, cmd->out, 1160 cmd->len, &cmd->read_len, 1161 cmd->continued); 1162 if (ret) 1163 break; 1164 } 1165 1166 xfer->ret = ret; 1167 complete(&xfer->comp); 1168 1169 if (ret < 0) 1170 svc_i3c_master_dequeue_xfer_locked(master, xfer); 1171 1172 xfer = list_first_entry_or_null(&master->xferqueue.list, 1173 struct svc_i3c_xfer, 1174 node); 1175 if (xfer) 1176 list_del_init(&xfer->node); 1177 1178 master->xferqueue.cur = xfer; 1179 svc_i3c_master_start_xfer_locked(master); 1180 } 1181 1182 static void svc_i3c_master_enqueue_xfer(struct svc_i3c_master *master, 1183 struct svc_i3c_xfer *xfer) 1184 { 1185 unsigned long flags; 1186 int ret; 1187 1188 ret = pm_runtime_resume_and_get(master->dev); 1189 if (ret < 0) { 1190 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); 1191 return; 1192 } 1193 1194 init_completion(&xfer->comp); 1195 spin_lock_irqsave(&master->xferqueue.lock, flags); 1196 if (master->xferqueue.cur) { 1197 list_add_tail(&xfer->node, &master->xferqueue.list); 1198 } else { 1199 master->xferqueue.cur = xfer; 1200 svc_i3c_master_start_xfer_locked(master); 1201 } 1202 spin_unlock_irqrestore(&master->xferqueue.lock, flags); 1203 1204 pm_runtime_mark_last_busy(master->dev); 1205 pm_runtime_put_autosuspend(master->dev); 1206 } 1207 1208 static bool 1209 svc_i3c_master_supports_ccc_cmd(struct i3c_master_controller *master, 1210 const struct i3c_ccc_cmd *cmd) 1211 { 1212 /* No software support for CCC commands targeting more than one slave */ 1213 return (cmd->ndests == 1); 1214 } 1215 1216 static int svc_i3c_master_send_bdcast_ccc_cmd(struct svc_i3c_master *master, 1217 struct i3c_ccc_cmd *ccc) 1218 { 1219 unsigned int xfer_len = ccc->dests[0].payload.len + 1; 1220 struct svc_i3c_xfer *xfer; 1221 struct svc_i3c_cmd *cmd; 1222 u8 *buf; 1223 int ret; 1224 1225 xfer = svc_i3c_master_alloc_xfer(master, 1); 1226 if (!xfer) 1227 return -ENOMEM; 1228 1229 buf = kmalloc(xfer_len, GFP_KERNEL); 1230 if (!buf) { 1231 svc_i3c_master_free_xfer(xfer); 1232 return -ENOMEM; 1233 } 1234 1235 buf[0] = ccc->id; 1236 memcpy(&buf[1], ccc->dests[0].payload.data, ccc->dests[0].payload.len); 1237 1238 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; 1239 1240 cmd = &xfer->cmds[0]; 1241 cmd->addr = ccc->dests[0].addr; 1242 cmd->rnw = ccc->rnw; 1243 cmd->in = NULL; 1244 cmd->out = buf; 1245 cmd->len = xfer_len; 1246 cmd->read_len = 0; 1247 cmd->continued = false; 1248 1249 mutex_lock(&master->lock); 1250 svc_i3c_master_enqueue_xfer(master, xfer); 1251 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) 1252 svc_i3c_master_dequeue_xfer(master, xfer); 1253 mutex_unlock(&master->lock); 1254 1255 ret = xfer->ret; 1256 kfree(buf); 1257 svc_i3c_master_free_xfer(xfer); 1258 1259 return ret; 1260 } 1261 1262 static int svc_i3c_master_send_direct_ccc_cmd(struct svc_i3c_master *master, 1263 struct i3c_ccc_cmd *ccc) 1264 { 1265 unsigned int xfer_len = ccc->dests[0].payload.len; 1266 unsigned int read_len = ccc->rnw ? xfer_len : 0; 1267 struct svc_i3c_xfer *xfer; 1268 struct svc_i3c_cmd *cmd; 1269 int ret; 1270 1271 xfer = svc_i3c_master_alloc_xfer(master, 2); 1272 if (!xfer) 1273 return -ENOMEM; 1274 1275 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; 1276 1277 /* Broadcasted message */ 1278 cmd = &xfer->cmds[0]; 1279 cmd->addr = I3C_BROADCAST_ADDR; 1280 cmd->rnw = 0; 1281 cmd->in = NULL; 1282 cmd->out = &ccc->id; 1283 cmd->len = 1; 1284 cmd->read_len = 0; 1285 cmd->continued = true; 1286 1287 /* Directed message */ 1288 cmd = &xfer->cmds[1]; 1289 cmd->addr = ccc->dests[0].addr; 1290 cmd->rnw = ccc->rnw; 1291 cmd->in = ccc->rnw ? ccc->dests[0].payload.data : NULL; 1292 cmd->out = ccc->rnw ? NULL : ccc->dests[0].payload.data, 1293 cmd->len = xfer_len; 1294 cmd->read_len = read_len; 1295 cmd->continued = false; 1296 1297 mutex_lock(&master->lock); 1298 svc_i3c_master_enqueue_xfer(master, xfer); 1299 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) 1300 svc_i3c_master_dequeue_xfer(master, xfer); 1301 mutex_unlock(&master->lock); 1302 1303 if (cmd->read_len != xfer_len) 1304 ccc->dests[0].payload.len = cmd->read_len; 1305 1306 ret = xfer->ret; 1307 svc_i3c_master_free_xfer(xfer); 1308 1309 return ret; 1310 } 1311 1312 static int svc_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, 1313 struct i3c_ccc_cmd *cmd) 1314 { 1315 struct svc_i3c_master *master = to_svc_i3c_master(m); 1316 bool broadcast = cmd->id < 0x80; 1317 int ret; 1318 1319 if (broadcast) 1320 ret = svc_i3c_master_send_bdcast_ccc_cmd(master, cmd); 1321 else 1322 ret = svc_i3c_master_send_direct_ccc_cmd(master, cmd); 1323 1324 if (ret) 1325 cmd->err = I3C_ERROR_M2; 1326 1327 return ret; 1328 } 1329 1330 static int svc_i3c_master_priv_xfers(struct i3c_dev_desc *dev, 1331 struct i3c_priv_xfer *xfers, 1332 int nxfers) 1333 { 1334 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1335 struct svc_i3c_master *master = to_svc_i3c_master(m); 1336 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1337 struct svc_i3c_xfer *xfer; 1338 int ret, i; 1339 1340 xfer = svc_i3c_master_alloc_xfer(master, nxfers); 1341 if (!xfer) 1342 return -ENOMEM; 1343 1344 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; 1345 1346 for (i = 0; i < nxfers; i++) { 1347 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; 1348 1349 cmd->addr = master->addrs[data->index]; 1350 cmd->rnw = xfers[i].rnw; 1351 cmd->in = xfers[i].rnw ? xfers[i].data.in : NULL; 1352 cmd->out = xfers[i].rnw ? NULL : xfers[i].data.out; 1353 cmd->len = xfers[i].len; 1354 cmd->read_len = xfers[i].rnw ? xfers[i].len : 0; 1355 cmd->continued = (i + 1) < nxfers; 1356 } 1357 1358 mutex_lock(&master->lock); 1359 svc_i3c_master_enqueue_xfer(master, xfer); 1360 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) 1361 svc_i3c_master_dequeue_xfer(master, xfer); 1362 mutex_unlock(&master->lock); 1363 1364 ret = xfer->ret; 1365 svc_i3c_master_free_xfer(xfer); 1366 1367 return ret; 1368 } 1369 1370 static int svc_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, 1371 const struct i2c_msg *xfers, 1372 int nxfers) 1373 { 1374 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1375 struct svc_i3c_master *master = to_svc_i3c_master(m); 1376 struct svc_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 1377 struct svc_i3c_xfer *xfer; 1378 int ret, i; 1379 1380 xfer = svc_i3c_master_alloc_xfer(master, nxfers); 1381 if (!xfer) 1382 return -ENOMEM; 1383 1384 xfer->type = SVC_I3C_MCTRL_TYPE_I2C; 1385 1386 for (i = 0; i < nxfers; i++) { 1387 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; 1388 1389 cmd->addr = master->addrs[data->index]; 1390 cmd->rnw = xfers[i].flags & I2C_M_RD; 1391 cmd->in = cmd->rnw ? xfers[i].buf : NULL; 1392 cmd->out = cmd->rnw ? NULL : xfers[i].buf; 1393 cmd->len = xfers[i].len; 1394 cmd->read_len = cmd->rnw ? xfers[i].len : 0; 1395 cmd->continued = (i + 1 < nxfers); 1396 } 1397 1398 mutex_lock(&master->lock); 1399 svc_i3c_master_enqueue_xfer(master, xfer); 1400 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) 1401 svc_i3c_master_dequeue_xfer(master, xfer); 1402 mutex_unlock(&master->lock); 1403 1404 ret = xfer->ret; 1405 svc_i3c_master_free_xfer(xfer); 1406 1407 return ret; 1408 } 1409 1410 static int svc_i3c_master_request_ibi(struct i3c_dev_desc *dev, 1411 const struct i3c_ibi_setup *req) 1412 { 1413 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1414 struct svc_i3c_master *master = to_svc_i3c_master(m); 1415 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1416 unsigned long flags; 1417 unsigned int i; 1418 1419 if (dev->ibi->max_payload_len > SVC_I3C_FIFO_SIZE) { 1420 dev_err(master->dev, "IBI max payload %d should be < %d\n", 1421 dev->ibi->max_payload_len, SVC_I3C_FIFO_SIZE); 1422 return -ERANGE; 1423 } 1424 1425 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); 1426 if (IS_ERR(data->ibi_pool)) 1427 return PTR_ERR(data->ibi_pool); 1428 1429 spin_lock_irqsave(&master->ibi.lock, flags); 1430 for (i = 0; i < master->ibi.num_slots; i++) { 1431 if (!master->ibi.slots[i]) { 1432 data->ibi = i; 1433 master->ibi.slots[i] = dev; 1434 break; 1435 } 1436 } 1437 spin_unlock_irqrestore(&master->ibi.lock, flags); 1438 1439 if (i < master->ibi.num_slots) 1440 return 0; 1441 1442 i3c_generic_ibi_free_pool(data->ibi_pool); 1443 data->ibi_pool = NULL; 1444 1445 return -ENOSPC; 1446 } 1447 1448 static void svc_i3c_master_free_ibi(struct i3c_dev_desc *dev) 1449 { 1450 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1451 struct svc_i3c_master *master = to_svc_i3c_master(m); 1452 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1453 unsigned long flags; 1454 1455 spin_lock_irqsave(&master->ibi.lock, flags); 1456 master->ibi.slots[data->ibi] = NULL; 1457 data->ibi = -1; 1458 spin_unlock_irqrestore(&master->ibi.lock, flags); 1459 1460 i3c_generic_ibi_free_pool(data->ibi_pool); 1461 } 1462 1463 static int svc_i3c_master_enable_ibi(struct i3c_dev_desc *dev) 1464 { 1465 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1466 struct svc_i3c_master *master = to_svc_i3c_master(m); 1467 int ret; 1468 1469 ret = pm_runtime_resume_and_get(master->dev); 1470 if (ret < 0) { 1471 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); 1472 return ret; 1473 } 1474 1475 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART); 1476 1477 return i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); 1478 } 1479 1480 static int svc_i3c_master_disable_ibi(struct i3c_dev_desc *dev) 1481 { 1482 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1483 struct svc_i3c_master *master = to_svc_i3c_master(m); 1484 int ret; 1485 1486 svc_i3c_master_disable_interrupts(master); 1487 1488 ret = i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); 1489 1490 pm_runtime_mark_last_busy(master->dev); 1491 pm_runtime_put_autosuspend(master->dev); 1492 1493 return ret; 1494 } 1495 1496 static void svc_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev, 1497 struct i3c_ibi_slot *slot) 1498 { 1499 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1500 1501 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot); 1502 } 1503 1504 static const struct i3c_master_controller_ops svc_i3c_master_ops = { 1505 .bus_init = svc_i3c_master_bus_init, 1506 .bus_cleanup = svc_i3c_master_bus_cleanup, 1507 .attach_i3c_dev = svc_i3c_master_attach_i3c_dev, 1508 .detach_i3c_dev = svc_i3c_master_detach_i3c_dev, 1509 .reattach_i3c_dev = svc_i3c_master_reattach_i3c_dev, 1510 .attach_i2c_dev = svc_i3c_master_attach_i2c_dev, 1511 .detach_i2c_dev = svc_i3c_master_detach_i2c_dev, 1512 .do_daa = svc_i3c_master_do_daa, 1513 .supports_ccc_cmd = svc_i3c_master_supports_ccc_cmd, 1514 .send_ccc_cmd = svc_i3c_master_send_ccc_cmd, 1515 .priv_xfers = svc_i3c_master_priv_xfers, 1516 .i2c_xfers = svc_i3c_master_i2c_xfers, 1517 .request_ibi = svc_i3c_master_request_ibi, 1518 .free_ibi = svc_i3c_master_free_ibi, 1519 .recycle_ibi_slot = svc_i3c_master_recycle_ibi_slot, 1520 .enable_ibi = svc_i3c_master_enable_ibi, 1521 .disable_ibi = svc_i3c_master_disable_ibi, 1522 }; 1523 1524 static int svc_i3c_master_prepare_clks(struct svc_i3c_master *master) 1525 { 1526 int ret = 0; 1527 1528 ret = clk_prepare_enable(master->pclk); 1529 if (ret) 1530 return ret; 1531 1532 ret = clk_prepare_enable(master->fclk); 1533 if (ret) { 1534 clk_disable_unprepare(master->pclk); 1535 return ret; 1536 } 1537 1538 ret = clk_prepare_enable(master->sclk); 1539 if (ret) { 1540 clk_disable_unprepare(master->pclk); 1541 clk_disable_unprepare(master->fclk); 1542 return ret; 1543 } 1544 1545 return 0; 1546 } 1547 1548 static void svc_i3c_master_unprepare_clks(struct svc_i3c_master *master) 1549 { 1550 clk_disable_unprepare(master->pclk); 1551 clk_disable_unprepare(master->fclk); 1552 clk_disable_unprepare(master->sclk); 1553 } 1554 1555 static int svc_i3c_master_probe(struct platform_device *pdev) 1556 { 1557 struct device *dev = &pdev->dev; 1558 struct svc_i3c_master *master; 1559 int ret; 1560 1561 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); 1562 if (!master) 1563 return -ENOMEM; 1564 1565 master->regs = devm_platform_ioremap_resource(pdev, 0); 1566 if (IS_ERR(master->regs)) 1567 return PTR_ERR(master->regs); 1568 1569 master->pclk = devm_clk_get(dev, "pclk"); 1570 if (IS_ERR(master->pclk)) 1571 return PTR_ERR(master->pclk); 1572 1573 master->fclk = devm_clk_get(dev, "fast_clk"); 1574 if (IS_ERR(master->fclk)) 1575 return PTR_ERR(master->fclk); 1576 1577 master->sclk = devm_clk_get(dev, "slow_clk"); 1578 if (IS_ERR(master->sclk)) 1579 return PTR_ERR(master->sclk); 1580 1581 master->irq = platform_get_irq(pdev, 0); 1582 if (master->irq < 0) 1583 return master->irq; 1584 1585 master->dev = dev; 1586 1587 ret = svc_i3c_master_prepare_clks(master); 1588 if (ret) 1589 return ret; 1590 1591 INIT_WORK(&master->hj_work, svc_i3c_master_hj_work); 1592 INIT_WORK(&master->ibi_work, svc_i3c_master_ibi_work); 1593 mutex_init(&master->lock); 1594 1595 ret = devm_request_irq(dev, master->irq, svc_i3c_master_irq_handler, 1596 IRQF_NO_SUSPEND, "svc-i3c-irq", master); 1597 if (ret) 1598 goto err_disable_clks; 1599 1600 master->free_slots = GENMASK(SVC_I3C_MAX_DEVS - 1, 0); 1601 1602 spin_lock_init(&master->xferqueue.lock); 1603 INIT_LIST_HEAD(&master->xferqueue.list); 1604 1605 spin_lock_init(&master->ibi.lock); 1606 master->ibi.num_slots = SVC_I3C_MAX_DEVS; 1607 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots, 1608 sizeof(*master->ibi.slots), 1609 GFP_KERNEL); 1610 if (!master->ibi.slots) { 1611 ret = -ENOMEM; 1612 goto err_disable_clks; 1613 } 1614 1615 platform_set_drvdata(pdev, master); 1616 1617 pm_runtime_set_autosuspend_delay(&pdev->dev, SVC_I3C_PM_TIMEOUT_MS); 1618 pm_runtime_use_autosuspend(&pdev->dev); 1619 pm_runtime_get_noresume(&pdev->dev); 1620 pm_runtime_set_active(&pdev->dev); 1621 pm_runtime_enable(&pdev->dev); 1622 1623 svc_i3c_master_reset(master); 1624 1625 /* Register the master */ 1626 ret = i3c_master_register(&master->base, &pdev->dev, 1627 &svc_i3c_master_ops, false); 1628 if (ret) 1629 goto rpm_disable; 1630 1631 pm_runtime_mark_last_busy(&pdev->dev); 1632 pm_runtime_put_autosuspend(&pdev->dev); 1633 1634 return 0; 1635 1636 rpm_disable: 1637 pm_runtime_dont_use_autosuspend(&pdev->dev); 1638 pm_runtime_put_noidle(&pdev->dev); 1639 pm_runtime_set_suspended(&pdev->dev); 1640 pm_runtime_disable(&pdev->dev); 1641 1642 err_disable_clks: 1643 svc_i3c_master_unprepare_clks(master); 1644 1645 return ret; 1646 } 1647 1648 static void svc_i3c_master_remove(struct platform_device *pdev) 1649 { 1650 struct svc_i3c_master *master = platform_get_drvdata(pdev); 1651 1652 i3c_master_unregister(&master->base); 1653 1654 pm_runtime_dont_use_autosuspend(&pdev->dev); 1655 pm_runtime_disable(&pdev->dev); 1656 } 1657 1658 static void svc_i3c_save_regs(struct svc_i3c_master *master) 1659 { 1660 master->saved_regs.mconfig = readl(master->regs + SVC_I3C_MCONFIG); 1661 master->saved_regs.mdynaddr = readl(master->regs + SVC_I3C_MDYNADDR); 1662 } 1663 1664 static void svc_i3c_restore_regs(struct svc_i3c_master *master) 1665 { 1666 if (readl(master->regs + SVC_I3C_MDYNADDR) != 1667 master->saved_regs.mdynaddr) { 1668 writel(master->saved_regs.mconfig, 1669 master->regs + SVC_I3C_MCONFIG); 1670 writel(master->saved_regs.mdynaddr, 1671 master->regs + SVC_I3C_MDYNADDR); 1672 } 1673 } 1674 1675 static int __maybe_unused svc_i3c_runtime_suspend(struct device *dev) 1676 { 1677 struct svc_i3c_master *master = dev_get_drvdata(dev); 1678 1679 svc_i3c_save_regs(master); 1680 svc_i3c_master_unprepare_clks(master); 1681 pinctrl_pm_select_sleep_state(dev); 1682 1683 return 0; 1684 } 1685 1686 static int __maybe_unused svc_i3c_runtime_resume(struct device *dev) 1687 { 1688 struct svc_i3c_master *master = dev_get_drvdata(dev); 1689 1690 pinctrl_pm_select_default_state(dev); 1691 svc_i3c_master_prepare_clks(master); 1692 1693 svc_i3c_restore_regs(master); 1694 1695 return 0; 1696 } 1697 1698 static const struct dev_pm_ops svc_i3c_pm_ops = { 1699 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1700 pm_runtime_force_resume) 1701 SET_RUNTIME_PM_OPS(svc_i3c_runtime_suspend, 1702 svc_i3c_runtime_resume, NULL) 1703 }; 1704 1705 static const struct of_device_id svc_i3c_master_of_match_tbl[] = { 1706 { .compatible = "silvaco,i3c-master-v1"}, 1707 { /* sentinel */ }, 1708 }; 1709 MODULE_DEVICE_TABLE(of, svc_i3c_master_of_match_tbl); 1710 1711 static struct platform_driver svc_i3c_master = { 1712 .probe = svc_i3c_master_probe, 1713 .remove_new = svc_i3c_master_remove, 1714 .driver = { 1715 .name = "silvaco-i3c-master", 1716 .of_match_table = svc_i3c_master_of_match_tbl, 1717 .pm = &svc_i3c_pm_ops, 1718 }, 1719 }; 1720 module_platform_driver(svc_i3c_master); 1721 1722 MODULE_AUTHOR("Conor Culhane <conor.culhane@silvaco.com>"); 1723 MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>"); 1724 MODULE_DESCRIPTION("Silvaco dual-role I3C master driver"); 1725 MODULE_LICENSE("GPL v2"); 1726