1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas I3C Controller driver 4 * Copyright (C) 2023-25 Renesas Electronics Corp. 5 * 6 * TODO: IBI support, HotJoin support, Target support 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/bitops.h> 11 #include <linux/cleanup.h> 12 #include <linux/clk.h> 13 #include <linux/completion.h> 14 #include <linux/err.h> 15 #include <linux/errno.h> 16 #include <linux/i2c.h> 17 #include <linux/i3c/master.h> 18 #include <linux/interrupt.h> 19 #include <linux/ioport.h> 20 #include <linux/iopoll.h> 21 #include <linux/list.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/reset.h> 27 #include <linux/slab.h> 28 #include "../internals.h" 29 30 #define PRTS 0x00 31 #define PRTS_PRTMD BIT(0) 32 33 #define BCTL 0x14 34 #define BCTL_INCBA BIT(0) 35 #define BCTL_HJACKCTL BIT(8) 36 #define BCTL_ABT BIT(29) 37 #define BCTL_BUSE BIT(31) 38 39 #define MSDVAD 0x18 40 #define MSDVAD_MDYAD(x) FIELD_PREP(GENMASK(21, 16), x) 41 #define MSDVAD_MDYADV BIT(31) 42 43 #define RSTCTL 0x20 44 #define RSTCTL_RI3CRST BIT(0) 45 #define RSTCTL_INTLRST BIT(16) 46 47 #define INST 0x30 48 49 #define IBINCTL 0x58 50 #define IBINCTL_NRHJCTL BIT(0) 51 #define IBINCTL_NRMRCTL BIT(1) 52 #define IBINCTL_NRSIRCTL BIT(3) 53 54 #define SVCTL 0x64 55 56 #define REFCKCTL 0x70 57 #define REFCKCTL_IREFCKS(x) FIELD_PREP(GENMASK(2, 0), x) 58 59 #define STDBR 0x74 60 #define STDBR_SBRLO(cond, x) FIELD_PREP(GENMASK(7, 0), (x) >> (cond)) 61 #define STDBR_SBRHO(cond, x) FIELD_PREP(GENMASK(15, 8), (x) >> (cond)) 62 #define STDBR_SBRLP(x) FIELD_PREP(GENMASK(21, 16), x) 63 #define STDBR_SBRHP(x) FIELD_PREP(GENMASK(29, 24), x) 64 #define STDBR_DSBRPO BIT(31) 65 66 #define EXTBR 0x78 67 #define EXTBR_EBRLO(x) FIELD_PREP(GENMASK(7, 0), x) 68 #define EXTBR_EBRHO(x) FIELD_PREP(GENMASK(15, 8), x) 69 #define EXTBR_EBRLP(x) FIELD_PREP(GENMASK(21, 16), x) 70 #define EXTBR_EBRHP(x) FIELD_PREP(GENMASK(29, 24), x) 71 72 #define BFRECDT 0x7c 73 #define BFRECDT_FRECYC(x) FIELD_PREP(GENMASK(8, 0), x) 74 75 #define BAVLCDT 0x80 76 #define BAVLCDT_AVLCYC(x) FIELD_PREP(GENMASK(8, 0), x) 77 78 #define BIDLCDT 0x84 79 #define BIDLCDT_IDLCYC(x) FIELD_PREP(GENMASK(17, 0), x) 80 81 #define ACKCTL 0xa0 82 #define ACKCTL_ACKT BIT(1) 83 #define ACKCTL_ACKTWP BIT(2) 84 85 #define SCSTRCTL 0xa4 86 #define SCSTRCTL_ACKTWE BIT(0) 87 #define SCSTRCTL_RWE BIT(1) 88 89 #define SCSTLCTL 0xb0 90 91 #define CNDCTL 0x140 92 #define CNDCTL_STCND BIT(0) 93 #define CNDCTL_SRCND BIT(1) 94 #define CNDCTL_SPCND BIT(2) 95 96 #define NCMDQP 0x150 /* Normal Command Queue */ 97 #define NCMDQP_CMD_ATTR(x) FIELD_PREP(GENMASK(2, 0), x) 98 #define NCMDQP_IMMED_XFER 0x01 99 #define NCMDQP_ADDR_ASSGN 0x02 100 #define NCMDQP_TID(x) FIELD_PREP(GENMASK(6, 3), x) 101 #define NCMDQP_CMD(x) FIELD_PREP(GENMASK(14, 7), x) 102 #define NCMDQP_CP BIT(15) 103 #define NCMDQP_DEV_INDEX(x) FIELD_PREP(GENMASK(20, 16), x) 104 #define NCMDQP_BYTE_CNT(x) FIELD_PREP(GENMASK(25, 23), x) 105 #define NCMDQP_DEV_COUNT(x) FIELD_PREP(GENMASK(29, 26), x) 106 #define NCMDQP_MODE(x) FIELD_PREP(GENMASK(28, 26), x) 107 #define NCMDQP_RNW(x) FIELD_PREP(GENMASK(29, 29), x) 108 #define NCMDQP_ROC BIT(30) 109 #define NCMDQP_TOC BIT(31) 110 #define NCMDQP_DATA_LENGTH(x) FIELD_PREP(GENMASK(31, 16), x) 111 112 #define NRSPQP 0x154 /* Normal Respone Queue */ 113 #define NRSPQP_NO_ERROR 0 114 #define NRSPQP_ERROR_CRC 1 115 #define NRSPQP_ERROR_PARITY 2 116 #define NRSPQP_ERROR_FRAME 3 117 #define NRSPQP_ERROR_IBA_NACK 4 118 #define NRSPQP_ERROR_ADDRESS_NACK 5 119 #define NRSPQP_ERROR_OVER_UNDER_FLOW 6 120 #define NRSPQP_ERROR_TRANSF_ABORT 8 121 #define NRSPQP_ERROR_I2C_W_NACK_ERR 9 122 #define NRSPQP_ERROR_UNSUPPORTED 10 123 #define NRSPQP_DATA_LEN(x) FIELD_GET(GENMASK(15, 0), x) 124 #define NRSPQP_ERR_STATUS(x) FIELD_GET(GENMASK(31, 28), x) 125 126 #define NTDTBP0 0x158 /* Normal Transfer Data Buffer */ 127 #define NTDTBP0_DEPTH 16 128 129 #define NQTHCTL 0x190 130 #define NQTHCTL_CMDQTH(x) FIELD_PREP(GENMASK(1, 0), x) 131 #define NQTHCTL_IBIDSSZ(x) FIELD_PREP(GENMASK(23, 16), x) 132 133 #define NTBTHCTL0 0x194 134 135 #define NRQTHCTL 0x1c0 136 137 #define BST 0x1d0 138 #define BST_STCNDDF BIT(0) 139 #define BST_SPCNDDF BIT(1) 140 #define BST_NACKDF BIT(4) 141 #define BST_TENDF BIT(8) 142 143 #define BSTE 0x1d4 144 #define BSTE_STCNDDE BIT(0) 145 #define BSTE_SPCNDDE BIT(1) 146 #define BSTE_NACKDE BIT(4) 147 #define BSTE_TENDE BIT(8) 148 #define BSTE_ALE BIT(16) 149 #define BSTE_TODE BIT(20) 150 #define BSTE_WUCNDDE BIT(24) 151 #define BSTE_ALL_FLAG (BSTE_STCNDDE | BSTE_SPCNDDE |\ 152 BSTE_NACKDE | BSTE_TENDE |\ 153 BSTE_ALE | BSTE_TODE | BSTE_WUCNDDE) 154 155 #define BIE 0x1d8 156 #define BIE_STCNDDIE BIT(0) 157 #define BIE_SPCNDDIE BIT(1) 158 #define BIE_NACKDIE BIT(4) 159 #define BIE_TENDIE BIT(8) 160 161 #define NTST 0x1e0 162 #define NTST_TDBEF0 BIT(0) 163 #define NTST_RDBFF0 BIT(1) 164 #define NTST_CMDQEF BIT(3) 165 #define NTST_RSPQFF BIT(4) 166 #define NTST_TABTF BIT(5) 167 #define NTST_TEF BIT(9) 168 169 #define NTSTE 0x1e4 170 #define NTSTE_TDBEE0 BIT(0) 171 #define NTSTE_RDBFE0 BIT(1) 172 #define NTSTE_IBIQEFE BIT(2) 173 #define NTSTE_CMDQEE BIT(3) 174 #define NTSTE_RSPQFE BIT(4) 175 #define NTSTE_TABTE BIT(5) 176 #define NTSTE_TEE BIT(9) 177 #define NTSTE_RSQFE BIT(20) 178 #define NTSTE_ALL_FLAG (NTSTE_TDBEE0 | NTSTE_RDBFE0 |\ 179 NTSTE_IBIQEFE | NTSTE_CMDQEE |\ 180 NTSTE_RSPQFE | NTSTE_TABTE |\ 181 NTSTE_TEE | NTSTE_RSQFE) 182 183 #define NTIE 0x1e8 184 #define NTIE_TDBEIE0 BIT(0) 185 #define NTIE_RDBFIE0 BIT(1) 186 #define NTIE_IBIQEFIE BIT(2) 187 #define NTIE_RSPQFIE BIT(4) 188 #define NTIE_RSQFIE BIT(20) 189 190 #define BCST 0x210 191 #define BCST_BFREF BIT(0) 192 193 #define DATBAS(x) (0x224 + 0x8 * (x)) 194 #define DATBAS_DVSTAD(x) FIELD_PREP(GENMASK(6, 0), x) 195 #define DATBAS_DVDYAD(x) FIELD_PREP(GENMASK(23, 16), x) 196 197 #define NDBSTLV0 0x398 198 #define NDBSTLV0_RDBLV(x) FIELD_GET(GENMASK(15, 8), x) 199 200 #define RENESAS_I3C_MAX_DEVS 8 201 #define I2C_INIT_MSG -1 202 203 enum i3c_internal_state { 204 I3C_INTERNAL_STATE_DISABLED, 205 I3C_INTERNAL_STATE_CONTROLLER_IDLE, 206 I3C_INTERNAL_STATE_CONTROLLER_ENTDAA, 207 I3C_INTERNAL_STATE_CONTROLLER_SETDASA, 208 I3C_INTERNAL_STATE_CONTROLLER_WRITE, 209 I3C_INTERNAL_STATE_CONTROLLER_READ, 210 I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE, 211 I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ, 212 }; 213 214 enum renesas_i3c_event { 215 I3C_COMMAND_ADDRESS_ASSIGNMENT, 216 I3C_WRITE, 217 I3C_READ, 218 I3C_COMMAND_WRITE, 219 I3C_COMMAND_READ, 220 }; 221 222 struct renesas_i3c_cmd { 223 const void *tx_buf; 224 void *rx_buf; 225 /* i2c xfer */ 226 u8 *i2c_buf; 227 const struct i2c_msg *msg; 228 int i2c_bytes_left; 229 int i2c_is_last; 230 u32 cmd0; 231 u32 len; 232 u32 tx_count; 233 u32 rx_count; 234 u32 err; 235 u8 rnw; 236 }; 237 238 struct renesas_i3c_xfer { 239 struct list_head node; 240 struct completion comp; 241 int ret; 242 bool is_i2c_xfer; 243 unsigned int ncmds; 244 struct renesas_i3c_cmd cmds[] __counted_by(ncmds); 245 }; 246 247 struct renesas_i3c_xferqueue { 248 struct list_head list; 249 struct renesas_i3c_xfer *cur; 250 /* Lock for accessing the xfer queue */ 251 spinlock_t lock; 252 }; 253 254 struct renesas_i3c { 255 void __iomem *regs; 256 struct clk *tclk; 257 struct reset_control *presetn; 258 struct reset_control *tresetn; 259 struct device *dev; 260 struct renesas_i3c_xferqueue xferqueue; 261 struct i3c_master_controller base; 262 u8 addrs[RENESAS_I3C_MAX_DEVS]; 263 unsigned long rate; 264 enum i3c_internal_state internal_state; 265 u32 free_pos; 266 u32 dyn_addr; 267 u32 i2c_STDBR; 268 u32 i3c_STDBR; 269 u32 extbr; 270 u16 maxdevs; 271 u8 refclk_div; 272 }; 273 274 struct renesas_i3c_i2c_dev_data { 275 u8 index; 276 }; 277 278 struct renesas_i3c_irq_desc { 279 const char *name; 280 irq_handler_t isr; 281 const char *desc; 282 }; 283 284 static inline void renesas_i3c_reg_update(void __iomem *reg, u32 mask, u32 val) 285 { 286 u32 data = readl(reg); 287 288 data &= ~mask; 289 data |= (val & mask); 290 writel(data, reg); 291 } 292 293 static inline u32 renesas_readl(void __iomem *base, u32 reg) 294 { 295 return readl(base + reg); 296 } 297 298 static inline void renesas_writel(void __iomem *base, u32 reg, u32 val) 299 { 300 writel(val, base + reg); 301 } 302 303 static void renesas_set_bit(void __iomem *base, u32 reg, u32 val) 304 { 305 renesas_i3c_reg_update(base + reg, val, val); 306 } 307 308 static void renesas_clear_bit(void __iomem *base, u32 reg, u32 val) 309 { 310 renesas_i3c_reg_update(base + reg, val, 0); 311 } 312 313 static inline struct renesas_i3c *to_renesas_i3c(struct i3c_master_controller *m) 314 { 315 return container_of(m, struct renesas_i3c, base); 316 } 317 318 static inline u32 datbas_dvdyad_with_parity(u8 addr) 319 { 320 return DATBAS_DVDYAD(addr | (parity8(addr) ? 0 : BIT(7))); 321 } 322 323 static int renesas_i3c_get_free_pos(struct renesas_i3c *i3c) 324 { 325 if (!(i3c->free_pos & GENMASK(i3c->maxdevs - 1, 0))) 326 return -ENOSPC; 327 328 return ffs(i3c->free_pos) - 1; 329 } 330 331 static int renesas_i3c_get_addr_pos(struct renesas_i3c *i3c, u8 addr) 332 { 333 int pos; 334 335 for (pos = 0; pos < i3c->maxdevs; pos++) { 336 if (addr == i3c->addrs[pos]) 337 return pos; 338 } 339 340 return -EINVAL; 341 } 342 343 static struct renesas_i3c_xfer *renesas_i3c_alloc_xfer(struct renesas_i3c *i3c, 344 unsigned int ncmds) 345 { 346 struct renesas_i3c_xfer *xfer; 347 348 xfer = kzalloc_flex(*xfer, cmds, ncmds); 349 if (!xfer) 350 return NULL; 351 352 INIT_LIST_HEAD(&xfer->node); 353 xfer->ncmds = ncmds; 354 xfer->ret = -ETIMEDOUT; 355 356 return xfer; 357 } 358 359 static void renesas_i3c_start_xfer_locked(struct renesas_i3c *i3c) 360 { 361 struct renesas_i3c_xfer *xfer = i3c->xferqueue.cur; 362 struct renesas_i3c_cmd *cmd; 363 u32 cmd1; 364 365 if (!xfer) 366 return; 367 368 cmd = xfer->cmds; 369 370 switch (i3c->internal_state) { 371 case I3C_INTERNAL_STATE_CONTROLLER_ENTDAA: 372 case I3C_INTERNAL_STATE_CONTROLLER_SETDASA: 373 renesas_set_bit(i3c->regs, NTIE, NTIE_RSPQFIE); 374 renesas_writel(i3c->regs, NCMDQP, cmd->cmd0); 375 renesas_writel(i3c->regs, NCMDQP, 0); 376 break; 377 case I3C_INTERNAL_STATE_CONTROLLER_WRITE: 378 case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE: 379 renesas_set_bit(i3c->regs, NTIE, NTIE_RSPQFIE); 380 if (cmd->len <= 4) { 381 cmd->cmd0 |= NCMDQP_CMD_ATTR(NCMDQP_IMMED_XFER); 382 cmd->cmd0 |= NCMDQP_BYTE_CNT(cmd->len); 383 cmd->tx_count = cmd->len; 384 cmd1 = cmd->len == 0 ? 0 : *(u32 *)cmd->tx_buf; 385 } else { 386 cmd1 = NCMDQP_DATA_LENGTH(cmd->len); 387 } 388 renesas_writel(i3c->regs, NCMDQP, cmd->cmd0); 389 renesas_writel(i3c->regs, NCMDQP, cmd1); 390 break; 391 case I3C_INTERNAL_STATE_CONTROLLER_READ: 392 case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ: 393 renesas_set_bit(i3c->regs, NTIE, NTIE_RDBFIE0); 394 cmd1 = NCMDQP_DATA_LENGTH(cmd->len); 395 renesas_writel(i3c->regs, NCMDQP, cmd->cmd0); 396 renesas_writel(i3c->regs, NCMDQP, cmd1); 397 break; 398 default: 399 break; 400 } 401 402 /* Clear the command queue empty flag */ 403 renesas_clear_bit(i3c->regs, NTST, NTST_CMDQEF); 404 } 405 406 static void renesas_i3c_dequeue_xfer_locked(struct renesas_i3c *i3c, 407 struct renesas_i3c_xfer *xfer) 408 { 409 if (i3c->xferqueue.cur == xfer) 410 i3c->xferqueue.cur = NULL; 411 else 412 list_del_init(&xfer->node); 413 } 414 415 static void renesas_i3c_dequeue_xfer(struct renesas_i3c *i3c, struct renesas_i3c_xfer *xfer) 416 { 417 scoped_guard(spinlock_irqsave, &i3c->xferqueue.lock) 418 renesas_i3c_dequeue_xfer_locked(i3c, xfer); 419 } 420 421 static void renesas_i3c_enqueue_xfer(struct renesas_i3c *i3c, struct renesas_i3c_xfer *xfer) 422 { 423 reinit_completion(&xfer->comp); 424 scoped_guard(spinlock_irqsave, &i3c->xferqueue.lock) { 425 if (i3c->xferqueue.cur) { 426 list_add_tail(&xfer->node, &i3c->xferqueue.list); 427 } else { 428 i3c->xferqueue.cur = xfer; 429 if (!xfer->is_i2c_xfer) 430 renesas_i3c_start_xfer_locked(i3c); 431 } 432 } 433 } 434 435 static void renesas_i3c_irqs_mask_and_clear_locked(struct renesas_i3c *i3c) 436 { 437 /* Disable all the interrupts. */ 438 renesas_writel(i3c->regs, BIE, 0); 439 renesas_writel(i3c->regs, NTIE, 0); 440 441 /* Clear normal transfer status flags. */ 442 renesas_writel(i3c->regs, NTST, 0); 443 444 /* Clear bus status flags. */ 445 renesas_writel(i3c->regs, BST, 0); 446 /* Read back registers to confirm writes have fully propagated. */ 447 renesas_readl(i3c->regs, BST); 448 } 449 450 static void renesas_i3c_irqs_mask_and_clear(struct renesas_i3c *i3c) 451 { 452 guard(spinlock_irqsave)(&i3c->xferqueue.lock); 453 454 renesas_i3c_irqs_mask_and_clear_locked(i3c); 455 } 456 457 static unsigned long renesas_i3c_wait_xfer(struct renesas_i3c *i3c, struct renesas_i3c_xfer *xfer) 458 { 459 unsigned long time_left; 460 461 renesas_i3c_enqueue_xfer(i3c, xfer); 462 463 time_left = wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)); 464 if (!time_left) 465 renesas_i3c_dequeue_xfer(i3c, xfer); 466 467 return time_left; 468 } 469 470 static void renesas_i3c_set_prts(struct renesas_i3c *i3c, u32 val) 471 { 472 /* Required sequence according to tnrza0140ae */ 473 renesas_set_bit(i3c->regs, RSTCTL, RSTCTL_INTLRST); 474 renesas_writel(i3c->regs, PRTS, val); 475 renesas_clear_bit(i3c->regs, RSTCTL, RSTCTL_INTLRST); 476 } 477 478 static void renesas_i3c_bus_enable(struct i3c_master_controller *m, bool i3c_mode) 479 { 480 struct renesas_i3c *i3c = to_renesas_i3c(m); 481 482 /* Setup either I3C or I2C protocol */ 483 if (i3c_mode) { 484 renesas_i3c_set_prts(i3c, 0); 485 /* Revisit: INCBA handling, especially after I2C transfers */ 486 renesas_set_bit(i3c->regs, BCTL, BCTL_HJACKCTL | BCTL_INCBA); 487 renesas_set_bit(i3c->regs, MSDVAD, MSDVAD_MDYADV); 488 renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR); 489 } else { 490 renesas_i3c_set_prts(i3c, PRTS_PRTMD); 491 renesas_writel(i3c->regs, STDBR, i3c->i2c_STDBR); 492 } 493 494 /* Enable I3C bus */ 495 renesas_set_bit(i3c->regs, BCTL, BCTL_BUSE); 496 } 497 498 static int renesas_i3c_reset(struct renesas_i3c *i3c) 499 { 500 u32 val; 501 int ret; 502 503 PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(i3c->dev, pm); 504 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 505 if (ret) 506 return ret; 507 508 renesas_writel(i3c->regs, BCTL, 0); 509 renesas_set_bit(i3c->regs, RSTCTL, RSTCTL_RI3CRST); 510 511 return read_poll_timeout(renesas_readl, val, !(val & RSTCTL_RI3CRST), 512 0, 1000, false, i3c->regs, RSTCTL); 513 } 514 515 static void renesas_i3c_hw_init(struct renesas_i3c *i3c) 516 { 517 u32 val; 518 519 /* Disable Slave Mode */ 520 renesas_writel(i3c->regs, SVCTL, 0); 521 522 /* Initialize Queue/Buffer threshold */ 523 renesas_writel(i3c->regs, NQTHCTL, NQTHCTL_IBIDSSZ(6) | 524 NQTHCTL_CMDQTH(1)); 525 526 /* The only supported configuration is two entries*/ 527 renesas_writel(i3c->regs, NTBTHCTL0, 0); 528 /* Interrupt when there is one entry in the queue */ 529 renesas_writel(i3c->regs, NRQTHCTL, 0); 530 531 /* Enable all Bus/Transfer Status Flags */ 532 renesas_writel(i3c->regs, BSTE, BSTE_ALL_FLAG); 533 renesas_writel(i3c->regs, NTSTE, NTSTE_ALL_FLAG); 534 535 /* Interrupt enable settings */ 536 renesas_writel(i3c->regs, BIE, BIE_NACKDIE | BIE_TENDIE); 537 renesas_writel(i3c->regs, NTIE, 0); 538 539 /* Clear Status register */ 540 renesas_writel(i3c->regs, NTST, 0); 541 renesas_writel(i3c->regs, INST, 0); 542 renesas_writel(i3c->regs, BST, 0); 543 544 /* Hot-Join Acknowlege setting. */ 545 renesas_set_bit(i3c->regs, BCTL, BCTL_HJACKCTL); 546 547 renesas_writel(i3c->regs, IBINCTL, IBINCTL_NRHJCTL | IBINCTL_NRMRCTL | 548 IBINCTL_NRSIRCTL); 549 550 renesas_writel(i3c->regs, SCSTLCTL, 0); 551 renesas_set_bit(i3c->regs, SCSTRCTL, SCSTRCTL_ACKTWE); 552 553 /* Bus condition timing */ 554 val = DIV_ROUND_UP(I3C_BUS_TBUF_MIXED_FM_MIN_NS, 555 NSEC_PER_SEC / i3c->rate); 556 renesas_writel(i3c->regs, BFRECDT, BFRECDT_FRECYC(val)); 557 558 val = DIV_ROUND_UP(I3C_BUS_TAVAL_MIN_NS, 559 NSEC_PER_SEC / i3c->rate); 560 renesas_writel(i3c->regs, BAVLCDT, BAVLCDT_AVLCYC(val)); 561 562 val = DIV_ROUND_UP(I3C_BUS_TIDLE_MIN_NS, 563 NSEC_PER_SEC / i3c->rate); 564 renesas_writel(i3c->regs, BIDLCDT, BIDLCDT_IDLCYC(val)); 565 } 566 567 static int renesas_i3c_bus_init(struct i3c_master_controller *m) 568 { 569 struct renesas_i3c *i3c = to_renesas_i3c(m); 570 struct i3c_bus *bus = i3c_master_get_bus(m); 571 struct i3c_device_info info = {}; 572 struct i2c_timings t; 573 u32 double_SBR; 574 int cks, pp_high_ticks, pp_low_ticks, i3c_total_ticks; 575 int od_high_ticks, od_low_ticks, i2c_total_ticks; 576 int ret; 577 578 i3c->rate = clk_get_rate(i3c->tclk); 579 if (!i3c->rate) 580 return -EINVAL; 581 582 i2c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i2c); 583 i3c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i3c); 584 585 i2c_parse_fw_timings(&m->dev, &t, true); 586 587 for (cks = 0; cks < 7; cks++) { 588 /* SCL low-period calculation in Open-drain mode */ 589 od_low_ticks = ((i2c_total_ticks * 6) / 10); 590 591 /* SCL clock calculation in Push-Pull mode */ 592 if (bus->mode == I3C_BUS_MODE_PURE) 593 pp_high_ticks = ((i3c_total_ticks * 5) / 10); 594 else 595 pp_high_ticks = DIV_ROUND_UP(I3C_BUS_THIGH_MIXED_MAX_NS, 596 NSEC_PER_SEC / i3c->rate); 597 pp_low_ticks = i3c_total_ticks - pp_high_ticks; 598 599 if ((od_low_ticks / 2) <= 0xFF && pp_low_ticks < 0x3F) 600 break; 601 602 i2c_total_ticks /= 2; 603 i3c_total_ticks /= 2; 604 i3c->rate /= 2; 605 } 606 607 /* SCL clock period calculation in Open-drain mode */ 608 if ((od_low_ticks / 2) > 0xFF || pp_low_ticks > 0x3F) { 609 dev_err(&m->dev, "invalid speed (i2c-scl = %lu Hz, i3c-scl = %lu Hz). Too slow.\n", 610 (unsigned long)bus->scl_rate.i2c, (unsigned long)bus->scl_rate.i3c); 611 return -EINVAL; 612 } 613 614 /* SCL high-period calculation in Open-drain mode */ 615 od_high_ticks = i2c_total_ticks - od_low_ticks; 616 617 /* Standard Bit Rate setting */ 618 double_SBR = od_low_ticks > 0xFF ? 1 : 0; 619 i3c->i3c_STDBR = (double_SBR ? STDBR_DSBRPO : 0) | 620 STDBR_SBRLO(double_SBR, od_low_ticks) | 621 STDBR_SBRHO(double_SBR, od_high_ticks) | 622 STDBR_SBRLP(pp_low_ticks) | 623 STDBR_SBRHP(pp_high_ticks); 624 625 od_low_ticks -= t.scl_fall_ns / (NSEC_PER_SEC / i3c->rate) + 1; 626 od_high_ticks -= t.scl_rise_ns / (NSEC_PER_SEC / i3c->rate) + 1; 627 i3c->i2c_STDBR = (double_SBR ? STDBR_DSBRPO : 0) | 628 STDBR_SBRLO(double_SBR, od_low_ticks) | 629 STDBR_SBRHO(double_SBR, od_high_ticks) | 630 STDBR_SBRLP(pp_low_ticks) | 631 STDBR_SBRHP(pp_high_ticks); 632 633 /* Extended Bit Rate setting */ 634 i3c->extbr = EXTBR_EBRLO(od_low_ticks) | EXTBR_EBRHO(od_high_ticks) | 635 EXTBR_EBRLP(pp_low_ticks) | EXTBR_EBRHP(pp_high_ticks); 636 637 ret = i3c_master_get_free_addr(m, 0); 638 if (ret < 0) 639 return ret; 640 641 info.dyn_addr = ret; 642 i3c->dyn_addr = ret; 643 i3c->refclk_div = cks; 644 645 ret = renesas_i3c_reset(i3c); 646 if (ret) 647 return ret; 648 649 PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(i3c->dev, pm); 650 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 651 if (ret) 652 return ret; 653 654 renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR); 655 renesas_writel(i3c->regs, EXTBR, i3c->extbr); 656 renesas_writel(i3c->regs, REFCKCTL, REFCKCTL_IREFCKS(cks)); 657 renesas_writel(i3c->regs, MSDVAD, MSDVAD_MDYAD(i3c->dyn_addr) | MSDVAD_MDYADV); 658 659 /* I3C hw init*/ 660 renesas_i3c_hw_init(i3c); 661 662 return i3c_master_set_info(&i3c->base, &info); 663 } 664 665 static void renesas_i3c_bus_cleanup(struct i3c_master_controller *m) 666 { 667 struct renesas_i3c *i3c = to_renesas_i3c(m); 668 669 renesas_i3c_reset(i3c); 670 } 671 672 static int renesas_i3c_daa(struct i3c_master_controller *m) 673 { 674 struct renesas_i3c *i3c = to_renesas_i3c(m); 675 struct renesas_i3c_cmd *cmd; 676 unsigned long time_left; 677 u32 olddevs, newdevs; 678 u8 last_addr = 0, pos; 679 int ret; 680 681 struct renesas_i3c_xfer *xfer __free(kfree) = renesas_i3c_alloc_xfer(i3c, 1); 682 if (!xfer) 683 return -ENOMEM; 684 685 init_completion(&xfer->comp); 686 cmd = xfer->cmds; 687 cmd->rx_count = i3c->maxdevs; 688 689 PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(i3c->dev, pm); 690 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 691 if (ret) 692 return ret; 693 694 /* Enable I3C bus. */ 695 renesas_i3c_bus_enable(m, true); 696 697 olddevs = ~(i3c->free_pos); 698 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_ENTDAA; 699 700 /* Setting DATBASn registers for target devices. */ 701 for (pos = 0; pos < i3c->maxdevs; pos++) { 702 if (olddevs & BIT(pos)) 703 continue; 704 705 ret = i3c_master_get_free_addr(m, last_addr + 1); 706 if (ret < 0) 707 return -ENOSPC; 708 709 i3c->addrs[pos] = ret; 710 last_addr = ret; 711 712 renesas_writel(i3c->regs, DATBAS(pos), datbas_dvdyad_with_parity(ret)); 713 } 714 715 ret = renesas_i3c_get_free_pos(i3c); 716 if (ret < 0) 717 return ret; 718 719 /* 720 * Setup the command descriptor to start the ENTDAA command 721 * and starting at the selected device index. 722 */ 723 cmd->cmd0 = NCMDQP_CMD_ATTR(NCMDQP_ADDR_ASSGN) | NCMDQP_ROC | 724 NCMDQP_TID(I3C_COMMAND_ADDRESS_ASSIGNMENT) | 725 NCMDQP_CMD(I3C_CCC_ENTDAA) | NCMDQP_DEV_INDEX(ret) | 726 NCMDQP_DEV_COUNT(i3c->maxdevs - ret) | NCMDQP_TOC; 727 728 time_left = renesas_i3c_wait_xfer(i3c, xfer); 729 if (!time_left) 730 renesas_i3c_irqs_mask_and_clear(i3c); 731 732 if (cmd->rx_count >= i3c->maxdevs) 733 newdevs = 0; 734 else 735 newdevs = GENMASK(i3c->maxdevs - cmd->rx_count - 1, 0); 736 737 newdevs &= ~olddevs; 738 739 for (pos = 0; pos < i3c->maxdevs; pos++) { 740 if (newdevs & BIT(pos)) 741 i3c_master_add_i3c_dev_locked(m, i3c->addrs[pos]); 742 } 743 744 return 0; 745 } 746 747 static bool renesas_i3c_supports_ccc_cmd(struct i3c_master_controller *m, 748 const struct i3c_ccc_cmd *cmd) 749 { 750 if (cmd->ndests > 1) 751 return false; 752 753 switch (cmd->id) { 754 case I3C_CCC_ENEC(true): 755 case I3C_CCC_ENEC(false): 756 case I3C_CCC_DISEC(true): 757 case I3C_CCC_DISEC(false): 758 case I3C_CCC_ENTAS(0, true): 759 case I3C_CCC_ENTAS(1, true): 760 case I3C_CCC_ENTAS(2, true): 761 case I3C_CCC_ENTAS(3, true): 762 case I3C_CCC_ENTAS(0, false): 763 case I3C_CCC_ENTAS(1, false): 764 case I3C_CCC_ENTAS(2, false): 765 case I3C_CCC_ENTAS(3, false): 766 case I3C_CCC_RSTDAA(true): 767 case I3C_CCC_RSTDAA(false): 768 case I3C_CCC_ENTDAA: 769 case I3C_CCC_DEFSLVS: 770 case I3C_CCC_SETMWL(true): 771 case I3C_CCC_SETMWL(false): 772 case I3C_CCC_SETMRL(true): 773 case I3C_CCC_SETMRL(false): 774 case I3C_CCC_ENTTM: 775 case I3C_CCC_SETDASA: 776 case I3C_CCC_SETNEWDA: 777 case I3C_CCC_GETMWL: 778 case I3C_CCC_GETMRL: 779 case I3C_CCC_GETPID: 780 case I3C_CCC_GETBCR: 781 case I3C_CCC_GETDCR: 782 case I3C_CCC_GETSTATUS: 783 case I3C_CCC_GETACCMST: 784 case I3C_CCC_GETMXDS: 785 return true; 786 default: 787 return false; 788 } 789 } 790 791 static int renesas_i3c_send_ccc_cmd(struct i3c_master_controller *m, 792 struct i3c_ccc_cmd *ccc) 793 { 794 struct renesas_i3c *i3c = to_renesas_i3c(m); 795 struct renesas_i3c_cmd *cmd; 796 unsigned long time_left; 797 int ret, pos = 0; 798 799 if (ccc->id & I3C_CCC_DIRECT) { 800 pos = renesas_i3c_get_addr_pos(i3c, ccc->dests[0].addr); 801 if (pos < 0) 802 return pos; 803 } 804 805 struct renesas_i3c_xfer *xfer __free(kfree) = renesas_i3c_alloc_xfer(i3c, 1); 806 if (!xfer) 807 return -ENOMEM; 808 809 init_completion(&xfer->comp); 810 cmd = xfer->cmds; 811 cmd->rnw = ccc->rnw; 812 cmd->cmd0 = 0; 813 814 PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(i3c->dev, pm); 815 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 816 if (ret) 817 return ret; 818 819 renesas_i3c_bus_enable(m, true); 820 821 /* Calculate the command descriptor. */ 822 switch (ccc->id) { 823 case I3C_CCC_SETDASA: 824 renesas_writel(i3c->regs, DATBAS(pos), 825 DATBAS_DVSTAD(ccc->dests[0].addr) | 826 DATBAS_DVDYAD(*(u8 *)ccc->dests[0].payload.data >> 1)); 827 cmd->cmd0 = NCMDQP_CMD_ATTR(NCMDQP_ADDR_ASSGN) | NCMDQP_ROC | 828 NCMDQP_TID(I3C_COMMAND_ADDRESS_ASSIGNMENT) | 829 NCMDQP_CMD(I3C_CCC_SETDASA) | NCMDQP_DEV_INDEX(pos) | 830 NCMDQP_DEV_COUNT(0) | NCMDQP_TOC; 831 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_SETDASA; 832 break; 833 default: 834 /* Calculate the command descriptor. */ 835 cmd->cmd0 = NCMDQP_TID(I3C_COMMAND_WRITE) | NCMDQP_MODE(0) | 836 NCMDQP_RNW(ccc->rnw) | NCMDQP_CMD(ccc->id) | 837 NCMDQP_ROC | NCMDQP_TOC | NCMDQP_CP | 838 NCMDQP_DEV_INDEX(pos); 839 840 if (ccc->rnw) { 841 cmd->rx_buf = ccc->dests[0].payload.data; 842 cmd->len = ccc->dests[0].payload.len; 843 cmd->rx_count = 0; 844 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ; 845 } else { 846 cmd->tx_buf = ccc->dests[0].payload.data; 847 cmd->len = ccc->dests[0].payload.len; 848 cmd->tx_count = 0; 849 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE; 850 } 851 } 852 853 time_left = renesas_i3c_wait_xfer(i3c, xfer); 854 if (!time_left) 855 renesas_i3c_irqs_mask_and_clear(i3c); 856 857 ret = xfer->ret; 858 if (ret) 859 ccc->err = I3C_ERROR_M2; 860 else if (ccc->rnw) 861 ccc->dests[0].payload.actual_len = cmd->rx_count; 862 863 return ret; 864 } 865 866 static int renesas_i3c_i3c_xfers(struct i3c_dev_desc *dev, struct i3c_xfer *i3c_xfers, 867 int i3c_nxfers, enum i3c_xfer_mode mode) 868 { 869 struct i3c_master_controller *m = i3c_dev_get_master(dev); 870 struct renesas_i3c *i3c = to_renesas_i3c(m); 871 struct renesas_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 872 unsigned long time_left; 873 bool xfer_failed = false; 874 int i, ret; 875 876 struct renesas_i3c_xfer *xfer __free(kfree) = renesas_i3c_alloc_xfer(i3c, 1); 877 if (!xfer) 878 return -ENOMEM; 879 880 init_completion(&xfer->comp); 881 882 PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(i3c->dev, pm); 883 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 884 if (ret) 885 return ret; 886 887 /* Enable I3C bus. */ 888 renesas_i3c_bus_enable(m, true); 889 890 for (i = 0; i < i3c_nxfers; i++) { 891 struct renesas_i3c_cmd *cmd = xfer->cmds; 892 893 /* Calculate the Transfer Command Descriptor */ 894 cmd->rnw = i3c_xfers[i].rnw; 895 cmd->cmd0 = NCMDQP_DEV_INDEX(data->index) | NCMDQP_MODE(0) | 896 NCMDQP_RNW(cmd->rnw) | NCMDQP_ROC | NCMDQP_TOC; 897 898 if (i3c_xfers[i].rnw) { 899 cmd->rx_count = 0; 900 cmd->cmd0 |= NCMDQP_TID(I3C_READ); 901 cmd->rx_buf = i3c_xfers[i].data.in; 902 cmd->len = i3c_xfers[i].len; 903 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_READ; 904 } else { 905 cmd->tx_count = 0; 906 cmd->cmd0 |= NCMDQP_TID(I3C_WRITE); 907 cmd->tx_buf = i3c_xfers[i].data.out; 908 cmd->len = i3c_xfers[i].len; 909 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_WRITE; 910 } 911 912 if (!i3c_xfers[i].rnw && i3c_xfers[i].len > 4) { 913 i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len); 914 if (cmd->len > NTDTBP0_DEPTH * sizeof(u32)) 915 renesas_set_bit(i3c->regs, NTIE, NTIE_TDBEIE0); 916 } 917 918 time_left = renesas_i3c_wait_xfer(i3c, xfer); 919 if (!time_left) 920 xfer_failed = true; 921 } 922 923 if (xfer_failed) 924 renesas_i3c_irqs_mask_and_clear(i3c); 925 926 return 0; 927 } 928 929 static int renesas_i3c_attach_i3c_dev(struct i3c_dev_desc *dev) 930 { 931 struct i3c_master_controller *m = i3c_dev_get_master(dev); 932 struct renesas_i3c *i3c = to_renesas_i3c(m); 933 struct renesas_i3c_i2c_dev_data *data; 934 int pos, ret; 935 936 pos = renesas_i3c_get_free_pos(i3c); 937 if (pos < 0) 938 return pos; 939 940 PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(i3c->dev, pm); 941 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 942 if (ret) 943 return ret; 944 945 data = kzalloc_obj(*data); 946 if (!data) 947 return -ENOMEM; 948 949 data->index = pos; 950 i3c->addrs[pos] = dev->info.dyn_addr ? : dev->info.static_addr; 951 i3c->free_pos &= ~BIT(pos); 952 953 renesas_writel(i3c->regs, DATBAS(pos), DATBAS_DVSTAD(dev->info.static_addr) | 954 datbas_dvdyad_with_parity(i3c->addrs[pos])); 955 i3c_dev_set_master_data(dev, data); 956 957 return 0; 958 } 959 960 static int renesas_i3c_reattach_i3c_dev(struct i3c_dev_desc *dev, 961 u8 old_dyn_addr) 962 { 963 struct i3c_master_controller *m = i3c_dev_get_master(dev); 964 struct renesas_i3c *i3c = to_renesas_i3c(m); 965 struct renesas_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 966 int pos, ret; 967 968 PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(i3c->dev, pm); 969 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 970 if (ret) 971 return ret; 972 973 pos = renesas_i3c_get_free_pos(i3c); 974 975 if (data->index > pos && pos >= 0) { 976 renesas_writel(i3c->regs, DATBAS(data->index), 0); 977 i3c->addrs[data->index] = 0; 978 i3c->free_pos |= BIT(data->index); 979 980 data->index = pos; 981 i3c->free_pos &= ~BIT(data->index); 982 } 983 984 i3c->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr : 985 dev->info.static_addr; 986 987 renesas_writel(i3c->regs, DATBAS(data->index), 988 DATBAS_DVSTAD(dev->info.static_addr) | 989 datbas_dvdyad_with_parity(i3c->addrs[data->index])); 990 991 return 0; 992 } 993 994 static void renesas_i3c_detach_i3c_dev(struct i3c_dev_desc *dev) 995 { 996 struct renesas_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 997 struct i3c_master_controller *m = i3c_dev_get_master(dev); 998 struct renesas_i3c *i3c = to_renesas_i3c(m); 999 int ret; 1000 1001 PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(i3c->dev, pm); 1002 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 1003 if (!ret) 1004 renesas_writel(i3c->regs, DATBAS(data->index), 0); 1005 1006 i3c_dev_set_master_data(dev, NULL); 1007 i3c->addrs[data->index] = 0; 1008 i3c->free_pos |= BIT(data->index); 1009 kfree(data); 1010 } 1011 1012 static int renesas_i3c_i2c_xfers(struct i2c_dev_desc *dev, 1013 struct i2c_msg *i2c_xfers, 1014 int i2c_nxfers) 1015 { 1016 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1017 struct renesas_i3c *i3c = to_renesas_i3c(m); 1018 struct renesas_i3c_cmd *cmd; 1019 u8 start_bit = CNDCTL_STCND; 1020 unsigned long time_left; 1021 bool xfer_failed = false; 1022 int i, ret; 1023 1024 if (!i2c_nxfers) 1025 return 0; 1026 1027 struct renesas_i3c_xfer *xfer __free(kfree) = renesas_i3c_alloc_xfer(i3c, 1); 1028 if (!xfer) 1029 return -ENOMEM; 1030 1031 init_completion(&xfer->comp); 1032 xfer->is_i2c_xfer = true; 1033 cmd = xfer->cmds; 1034 1035 PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(i3c->dev, pm); 1036 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 1037 if (ret) 1038 return ret; 1039 1040 renesas_i3c_bus_enable(m, false); 1041 1042 if (!(renesas_readl(i3c->regs, BCST) & BCST_BFREF)) { 1043 cmd->err = -EBUSY; 1044 return cmd->err; 1045 } 1046 1047 renesas_writel(i3c->regs, BST, 0); 1048 1049 renesas_i3c_enqueue_xfer(i3c, xfer); 1050 1051 for (i = 0; i < i2c_nxfers; i++) { 1052 cmd->i2c_bytes_left = I2C_INIT_MSG; 1053 cmd->i2c_buf = i2c_xfers[i].buf; 1054 cmd->msg = &i2c_xfers[i]; 1055 cmd->i2c_is_last = (i == i2c_nxfers - 1); 1056 1057 renesas_set_bit(i3c->regs, BIE, BIE_NACKDIE); 1058 renesas_set_bit(i3c->regs, NTIE, NTIE_TDBEIE0); 1059 renesas_set_bit(i3c->regs, BIE, BIE_STCNDDIE); 1060 1061 /* Issue Start condition */ 1062 renesas_set_bit(i3c->regs, CNDCTL, start_bit); 1063 1064 renesas_set_bit(i3c->regs, NTSTE, NTSTE_TDBEE0); 1065 1066 time_left = wait_for_completion_timeout(&xfer->comp, m->i2c.timeout); 1067 if (!time_left) 1068 xfer_failed = true; 1069 1070 if (cmd->err) 1071 break; 1072 1073 start_bit = CNDCTL_SRCND; 1074 } 1075 1076 renesas_i3c_dequeue_xfer(i3c, xfer); 1077 1078 if (xfer_failed) 1079 renesas_i3c_irqs_mask_and_clear(i3c); 1080 1081 return cmd->err; 1082 } 1083 1084 static int renesas_i3c_attach_i2c_dev(struct i2c_dev_desc *dev) 1085 { 1086 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1087 struct renesas_i3c *i3c = to_renesas_i3c(m); 1088 struct renesas_i3c_i2c_dev_data *data; 1089 int pos; 1090 1091 pos = renesas_i3c_get_free_pos(i3c); 1092 if (pos < 0) 1093 return pos; 1094 1095 data = kzalloc_obj(*data); 1096 if (!data) 1097 return -ENOMEM; 1098 1099 data->index = pos; 1100 i3c->addrs[pos] = dev->addr; 1101 i3c->free_pos &= ~BIT(pos); 1102 i2c_dev_set_master_data(dev, data); 1103 1104 return 0; 1105 } 1106 1107 static void renesas_i3c_detach_i2c_dev(struct i2c_dev_desc *dev) 1108 { 1109 struct renesas_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 1110 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1111 struct renesas_i3c *i3c = to_renesas_i3c(m); 1112 1113 i2c_dev_set_master_data(dev, NULL); 1114 i3c->addrs[data->index] = 0; 1115 i3c->free_pos |= BIT(data->index); 1116 kfree(data); 1117 } 1118 1119 static irqreturn_t renesas_i3c_tx_isr(int irq, void *data) 1120 { 1121 struct renesas_i3c *i3c = data; 1122 struct renesas_i3c_xfer *xfer; 1123 struct renesas_i3c_cmd *cmd; 1124 u8 val; 1125 1126 scoped_guard(spinlock, &i3c->xferqueue.lock) { 1127 xfer = i3c->xferqueue.cur; 1128 if (!xfer) { 1129 renesas_i3c_irqs_mask_and_clear_locked(i3c); 1130 return IRQ_HANDLED; 1131 } 1132 1133 cmd = xfer->cmds; 1134 1135 if (xfer->is_i2c_xfer) { 1136 if (!cmd->i2c_bytes_left) 1137 return IRQ_NONE; 1138 1139 if (cmd->i2c_bytes_left != I2C_INIT_MSG) { 1140 val = *cmd->i2c_buf; 1141 cmd->i2c_buf++; 1142 cmd->i2c_bytes_left--; 1143 renesas_writel(i3c->regs, NTDTBP0, val); 1144 } 1145 1146 if (cmd->i2c_bytes_left == 0) { 1147 renesas_clear_bit(i3c->regs, NTIE, NTIE_TDBEIE0); 1148 renesas_set_bit(i3c->regs, BIE, BIE_TENDIE); 1149 } 1150 1151 /* Clear the Transmit Buffer Empty status flag. */ 1152 renesas_clear_bit(i3c->regs, NTST, NTST_TDBEF0); 1153 } else { 1154 i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len); 1155 } 1156 } 1157 1158 return IRQ_HANDLED; 1159 } 1160 1161 static irqreturn_t renesas_i3c_resp_isr(int irq, void *data) 1162 { 1163 struct renesas_i3c *i3c = data; 1164 struct renesas_i3c_xfer *xfer; 1165 struct renesas_i3c_cmd *cmd; 1166 u32 resp_descriptor = renesas_readl(i3c->regs, NRSPQP); 1167 u32 bytes_remaining = 0; 1168 u32 ntst, data_len; 1169 int ret = 0; 1170 1171 scoped_guard(spinlock, &i3c->xferqueue.lock) { 1172 xfer = i3c->xferqueue.cur; 1173 if (!xfer) { 1174 renesas_i3c_irqs_mask_and_clear_locked(i3c); 1175 return IRQ_HANDLED; 1176 } 1177 1178 cmd = xfer->cmds; 1179 1180 /* Clear the Respone Queue Full status flag*/ 1181 renesas_clear_bit(i3c->regs, NTST, NTST_RSPQFF); 1182 1183 data_len = NRSPQP_DATA_LEN(resp_descriptor); 1184 1185 switch (i3c->internal_state) { 1186 case I3C_INTERNAL_STATE_CONTROLLER_ENTDAA: 1187 cmd->rx_count = data_len; 1188 break; 1189 case I3C_INTERNAL_STATE_CONTROLLER_WRITE: 1190 case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE: 1191 /* Disable the transmit IRQ if it hasn't been disabled already. */ 1192 renesas_clear_bit(i3c->regs, NTIE, NTIE_TDBEIE0); 1193 break; 1194 case I3C_INTERNAL_STATE_CONTROLLER_READ: 1195 case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ: 1196 if (!cmd->err) { 1197 u32 rx_count = min(cmd->rx_count, data_len); 1198 1199 bytes_remaining = data_len - rx_count; 1200 if (bytes_remaining) 1201 i3c_readl_fifo(i3c->regs + NTDTBP0, 1202 cmd->rx_buf + rx_count, 1203 bytes_remaining); 1204 cmd->rx_count = data_len; 1205 } 1206 renesas_clear_bit(i3c->regs, NTIE, NTIE_RDBFIE0); 1207 break; 1208 default: 1209 break; 1210 } 1211 1212 switch (NRSPQP_ERR_STATUS(resp_descriptor)) { 1213 case NRSPQP_NO_ERROR: 1214 break; 1215 case NRSPQP_ERROR_PARITY: 1216 case NRSPQP_ERROR_IBA_NACK: 1217 case NRSPQP_ERROR_TRANSF_ABORT: 1218 case NRSPQP_ERROR_CRC: 1219 case NRSPQP_ERROR_FRAME: 1220 ret = -EIO; 1221 break; 1222 case NRSPQP_ERROR_OVER_UNDER_FLOW: 1223 ret = -ENOSPC; 1224 break; 1225 case NRSPQP_ERROR_UNSUPPORTED: 1226 ret = -EOPNOTSUPP; 1227 break; 1228 case NRSPQP_ERROR_I2C_W_NACK_ERR: 1229 case NRSPQP_ERROR_ADDRESS_NACK: 1230 default: 1231 ret = -EINVAL; 1232 break; 1233 } 1234 1235 /* 1236 * If the transfer was aborted, then the abort flag must be cleared 1237 * before notifying the application that a transfer has completed. 1238 */ 1239 ntst = renesas_readl(i3c->regs, NTST); 1240 if (ntst & NTST_TABTF) 1241 renesas_clear_bit(i3c->regs, BCTL, BCTL_ABT); 1242 1243 /* Clear error status flags. */ 1244 renesas_clear_bit(i3c->regs, NTST, NTST_TEF | NTST_TABTF); 1245 1246 xfer->ret = ret; 1247 complete(&xfer->comp); 1248 1249 xfer = list_first_entry_or_null(&i3c->xferqueue.list, 1250 struct renesas_i3c_xfer, node); 1251 if (xfer) 1252 list_del_init(&xfer->node); 1253 1254 i3c->xferqueue.cur = xfer; 1255 } 1256 1257 return IRQ_HANDLED; 1258 } 1259 1260 static irqreturn_t renesas_i3c_tend_isr(int irq, void *data) 1261 { 1262 struct renesas_i3c *i3c = data; 1263 struct renesas_i3c_xfer *xfer; 1264 struct renesas_i3c_cmd *cmd; 1265 1266 scoped_guard(spinlock, &i3c->xferqueue.lock) { 1267 xfer = i3c->xferqueue.cur; 1268 if (!xfer) { 1269 renesas_i3c_irqs_mask_and_clear_locked(i3c); 1270 return IRQ_HANDLED; 1271 } 1272 1273 cmd = xfer->cmds; 1274 1275 if (xfer->is_i2c_xfer) { 1276 if (renesas_readl(i3c->regs, BST) & BST_NACKDF) { 1277 /* We got a NACKIE */ 1278 renesas_readl(i3c->regs, NTDTBP0); /* dummy read */ 1279 renesas_clear_bit(i3c->regs, BST, BST_NACKDF); 1280 cmd->err = -ENXIO; 1281 } else if (cmd->i2c_bytes_left) { 1282 renesas_set_bit(i3c->regs, NTIE, NTIE_TDBEIE0); 1283 return IRQ_NONE; 1284 } 1285 1286 if (cmd->i2c_is_last || cmd->err) { 1287 renesas_clear_bit(i3c->regs, BIE, BIE_TENDIE); 1288 renesas_set_bit(i3c->regs, BIE, BIE_SPCNDDIE); 1289 renesas_set_bit(i3c->regs, CNDCTL, CNDCTL_SPCND); 1290 } else { 1291 /* Transfer is complete, but do not send STOP */ 1292 renesas_clear_bit(i3c->regs, NTSTE, NTSTE_TDBEE0); 1293 renesas_clear_bit(i3c->regs, BIE, BIE_TENDIE); 1294 xfer->ret = 0; 1295 complete(&xfer->comp); 1296 } 1297 } 1298 1299 /* Clear the Transmit Buffer Empty status flag. */ 1300 renesas_clear_bit(i3c->regs, BST, BST_TENDF); 1301 } 1302 1303 return IRQ_HANDLED; 1304 } 1305 1306 static irqreturn_t renesas_i3c_rx_isr(int irq, void *data) 1307 { 1308 struct renesas_i3c *i3c = data; 1309 struct renesas_i3c_xfer *xfer; 1310 struct renesas_i3c_cmd *cmd; 1311 int read_bytes; 1312 1313 /* If resp_isr already read the data and updated 'xfer', we can just leave */ 1314 if (!(renesas_readl(i3c->regs, NTIE) & NTIE_RDBFIE0)) 1315 return IRQ_NONE; 1316 1317 scoped_guard(spinlock, &i3c->xferqueue.lock) { 1318 xfer = i3c->xferqueue.cur; 1319 if (!xfer) { 1320 renesas_i3c_irqs_mask_and_clear_locked(i3c); 1321 return IRQ_HANDLED; 1322 } 1323 1324 cmd = xfer->cmds; 1325 1326 if (xfer->is_i2c_xfer) { 1327 if (!cmd->i2c_bytes_left) 1328 return IRQ_NONE; 1329 1330 if (cmd->i2c_bytes_left == I2C_INIT_MSG) { 1331 cmd->i2c_bytes_left = cmd->msg->len; 1332 renesas_set_bit(i3c->regs, SCSTRCTL, SCSTRCTL_RWE); 1333 renesas_readl(i3c->regs, NTDTBP0); /* dummy read */ 1334 if (cmd->i2c_bytes_left == 1) 1335 renesas_writel(i3c->regs, ACKCTL, ACKCTL_ACKT | ACKCTL_ACKTWP); 1336 return IRQ_HANDLED; 1337 } 1338 1339 if (cmd->i2c_bytes_left == 1) { 1340 /* STOP must come before we set ACKCTL! */ 1341 if (cmd->i2c_is_last) { 1342 renesas_set_bit(i3c->regs, BIE, BIE_SPCNDDIE); 1343 renesas_clear_bit(i3c->regs, BST, BST_SPCNDDF); 1344 renesas_set_bit(i3c->regs, CNDCTL, CNDCTL_SPCND); 1345 } 1346 renesas_writel(i3c->regs, ACKCTL, ACKCTL_ACKT | ACKCTL_ACKTWP); 1347 } else { 1348 renesas_writel(i3c->regs, ACKCTL, ACKCTL_ACKTWP); 1349 } 1350 1351 /* Reading acks the RIE interrupt */ 1352 *cmd->i2c_buf = renesas_readl(i3c->regs, NTDTBP0); 1353 cmd->i2c_buf++; 1354 cmd->i2c_bytes_left--; 1355 } else { 1356 read_bytes = NDBSTLV0_RDBLV(renesas_readl(i3c->regs, NDBSTLV0)) * sizeof(u32); 1357 i3c_readl_fifo(i3c->regs + NTDTBP0, cmd->rx_buf, read_bytes); 1358 cmd->rx_count = read_bytes; 1359 } 1360 1361 /* Clear the Read Buffer Full status flag. */ 1362 renesas_clear_bit(i3c->regs, NTST, NTST_RDBFF0); 1363 } 1364 1365 return IRQ_HANDLED; 1366 } 1367 1368 static irqreturn_t renesas_i3c_stop_isr(int irq, void *data) 1369 { 1370 struct renesas_i3c *i3c = data; 1371 struct renesas_i3c_xfer *xfer; 1372 1373 scoped_guard(spinlock, &i3c->xferqueue.lock) { 1374 renesas_i3c_irqs_mask_and_clear_locked(i3c); 1375 renesas_clear_bit(i3c->regs, SCSTRCTL, SCSTRCTL_RWE); 1376 1377 xfer = i3c->xferqueue.cur; 1378 if (!xfer) 1379 return IRQ_HANDLED; 1380 1381 xfer->ret = 0; 1382 complete(&xfer->comp); 1383 } 1384 1385 return IRQ_HANDLED; 1386 } 1387 1388 static irqreturn_t renesas_i3c_start_isr(int irq, void *data) 1389 { 1390 struct renesas_i3c *i3c = data; 1391 struct renesas_i3c_xfer *xfer; 1392 struct renesas_i3c_cmd *cmd; 1393 u8 val; 1394 1395 scoped_guard(spinlock, &i3c->xferqueue.lock) { 1396 xfer = i3c->xferqueue.cur; 1397 if (!xfer) { 1398 renesas_i3c_irqs_mask_and_clear_locked(i3c); 1399 return IRQ_HANDLED; 1400 } 1401 1402 cmd = xfer->cmds; 1403 1404 if (xfer->is_i2c_xfer) { 1405 if (!cmd->i2c_bytes_left) 1406 return IRQ_NONE; 1407 1408 if (cmd->i2c_bytes_left == I2C_INIT_MSG) { 1409 if (cmd->msg->flags & I2C_M_RD) { 1410 /* On read, switch over to receive interrupt */ 1411 renesas_clear_bit(i3c->regs, NTIE, NTIE_TDBEIE0); 1412 renesas_set_bit(i3c->regs, NTIE, NTIE_RDBFIE0); 1413 } else { 1414 /* On write, initialize length */ 1415 cmd->i2c_bytes_left = cmd->msg->len; 1416 } 1417 1418 val = i2c_8bit_addr_from_msg(cmd->msg); 1419 renesas_writel(i3c->regs, NTDTBP0, val); 1420 } 1421 } 1422 1423 renesas_clear_bit(i3c->regs, BIE, BIE_STCNDDIE); 1424 renesas_clear_bit(i3c->regs, BST, BST_STCNDDF); 1425 } 1426 1427 return IRQ_HANDLED; 1428 } 1429 1430 static const struct i3c_master_controller_ops renesas_i3c_ops = { 1431 .bus_init = renesas_i3c_bus_init, 1432 .bus_cleanup = renesas_i3c_bus_cleanup, 1433 .attach_i3c_dev = renesas_i3c_attach_i3c_dev, 1434 .reattach_i3c_dev = renesas_i3c_reattach_i3c_dev, 1435 .detach_i3c_dev = renesas_i3c_detach_i3c_dev, 1436 .do_daa = renesas_i3c_daa, 1437 .supports_ccc_cmd = renesas_i3c_supports_ccc_cmd, 1438 .send_ccc_cmd = renesas_i3c_send_ccc_cmd, 1439 .i3c_xfers = renesas_i3c_i3c_xfers, 1440 .attach_i2c_dev = renesas_i3c_attach_i2c_dev, 1441 .detach_i2c_dev = renesas_i3c_detach_i2c_dev, 1442 .i2c_xfers = renesas_i3c_i2c_xfers, 1443 }; 1444 1445 static const struct renesas_i3c_irq_desc renesas_i3c_irqs[] = { 1446 { .name = "resp", .isr = renesas_i3c_resp_isr, .desc = "i3c-resp" }, 1447 { .name = "rx", .isr = renesas_i3c_rx_isr, .desc = "i3c-rx" }, 1448 { .name = "tx", .isr = renesas_i3c_tx_isr, .desc = "i3c-tx" }, 1449 { .name = "st", .isr = renesas_i3c_start_isr, .desc = "i3c-start" }, 1450 { .name = "sp", .isr = renesas_i3c_stop_isr, .desc = "i3c-stop" }, 1451 { .name = "tend", .isr = renesas_i3c_tend_isr, .desc = "i3c-tend" }, 1452 { .name = "nack", .isr = renesas_i3c_tend_isr, .desc = "i3c-nack" }, 1453 }; 1454 1455 static int renesas_i3c_probe(struct platform_device *pdev) 1456 { 1457 struct renesas_i3c *i3c; 1458 int ret, i; 1459 1460 i3c = devm_kzalloc(&pdev->dev, sizeof(*i3c), GFP_KERNEL); 1461 if (!i3c) 1462 return -ENOMEM; 1463 1464 i3c->regs = devm_platform_ioremap_resource(pdev, 0); 1465 if (IS_ERR(i3c->regs)) 1466 return PTR_ERR(i3c->regs); 1467 1468 i3c->tclk = devm_clk_get(&pdev->dev, "tclk"); 1469 if (IS_ERR(i3c->tclk)) 1470 return dev_err_probe(&pdev->dev, PTR_ERR(i3c->tclk), "Failed to get tclk"); 1471 1472 i3c->dev = &pdev->dev; 1473 pm_runtime_set_autosuspend_delay(&pdev->dev, 300); 1474 pm_runtime_use_autosuspend(&pdev->dev); 1475 ret = devm_pm_runtime_enable(&pdev->dev); 1476 if (ret) 1477 return ret; 1478 1479 i3c->tresetn = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, "tresetn"); 1480 if (IS_ERR(i3c->tresetn)) 1481 return dev_err_probe(&pdev->dev, PTR_ERR(i3c->tresetn), 1482 "Error: missing tresetn ctrl\n"); 1483 1484 i3c->presetn = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, "presetn"); 1485 if (IS_ERR(i3c->presetn)) 1486 return dev_err_probe(&pdev->dev, PTR_ERR(i3c->presetn), 1487 "Error: missing presetn ctrl\n"); 1488 1489 spin_lock_init(&i3c->xferqueue.lock); 1490 INIT_LIST_HEAD(&i3c->xferqueue.list); 1491 1492 ret = renesas_i3c_reset(i3c); 1493 if (ret) 1494 return ret; 1495 1496 for (i = 0; i < ARRAY_SIZE(renesas_i3c_irqs); i++) { 1497 const char *irqname; 1498 1499 ret = platform_get_irq_byname(pdev, renesas_i3c_irqs[i].name); 1500 if (ret < 0) 1501 return ret; 1502 1503 irqname = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s:%s", dev_name(&pdev->dev), 1504 renesas_i3c_irqs[i].desc); 1505 if (!irqname) 1506 return -ENOMEM; 1507 1508 ret = devm_request_irq(&pdev->dev, ret, renesas_i3c_irqs[i].isr, 1509 0, irqname, i3c); 1510 if (ret) 1511 return ret; 1512 } 1513 1514 platform_set_drvdata(pdev, i3c); 1515 1516 i3c->maxdevs = RENESAS_I3C_MAX_DEVS; 1517 i3c->free_pos = GENMASK(i3c->maxdevs - 1, 0); 1518 1519 return i3c_master_register(&i3c->base, &pdev->dev, &renesas_i3c_ops, false); 1520 } 1521 1522 static void renesas_i3c_remove(struct platform_device *pdev) 1523 { 1524 struct renesas_i3c *i3c = platform_get_drvdata(pdev); 1525 1526 i3c_master_unregister(&i3c->base); 1527 } 1528 1529 static int renesas_i3c_suspend(struct device *dev) 1530 { 1531 struct renesas_i3c *i3c = dev_get_drvdata(dev); 1532 struct reset_control_bulk_data resets[] = { 1533 { .rstc = i3c->presetn }, 1534 { .rstc = i3c->tresetn }, 1535 }; 1536 int ret; 1537 1538 i2c_mark_adapter_suspended(&i3c->base.i2c); 1539 1540 ret = reset_control_bulk_assert(ARRAY_SIZE(resets), resets); 1541 if (ret) 1542 goto err_mark_resumed; 1543 1544 return 0; 1545 1546 err_mark_resumed: 1547 i2c_mark_adapter_resumed(&i3c->base.i2c); 1548 1549 return ret; 1550 } 1551 1552 static int renesas_i3c_resume(struct device *dev) 1553 { 1554 struct renesas_i3c *i3c = dev_get_drvdata(dev); 1555 struct reset_control_bulk_data resets[] = { 1556 { .rstc = i3c->presetn }, 1557 { .rstc = i3c->tresetn }, 1558 }; 1559 int ret; 1560 1561 ret = reset_control_bulk_deassert(ARRAY_SIZE(resets), resets); 1562 if (ret) 1563 return ret; 1564 1565 ret = renesas_i3c_reset(i3c); 1566 if (ret) 1567 goto err_resets_asserted; 1568 1569 ret = pm_runtime_resume_and_get(dev); 1570 if (ret) 1571 goto err_resets_asserted; 1572 1573 /* Re-store I3C registers value. */ 1574 renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR); 1575 renesas_writel(i3c->regs, EXTBR, i3c->extbr); 1576 renesas_writel(i3c->regs, REFCKCTL, 1577 REFCKCTL_IREFCKS(i3c->refclk_div)); 1578 renesas_writel(i3c->regs, MSDVAD, MSDVAD_MDYADV | 1579 MSDVAD_MDYAD(i3c->dyn_addr)); 1580 1581 /* I3C hw init. */ 1582 renesas_i3c_hw_init(i3c); 1583 1584 ret = i3c_master_do_daa_ext(&i3c->base, true); 1585 if (ret) 1586 dev_err(dev, "DAA failed on resume, ret=%d", ret); 1587 1588 i2c_mark_adapter_resumed(&i3c->base.i2c); 1589 1590 pm_runtime_put_autosuspend(dev); 1591 1592 /* 1593 * I3C devices may have retained their dynamic address anyway. Do not 1594 * fail the resume because of DAA error. 1595 */ 1596 return 0; 1597 1598 err_resets_asserted: 1599 /* 1600 * If this happens, there is no way to recover from this state without 1601 * reloading the driver. We want to avoid keeping the reset line 1602 * deasserted unnecessarily. The runtime paths will still work correctly 1603 * even if the IP registers are accessed while reset is asserted (e.g. 1604 * if a runtime path is triggered after a failed resume). Checked on 1605 * RZ/G3S. 1606 */ 1607 reset_control_bulk_assert(ARRAY_SIZE(resets), resets); 1608 return ret; 1609 } 1610 1611 static const struct dev_pm_ops renesas_i3c_pm_ops = { 1612 SYSTEM_SLEEP_PM_OPS(renesas_i3c_suspend, renesas_i3c_resume) 1613 }; 1614 1615 static const struct of_device_id renesas_i3c_of_ids[] = { 1616 { .compatible = "renesas,r9a08g045-i3c" }, 1617 { .compatible = "renesas,r9a09g047-i3c" }, 1618 { /* sentinel */ }, 1619 }; 1620 MODULE_DEVICE_TABLE(of, renesas_i3c_of_ids); 1621 1622 static struct platform_driver renesas_i3c = { 1623 .probe = renesas_i3c_probe, 1624 .remove = renesas_i3c_remove, 1625 .driver = { 1626 .name = "renesas-i3c", 1627 .of_match_table = renesas_i3c_of_ids, 1628 .pm = pm_sleep_ptr(&renesas_i3c_pm_ops), 1629 }, 1630 }; 1631 module_platform_driver(renesas_i3c); 1632 1633 MODULE_AUTHOR("Wolfram Sang <wsa+renesas@sang-engineering.com>"); 1634 MODULE_AUTHOR("Renesas BSP teams"); 1635 MODULE_DESCRIPTION("Renesas I3C controller driver"); 1636 MODULE_LICENSE("GPL"); 1637