1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2020, MIPI Alliance, Inc. 4 * 5 * Author: Nicolas Pitre <npitre@baylibre.com> 6 * 7 * Common HCI stuff 8 */ 9 10 #ifndef HCI_H 11 #define HCI_H 12 13 #include <linux/io.h> 14 15 /* 32-bit word aware bit and mask macros */ 16 #define W0_MASK(h, l) GENMASK((h) - 0, (l) - 0) 17 #define W1_MASK(h, l) GENMASK((h) - 32, (l) - 32) 18 #define W2_MASK(h, l) GENMASK((h) - 64, (l) - 64) 19 #define W3_MASK(h, l) GENMASK((h) - 96, (l) - 96) 20 21 /* Same for single bit macros (trailing _ to align with W*_MASK width) */ 22 #define W0_BIT_(x) BIT((x) - 0) 23 #define W1_BIT_(x) BIT((x) - 32) 24 #define W2_BIT_(x) BIT((x) - 64) 25 #define W3_BIT_(x) BIT((x) - 96) 26 27 #define reg_read(r) readl(hci->base_regs + (r)) 28 #define reg_write(r, v) writel(v, hci->base_regs + (r)) 29 #define reg_set(r, v) reg_write(r, reg_read(r) | (v)) 30 #define reg_clear(r, v) reg_write(r, reg_read(r) & ~(v)) 31 32 struct hci_cmd_ops; 33 34 /* Our main structure */ 35 struct i3c_hci { 36 struct i3c_master_controller master; 37 void __iomem *base_regs; 38 void __iomem *DAT_regs; 39 void __iomem *DCT_regs; 40 void __iomem *RHS_regs; 41 void __iomem *PIO_regs; 42 void __iomem *EXTCAPS_regs; 43 void __iomem *AUTOCMD_regs; 44 void __iomem *DEBUG_regs; 45 const struct hci_io_ops *io; 46 void *io_data; 47 const struct hci_cmd_ops *cmd; 48 atomic_t next_cmd_tid; 49 u32 caps; 50 unsigned int quirks; 51 unsigned int DAT_entries; 52 unsigned int DAT_entry_size; 53 void *DAT_data; 54 unsigned int DCT_entries; 55 unsigned int DCT_entry_size; 56 u8 version_major; 57 u8 version_minor; 58 u8 revision; 59 u32 vendor_mipi_id; 60 u32 vendor_version_id; 61 u32 vendor_product_id; 62 void *vendor_data; 63 }; 64 65 66 /* 67 * Structure to represent a master initiated transfer. 68 * The rnw, data and data_len fields must be initialized before calling any 69 * hci->cmd->*() method. The cmd method will initialize cmd_desc[] and 70 * possibly modify (clear) the data field. Then xfer->cmd_desc[0] can 71 * be augmented with CMD_0_ROC and/or CMD_0_TOC. 72 * The completion field needs to be initialized before queueing with 73 * hci->io->queue_xfer(), and requires CMD_0_ROC to be set. 74 */ 75 struct hci_xfer { 76 u32 cmd_desc[4]; 77 u32 response; 78 bool rnw; 79 void *data; 80 unsigned int data_len; 81 unsigned int cmd_tid; 82 struct completion *completion; 83 union { 84 struct { 85 /* PIO specific */ 86 struct hci_xfer *next_xfer; 87 struct hci_xfer *next_data; 88 struct hci_xfer *next_resp; 89 unsigned int data_left; 90 u32 data_word_before_partial; 91 }; 92 struct { 93 /* DMA specific */ 94 struct i3c_dma *dma; 95 int ring_number; 96 int ring_entry; 97 }; 98 }; 99 }; 100 101 static inline struct hci_xfer *hci_alloc_xfer(unsigned int n) 102 { 103 return kcalloc(n, sizeof(struct hci_xfer), GFP_KERNEL); 104 } 105 106 static inline void hci_free_xfer(struct hci_xfer *xfer, unsigned int n) 107 { 108 kfree(xfer); 109 } 110 111 112 /* This abstracts PIO vs DMA operations */ 113 struct hci_io_ops { 114 bool (*irq_handler)(struct i3c_hci *hci); 115 int (*queue_xfer)(struct i3c_hci *hci, struct hci_xfer *xfer, int n); 116 bool (*dequeue_xfer)(struct i3c_hci *hci, struct hci_xfer *xfer, int n); 117 int (*request_ibi)(struct i3c_hci *hci, struct i3c_dev_desc *dev, 118 const struct i3c_ibi_setup *req); 119 void (*free_ibi)(struct i3c_hci *hci, struct i3c_dev_desc *dev); 120 void (*recycle_ibi_slot)(struct i3c_hci *hci, struct i3c_dev_desc *dev, 121 struct i3c_ibi_slot *slot); 122 int (*init)(struct i3c_hci *hci); 123 void (*cleanup)(struct i3c_hci *hci); 124 }; 125 126 extern const struct hci_io_ops mipi_i3c_hci_pio; 127 extern const struct hci_io_ops mipi_i3c_hci_dma; 128 129 130 /* Our per device master private data */ 131 struct i3c_hci_dev_data { 132 int dat_idx; 133 void *ibi_data; 134 }; 135 136 137 /* list of quirks */ 138 #define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */ 139 #define HCI_QUIRK_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */ 140 #define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD platforms */ 141 #define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD platforms */ 142 143 144 /* global functions */ 145 void mipi_i3c_hci_resume(struct i3c_hci *hci); 146 void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); 147 void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); 148 void amd_set_od_pp_timing(struct i3c_hci *hci); 149 void amd_set_resp_buf_thld(struct i3c_hci *hci); 150 151 #endif 152