1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2020, MIPI Alliance, Inc. 4 * 5 * Author: Nicolas Pitre <npitre@baylibre.com> 6 * 7 * I3C HCI v2.0 Command Descriptor Handling 8 * 9 * Note: The I3C HCI v2.0 spec is still in flux. The code here will change. 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/i3c/master.h> 14 15 #include "hci.h" 16 #include "cmd.h" 17 #include "xfer_mode_rate.h" 18 19 /* 20 * Unified Data Transfer Command 21 */ 22 23 #define CMD_0_ATTR_U FIELD_PREP(CMD_0_ATTR, 0x4) 24 25 #define CMD_U3_HDR_TSP_ML_CTRL(v) FIELD_PREP(W3_MASK(107, 104), v) 26 #define CMD_U3_IDB4(v) FIELD_PREP(W3_MASK(103, 96), v) 27 #define CMD_U3_HDR_CMD(v) FIELD_PREP(W3_MASK(103, 96), v) 28 #define CMD_U2_IDB3(v) FIELD_PREP(W2_MASK( 95, 88), v) 29 #define CMD_U2_HDR_BT(v) FIELD_PREP(W2_MASK( 95, 88), v) 30 #define CMD_U2_IDB2(v) FIELD_PREP(W2_MASK( 87, 80), v) 31 #define CMD_U2_BT_CMD2(v) FIELD_PREP(W2_MASK( 87, 80), v) 32 #define CMD_U2_IDB1(v) FIELD_PREP(W2_MASK( 79, 72), v) 33 #define CMD_U2_BT_CMD1(v) FIELD_PREP(W2_MASK( 79, 72), v) 34 #define CMD_U2_IDB0(v) FIELD_PREP(W2_MASK( 71, 64), v) 35 #define CMD_U2_BT_CMD0(v) FIELD_PREP(W2_MASK( 71, 64), v) 36 #define CMD_U1_ERR_HANDLING(v) FIELD_PREP(W1_MASK( 63, 62), v) 37 #define CMD_U1_ADD_FUNC(v) FIELD_PREP(W1_MASK( 61, 56), v) 38 #define CMD_U1_COMBO_XFER W1_BIT_( 55) 39 #define CMD_U1_DATA_LENGTH(v) FIELD_PREP(W1_MASK( 53, 32), v) 40 #define CMD_U0_TOC W0_BIT_( 31) 41 #define CMD_U0_ROC W0_BIT_( 30) 42 #define CMD_U0_MAY_YIELD W0_BIT_( 29) 43 #define CMD_U0_NACK_RCNT(v) FIELD_PREP(W0_MASK( 28, 27), v) 44 #define CMD_U0_IDB_COUNT(v) FIELD_PREP(W0_MASK( 26, 24), v) 45 #define CMD_U0_MODE_INDEX(v) FIELD_PREP(W0_MASK( 22, 18), v) 46 #define CMD_U0_XFER_RATE(v) FIELD_PREP(W0_MASK( 17, 15), v) 47 #define CMD_U0_DEV_ADDRESS(v) FIELD_PREP(W0_MASK( 14, 8), v) 48 #define CMD_U0_RnW W0_BIT_( 7) 49 #define CMD_U0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v) 50 51 /* 52 * Address Assignment Command 53 */ 54 55 #define CMD_0_ATTR_A FIELD_PREP(CMD_0_ATTR, 0x2) 56 57 #define CMD_A1_DATA_LENGTH(v) FIELD_PREP(W1_MASK( 53, 32), v) 58 #define CMD_A0_TOC W0_BIT_( 31) 59 #define CMD_A0_ROC W0_BIT_( 30) 60 #define CMD_A0_XFER_RATE(v) FIELD_PREP(W0_MASK( 17, 15), v) 61 #define CMD_A0_ASSIGN_ADDRESS(v) FIELD_PREP(W0_MASK( 14, 8), v) 62 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v) 63 64 static unsigned int get_i3c_rate_idx(struct i3c_hci *hci) 65 { 66 struct i3c_bus *bus = i3c_master_get_bus(&hci->master); 67 68 if (bus->scl_rate.i3c >= 12000000) 69 return XFERRATE_I3C_SDR0; 70 if (bus->scl_rate.i3c > 8000000) 71 return XFERRATE_I3C_SDR1; 72 if (bus->scl_rate.i3c > 6000000) 73 return XFERRATE_I3C_SDR2; 74 if (bus->scl_rate.i3c > 4000000) 75 return XFERRATE_I3C_SDR3; 76 if (bus->scl_rate.i3c > 2000000) 77 return XFERRATE_I3C_SDR4; 78 return XFERRATE_I3C_SDR_FM_FMP; 79 } 80 81 static unsigned int get_i2c_rate_idx(struct i3c_hci *hci) 82 { 83 struct i3c_bus *bus = i3c_master_get_bus(&hci->master); 84 85 if (bus->scl_rate.i2c >= 1000000) 86 return XFERRATE_I2C_FMP; 87 return XFERRATE_I2C_FM; 88 } 89 90 static void hci_cmd_v2_prep_private_xfer(struct i3c_hci *hci, 91 struct hci_xfer *xfer, 92 u8 addr, unsigned int mode, 93 unsigned int rate) 94 { 95 u8 *data = xfer->data; 96 unsigned int data_len = xfer->data_len; 97 bool rnw = xfer->rnw; 98 99 xfer->cmd_tid = hci_get_tid(); 100 101 if (!rnw && data_len <= 5) { 102 xfer->cmd_desc[0] = 103 CMD_0_ATTR_U | 104 CMD_U0_TID(xfer->cmd_tid) | 105 CMD_U0_DEV_ADDRESS(addr) | 106 CMD_U0_XFER_RATE(rate) | 107 CMD_U0_MODE_INDEX(mode) | 108 CMD_U0_IDB_COUNT(data_len); 109 xfer->cmd_desc[1] = 110 CMD_U1_DATA_LENGTH(0); 111 xfer->cmd_desc[2] = 0; 112 xfer->cmd_desc[3] = 0; 113 switch (data_len) { 114 case 5: 115 xfer->cmd_desc[3] |= CMD_U3_IDB4(data[4]); 116 fallthrough; 117 case 4: 118 xfer->cmd_desc[2] |= CMD_U2_IDB3(data[3]); 119 fallthrough; 120 case 3: 121 xfer->cmd_desc[2] |= CMD_U2_IDB2(data[2]); 122 fallthrough; 123 case 2: 124 xfer->cmd_desc[2] |= CMD_U2_IDB1(data[1]); 125 fallthrough; 126 case 1: 127 xfer->cmd_desc[2] |= CMD_U2_IDB0(data[0]); 128 fallthrough; 129 case 0: 130 break; 131 } 132 /* we consumed all the data with the cmd descriptor */ 133 xfer->data = NULL; 134 } else { 135 xfer->cmd_desc[0] = 136 CMD_0_ATTR_U | 137 CMD_U0_TID(xfer->cmd_tid) | 138 (rnw ? CMD_U0_RnW : 0) | 139 CMD_U0_DEV_ADDRESS(addr) | 140 CMD_U0_XFER_RATE(rate) | 141 CMD_U0_MODE_INDEX(mode); 142 xfer->cmd_desc[1] = 143 CMD_U1_DATA_LENGTH(data_len); 144 xfer->cmd_desc[2] = 0; 145 xfer->cmd_desc[3] = 0; 146 } 147 } 148 149 static int hci_cmd_v2_prep_ccc(struct i3c_hci *hci, struct hci_xfer *xfer, 150 u8 ccc_addr, u8 ccc_cmd, bool raw) 151 { 152 unsigned int mode = XFERMODE_IDX_I3C_SDR; 153 unsigned int rate = get_i3c_rate_idx(hci); 154 u8 *data = xfer->data; 155 unsigned int data_len = xfer->data_len; 156 bool rnw = xfer->rnw; 157 158 if (raw && ccc_addr != I3C_BROADCAST_ADDR) { 159 hci_cmd_v2_prep_private_xfer(hci, xfer, ccc_addr, mode, rate); 160 return 0; 161 } 162 163 xfer->cmd_tid = hci_get_tid(); 164 165 if (!rnw && data_len <= 4) { 166 xfer->cmd_desc[0] = 167 CMD_0_ATTR_U | 168 CMD_U0_TID(xfer->cmd_tid) | 169 CMD_U0_DEV_ADDRESS(ccc_addr) | 170 CMD_U0_XFER_RATE(rate) | 171 CMD_U0_MODE_INDEX(mode) | 172 CMD_U0_IDB_COUNT(data_len + (!raw ? 0 : 1)); 173 xfer->cmd_desc[1] = 174 CMD_U1_DATA_LENGTH(0); 175 xfer->cmd_desc[2] = 176 CMD_U2_IDB0(ccc_cmd); 177 xfer->cmd_desc[3] = 0; 178 switch (data_len) { 179 case 4: 180 xfer->cmd_desc[3] |= CMD_U3_IDB4(data[3]); 181 fallthrough; 182 case 3: 183 xfer->cmd_desc[2] |= CMD_U2_IDB3(data[2]); 184 fallthrough; 185 case 2: 186 xfer->cmd_desc[2] |= CMD_U2_IDB2(data[1]); 187 fallthrough; 188 case 1: 189 xfer->cmd_desc[2] |= CMD_U2_IDB1(data[0]); 190 fallthrough; 191 case 0: 192 break; 193 } 194 /* we consumed all the data with the cmd descriptor */ 195 xfer->data = NULL; 196 } else { 197 xfer->cmd_desc[0] = 198 CMD_0_ATTR_U | 199 CMD_U0_TID(xfer->cmd_tid) | 200 (rnw ? CMD_U0_RnW : 0) | 201 CMD_U0_DEV_ADDRESS(ccc_addr) | 202 CMD_U0_XFER_RATE(rate) | 203 CMD_U0_MODE_INDEX(mode) | 204 CMD_U0_IDB_COUNT(!raw ? 0 : 1); 205 xfer->cmd_desc[1] = 206 CMD_U1_DATA_LENGTH(data_len); 207 xfer->cmd_desc[2] = 208 CMD_U2_IDB0(ccc_cmd); 209 xfer->cmd_desc[3] = 0; 210 } 211 212 return 0; 213 } 214 215 static void hci_cmd_v2_prep_i3c_xfer(struct i3c_hci *hci, 216 struct i3c_dev_desc *dev, 217 struct hci_xfer *xfer) 218 { 219 unsigned int mode = XFERMODE_IDX_I3C_SDR; 220 unsigned int rate = get_i3c_rate_idx(hci); 221 u8 addr = dev->info.dyn_addr; 222 223 hci_cmd_v2_prep_private_xfer(hci, xfer, addr, mode, rate); 224 } 225 226 static void hci_cmd_v2_prep_i2c_xfer(struct i3c_hci *hci, 227 struct i2c_dev_desc *dev, 228 struct hci_xfer *xfer) 229 { 230 unsigned int mode = XFERMODE_IDX_I2C; 231 unsigned int rate = get_i2c_rate_idx(hci); 232 u8 addr = dev->addr; 233 234 hci_cmd_v2_prep_private_xfer(hci, xfer, addr, mode, rate); 235 } 236 237 static int hci_cmd_v2_daa(struct i3c_hci *hci) 238 { 239 struct hci_xfer *xfer; 240 int ret; 241 u8 next_addr = 0; 242 u32 device_id[2]; 243 u64 pid; 244 unsigned int dcr, bcr; 245 DECLARE_COMPLETION_ONSTACK(done); 246 247 xfer = hci_alloc_xfer(2); 248 if (!xfer) 249 return -ENOMEM; 250 251 xfer[0].data = &device_id; 252 xfer[0].data_len = 8; 253 xfer[0].rnw = true; 254 xfer[0].cmd_desc[1] = CMD_A1_DATA_LENGTH(8); 255 xfer[1].completion = &done; 256 xfer[1].timeout = HZ; 257 258 for (;;) { 259 ret = i3c_master_get_free_addr(&hci->master, next_addr); 260 if (ret < 0) 261 break; 262 next_addr = ret; 263 dev_dbg(&hci->master.dev, "next_addr = 0x%02x", next_addr); 264 xfer[0].cmd_tid = hci_get_tid(); 265 xfer[0].cmd_desc[0] = 266 CMD_0_ATTR_A | 267 CMD_A0_TID(xfer[0].cmd_tid) | 268 CMD_A0_ROC; 269 xfer[1].cmd_tid = hci_get_tid(); 270 xfer[1].cmd_desc[0] = 271 CMD_0_ATTR_A | 272 CMD_A0_TID(xfer[1].cmd_tid) | 273 CMD_A0_ASSIGN_ADDRESS(next_addr) | 274 CMD_A0_ROC | 275 CMD_A0_TOC; 276 ret = i3c_hci_process_xfer(hci, xfer, 2); 277 if (ret) 278 break; 279 if (RESP_STATUS(xfer[0].response) != RESP_SUCCESS) { 280 ret = 0; /* no more devices to be assigned */ 281 break; 282 } 283 if (RESP_STATUS(xfer[1].response) != RESP_SUCCESS) { 284 ret = -EIO; 285 break; 286 } 287 288 pid = FIELD_GET(W1_MASK(47, 32), device_id[1]); 289 pid = (pid << 32) | device_id[0]; 290 bcr = FIELD_GET(W1_MASK(55, 48), device_id[1]); 291 dcr = FIELD_GET(W1_MASK(63, 56), device_id[1]); 292 dev_dbg(&hci->master.dev, 293 "assigned address %#x to device PID=0x%llx DCR=%#x BCR=%#x", 294 next_addr, pid, dcr, bcr); 295 /* 296 * TODO: Extend the subsystem layer to allow for registering 297 * new device and provide BCR/DCR/PID at the same time. 298 */ 299 ret = i3c_master_add_i3c_dev_locked(&hci->master, next_addr); 300 if (ret) 301 break; 302 } 303 304 hci_free_xfer(xfer, 2); 305 return ret; 306 } 307 308 const struct hci_cmd_ops mipi_i3c_hci_cmd_v2 = { 309 .prep_ccc = hci_cmd_v2_prep_ccc, 310 .prep_i3c_xfer = hci_cmd_v2_prep_i3c_xfer, 311 .prep_i2c_xfer = hci_cmd_v2_prep_i2c_xfer, 312 .perform_daa = hci_cmd_v2_daa, 313 }; 314