1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. 4 * 5 * Author: Vitor Soares <vitor.soares@synopsys.com> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/completion.h> 11 #include <linux/err.h> 12 #include <linux/errno.h> 13 #include <linux/i3c/master.h> 14 #include <linux/interrupt.h> 15 #include <linux/ioport.h> 16 #include <linux/iopoll.h> 17 #include <linux/list.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/reset.h> 24 #include <linux/slab.h> 25 26 #include "../internals.h" 27 #include "dw-i3c-master.h" 28 29 #define DEVICE_CTRL 0x0 30 #define DEV_CTRL_ENABLE BIT(31) 31 #define DEV_CTRL_RESUME BIT(30) 32 #define DEV_CTRL_HOT_JOIN_NACK BIT(8) 33 #define DEV_CTRL_I2C_SLAVE_PRESENT BIT(7) 34 35 #define DEVICE_ADDR 0x4 36 #define DEV_ADDR_DYNAMIC_ADDR_VALID BIT(31) 37 #define DEV_ADDR_DYNAMIC(x) (((x) << 16) & GENMASK(22, 16)) 38 39 #define HW_CAPABILITY 0x8 40 #define COMMAND_QUEUE_PORT 0xc 41 #define COMMAND_PORT_TOC BIT(30) 42 #define COMMAND_PORT_READ_TRANSFER BIT(28) 43 #define COMMAND_PORT_SDAP BIT(27) 44 #define COMMAND_PORT_ROC BIT(26) 45 #define COMMAND_PORT_SPEED(x) (((x) << 21) & GENMASK(23, 21)) 46 #define COMMAND_PORT_DEV_INDEX(x) (((x) << 16) & GENMASK(20, 16)) 47 #define COMMAND_PORT_CP BIT(15) 48 #define COMMAND_PORT_CMD(x) (((x) << 7) & GENMASK(14, 7)) 49 #define COMMAND_PORT_TID(x) (((x) << 3) & GENMASK(6, 3)) 50 51 #define COMMAND_PORT_ARG_DATA_LEN(x) (((x) << 16) & GENMASK(31, 16)) 52 #define COMMAND_PORT_ARG_DATA_LEN_MAX 65536 53 #define COMMAND_PORT_TRANSFER_ARG 0x01 54 55 #define COMMAND_PORT_SDA_DATA_BYTE_3(x) (((x) << 24) & GENMASK(31, 24)) 56 #define COMMAND_PORT_SDA_DATA_BYTE_2(x) (((x) << 16) & GENMASK(23, 16)) 57 #define COMMAND_PORT_SDA_DATA_BYTE_1(x) (((x) << 8) & GENMASK(15, 8)) 58 #define COMMAND_PORT_SDA_BYTE_STRB_3 BIT(5) 59 #define COMMAND_PORT_SDA_BYTE_STRB_2 BIT(4) 60 #define COMMAND_PORT_SDA_BYTE_STRB_1 BIT(3) 61 #define COMMAND_PORT_SHORT_DATA_ARG 0x02 62 63 #define COMMAND_PORT_DEV_COUNT(x) (((x) << 21) & GENMASK(25, 21)) 64 #define COMMAND_PORT_ADDR_ASSGN_CMD 0x03 65 66 #define RESPONSE_QUEUE_PORT 0x10 67 #define RESPONSE_PORT_ERR_STATUS(x) (((x) & GENMASK(31, 28)) >> 28) 68 #define RESPONSE_NO_ERROR 0 69 #define RESPONSE_ERROR_CRC 1 70 #define RESPONSE_ERROR_PARITY 2 71 #define RESPONSE_ERROR_FRAME 3 72 #define RESPONSE_ERROR_IBA_NACK 4 73 #define RESPONSE_ERROR_ADDRESS_NACK 5 74 #define RESPONSE_ERROR_OVER_UNDER_FLOW 6 75 #define RESPONSE_ERROR_TRANSF_ABORT 8 76 #define RESPONSE_ERROR_I2C_W_NACK_ERR 9 77 #define RESPONSE_PORT_TID(x) (((x) & GENMASK(27, 24)) >> 24) 78 #define RESPONSE_PORT_DATA_LEN(x) ((x) & GENMASK(15, 0)) 79 80 #define RX_TX_DATA_PORT 0x14 81 #define IBI_QUEUE_STATUS 0x18 82 #define IBI_QUEUE_STATUS_IBI_ID(x) (((x) & GENMASK(15, 8)) >> 8) 83 #define IBI_QUEUE_STATUS_DATA_LEN(x) ((x) & GENMASK(7, 0)) 84 #define IBI_QUEUE_IBI_ADDR(x) (IBI_QUEUE_STATUS_IBI_ID(x) >> 1) 85 #define IBI_QUEUE_IBI_RNW(x) (IBI_QUEUE_STATUS_IBI_ID(x) & BIT(0)) 86 #define IBI_TYPE_MR(x) \ 87 ((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x)) 88 #define IBI_TYPE_HJ(x) \ 89 ((IBI_QUEUE_IBI_ADDR(x) == I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x)) 90 #define IBI_TYPE_SIRQ(x) \ 91 ((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && IBI_QUEUE_IBI_RNW(x)) 92 93 #define QUEUE_THLD_CTRL 0x1c 94 #define QUEUE_THLD_CTRL_IBI_STAT_MASK GENMASK(31, 24) 95 #define QUEUE_THLD_CTRL_IBI_STAT(x) (((x) - 1) << 24) 96 #define QUEUE_THLD_CTRL_IBI_DATA_MASK GENMASK(20, 16) 97 #define QUEUE_THLD_CTRL_IBI_DATA(x) ((x) << 16) 98 #define QUEUE_THLD_CTRL_RESP_BUF_MASK GENMASK(15, 8) 99 #define QUEUE_THLD_CTRL_RESP_BUF(x) (((x) - 1) << 8) 100 101 #define DATA_BUFFER_THLD_CTRL 0x20 102 #define DATA_BUFFER_THLD_CTRL_RX_BUF GENMASK(11, 8) 103 104 #define IBI_QUEUE_CTRL 0x24 105 #define IBI_MR_REQ_REJECT 0x2C 106 #define IBI_SIR_REQ_REJECT 0x30 107 #define IBI_REQ_REJECT_ALL GENMASK(31, 0) 108 109 #define RESET_CTRL 0x34 110 #define RESET_CTRL_IBI_QUEUE BIT(5) 111 #define RESET_CTRL_RX_FIFO BIT(4) 112 #define RESET_CTRL_TX_FIFO BIT(3) 113 #define RESET_CTRL_RESP_QUEUE BIT(2) 114 #define RESET_CTRL_CMD_QUEUE BIT(1) 115 #define RESET_CTRL_SOFT BIT(0) 116 117 #define SLV_EVENT_CTRL 0x38 118 #define INTR_STATUS 0x3c 119 #define INTR_STATUS_EN 0x40 120 #define INTR_SIGNAL_EN 0x44 121 #define INTR_FORCE 0x48 122 #define INTR_BUSOWNER_UPDATE_STAT BIT(13) 123 #define INTR_IBI_UPDATED_STAT BIT(12) 124 #define INTR_READ_REQ_RECV_STAT BIT(11) 125 #define INTR_DEFSLV_STAT BIT(10) 126 #define INTR_TRANSFER_ERR_STAT BIT(9) 127 #define INTR_DYN_ADDR_ASSGN_STAT BIT(8) 128 #define INTR_CCC_UPDATED_STAT BIT(6) 129 #define INTR_TRANSFER_ABORT_STAT BIT(5) 130 #define INTR_RESP_READY_STAT BIT(4) 131 #define INTR_CMD_QUEUE_READY_STAT BIT(3) 132 #define INTR_IBI_THLD_STAT BIT(2) 133 #define INTR_RX_THLD_STAT BIT(1) 134 #define INTR_TX_THLD_STAT BIT(0) 135 #define INTR_ALL (INTR_BUSOWNER_UPDATE_STAT | \ 136 INTR_IBI_UPDATED_STAT | \ 137 INTR_READ_REQ_RECV_STAT | \ 138 INTR_DEFSLV_STAT | \ 139 INTR_TRANSFER_ERR_STAT | \ 140 INTR_DYN_ADDR_ASSGN_STAT | \ 141 INTR_CCC_UPDATED_STAT | \ 142 INTR_TRANSFER_ABORT_STAT | \ 143 INTR_RESP_READY_STAT | \ 144 INTR_CMD_QUEUE_READY_STAT | \ 145 INTR_IBI_THLD_STAT | \ 146 INTR_TX_THLD_STAT | \ 147 INTR_RX_THLD_STAT) 148 149 #define INTR_MASTER_MASK (INTR_TRANSFER_ERR_STAT | \ 150 INTR_RESP_READY_STAT) 151 152 #define QUEUE_STATUS_LEVEL 0x4c 153 #define QUEUE_STATUS_IBI_STATUS_CNT(x) (((x) & GENMASK(28, 24)) >> 24) 154 #define QUEUE_STATUS_IBI_BUF_BLR(x) (((x) & GENMASK(23, 16)) >> 16) 155 #define QUEUE_STATUS_LEVEL_RESP(x) (((x) & GENMASK(15, 8)) >> 8) 156 #define QUEUE_STATUS_LEVEL_CMD(x) ((x) & GENMASK(7, 0)) 157 158 #define DATA_BUFFER_STATUS_LEVEL 0x50 159 #define DATA_BUFFER_STATUS_LEVEL_TX(x) ((x) & GENMASK(7, 0)) 160 161 #define PRESENT_STATE 0x54 162 #define CCC_DEVICE_STATUS 0x58 163 #define DEVICE_ADDR_TABLE_POINTER 0x5c 164 #define DEVICE_ADDR_TABLE_DEPTH(x) (((x) & GENMASK(31, 16)) >> 16) 165 #define DEVICE_ADDR_TABLE_ADDR(x) ((x) & GENMASK(7, 0)) 166 167 #define DEV_CHAR_TABLE_POINTER 0x60 168 #define VENDOR_SPECIFIC_REG_POINTER 0x6c 169 #define SLV_PID_VALUE 0x74 170 #define SLV_CHAR_CTRL 0x78 171 #define SLV_MAX_LEN 0x7c 172 #define MAX_READ_TURNAROUND 0x80 173 #define MAX_DATA_SPEED 0x84 174 #define SLV_DEBUG_STATUS 0x88 175 #define SLV_INTR_REQ 0x8c 176 #define DEVICE_CTRL_EXTENDED 0xb0 177 #define SCL_I3C_OD_TIMING 0xb4 178 #define SCL_I3C_PP_TIMING 0xb8 179 #define SCL_I3C_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16)) 180 #define SCL_I3C_TIMING_LCNT(x) ((x) & GENMASK(7, 0)) 181 #define SCL_I3C_TIMING_CNT_MIN 5 182 183 #define SCL_I2C_FM_TIMING 0xbc 184 #define SCL_I2C_FM_TIMING_HCNT(x) (((x) << 16) & GENMASK(31, 16)) 185 #define SCL_I2C_FM_TIMING_LCNT(x) ((x) & GENMASK(15, 0)) 186 187 #define SCL_I2C_FMP_TIMING 0xc0 188 #define SCL_I2C_FMP_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16)) 189 #define SCL_I2C_FMP_TIMING_LCNT(x) ((x) & GENMASK(15, 0)) 190 191 #define SCL_EXT_LCNT_TIMING 0xc8 192 #define SCL_EXT_LCNT_4(x) (((x) << 24) & GENMASK(31, 24)) 193 #define SCL_EXT_LCNT_3(x) (((x) << 16) & GENMASK(23, 16)) 194 #define SCL_EXT_LCNT_2(x) (((x) << 8) & GENMASK(15, 8)) 195 #define SCL_EXT_LCNT_1(x) ((x) & GENMASK(7, 0)) 196 197 #define SCL_EXT_TERMN_LCNT_TIMING 0xcc 198 #define BUS_FREE_TIMING 0xd4 199 #define BUS_I3C_MST_FREE(x) ((x) & GENMASK(15, 0)) 200 201 #define BUS_IDLE_TIMING 0xd8 202 #define I3C_VER_ID 0xe0 203 #define I3C_VER_TYPE 0xe4 204 #define EXTENDED_CAPABILITY 0xe8 205 #define SLAVE_CONFIG 0xec 206 207 #define DEV_ADDR_TABLE_IBI_MDB BIT(12) 208 #define DEV_ADDR_TABLE_SIR_REJECT BIT(13) 209 #define DEV_ADDR_TABLE_LEGACY_I2C_DEV BIT(31) 210 #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) (((x) << 16) & GENMASK(23, 16)) 211 #define DEV_ADDR_TABLE_STATIC_ADDR(x) ((x) & GENMASK(6, 0)) 212 #define DEV_ADDR_TABLE_LOC(start, idx) ((start) + ((idx) << 2)) 213 214 #define I3C_BUS_SDR1_SCL_RATE 8000000 215 #define I3C_BUS_SDR2_SCL_RATE 6000000 216 #define I3C_BUS_SDR3_SCL_RATE 4000000 217 #define I3C_BUS_SDR4_SCL_RATE 2000000 218 #define I3C_BUS_I2C_FM_TLOW_MIN_NS 1300 219 #define I3C_BUS_I2C_FMP_TLOW_MIN_NS 500 220 #define I3C_BUS_THIGH_MAX_NS 41 221 222 #define XFER_TIMEOUT (msecs_to_jiffies(1000)) 223 #define RPM_AUTOSUSPEND_TIMEOUT 1000 /* ms */ 224 225 /* Timing values to configure 12.5MHz frequency */ 226 #define AMD_I3C_OD_TIMING 0x4C007C 227 #define AMD_I3C_PP_TIMING 0x8001A 228 229 /* List of quirks */ 230 #define AMD_I3C_OD_PP_TIMING BIT(1) 231 232 struct dw_i3c_cmd { 233 u32 cmd_lo; 234 u32 cmd_hi; 235 u16 tx_len; 236 const void *tx_buf; 237 u16 rx_len; 238 void *rx_buf; 239 u8 error; 240 }; 241 242 struct dw_i3c_xfer { 243 struct list_head node; 244 struct completion comp; 245 int ret; 246 unsigned int ncmds; 247 struct dw_i3c_cmd cmds[] __counted_by(ncmds); 248 }; 249 250 struct dw_i3c_i2c_dev_data { 251 u8 index; 252 struct i3c_generic_ibi_pool *ibi_pool; 253 }; 254 255 static bool dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m, 256 const struct i3c_ccc_cmd *cmd) 257 { 258 if (cmd->ndests > 1) 259 return false; 260 261 switch (cmd->id) { 262 case I3C_CCC_ENEC(true): 263 case I3C_CCC_ENEC(false): 264 case I3C_CCC_DISEC(true): 265 case I3C_CCC_DISEC(false): 266 case I3C_CCC_ENTAS(0, true): 267 case I3C_CCC_ENTAS(0, false): 268 case I3C_CCC_RSTDAA(true): 269 case I3C_CCC_RSTDAA(false): 270 case I3C_CCC_ENTDAA: 271 case I3C_CCC_SETMWL(true): 272 case I3C_CCC_SETMWL(false): 273 case I3C_CCC_SETMRL(true): 274 case I3C_CCC_SETMRL(false): 275 case I3C_CCC_ENTHDR(0): 276 case I3C_CCC_SETDASA: 277 case I3C_CCC_SETNEWDA: 278 case I3C_CCC_GETMWL: 279 case I3C_CCC_GETMRL: 280 case I3C_CCC_GETPID: 281 case I3C_CCC_GETBCR: 282 case I3C_CCC_GETDCR: 283 case I3C_CCC_GETSTATUS: 284 case I3C_CCC_GETMXDS: 285 case I3C_CCC_GETHDRCAP: 286 return true; 287 default: 288 return false; 289 } 290 } 291 292 static inline struct dw_i3c_master * 293 to_dw_i3c_master(struct i3c_master_controller *master) 294 { 295 return container_of(master, struct dw_i3c_master, base); 296 } 297 298 static void dw_i3c_master_disable(struct dw_i3c_master *master) 299 { 300 writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_ENABLE, 301 master->regs + DEVICE_CTRL); 302 } 303 304 static void dw_i3c_master_enable(struct dw_i3c_master *master) 305 { 306 u32 dev_ctrl; 307 308 dev_ctrl = readl(master->regs + DEVICE_CTRL); 309 /* For now don't support Hot-Join */ 310 dev_ctrl |= DEV_CTRL_HOT_JOIN_NACK; 311 if (master->i2c_slv_prsnt) 312 dev_ctrl |= DEV_CTRL_I2C_SLAVE_PRESENT; 313 writel(dev_ctrl | DEV_CTRL_ENABLE, 314 master->regs + DEVICE_CTRL); 315 } 316 317 static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr) 318 { 319 int pos; 320 321 for (pos = 0; pos < master->maxdevs; pos++) { 322 if (addr == master->devs[pos].addr) 323 return pos; 324 } 325 326 return -EINVAL; 327 } 328 329 static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master) 330 { 331 if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0))) 332 return -ENOSPC; 333 334 return ffs(master->free_pos) - 1; 335 } 336 337 static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master, 338 const u8 *bytes, int nbytes) 339 { 340 i3c_writel_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes); 341 } 342 343 static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master, 344 u8 *bytes, int nbytes) 345 { 346 i3c_readl_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes); 347 } 348 349 static void dw_i3c_master_read_ibi_fifo(struct dw_i3c_master *master, 350 u8 *bytes, int nbytes) 351 { 352 i3c_readl_fifo(master->regs + IBI_QUEUE_STATUS, bytes, nbytes); 353 } 354 355 static struct dw_i3c_xfer * 356 dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds) 357 { 358 struct dw_i3c_xfer *xfer; 359 360 xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL); 361 if (!xfer) 362 return NULL; 363 364 INIT_LIST_HEAD(&xfer->node); 365 xfer->ncmds = ncmds; 366 xfer->ret = -ETIMEDOUT; 367 368 return xfer; 369 } 370 371 static void dw_i3c_master_free_xfer(struct dw_i3c_xfer *xfer) 372 { 373 kfree(xfer); 374 } 375 376 static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master) 377 { 378 struct dw_i3c_xfer *xfer = master->xferqueue.cur; 379 unsigned int i; 380 u32 thld_ctrl; 381 382 if (!xfer) 383 return; 384 385 for (i = 0; i < xfer->ncmds; i++) { 386 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 387 388 dw_i3c_master_wr_tx_fifo(master, cmd->tx_buf, cmd->tx_len); 389 } 390 391 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL); 392 thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK; 393 thld_ctrl |= QUEUE_THLD_CTRL_RESP_BUF(xfer->ncmds); 394 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); 395 396 for (i = 0; i < xfer->ncmds; i++) { 397 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 398 399 writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT); 400 writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT); 401 } 402 } 403 404 static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master, 405 struct dw_i3c_xfer *xfer) 406 { 407 unsigned long flags; 408 409 init_completion(&xfer->comp); 410 spin_lock_irqsave(&master->xferqueue.lock, flags); 411 if (master->xferqueue.cur) { 412 list_add_tail(&xfer->node, &master->xferqueue.list); 413 } else { 414 master->xferqueue.cur = xfer; 415 dw_i3c_master_start_xfer_locked(master); 416 } 417 spin_unlock_irqrestore(&master->xferqueue.lock, flags); 418 } 419 420 static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master, 421 struct dw_i3c_xfer *xfer) 422 { 423 if (master->xferqueue.cur == xfer) { 424 u32 status; 425 426 master->xferqueue.cur = NULL; 427 428 writel(RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO | 429 RESET_CTRL_RESP_QUEUE | RESET_CTRL_CMD_QUEUE, 430 master->regs + RESET_CTRL); 431 432 readl_poll_timeout_atomic(master->regs + RESET_CTRL, status, 433 !status, 10, 1000000); 434 } else { 435 list_del_init(&xfer->node); 436 } 437 } 438 439 static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master, 440 struct dw_i3c_xfer *xfer) 441 { 442 unsigned long flags; 443 444 spin_lock_irqsave(&master->xferqueue.lock, flags); 445 dw_i3c_master_dequeue_xfer_locked(master, xfer); 446 spin_unlock_irqrestore(&master->xferqueue.lock, flags); 447 } 448 449 static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr) 450 { 451 struct dw_i3c_xfer *xfer = master->xferqueue.cur; 452 int i, ret = 0; 453 u32 nresp; 454 455 if (!xfer) 456 return; 457 458 nresp = readl(master->regs + QUEUE_STATUS_LEVEL); 459 nresp = QUEUE_STATUS_LEVEL_RESP(nresp); 460 461 for (i = 0; i < nresp; i++) { 462 struct dw_i3c_cmd *cmd; 463 u32 resp; 464 465 resp = readl(master->regs + RESPONSE_QUEUE_PORT); 466 467 cmd = &xfer->cmds[RESPONSE_PORT_TID(resp)]; 468 cmd->rx_len = RESPONSE_PORT_DATA_LEN(resp); 469 cmd->error = RESPONSE_PORT_ERR_STATUS(resp); 470 if (cmd->rx_len && !cmd->error) 471 dw_i3c_master_read_rx_fifo(master, cmd->rx_buf, 472 cmd->rx_len); 473 } 474 475 for (i = 0; i < nresp; i++) { 476 switch (xfer->cmds[i].error) { 477 case RESPONSE_NO_ERROR: 478 break; 479 case RESPONSE_ERROR_PARITY: 480 case RESPONSE_ERROR_IBA_NACK: 481 case RESPONSE_ERROR_TRANSF_ABORT: 482 case RESPONSE_ERROR_CRC: 483 case RESPONSE_ERROR_FRAME: 484 ret = -EIO; 485 break; 486 case RESPONSE_ERROR_OVER_UNDER_FLOW: 487 ret = -ENOSPC; 488 break; 489 case RESPONSE_ERROR_I2C_W_NACK_ERR: 490 case RESPONSE_ERROR_ADDRESS_NACK: 491 default: 492 ret = -EINVAL; 493 break; 494 } 495 } 496 497 xfer->ret = ret; 498 complete(&xfer->comp); 499 500 if (ret < 0) { 501 dw_i3c_master_dequeue_xfer_locked(master, xfer); 502 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME, 503 master->regs + DEVICE_CTRL); 504 } 505 506 xfer = list_first_entry_or_null(&master->xferqueue.list, 507 struct dw_i3c_xfer, 508 node); 509 if (xfer) 510 list_del_init(&xfer->node); 511 512 master->xferqueue.cur = xfer; 513 dw_i3c_master_start_xfer_locked(master); 514 } 515 516 static void dw_i3c_master_set_intr_regs(struct dw_i3c_master *master) 517 { 518 u32 thld_ctrl; 519 520 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL); 521 thld_ctrl &= ~(QUEUE_THLD_CTRL_RESP_BUF_MASK | 522 QUEUE_THLD_CTRL_IBI_STAT_MASK | 523 QUEUE_THLD_CTRL_IBI_DATA_MASK); 524 thld_ctrl |= QUEUE_THLD_CTRL_IBI_STAT(1) | 525 QUEUE_THLD_CTRL_IBI_DATA(31); 526 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); 527 528 thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL); 529 thld_ctrl &= ~DATA_BUFFER_THLD_CTRL_RX_BUF; 530 writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL); 531 532 writel(INTR_ALL, master->regs + INTR_STATUS); 533 writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN); 534 writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN); 535 536 master->sir_rej_mask = IBI_REQ_REJECT_ALL; 537 writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT); 538 539 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT); 540 } 541 542 static int dw_i3c_clk_cfg(struct dw_i3c_master *master) 543 { 544 unsigned long core_rate, core_period; 545 u32 scl_timing; 546 u8 hcnt, lcnt; 547 548 core_rate = clk_get_rate(master->core_clk); 549 if (!core_rate) 550 return -EINVAL; 551 552 core_period = DIV_ROUND_UP(1000000000, core_rate); 553 554 hcnt = DIV_ROUND_UP(I3C_BUS_THIGH_MAX_NS, core_period) - 1; 555 if (hcnt < SCL_I3C_TIMING_CNT_MIN) 556 hcnt = SCL_I3C_TIMING_CNT_MIN; 557 558 lcnt = DIV_ROUND_UP(core_rate, master->base.bus.scl_rate.i3c) - hcnt; 559 if (lcnt < SCL_I3C_TIMING_CNT_MIN) 560 lcnt = SCL_I3C_TIMING_CNT_MIN; 561 562 scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt); 563 writel(scl_timing, master->regs + SCL_I3C_PP_TIMING); 564 master->i3c_pp_timing = scl_timing; 565 566 /* 567 * In pure i3c mode, MST_FREE represents tCAS. In shared mode, this 568 * will be set up by dw_i2c_clk_cfg as tLOW. 569 */ 570 if (master->base.bus.mode == I3C_BUS_MODE_PURE) { 571 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); 572 master->bus_free_timing = BUS_I3C_MST_FREE(lcnt); 573 } 574 575 lcnt = max_t(u8, 576 DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period), lcnt); 577 scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt); 578 writel(scl_timing, master->regs + SCL_I3C_OD_TIMING); 579 master->i3c_od_timing = scl_timing; 580 581 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR1_SCL_RATE) - hcnt; 582 scl_timing = SCL_EXT_LCNT_1(lcnt); 583 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR2_SCL_RATE) - hcnt; 584 scl_timing |= SCL_EXT_LCNT_2(lcnt); 585 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR3_SCL_RATE) - hcnt; 586 scl_timing |= SCL_EXT_LCNT_3(lcnt); 587 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR4_SCL_RATE) - hcnt; 588 scl_timing |= SCL_EXT_LCNT_4(lcnt); 589 writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING); 590 master->ext_lcnt_timing = scl_timing; 591 592 return 0; 593 } 594 595 static int dw_i2c_clk_cfg(struct dw_i3c_master *master) 596 { 597 unsigned long core_rate, core_period; 598 u16 hcnt, lcnt; 599 u32 scl_timing; 600 601 core_rate = clk_get_rate(master->core_clk); 602 if (!core_rate) 603 return -EINVAL; 604 605 core_period = DIV_ROUND_UP(1000000000, core_rate); 606 607 lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FMP_TLOW_MIN_NS, core_period); 608 hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_PLUS_SCL_MAX_RATE) - lcnt; 609 scl_timing = SCL_I2C_FMP_TIMING_HCNT(hcnt) | 610 SCL_I2C_FMP_TIMING_LCNT(lcnt); 611 writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING); 612 master->i2c_fmp_timing = scl_timing; 613 614 lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FM_TLOW_MIN_NS, core_period); 615 hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_SCL_MAX_RATE) - lcnt; 616 scl_timing = SCL_I2C_FM_TIMING_HCNT(hcnt) | 617 SCL_I2C_FM_TIMING_LCNT(lcnt); 618 writel(scl_timing, master->regs + SCL_I2C_FM_TIMING); 619 master->i2c_fm_timing = scl_timing; 620 621 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); 622 master->bus_free_timing = BUS_I3C_MST_FREE(lcnt); 623 624 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT, 625 master->regs + DEVICE_CTRL); 626 master->i2c_slv_prsnt = true; 627 628 return 0; 629 } 630 631 static int dw_i3c_master_bus_init(struct i3c_master_controller *m) 632 { 633 struct dw_i3c_master *master = to_dw_i3c_master(m); 634 struct i3c_bus *bus = i3c_master_get_bus(m); 635 struct i3c_device_info info = { }; 636 int ret; 637 638 ret = pm_runtime_resume_and_get(master->dev); 639 if (ret < 0) { 640 dev_err(master->dev, 641 "<%s> cannot resume i3c bus master, err: %d\n", 642 __func__, ret); 643 return ret; 644 } 645 646 ret = master->platform_ops->init(master); 647 if (ret) 648 goto rpm_out; 649 650 switch (bus->mode) { 651 case I3C_BUS_MODE_MIXED_FAST: 652 case I3C_BUS_MODE_MIXED_LIMITED: 653 ret = dw_i2c_clk_cfg(master); 654 if (ret) 655 goto rpm_out; 656 fallthrough; 657 case I3C_BUS_MODE_PURE: 658 ret = dw_i3c_clk_cfg(master); 659 if (ret) 660 goto rpm_out; 661 break; 662 default: 663 ret = -EINVAL; 664 goto rpm_out; 665 } 666 667 ret = i3c_master_get_free_addr(m, 0); 668 if (ret < 0) 669 goto rpm_out; 670 671 writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret), 672 master->regs + DEVICE_ADDR); 673 master->dev_addr = ret; 674 memset(&info, 0, sizeof(info)); 675 info.dyn_addr = ret; 676 677 ret = i3c_master_set_info(&master->base, &info); 678 if (ret) 679 goto rpm_out; 680 681 dw_i3c_master_set_intr_regs(master); 682 dw_i3c_master_enable(master); 683 684 rpm_out: 685 pm_runtime_put_autosuspend(master->dev); 686 return ret; 687 } 688 689 static void dw_i3c_master_bus_cleanup(struct i3c_master_controller *m) 690 { 691 struct dw_i3c_master *master = to_dw_i3c_master(m); 692 693 dw_i3c_master_disable(master); 694 } 695 696 static int dw_i3c_ccc_set(struct dw_i3c_master *master, 697 struct i3c_ccc_cmd *ccc) 698 { 699 struct dw_i3c_xfer *xfer; 700 struct dw_i3c_cmd *cmd; 701 int ret, pos = 0; 702 703 if (ccc->id & I3C_CCC_DIRECT) { 704 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); 705 if (pos < 0) 706 return pos; 707 } 708 709 xfer = dw_i3c_master_alloc_xfer(master, 1); 710 if (!xfer) 711 return -ENOMEM; 712 713 cmd = xfer->cmds; 714 cmd->tx_buf = ccc->dests[0].payload.data; 715 cmd->tx_len = ccc->dests[0].payload.len; 716 717 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) | 718 COMMAND_PORT_TRANSFER_ARG; 719 720 cmd->cmd_lo = COMMAND_PORT_CP | 721 COMMAND_PORT_DEV_INDEX(pos) | 722 COMMAND_PORT_CMD(ccc->id) | 723 COMMAND_PORT_TOC | 724 COMMAND_PORT_ROC; 725 726 dw_i3c_master_enqueue_xfer(master, xfer); 727 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 728 dw_i3c_master_dequeue_xfer(master, xfer); 729 730 ret = xfer->ret; 731 if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK) 732 ccc->err = I3C_ERROR_M2; 733 734 dw_i3c_master_free_xfer(xfer); 735 736 return ret; 737 } 738 739 static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc) 740 { 741 struct dw_i3c_xfer *xfer; 742 struct dw_i3c_cmd *cmd; 743 int ret, pos; 744 745 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); 746 if (pos < 0) 747 return pos; 748 749 xfer = dw_i3c_master_alloc_xfer(master, 1); 750 if (!xfer) 751 return -ENOMEM; 752 753 cmd = xfer->cmds; 754 cmd->rx_buf = ccc->dests[0].payload.data; 755 cmd->rx_len = ccc->dests[0].payload.len; 756 757 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) | 758 COMMAND_PORT_TRANSFER_ARG; 759 760 cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER | 761 COMMAND_PORT_CP | 762 COMMAND_PORT_DEV_INDEX(pos) | 763 COMMAND_PORT_CMD(ccc->id) | 764 COMMAND_PORT_TOC | 765 COMMAND_PORT_ROC; 766 767 dw_i3c_master_enqueue_xfer(master, xfer); 768 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 769 dw_i3c_master_dequeue_xfer(master, xfer); 770 771 ret = xfer->ret; 772 if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK) 773 ccc->err = I3C_ERROR_M2; 774 dw_i3c_master_free_xfer(xfer); 775 776 return ret; 777 } 778 779 static void amd_configure_od_pp_quirk(struct dw_i3c_master *master) 780 { 781 master->i3c_od_timing = AMD_I3C_OD_TIMING; 782 master->i3c_pp_timing = AMD_I3C_PP_TIMING; 783 } 784 785 static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, 786 struct i3c_ccc_cmd *ccc) 787 { 788 struct dw_i3c_master *master = to_dw_i3c_master(m); 789 int ret = 0; 790 791 if (ccc->id == I3C_CCC_ENTDAA) 792 return -EINVAL; 793 794 /* AMD platform specific OD and PP timings */ 795 if (master->quirks & AMD_I3C_OD_PP_TIMING) { 796 amd_configure_od_pp_quirk(master); 797 writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING); 798 writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING); 799 } 800 801 ret = pm_runtime_resume_and_get(master->dev); 802 if (ret < 0) { 803 dev_err(master->dev, 804 "<%s> cannot resume i3c bus master, err: %d\n", 805 __func__, ret); 806 return ret; 807 } 808 809 if (ccc->rnw) 810 ret = dw_i3c_ccc_get(master, ccc); 811 else 812 ret = dw_i3c_ccc_set(master, ccc); 813 814 pm_runtime_put_autosuspend(master->dev); 815 return ret; 816 } 817 818 static int dw_i3c_master_daa(struct i3c_master_controller *m) 819 { 820 struct dw_i3c_master *master = to_dw_i3c_master(m); 821 struct dw_i3c_xfer *xfer; 822 struct dw_i3c_cmd *cmd; 823 u32 olddevs, newdevs; 824 u8 last_addr = 0; 825 int ret, pos; 826 827 ret = pm_runtime_resume_and_get(master->dev); 828 if (ret < 0) { 829 dev_err(master->dev, 830 "<%s> cannot resume i3c bus master, err: %d\n", 831 __func__, ret); 832 return ret; 833 } 834 835 olddevs = ~(master->free_pos); 836 837 /* Prepare DAT before launching DAA. */ 838 for (pos = 0; pos < master->maxdevs; pos++) { 839 if (olddevs & BIT(pos)) 840 continue; 841 842 ret = i3c_master_get_free_addr(m, last_addr + 1); 843 if (ret < 0) { 844 ret = -ENOSPC; 845 goto rpm_out; 846 } 847 848 master->devs[pos].addr = ret; 849 last_addr = ret; 850 851 ret |= parity8(ret) ? 0 : BIT(7); 852 853 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(ret), 854 master->regs + 855 DEV_ADDR_TABLE_LOC(master->datstartaddr, pos)); 856 857 ret = 0; 858 } 859 860 xfer = dw_i3c_master_alloc_xfer(master, 1); 861 if (!xfer) { 862 ret = -ENOMEM; 863 goto rpm_out; 864 } 865 866 pos = dw_i3c_master_get_free_pos(master); 867 if (pos < 0) { 868 dw_i3c_master_free_xfer(xfer); 869 ret = pos; 870 goto rpm_out; 871 } 872 cmd = &xfer->cmds[0]; 873 cmd->cmd_hi = 0x1; 874 cmd->cmd_lo = COMMAND_PORT_DEV_COUNT(master->maxdevs - pos) | 875 COMMAND_PORT_DEV_INDEX(pos) | 876 COMMAND_PORT_CMD(I3C_CCC_ENTDAA) | 877 COMMAND_PORT_ADDR_ASSGN_CMD | 878 COMMAND_PORT_TOC | 879 COMMAND_PORT_ROC; 880 881 dw_i3c_master_enqueue_xfer(master, xfer); 882 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 883 dw_i3c_master_dequeue_xfer(master, xfer); 884 885 newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0); 886 newdevs &= ~olddevs; 887 888 for (pos = 0; pos < master->maxdevs; pos++) { 889 if (newdevs & BIT(pos)) 890 i3c_master_add_i3c_dev_locked(m, master->devs[pos].addr); 891 } 892 893 dw_i3c_master_free_xfer(xfer); 894 895 rpm_out: 896 pm_runtime_put_autosuspend(master->dev); 897 return ret; 898 } 899 900 static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev, 901 struct i3c_priv_xfer *i3c_xfers, 902 int i3c_nxfers) 903 { 904 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 905 struct i3c_master_controller *m = i3c_dev_get_master(dev); 906 struct dw_i3c_master *master = to_dw_i3c_master(m); 907 unsigned int nrxwords = 0, ntxwords = 0; 908 struct dw_i3c_xfer *xfer; 909 int i, ret = 0; 910 911 if (!i3c_nxfers) 912 return 0; 913 914 if (i3c_nxfers > master->caps.cmdfifodepth) 915 return -EOPNOTSUPP; 916 917 for (i = 0; i < i3c_nxfers; i++) { 918 if (i3c_xfers[i].rnw) 919 nrxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4); 920 else 921 ntxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4); 922 } 923 924 if (ntxwords > master->caps.datafifodepth || 925 nrxwords > master->caps.datafifodepth) 926 return -EOPNOTSUPP; 927 928 xfer = dw_i3c_master_alloc_xfer(master, i3c_nxfers); 929 if (!xfer) 930 return -ENOMEM; 931 932 ret = pm_runtime_resume_and_get(master->dev); 933 if (ret < 0) { 934 dev_err(master->dev, 935 "<%s> cannot resume i3c bus master, err: %d\n", 936 __func__, ret); 937 return ret; 938 } 939 940 for (i = 0; i < i3c_nxfers; i++) { 941 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 942 943 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i3c_xfers[i].len) | 944 COMMAND_PORT_TRANSFER_ARG; 945 946 if (i3c_xfers[i].rnw) { 947 cmd->rx_buf = i3c_xfers[i].data.in; 948 cmd->rx_len = i3c_xfers[i].len; 949 cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER | 950 COMMAND_PORT_SPEED(dev->info.max_read_ds); 951 952 } else { 953 cmd->tx_buf = i3c_xfers[i].data.out; 954 cmd->tx_len = i3c_xfers[i].len; 955 cmd->cmd_lo = 956 COMMAND_PORT_SPEED(dev->info.max_write_ds); 957 } 958 959 cmd->cmd_lo |= COMMAND_PORT_TID(i) | 960 COMMAND_PORT_DEV_INDEX(data->index) | 961 COMMAND_PORT_ROC; 962 963 if (i == (i3c_nxfers - 1)) 964 cmd->cmd_lo |= COMMAND_PORT_TOC; 965 } 966 967 dw_i3c_master_enqueue_xfer(master, xfer); 968 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 969 dw_i3c_master_dequeue_xfer(master, xfer); 970 971 for (i = 0; i < i3c_nxfers; i++) { 972 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 973 974 if (i3c_xfers[i].rnw) 975 i3c_xfers[i].len = cmd->rx_len; 976 } 977 978 ret = xfer->ret; 979 dw_i3c_master_free_xfer(xfer); 980 981 pm_runtime_put_autosuspend(master->dev); 982 return ret; 983 } 984 985 static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, 986 u8 old_dyn_addr) 987 { 988 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 989 struct i3c_master_controller *m = i3c_dev_get_master(dev); 990 struct dw_i3c_master *master = to_dw_i3c_master(m); 991 int pos; 992 993 pos = dw_i3c_master_get_free_pos(master); 994 995 if (data->index > pos && pos > 0) { 996 writel(0, 997 master->regs + 998 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 999 1000 master->devs[data->index].addr = 0; 1001 master->free_pos |= BIT(data->index); 1002 1003 data->index = pos; 1004 master->devs[pos].addr = dev->info.dyn_addr; 1005 master->free_pos &= ~BIT(pos); 1006 } 1007 1008 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(dev->info.dyn_addr), 1009 master->regs + 1010 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 1011 1012 master->devs[data->index].addr = dev->info.dyn_addr; 1013 1014 return 0; 1015 } 1016 1017 static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev) 1018 { 1019 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1020 struct dw_i3c_master *master = to_dw_i3c_master(m); 1021 struct dw_i3c_i2c_dev_data *data; 1022 int pos; 1023 1024 pos = dw_i3c_master_get_free_pos(master); 1025 if (pos < 0) 1026 return pos; 1027 1028 data = kzalloc(sizeof(*data), GFP_KERNEL); 1029 if (!data) 1030 return -ENOMEM; 1031 1032 data->index = pos; 1033 master->devs[pos].addr = dev->info.dyn_addr ? : dev->info.static_addr; 1034 master->free_pos &= ~BIT(pos); 1035 i3c_dev_set_master_data(dev, data); 1036 1037 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr), 1038 master->regs + 1039 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 1040 1041 return 0; 1042 } 1043 1044 static void dw_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) 1045 { 1046 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1047 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1048 struct dw_i3c_master *master = to_dw_i3c_master(m); 1049 1050 writel(0, 1051 master->regs + 1052 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 1053 1054 i3c_dev_set_master_data(dev, NULL); 1055 master->devs[data->index].addr = 0; 1056 master->free_pos |= BIT(data->index); 1057 kfree(data); 1058 } 1059 1060 static int dw_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, 1061 struct i2c_msg *i2c_xfers, 1062 int i2c_nxfers) 1063 { 1064 struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 1065 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1066 struct dw_i3c_master *master = to_dw_i3c_master(m); 1067 unsigned int nrxwords = 0, ntxwords = 0; 1068 struct dw_i3c_xfer *xfer; 1069 int i, ret = 0; 1070 1071 if (!i2c_nxfers) 1072 return 0; 1073 1074 if (i2c_nxfers > master->caps.cmdfifodepth) 1075 return -EOPNOTSUPP; 1076 1077 for (i = 0; i < i2c_nxfers; i++) { 1078 if (i2c_xfers[i].flags & I2C_M_RD) 1079 nrxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4); 1080 else 1081 ntxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4); 1082 } 1083 1084 if (ntxwords > master->caps.datafifodepth || 1085 nrxwords > master->caps.datafifodepth) 1086 return -EOPNOTSUPP; 1087 1088 xfer = dw_i3c_master_alloc_xfer(master, i2c_nxfers); 1089 if (!xfer) 1090 return -ENOMEM; 1091 1092 ret = pm_runtime_resume_and_get(master->dev); 1093 if (ret < 0) { 1094 dev_err(master->dev, 1095 "<%s> cannot resume i3c bus master, err: %d\n", 1096 __func__, ret); 1097 return ret; 1098 } 1099 1100 for (i = 0; i < i2c_nxfers; i++) { 1101 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 1102 1103 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i2c_xfers[i].len) | 1104 COMMAND_PORT_TRANSFER_ARG; 1105 1106 cmd->cmd_lo = COMMAND_PORT_TID(i) | 1107 COMMAND_PORT_DEV_INDEX(data->index) | 1108 COMMAND_PORT_ROC; 1109 1110 if (i2c_xfers[i].flags & I2C_M_RD) { 1111 cmd->cmd_lo |= COMMAND_PORT_READ_TRANSFER; 1112 cmd->rx_buf = i2c_xfers[i].buf; 1113 cmd->rx_len = i2c_xfers[i].len; 1114 } else { 1115 cmd->tx_buf = i2c_xfers[i].buf; 1116 cmd->tx_len = i2c_xfers[i].len; 1117 } 1118 1119 if (i == (i2c_nxfers - 1)) 1120 cmd->cmd_lo |= COMMAND_PORT_TOC; 1121 } 1122 1123 dw_i3c_master_enqueue_xfer(master, xfer); 1124 if (!wait_for_completion_timeout(&xfer->comp, m->i2c.timeout)) 1125 dw_i3c_master_dequeue_xfer(master, xfer); 1126 1127 ret = xfer->ret; 1128 dw_i3c_master_free_xfer(xfer); 1129 1130 pm_runtime_put_autosuspend(master->dev); 1131 return ret; 1132 } 1133 1134 static int dw_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) 1135 { 1136 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1137 struct dw_i3c_master *master = to_dw_i3c_master(m); 1138 struct dw_i3c_i2c_dev_data *data; 1139 int pos; 1140 1141 pos = dw_i3c_master_get_free_pos(master); 1142 if (pos < 0) 1143 return pos; 1144 1145 data = kzalloc(sizeof(*data), GFP_KERNEL); 1146 if (!data) 1147 return -ENOMEM; 1148 1149 data->index = pos; 1150 master->devs[pos].addr = dev->addr; 1151 master->devs[pos].is_i2c_addr = true; 1152 master->free_pos &= ~BIT(pos); 1153 i2c_dev_set_master_data(dev, data); 1154 1155 writel(DEV_ADDR_TABLE_LEGACY_I2C_DEV | 1156 DEV_ADDR_TABLE_STATIC_ADDR(dev->addr), 1157 master->regs + 1158 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 1159 1160 return 0; 1161 } 1162 1163 static void dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) 1164 { 1165 struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 1166 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1167 struct dw_i3c_master *master = to_dw_i3c_master(m); 1168 1169 writel(0, 1170 master->regs + 1171 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 1172 1173 i2c_dev_set_master_data(dev, NULL); 1174 master->devs[data->index].addr = 0; 1175 master->free_pos |= BIT(data->index); 1176 kfree(data); 1177 } 1178 1179 static int dw_i3c_master_request_ibi(struct i3c_dev_desc *dev, 1180 const struct i3c_ibi_setup *req) 1181 { 1182 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1183 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1184 struct dw_i3c_master *master = to_dw_i3c_master(m); 1185 unsigned long flags; 1186 1187 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); 1188 if (IS_ERR(data->ibi_pool)) 1189 return PTR_ERR(data->ibi_pool); 1190 1191 spin_lock_irqsave(&master->devs_lock, flags); 1192 master->devs[data->index].ibi_dev = dev; 1193 spin_unlock_irqrestore(&master->devs_lock, flags); 1194 1195 return 0; 1196 } 1197 1198 static void dw_i3c_master_free_ibi(struct i3c_dev_desc *dev) 1199 { 1200 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1201 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1202 struct dw_i3c_master *master = to_dw_i3c_master(m); 1203 unsigned long flags; 1204 1205 spin_lock_irqsave(&master->devs_lock, flags); 1206 master->devs[data->index].ibi_dev = NULL; 1207 spin_unlock_irqrestore(&master->devs_lock, flags); 1208 1209 i3c_generic_ibi_free_pool(data->ibi_pool); 1210 data->ibi_pool = NULL; 1211 } 1212 1213 static void dw_i3c_master_enable_sir_signal(struct dw_i3c_master *master, bool enable) 1214 { 1215 u32 reg; 1216 1217 reg = readl(master->regs + INTR_STATUS_EN); 1218 reg &= ~INTR_IBI_THLD_STAT; 1219 if (enable) 1220 reg |= INTR_IBI_THLD_STAT; 1221 writel(reg, master->regs + INTR_STATUS_EN); 1222 1223 reg = readl(master->regs + INTR_SIGNAL_EN); 1224 reg &= ~INTR_IBI_THLD_STAT; 1225 if (enable) 1226 reg |= INTR_IBI_THLD_STAT; 1227 writel(reg, master->regs + INTR_SIGNAL_EN); 1228 } 1229 1230 static void dw_i3c_master_set_sir_enabled(struct dw_i3c_master *master, 1231 struct i3c_dev_desc *dev, 1232 u8 idx, bool enable) 1233 { 1234 unsigned long flags; 1235 u32 dat_entry, reg; 1236 bool global; 1237 1238 dat_entry = DEV_ADDR_TABLE_LOC(master->datstartaddr, idx); 1239 1240 spin_lock_irqsave(&master->devs_lock, flags); 1241 reg = readl(master->regs + dat_entry); 1242 if (enable) { 1243 reg &= ~DEV_ADDR_TABLE_SIR_REJECT; 1244 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) 1245 reg |= DEV_ADDR_TABLE_IBI_MDB; 1246 } else { 1247 reg |= DEV_ADDR_TABLE_SIR_REJECT; 1248 } 1249 master->platform_ops->set_dat_ibi(master, dev, enable, ®); 1250 writel(reg, master->regs + dat_entry); 1251 1252 if (enable) { 1253 global = (master->sir_rej_mask == IBI_REQ_REJECT_ALL); 1254 master->sir_rej_mask &= ~BIT(idx); 1255 } else { 1256 bool hj_rejected = !!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_HOT_JOIN_NACK); 1257 1258 master->sir_rej_mask |= BIT(idx); 1259 global = (master->sir_rej_mask == IBI_REQ_REJECT_ALL) && hj_rejected; 1260 } 1261 writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT); 1262 1263 if (global) 1264 dw_i3c_master_enable_sir_signal(master, enable); 1265 1266 1267 spin_unlock_irqrestore(&master->devs_lock, flags); 1268 } 1269 1270 static int dw_i3c_master_enable_hotjoin(struct i3c_master_controller *m) 1271 { 1272 struct dw_i3c_master *master = to_dw_i3c_master(m); 1273 int ret; 1274 1275 ret = pm_runtime_resume_and_get(master->dev); 1276 if (ret < 0) { 1277 dev_err(master->dev, 1278 "<%s> cannot resume i3c bus master, err: %d\n", 1279 __func__, ret); 1280 return ret; 1281 } 1282 1283 dw_i3c_master_enable_sir_signal(master, true); 1284 writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_HOT_JOIN_NACK, 1285 master->regs + DEVICE_CTRL); 1286 1287 return 0; 1288 } 1289 1290 static int dw_i3c_master_disable_hotjoin(struct i3c_master_controller *m) 1291 { 1292 struct dw_i3c_master *master = to_dw_i3c_master(m); 1293 1294 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK, 1295 master->regs + DEVICE_CTRL); 1296 1297 pm_runtime_put_autosuspend(master->dev); 1298 return 0; 1299 } 1300 1301 static int dw_i3c_master_enable_ibi(struct i3c_dev_desc *dev) 1302 { 1303 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1304 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1305 struct dw_i3c_master *master = to_dw_i3c_master(m); 1306 int rc; 1307 1308 rc = pm_runtime_resume_and_get(master->dev); 1309 if (rc < 0) { 1310 dev_err(master->dev, 1311 "<%s> cannot resume i3c bus master, err: %d\n", 1312 __func__, rc); 1313 return rc; 1314 } 1315 1316 dw_i3c_master_set_sir_enabled(master, dev, data->index, true); 1317 1318 rc = i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); 1319 1320 if (rc) { 1321 dw_i3c_master_set_sir_enabled(master, dev, data->index, false); 1322 pm_runtime_put_autosuspend(master->dev); 1323 } 1324 1325 return rc; 1326 } 1327 1328 static int dw_i3c_master_disable_ibi(struct i3c_dev_desc *dev) 1329 { 1330 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1331 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1332 struct dw_i3c_master *master = to_dw_i3c_master(m); 1333 int rc; 1334 1335 rc = i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); 1336 if (rc) 1337 return rc; 1338 1339 dw_i3c_master_set_sir_enabled(master, dev, data->index, false); 1340 1341 pm_runtime_put_autosuspend(master->dev); 1342 return 0; 1343 } 1344 1345 static void dw_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev, 1346 struct i3c_ibi_slot *slot) 1347 { 1348 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1349 1350 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot); 1351 } 1352 1353 static void dw_i3c_master_drain_ibi_queue(struct dw_i3c_master *master, 1354 int len) 1355 { 1356 int i; 1357 1358 for (i = 0; i < DIV_ROUND_UP(len, 4); i++) 1359 readl(master->regs + IBI_QUEUE_STATUS); 1360 } 1361 1362 static void dw_i3c_master_handle_ibi_sir(struct dw_i3c_master *master, 1363 u32 status) 1364 { 1365 struct dw_i3c_i2c_dev_data *data; 1366 struct i3c_ibi_slot *slot; 1367 struct i3c_dev_desc *dev; 1368 unsigned long flags; 1369 u8 addr, len; 1370 int idx; 1371 1372 addr = IBI_QUEUE_IBI_ADDR(status); 1373 len = IBI_QUEUE_STATUS_DATA_LEN(status); 1374 1375 /* 1376 * We be tempted to check the error status in bit 30; however, due 1377 * to the PEC errata workaround on some platform implementations (see 1378 * ast2600_i3c_set_dat_ibi()), those will almost always have a PEC 1379 * error on IBI payload data, as well as losing the last byte of 1380 * payload. 1381 * 1382 * If we implement error status checking on that bit, we may need 1383 * a new platform op to validate it. 1384 */ 1385 1386 spin_lock_irqsave(&master->devs_lock, flags); 1387 idx = dw_i3c_master_get_addr_pos(master, addr); 1388 if (idx < 0) { 1389 dev_dbg_ratelimited(&master->base.dev, 1390 "IBI from unknown addr 0x%x\n", addr); 1391 goto err_drain; 1392 } 1393 1394 dev = master->devs[idx].ibi_dev; 1395 if (!dev || !dev->ibi) { 1396 dev_dbg_ratelimited(&master->base.dev, 1397 "IBI from non-requested dev idx %d\n", idx); 1398 goto err_drain; 1399 } 1400 1401 data = i3c_dev_get_master_data(dev); 1402 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool); 1403 if (!slot) { 1404 dev_dbg_ratelimited(&master->base.dev, 1405 "No IBI slots available\n"); 1406 goto err_drain; 1407 } 1408 1409 if (dev->ibi->max_payload_len < len) { 1410 dev_dbg_ratelimited(&master->base.dev, 1411 "IBI payload len %d greater than max %d\n", 1412 len, dev->ibi->max_payload_len); 1413 goto err_drain; 1414 } 1415 1416 if (len) { 1417 dw_i3c_master_read_ibi_fifo(master, slot->data, len); 1418 slot->len = len; 1419 } 1420 i3c_master_queue_ibi(dev, slot); 1421 1422 spin_unlock_irqrestore(&master->devs_lock, flags); 1423 1424 return; 1425 1426 err_drain: 1427 dw_i3c_master_drain_ibi_queue(master, len); 1428 1429 spin_unlock_irqrestore(&master->devs_lock, flags); 1430 } 1431 1432 /* "ibis": referring to In-Band Interrupts, and not 1433 * https://en.wikipedia.org/wiki/Australian_white_ibis. The latter should 1434 * not be handled. 1435 */ 1436 static void dw_i3c_master_irq_handle_ibis(struct dw_i3c_master *master) 1437 { 1438 unsigned int i, len, n_ibis; 1439 u32 reg; 1440 1441 reg = readl(master->regs + QUEUE_STATUS_LEVEL); 1442 n_ibis = QUEUE_STATUS_IBI_STATUS_CNT(reg); 1443 if (!n_ibis) 1444 return; 1445 1446 for (i = 0; i < n_ibis; i++) { 1447 reg = readl(master->regs + IBI_QUEUE_STATUS); 1448 1449 if (IBI_TYPE_SIRQ(reg)) { 1450 dw_i3c_master_handle_ibi_sir(master, reg); 1451 } else if (IBI_TYPE_HJ(reg)) { 1452 queue_work(master->base.wq, &master->hj_work); 1453 } else { 1454 len = IBI_QUEUE_STATUS_DATA_LEN(reg); 1455 dev_info(&master->base.dev, 1456 "unsupported IBI type 0x%lx len %d\n", 1457 IBI_QUEUE_STATUS_IBI_ID(reg), len); 1458 dw_i3c_master_drain_ibi_queue(master, len); 1459 } 1460 } 1461 } 1462 1463 static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id) 1464 { 1465 struct dw_i3c_master *master = dev_id; 1466 u32 status; 1467 1468 status = readl(master->regs + INTR_STATUS); 1469 1470 if (!(status & readl(master->regs + INTR_STATUS_EN))) { 1471 writel(INTR_ALL, master->regs + INTR_STATUS); 1472 return IRQ_NONE; 1473 } 1474 1475 spin_lock(&master->xferqueue.lock); 1476 dw_i3c_master_end_xfer_locked(master, status); 1477 if (status & INTR_TRANSFER_ERR_STAT) 1478 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS); 1479 spin_unlock(&master->xferqueue.lock); 1480 1481 if (status & INTR_IBI_THLD_STAT) 1482 dw_i3c_master_irq_handle_ibis(master); 1483 1484 return IRQ_HANDLED; 1485 } 1486 1487 static const struct i3c_master_controller_ops dw_mipi_i3c_ops = { 1488 .bus_init = dw_i3c_master_bus_init, 1489 .bus_cleanup = dw_i3c_master_bus_cleanup, 1490 .attach_i3c_dev = dw_i3c_master_attach_i3c_dev, 1491 .reattach_i3c_dev = dw_i3c_master_reattach_i3c_dev, 1492 .detach_i3c_dev = dw_i3c_master_detach_i3c_dev, 1493 .do_daa = dw_i3c_master_daa, 1494 .supports_ccc_cmd = dw_i3c_master_supports_ccc_cmd, 1495 .send_ccc_cmd = dw_i3c_master_send_ccc_cmd, 1496 .priv_xfers = dw_i3c_master_priv_xfers, 1497 .attach_i2c_dev = dw_i3c_master_attach_i2c_dev, 1498 .detach_i2c_dev = dw_i3c_master_detach_i2c_dev, 1499 .i2c_xfers = dw_i3c_master_i2c_xfers, 1500 .request_ibi = dw_i3c_master_request_ibi, 1501 .free_ibi = dw_i3c_master_free_ibi, 1502 .enable_ibi = dw_i3c_master_enable_ibi, 1503 .disable_ibi = dw_i3c_master_disable_ibi, 1504 .recycle_ibi_slot = dw_i3c_master_recycle_ibi_slot, 1505 .enable_hotjoin = dw_i3c_master_enable_hotjoin, 1506 .disable_hotjoin = dw_i3c_master_disable_hotjoin, 1507 }; 1508 1509 /* default platform ops implementations */ 1510 static int dw_i3c_platform_init_nop(struct dw_i3c_master *i3c) 1511 { 1512 return 0; 1513 } 1514 1515 static void dw_i3c_platform_set_dat_ibi_nop(struct dw_i3c_master *i3c, 1516 struct i3c_dev_desc *dev, 1517 bool enable, u32 *dat) 1518 { 1519 } 1520 1521 static const struct dw_i3c_platform_ops dw_i3c_platform_ops_default = { 1522 .init = dw_i3c_platform_init_nop, 1523 .set_dat_ibi = dw_i3c_platform_set_dat_ibi_nop, 1524 }; 1525 1526 static void dw_i3c_hj_work(struct work_struct *work) 1527 { 1528 struct dw_i3c_master *master = 1529 container_of(work, typeof(*master), hj_work); 1530 1531 i3c_master_do_daa(&master->base); 1532 } 1533 1534 int dw_i3c_common_probe(struct dw_i3c_master *master, 1535 struct platform_device *pdev) 1536 { 1537 int ret, irq; 1538 1539 if (!master->platform_ops) 1540 master->platform_ops = &dw_i3c_platform_ops_default; 1541 1542 master->dev = &pdev->dev; 1543 1544 master->regs = devm_platform_ioremap_resource(pdev, 0); 1545 if (IS_ERR(master->regs)) 1546 return PTR_ERR(master->regs); 1547 1548 master->core_clk = devm_clk_get_enabled(&pdev->dev, NULL); 1549 if (IS_ERR(master->core_clk)) 1550 return PTR_ERR(master->core_clk); 1551 1552 master->pclk = devm_clk_get_optional_enabled(&pdev->dev, "pclk"); 1553 if (IS_ERR(master->pclk)) 1554 return PTR_ERR(master->pclk); 1555 1556 master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, 1557 "core_rst"); 1558 if (IS_ERR(master->core_rst)) 1559 return PTR_ERR(master->core_rst); 1560 1561 reset_control_deassert(master->core_rst); 1562 1563 spin_lock_init(&master->xferqueue.lock); 1564 INIT_LIST_HEAD(&master->xferqueue.list); 1565 1566 writel(INTR_ALL, master->regs + INTR_STATUS); 1567 irq = platform_get_irq(pdev, 0); 1568 ret = devm_request_irq(&pdev->dev, irq, 1569 dw_i3c_master_irq_handler, 0, 1570 dev_name(&pdev->dev), master); 1571 if (ret) 1572 goto err_assert_rst; 1573 1574 platform_set_drvdata(pdev, master); 1575 1576 pm_runtime_set_autosuspend_delay(&pdev->dev, RPM_AUTOSUSPEND_TIMEOUT); 1577 pm_runtime_use_autosuspend(&pdev->dev); 1578 pm_runtime_set_active(&pdev->dev); 1579 pm_runtime_enable(&pdev->dev); 1580 1581 /* Information regarding the FIFOs/QUEUEs depth */ 1582 ret = readl(master->regs + QUEUE_STATUS_LEVEL); 1583 master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret); 1584 1585 ret = readl(master->regs + DATA_BUFFER_STATUS_LEVEL); 1586 master->caps.datafifodepth = DATA_BUFFER_STATUS_LEVEL_TX(ret); 1587 1588 ret = readl(master->regs + DEVICE_ADDR_TABLE_POINTER); 1589 master->datstartaddr = ret; 1590 master->maxdevs = ret >> 16; 1591 master->free_pos = GENMASK(master->maxdevs - 1, 0); 1592 1593 master->quirks = (unsigned long)device_get_match_data(&pdev->dev); 1594 1595 INIT_WORK(&master->hj_work, dw_i3c_hj_work); 1596 ret = i3c_master_register(&master->base, &pdev->dev, 1597 &dw_mipi_i3c_ops, false); 1598 if (ret) 1599 goto err_disable_pm; 1600 1601 return 0; 1602 1603 err_disable_pm: 1604 pm_runtime_disable(&pdev->dev); 1605 pm_runtime_set_suspended(&pdev->dev); 1606 pm_runtime_dont_use_autosuspend(&pdev->dev); 1607 1608 err_assert_rst: 1609 reset_control_assert(master->core_rst); 1610 1611 return ret; 1612 } 1613 EXPORT_SYMBOL_GPL(dw_i3c_common_probe); 1614 1615 void dw_i3c_common_remove(struct dw_i3c_master *master) 1616 { 1617 cancel_work_sync(&master->hj_work); 1618 i3c_master_unregister(&master->base); 1619 1620 pm_runtime_disable(master->dev); 1621 pm_runtime_set_suspended(master->dev); 1622 pm_runtime_dont_use_autosuspend(master->dev); 1623 } 1624 EXPORT_SYMBOL_GPL(dw_i3c_common_remove); 1625 1626 /* base platform implementation */ 1627 1628 static int dw_i3c_probe(struct platform_device *pdev) 1629 { 1630 struct dw_i3c_master *master; 1631 1632 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 1633 if (!master) 1634 return -ENOMEM; 1635 1636 return dw_i3c_common_probe(master, pdev); 1637 } 1638 1639 static void dw_i3c_remove(struct platform_device *pdev) 1640 { 1641 struct dw_i3c_master *master = platform_get_drvdata(pdev); 1642 1643 dw_i3c_common_remove(master); 1644 } 1645 1646 static void dw_i3c_master_restore_addrs(struct dw_i3c_master *master) 1647 { 1648 u32 pos, reg_val; 1649 1650 writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(master->dev_addr), 1651 master->regs + DEVICE_ADDR); 1652 1653 for (pos = 0; pos < master->maxdevs; pos++) { 1654 if (master->free_pos & BIT(pos)) 1655 continue; 1656 1657 if (master->devs[pos].is_i2c_addr) 1658 reg_val = DEV_ADDR_TABLE_LEGACY_I2C_DEV | 1659 DEV_ADDR_TABLE_STATIC_ADDR(master->devs[pos].addr); 1660 else 1661 reg_val = DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr); 1662 1663 writel(reg_val, master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos)); 1664 } 1665 } 1666 1667 static void dw_i3c_master_restore_timing_regs(struct dw_i3c_master *master) 1668 { 1669 /* AMD platform specific OD and PP timings */ 1670 if (master->quirks & AMD_I3C_OD_PP_TIMING) 1671 amd_configure_od_pp_quirk(master); 1672 1673 writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING); 1674 writel(master->bus_free_timing, master->regs + BUS_FREE_TIMING); 1675 writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING); 1676 writel(master->ext_lcnt_timing, master->regs + SCL_EXT_LCNT_TIMING); 1677 1678 if (master->i2c_slv_prsnt) { 1679 writel(master->i2c_fmp_timing, master->regs + SCL_I2C_FMP_TIMING); 1680 writel(master->i2c_fm_timing, master->regs + SCL_I2C_FM_TIMING); 1681 } 1682 } 1683 1684 static int dw_i3c_master_enable_clks(struct dw_i3c_master *master) 1685 { 1686 int ret = 0; 1687 1688 ret = clk_prepare_enable(master->core_clk); 1689 if (ret) 1690 return ret; 1691 1692 ret = clk_prepare_enable(master->pclk); 1693 if (ret) { 1694 clk_disable_unprepare(master->core_clk); 1695 return ret; 1696 } 1697 1698 return 0; 1699 } 1700 1701 static inline void dw_i3c_master_disable_clks(struct dw_i3c_master *master) 1702 { 1703 clk_disable_unprepare(master->pclk); 1704 clk_disable_unprepare(master->core_clk); 1705 } 1706 1707 static int __maybe_unused dw_i3c_master_runtime_suspend(struct device *dev) 1708 { 1709 struct dw_i3c_master *master = dev_get_drvdata(dev); 1710 1711 dw_i3c_master_disable(master); 1712 1713 reset_control_assert(master->core_rst); 1714 dw_i3c_master_disable_clks(master); 1715 pinctrl_pm_select_sleep_state(dev); 1716 return 0; 1717 } 1718 1719 static int __maybe_unused dw_i3c_master_runtime_resume(struct device *dev) 1720 { 1721 struct dw_i3c_master *master = dev_get_drvdata(dev); 1722 1723 pinctrl_pm_select_default_state(dev); 1724 dw_i3c_master_enable_clks(master); 1725 reset_control_deassert(master->core_rst); 1726 1727 dw_i3c_master_set_intr_regs(master); 1728 dw_i3c_master_restore_timing_regs(master); 1729 dw_i3c_master_restore_addrs(master); 1730 1731 dw_i3c_master_enable(master); 1732 return 0; 1733 } 1734 1735 static const struct dev_pm_ops dw_i3c_pm_ops = { 1736 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1737 SET_RUNTIME_PM_OPS(dw_i3c_master_runtime_suspend, dw_i3c_master_runtime_resume, NULL) 1738 }; 1739 1740 static const struct of_device_id dw_i3c_master_of_match[] = { 1741 { .compatible = "snps,dw-i3c-master-1.00a", }, 1742 {}, 1743 }; 1744 MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match); 1745 1746 static const struct acpi_device_id amd_i3c_device_match[] = { 1747 { "AMDI0015", AMD_I3C_OD_PP_TIMING }, 1748 { } 1749 }; 1750 MODULE_DEVICE_TABLE(acpi, amd_i3c_device_match); 1751 1752 static struct platform_driver dw_i3c_driver = { 1753 .probe = dw_i3c_probe, 1754 .remove = dw_i3c_remove, 1755 .driver = { 1756 .name = "dw-i3c-master", 1757 .of_match_table = dw_i3c_master_of_match, 1758 .acpi_match_table = amd_i3c_device_match, 1759 .pm = &dw_i3c_pm_ops, 1760 }, 1761 }; 1762 module_platform_driver(dw_i3c_driver); 1763 1764 MODULE_AUTHOR("Vitor Soares <vitor.soares@synopsys.com>"); 1765 MODULE_DESCRIPTION("DesignWare MIPI I3C driver"); 1766 MODULE_LICENSE("GPL v2"); 1767