1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. 4 * 5 * Author: Vitor Soares <vitor.soares@synopsys.com> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/cleanup.h> 11 #include <linux/clk.h> 12 #include <linux/completion.h> 13 #include <linux/err.h> 14 #include <linux/errno.h> 15 #include <linux/i3c/master.h> 16 #include <linux/interrupt.h> 17 #include <linux/ioport.h> 18 #include <linux/iopoll.h> 19 #include <linux/list.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/pinctrl/consumer.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/reset.h> 26 #include <linux/slab.h> 27 28 #include "../internals.h" 29 #include "dw-i3c-master.h" 30 31 #define DEVICE_CTRL 0x0 32 #define DEV_CTRL_ENABLE BIT(31) 33 #define DEV_CTRL_RESUME BIT(30) 34 #define DEV_CTRL_HOT_JOIN_NACK BIT(8) 35 #define DEV_CTRL_I2C_SLAVE_PRESENT BIT(7) 36 37 #define DEVICE_ADDR 0x4 38 #define DEV_ADDR_DYNAMIC_ADDR_VALID BIT(31) 39 #define DEV_ADDR_DYNAMIC(x) (((x) << 16) & GENMASK(22, 16)) 40 41 #define HW_CAPABILITY 0x8 42 #define COMMAND_QUEUE_PORT 0xc 43 #define COMMAND_PORT_TOC BIT(30) 44 #define COMMAND_PORT_READ_TRANSFER BIT(28) 45 #define COMMAND_PORT_SDAP BIT(27) 46 #define COMMAND_PORT_ROC BIT(26) 47 #define COMMAND_PORT_SPEED(x) (((x) << 21) & GENMASK(23, 21)) 48 #define COMMAND_PORT_DEV_INDEX(x) (((x) << 16) & GENMASK(20, 16)) 49 #define COMMAND_PORT_CP BIT(15) 50 #define COMMAND_PORT_CMD(x) (((x) << 7) & GENMASK(14, 7)) 51 #define COMMAND_PORT_TID(x) (((x) << 3) & GENMASK(6, 3)) 52 53 #define COMMAND_PORT_ARG_DATA_LEN(x) (((x) << 16) & GENMASK(31, 16)) 54 #define COMMAND_PORT_ARG_DATA_LEN_MAX 65536 55 #define COMMAND_PORT_TRANSFER_ARG 0x01 56 57 #define COMMAND_PORT_SDA_DATA_BYTE_3(x) (((x) << 24) & GENMASK(31, 24)) 58 #define COMMAND_PORT_SDA_DATA_BYTE_2(x) (((x) << 16) & GENMASK(23, 16)) 59 #define COMMAND_PORT_SDA_DATA_BYTE_1(x) (((x) << 8) & GENMASK(15, 8)) 60 #define COMMAND_PORT_SDA_BYTE_STRB_3 BIT(5) 61 #define COMMAND_PORT_SDA_BYTE_STRB_2 BIT(4) 62 #define COMMAND_PORT_SDA_BYTE_STRB_1 BIT(3) 63 #define COMMAND_PORT_SHORT_DATA_ARG 0x02 64 65 #define COMMAND_PORT_DEV_COUNT(x) (((x) << 21) & GENMASK(25, 21)) 66 #define COMMAND_PORT_ADDR_ASSGN_CMD 0x03 67 68 #define RESPONSE_QUEUE_PORT 0x10 69 #define RESPONSE_PORT_ERR_STATUS(x) (((x) & GENMASK(31, 28)) >> 28) 70 #define RESPONSE_NO_ERROR 0 71 #define RESPONSE_ERROR_CRC 1 72 #define RESPONSE_ERROR_PARITY 2 73 #define RESPONSE_ERROR_FRAME 3 74 #define RESPONSE_ERROR_IBA_NACK 4 75 #define RESPONSE_ERROR_ADDRESS_NACK 5 76 #define RESPONSE_ERROR_OVER_UNDER_FLOW 6 77 #define RESPONSE_ERROR_TRANSF_ABORT 8 78 #define RESPONSE_ERROR_I2C_W_NACK_ERR 9 79 #define RESPONSE_PORT_TID(x) (((x) & GENMASK(27, 24)) >> 24) 80 #define RESPONSE_PORT_DATA_LEN(x) ((x) & GENMASK(15, 0)) 81 82 #define RX_TX_DATA_PORT 0x14 83 #define IBI_QUEUE_STATUS 0x18 84 #define IBI_QUEUE_STATUS_IBI_ID(x) (((x) & GENMASK(15, 8)) >> 8) 85 #define IBI_QUEUE_STATUS_DATA_LEN(x) ((x) & GENMASK(7, 0)) 86 #define IBI_QUEUE_IBI_ADDR(x) (IBI_QUEUE_STATUS_IBI_ID(x) >> 1) 87 #define IBI_QUEUE_IBI_RNW(x) (IBI_QUEUE_STATUS_IBI_ID(x) & BIT(0)) 88 #define IBI_TYPE_MR(x) \ 89 ((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x)) 90 #define IBI_TYPE_HJ(x) \ 91 ((IBI_QUEUE_IBI_ADDR(x) == I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x)) 92 #define IBI_TYPE_SIRQ(x) \ 93 ((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && IBI_QUEUE_IBI_RNW(x)) 94 95 #define QUEUE_THLD_CTRL 0x1c 96 #define QUEUE_THLD_CTRL_IBI_STAT_MASK GENMASK(31, 24) 97 #define QUEUE_THLD_CTRL_IBI_STAT(x) (((x) - 1) << 24) 98 #define QUEUE_THLD_CTRL_IBI_DATA_MASK GENMASK(20, 16) 99 #define QUEUE_THLD_CTRL_IBI_DATA(x) ((x) << 16) 100 #define QUEUE_THLD_CTRL_RESP_BUF_MASK GENMASK(15, 8) 101 #define QUEUE_THLD_CTRL_RESP_BUF(x) (((x) - 1) << 8) 102 103 #define DATA_BUFFER_THLD_CTRL 0x20 104 #define DATA_BUFFER_THLD_CTRL_RX_BUF GENMASK(11, 8) 105 106 #define IBI_QUEUE_CTRL 0x24 107 #define IBI_MR_REQ_REJECT 0x2C 108 #define IBI_SIR_REQ_REJECT 0x30 109 #define IBI_REQ_REJECT_ALL GENMASK(31, 0) 110 111 #define RESET_CTRL 0x34 112 #define RESET_CTRL_IBI_QUEUE BIT(5) 113 #define RESET_CTRL_RX_FIFO BIT(4) 114 #define RESET_CTRL_TX_FIFO BIT(3) 115 #define RESET_CTRL_RESP_QUEUE BIT(2) 116 #define RESET_CTRL_CMD_QUEUE BIT(1) 117 #define RESET_CTRL_SOFT BIT(0) 118 119 #define SLV_EVENT_CTRL 0x38 120 #define INTR_STATUS 0x3c 121 #define INTR_STATUS_EN 0x40 122 #define INTR_SIGNAL_EN 0x44 123 #define INTR_FORCE 0x48 124 #define INTR_BUSOWNER_UPDATE_STAT BIT(13) 125 #define INTR_IBI_UPDATED_STAT BIT(12) 126 #define INTR_READ_REQ_RECV_STAT BIT(11) 127 #define INTR_DEFSLV_STAT BIT(10) 128 #define INTR_TRANSFER_ERR_STAT BIT(9) 129 #define INTR_DYN_ADDR_ASSGN_STAT BIT(8) 130 #define INTR_CCC_UPDATED_STAT BIT(6) 131 #define INTR_TRANSFER_ABORT_STAT BIT(5) 132 #define INTR_RESP_READY_STAT BIT(4) 133 #define INTR_CMD_QUEUE_READY_STAT BIT(3) 134 #define INTR_IBI_THLD_STAT BIT(2) 135 #define INTR_RX_THLD_STAT BIT(1) 136 #define INTR_TX_THLD_STAT BIT(0) 137 #define INTR_ALL (INTR_BUSOWNER_UPDATE_STAT | \ 138 INTR_IBI_UPDATED_STAT | \ 139 INTR_READ_REQ_RECV_STAT | \ 140 INTR_DEFSLV_STAT | \ 141 INTR_TRANSFER_ERR_STAT | \ 142 INTR_DYN_ADDR_ASSGN_STAT | \ 143 INTR_CCC_UPDATED_STAT | \ 144 INTR_TRANSFER_ABORT_STAT | \ 145 INTR_RESP_READY_STAT | \ 146 INTR_CMD_QUEUE_READY_STAT | \ 147 INTR_IBI_THLD_STAT | \ 148 INTR_TX_THLD_STAT | \ 149 INTR_RX_THLD_STAT) 150 151 #define INTR_MASTER_MASK (INTR_TRANSFER_ERR_STAT | \ 152 INTR_RESP_READY_STAT) 153 154 #define QUEUE_STATUS_LEVEL 0x4c 155 #define QUEUE_STATUS_IBI_STATUS_CNT(x) (((x) & GENMASK(28, 24)) >> 24) 156 #define QUEUE_STATUS_IBI_BUF_BLR(x) (((x) & GENMASK(23, 16)) >> 16) 157 #define QUEUE_STATUS_LEVEL_RESP(x) (((x) & GENMASK(15, 8)) >> 8) 158 #define QUEUE_STATUS_LEVEL_CMD(x) ((x) & GENMASK(7, 0)) 159 160 #define DATA_BUFFER_STATUS_LEVEL 0x50 161 #define DATA_BUFFER_STATUS_LEVEL_TX(x) ((x) & GENMASK(7, 0)) 162 163 #define PRESENT_STATE 0x54 164 #define CCC_DEVICE_STATUS 0x58 165 #define DEVICE_ADDR_TABLE_POINTER 0x5c 166 #define DEVICE_ADDR_TABLE_DEPTH(x) (((x) & GENMASK(31, 16)) >> 16) 167 #define DEVICE_ADDR_TABLE_ADDR(x) ((x) & GENMASK(7, 0)) 168 169 #define DEV_CHAR_TABLE_POINTER 0x60 170 #define VENDOR_SPECIFIC_REG_POINTER 0x6c 171 #define SLV_PID_VALUE 0x74 172 #define SLV_CHAR_CTRL 0x78 173 #define SLV_MAX_LEN 0x7c 174 #define MAX_READ_TURNAROUND 0x80 175 #define MAX_DATA_SPEED 0x84 176 #define SLV_DEBUG_STATUS 0x88 177 #define SLV_INTR_REQ 0x8c 178 #define DEVICE_CTRL_EXTENDED 0xb0 179 #define SCL_I3C_OD_TIMING 0xb4 180 #define SCL_I3C_PP_TIMING 0xb8 181 #define SCL_I3C_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16)) 182 #define SCL_I3C_TIMING_LCNT(x) ((x) & GENMASK(7, 0)) 183 #define SCL_I3C_TIMING_CNT_MIN 5 184 185 #define SCL_I2C_FM_TIMING 0xbc 186 #define SCL_I2C_FM_TIMING_HCNT(x) (((x) << 16) & GENMASK(31, 16)) 187 #define SCL_I2C_FM_TIMING_LCNT(x) ((x) & GENMASK(15, 0)) 188 189 #define SCL_I2C_FMP_TIMING 0xc0 190 #define SCL_I2C_FMP_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16)) 191 #define SCL_I2C_FMP_TIMING_LCNT(x) ((x) & GENMASK(15, 0)) 192 193 #define SCL_EXT_LCNT_TIMING 0xc8 194 #define SCL_EXT_LCNT_4(x) (((x) << 24) & GENMASK(31, 24)) 195 #define SCL_EXT_LCNT_3(x) (((x) << 16) & GENMASK(23, 16)) 196 #define SCL_EXT_LCNT_2(x) (((x) << 8) & GENMASK(15, 8)) 197 #define SCL_EXT_LCNT_1(x) ((x) & GENMASK(7, 0)) 198 199 #define SCL_EXT_TERMN_LCNT_TIMING 0xcc 200 #define BUS_FREE_TIMING 0xd4 201 #define BUS_I3C_MST_FREE(x) ((x) & GENMASK(15, 0)) 202 203 #define BUS_IDLE_TIMING 0xd8 204 #define I3C_VER_ID 0xe0 205 #define I3C_VER_TYPE 0xe4 206 #define EXTENDED_CAPABILITY 0xe8 207 #define SLAVE_CONFIG 0xec 208 209 #define DYN_ADDR_LO_MASK GENMASK(4, 0) 210 #define DYN_ADDR_HI_MASK GENMASK(6, 5) 211 #define IBI_SIR_BIT_MOD 32 /* 32-bit vector */ 212 213 #define DW_I3C_DEV_NACK_RETRY_CNT_MAX 0x3 214 #define DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK GENMASK(30, 29) 215 #define DEV_ADDR_TABLE_DYNAMIC_MASK GENMASK(23, 16) 216 #define DEV_ADDR_TABLE_STATIC_MASK GENMASK(6, 0) 217 #define DEV_ADDR_TABLE_IBI_MDB BIT(12) 218 #define DEV_ADDR_TABLE_SIR_REJECT BIT(13) 219 #define DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(x) \ 220 FIELD_PREP(DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK, (x)) 221 #define DEV_ADDR_TABLE_LEGACY_I2C_DEV BIT(31) 222 #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) FIELD_PREP(DEV_ADDR_TABLE_DYNAMIC_MASK, x) 223 #define DEV_ADDR_TABLE_STATIC_ADDR(x) FIELD_PREP(DEV_ADDR_TABLE_STATIC_MASK, x) 224 #define DEV_ADDR_TABLE_LOC(start, idx) ((start) + ((idx) << 2)) 225 #define DEV_ADDR_TABLE_GET_DYNAMIC_ADDR(x) FIELD_GET(DEV_ADDR_TABLE_DYNAMIC_MASK, x) 226 227 #define I3C_BUS_SDR1_SCL_RATE 8000000 228 #define I3C_BUS_SDR2_SCL_RATE 6000000 229 #define I3C_BUS_SDR3_SCL_RATE 4000000 230 #define I3C_BUS_SDR4_SCL_RATE 2000000 231 #define I3C_BUS_I2C_FM_TLOW_MIN_NS 1300 232 #define I3C_BUS_I2C_FMP_TLOW_MIN_NS 500 233 #define I3C_BUS_THIGH_MAX_NS 41 234 235 #define XFER_TIMEOUT (msecs_to_jiffies(1000)) 236 #define RPM_AUTOSUSPEND_TIMEOUT 1000 /* ms */ 237 238 /* Timing values to configure 12.5MHz frequency */ 239 #define AMD_I3C_OD_TIMING 0x4C007C 240 #define AMD_I3C_PP_TIMING 0x8001A 241 242 /* List of quirks */ 243 #define AMD_I3C_OD_PP_TIMING BIT(1) 244 #define DW_I3C_DISABLE_RUNTIME_PM_QUIRK BIT(2) 245 #define DW_I3C_ACPI_SKIP_CLK_RST BIT(3) 246 247 struct dw_i3c_cmd { 248 u32 cmd_lo; 249 u32 cmd_hi; 250 u16 tx_len; 251 u16 rx_len; 252 u8 error; 253 const void *tx_buf; 254 void *rx_buf; 255 }; 256 257 struct dw_i3c_xfer { 258 struct list_head node; 259 struct completion comp; 260 int ret; 261 unsigned int ncmds; 262 struct dw_i3c_cmd cmds[] __counted_by(ncmds); 263 }; 264 265 struct dw_i3c_i2c_dev_data { 266 u8 index; 267 struct i3c_generic_ibi_pool *ibi_pool; 268 }; 269 270 struct dw_i3c_drvdata { 271 u32 flags; 272 }; 273 274 static inline u32 get_ibi_sir_bit_index(u8 addr) 275 { 276 u32 lo = FIELD_GET(DYN_ADDR_LO_MASK, addr); 277 u32 hi = FIELD_GET(DYN_ADDR_HI_MASK, addr); 278 279 return (lo + hi) % IBI_SIR_BIT_MOD; 280 } 281 282 static bool dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m, 283 const struct i3c_ccc_cmd *cmd) 284 { 285 if (cmd->ndests > 1) 286 return false; 287 288 switch (cmd->id) { 289 case I3C_CCC_ENEC(true): 290 case I3C_CCC_ENEC(false): 291 case I3C_CCC_DISEC(true): 292 case I3C_CCC_DISEC(false): 293 case I3C_CCC_ENTAS(0, true): 294 case I3C_CCC_ENTAS(0, false): 295 case I3C_CCC_RSTDAA(true): 296 case I3C_CCC_RSTDAA(false): 297 case I3C_CCC_ENTDAA: 298 case I3C_CCC_SETMWL(true): 299 case I3C_CCC_SETMWL(false): 300 case I3C_CCC_SETMRL(true): 301 case I3C_CCC_SETMRL(false): 302 case I3C_CCC_ENTHDR(0): 303 case I3C_CCC_SETDASA: 304 case I3C_CCC_SETNEWDA: 305 case I3C_CCC_GETMWL: 306 case I3C_CCC_GETMRL: 307 case I3C_CCC_GETPID: 308 case I3C_CCC_GETBCR: 309 case I3C_CCC_GETDCR: 310 case I3C_CCC_GETSTATUS: 311 case I3C_CCC_GETMXDS: 312 case I3C_CCC_GETHDRCAP: 313 case I3C_CCC_SETAASA: 314 case I3C_CCC_VENDOR(0, true): /* SETHID */ 315 return true; 316 default: 317 return false; 318 } 319 } 320 321 static inline struct dw_i3c_master * 322 to_dw_i3c_master(struct i3c_master_controller *master) 323 { 324 return container_of(master, struct dw_i3c_master, base); 325 } 326 327 static void dw_i3c_master_disable(struct dw_i3c_master *master) 328 { 329 writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_ENABLE, 330 master->regs + DEVICE_CTRL); 331 } 332 333 static void dw_i3c_master_enable(struct dw_i3c_master *master) 334 { 335 u32 dev_ctrl; 336 337 dev_ctrl = readl(master->regs + DEVICE_CTRL); 338 /* For now don't support Hot-Join */ 339 dev_ctrl |= DEV_CTRL_HOT_JOIN_NACK; 340 if (master->i2c_slv_prsnt) 341 dev_ctrl |= DEV_CTRL_I2C_SLAVE_PRESENT; 342 writel(dev_ctrl | DEV_CTRL_ENABLE, 343 master->regs + DEVICE_CTRL); 344 } 345 346 static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr) 347 { 348 int pos; 349 350 for (pos = 0; pos < master->maxdevs; pos++) { 351 if (addr == master->devs[pos].addr) 352 return pos; 353 } 354 355 return -EINVAL; 356 } 357 358 static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master) 359 { 360 if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0))) 361 return -ENOSPC; 362 363 return ffs(master->free_pos) - 1; 364 } 365 366 static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master, 367 const u8 *bytes, int nbytes) 368 { 369 i3c_writel_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes); 370 } 371 372 static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master, 373 u8 *bytes, int nbytes) 374 { 375 i3c_readl_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes); 376 } 377 378 static void dw_i3c_master_read_ibi_fifo(struct dw_i3c_master *master, 379 u8 *bytes, int nbytes) 380 { 381 i3c_readl_fifo(master->regs + IBI_QUEUE_STATUS, bytes, nbytes); 382 } 383 384 static struct dw_i3c_xfer * 385 dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds) 386 { 387 struct dw_i3c_xfer *xfer; 388 389 xfer = kzalloc_flex(*xfer, cmds, ncmds); 390 if (!xfer) 391 return NULL; 392 393 INIT_LIST_HEAD(&xfer->node); 394 xfer->ncmds = ncmds; 395 xfer->ret = -ETIMEDOUT; 396 397 return xfer; 398 } 399 400 static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master) 401 { 402 struct dw_i3c_xfer *xfer = master->xferqueue.cur; 403 unsigned int i; 404 u32 thld_ctrl; 405 406 if (!xfer) 407 return; 408 409 for (i = 0; i < xfer->ncmds; i++) { 410 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 411 412 dw_i3c_master_wr_tx_fifo(master, cmd->tx_buf, cmd->tx_len); 413 } 414 415 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL); 416 thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK; 417 thld_ctrl |= QUEUE_THLD_CTRL_RESP_BUF(xfer->ncmds); 418 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); 419 420 for (i = 0; i < xfer->ncmds; i++) { 421 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 422 423 writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT); 424 writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT); 425 } 426 } 427 428 static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master, 429 struct dw_i3c_xfer *xfer) 430 { 431 init_completion(&xfer->comp); 432 guard(spinlock_irqsave)(&master->xferqueue.lock); 433 if (master->xferqueue.cur) { 434 list_add_tail(&xfer->node, &master->xferqueue.list); 435 } else { 436 master->xferqueue.cur = xfer; 437 dw_i3c_master_start_xfer_locked(master); 438 } 439 } 440 441 static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master, 442 struct dw_i3c_xfer *xfer) 443 { 444 if (master->xferqueue.cur == xfer) { 445 u32 status; 446 447 master->xferqueue.cur = NULL; 448 449 writel(RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO | 450 RESET_CTRL_RESP_QUEUE | RESET_CTRL_CMD_QUEUE, 451 master->regs + RESET_CTRL); 452 453 readl_poll_timeout_atomic(master->regs + RESET_CTRL, status, 454 !status, 10, 1000000); 455 } else { 456 list_del_init(&xfer->node); 457 } 458 } 459 460 static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master, 461 struct dw_i3c_xfer *xfer) 462 { 463 guard(spinlock_irqsave)(&master->xferqueue.lock); 464 dw_i3c_master_dequeue_xfer_locked(master, xfer); 465 } 466 467 static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr) 468 { 469 struct dw_i3c_xfer *xfer = master->xferqueue.cur; 470 int i, ret = 0; 471 u32 nresp; 472 473 if (!xfer) 474 return; 475 476 nresp = readl(master->regs + QUEUE_STATUS_LEVEL); 477 nresp = QUEUE_STATUS_LEVEL_RESP(nresp); 478 479 for (i = 0; i < nresp; i++) { 480 struct dw_i3c_cmd *cmd; 481 u32 resp; 482 483 resp = readl(master->regs + RESPONSE_QUEUE_PORT); 484 485 cmd = &xfer->cmds[RESPONSE_PORT_TID(resp)]; 486 cmd->rx_len = RESPONSE_PORT_DATA_LEN(resp); 487 cmd->error = RESPONSE_PORT_ERR_STATUS(resp); 488 if (cmd->rx_len && !cmd->error) 489 dw_i3c_master_read_rx_fifo(master, cmd->rx_buf, 490 cmd->rx_len); 491 } 492 493 for (i = 0; i < nresp; i++) { 494 switch (xfer->cmds[i].error) { 495 case RESPONSE_NO_ERROR: 496 break; 497 case RESPONSE_ERROR_PARITY: 498 case RESPONSE_ERROR_IBA_NACK: 499 case RESPONSE_ERROR_ADDRESS_NACK: 500 case RESPONSE_ERROR_TRANSF_ABORT: 501 case RESPONSE_ERROR_CRC: 502 case RESPONSE_ERROR_FRAME: 503 ret = -EIO; 504 break; 505 case RESPONSE_ERROR_OVER_UNDER_FLOW: 506 ret = -ENOSPC; 507 break; 508 case RESPONSE_ERROR_I2C_W_NACK_ERR: 509 default: 510 ret = -EINVAL; 511 break; 512 } 513 } 514 515 xfer->ret = ret; 516 complete(&xfer->comp); 517 518 if (ret < 0) { 519 dw_i3c_master_dequeue_xfer_locked(master, xfer); 520 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME, 521 master->regs + DEVICE_CTRL); 522 } 523 524 xfer = list_first_entry_or_null(&master->xferqueue.list, 525 struct dw_i3c_xfer, 526 node); 527 if (xfer) 528 list_del_init(&xfer->node); 529 530 master->xferqueue.cur = xfer; 531 dw_i3c_master_start_xfer_locked(master); 532 } 533 534 static void dw_i3c_master_set_intr_regs(struct dw_i3c_master *master) 535 { 536 u32 thld_ctrl; 537 538 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL); 539 thld_ctrl &= ~(QUEUE_THLD_CTRL_RESP_BUF_MASK | 540 QUEUE_THLD_CTRL_IBI_STAT_MASK | 541 QUEUE_THLD_CTRL_IBI_DATA_MASK); 542 thld_ctrl |= QUEUE_THLD_CTRL_IBI_STAT(1) | 543 QUEUE_THLD_CTRL_IBI_DATA(31); 544 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); 545 546 thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL); 547 thld_ctrl &= ~DATA_BUFFER_THLD_CTRL_RX_BUF; 548 writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL); 549 550 writel(INTR_ALL, master->regs + INTR_STATUS); 551 writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN); 552 writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN); 553 554 master->sir_rej_mask = IBI_REQ_REJECT_ALL; 555 writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT); 556 557 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT); 558 } 559 560 static unsigned long dw_i3c_master_get_core_rate(struct dw_i3c_master *master) 561 { 562 unsigned int core_rate_prop; 563 564 if (master->core_clk) 565 return clk_get_rate(master->core_clk); 566 567 if (device_property_read_u32(master->dev, "clock-frequency", &core_rate_prop)) { 568 dev_err(master->dev, "missing clock-frequency property\n"); 569 return 0; 570 } 571 572 return core_rate_prop; 573 } 574 575 static void amd_configure_od_pp_quirk(struct dw_i3c_master *master) 576 { 577 master->i3c_od_timing = AMD_I3C_OD_TIMING; 578 master->i3c_od_timing_normal = AMD_I3C_OD_TIMING; 579 master->i3c_pp_timing = AMD_I3C_PP_TIMING; 580 } 581 582 static int dw_i3c_clk_cfg(struct dw_i3c_master *master) 583 { 584 unsigned long core_rate, core_period; 585 u32 scl_timing; 586 u8 hcnt, lcnt; 587 588 core_rate = dw_i3c_master_get_core_rate(master); 589 if (!core_rate) 590 return -EINVAL; 591 592 core_period = DIV_ROUND_UP(1000000000, core_rate); 593 594 hcnt = DIV_ROUND_UP(I3C_BUS_THIGH_MAX_NS, core_period) - 1; 595 if (hcnt < SCL_I3C_TIMING_CNT_MIN) 596 hcnt = SCL_I3C_TIMING_CNT_MIN; 597 598 lcnt = DIV_ROUND_UP(core_rate, master->base.bus.scl_rate.i3c) - hcnt; 599 if (lcnt < SCL_I3C_TIMING_CNT_MIN) 600 lcnt = SCL_I3C_TIMING_CNT_MIN; 601 602 scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt); 603 writel(scl_timing, master->regs + SCL_I3C_PP_TIMING); 604 master->i3c_pp_timing = scl_timing; 605 606 /* 607 * In pure i3c mode, MST_FREE represents tCAS. In shared mode, this 608 * will be set up by dw_i2c_clk_cfg as tLOW. 609 */ 610 if (master->base.bus.mode == I3C_BUS_MODE_PURE) { 611 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); 612 master->bus_free_timing = BUS_I3C_MST_FREE(lcnt); 613 } 614 615 lcnt = max_t(u8, 616 DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period), lcnt); 617 scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt); 618 writel(scl_timing, master->regs + SCL_I3C_OD_TIMING); 619 master->i3c_od_timing = scl_timing; 620 master->i3c_od_timing_normal = scl_timing; 621 622 /* 623 * AMD legacy platforms need fixed OD/PP timings. Cache them as the 624 * normal OD baseline so set_speed(NORMAL) restores AMD values, and 625 * set_speed(SLOW) can stretch HCNT while keeping the AMD LCNT. 626 */ 627 if (master->quirks & AMD_I3C_OD_PP_TIMING) { 628 amd_configure_od_pp_quirk(master); 629 writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING); 630 writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING); 631 } 632 633 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR1_SCL_RATE) - hcnt; 634 scl_timing = SCL_EXT_LCNT_1(lcnt); 635 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR2_SCL_RATE) - hcnt; 636 scl_timing |= SCL_EXT_LCNT_2(lcnt); 637 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR3_SCL_RATE) - hcnt; 638 scl_timing |= SCL_EXT_LCNT_3(lcnt); 639 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR4_SCL_RATE) - hcnt; 640 scl_timing |= SCL_EXT_LCNT_4(lcnt); 641 writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING); 642 master->ext_lcnt_timing = scl_timing; 643 644 return 0; 645 } 646 647 static int dw_i2c_clk_cfg(struct dw_i3c_master *master) 648 { 649 unsigned long core_rate, core_period; 650 u16 hcnt, lcnt; 651 u32 scl_timing; 652 653 core_rate = dw_i3c_master_get_core_rate(master); 654 if (!core_rate) 655 return -EINVAL; 656 657 core_period = DIV_ROUND_UP(1000000000, core_rate); 658 659 lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FMP_TLOW_MIN_NS, core_period); 660 hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_PLUS_SCL_MAX_RATE) - lcnt; 661 scl_timing = SCL_I2C_FMP_TIMING_HCNT(hcnt) | 662 SCL_I2C_FMP_TIMING_LCNT(lcnt); 663 writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING); 664 master->i2c_fmp_timing = scl_timing; 665 666 lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FM_TLOW_MIN_NS, core_period); 667 hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_SCL_MAX_RATE) - lcnt; 668 scl_timing = SCL_I2C_FM_TIMING_HCNT(hcnt) | 669 SCL_I2C_FM_TIMING_LCNT(lcnt); 670 writel(scl_timing, master->regs + SCL_I2C_FM_TIMING); 671 master->i2c_fm_timing = scl_timing; 672 673 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); 674 master->bus_free_timing = BUS_I3C_MST_FREE(lcnt); 675 676 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT, 677 master->regs + DEVICE_CTRL); 678 master->i2c_slv_prsnt = true; 679 680 return 0; 681 } 682 683 static int dw_i3c_master_bus_init(struct i3c_master_controller *m) 684 { 685 struct dw_i3c_master *master = to_dw_i3c_master(m); 686 struct i3c_bus *bus = i3c_master_get_bus(m); 687 struct i3c_device_info info = { }; 688 int ret; 689 690 ret = pm_runtime_resume_and_get(master->dev); 691 if (ret < 0) { 692 dev_err(master->dev, 693 "<%s> cannot resume i3c bus master, err: %d\n", 694 __func__, ret); 695 return ret; 696 } 697 698 ret = master->platform_ops->init(master); 699 if (ret) 700 goto rpm_out; 701 702 switch (bus->mode) { 703 case I3C_BUS_MODE_MIXED_FAST: 704 case I3C_BUS_MODE_MIXED_LIMITED: 705 ret = dw_i2c_clk_cfg(master); 706 if (ret) 707 goto rpm_out; 708 fallthrough; 709 case I3C_BUS_MODE_PURE: 710 ret = dw_i3c_clk_cfg(master); 711 if (ret) 712 goto rpm_out; 713 break; 714 default: 715 ret = -EINVAL; 716 goto rpm_out; 717 } 718 719 ret = i3c_master_get_free_addr(m, 0); 720 if (ret < 0) 721 goto rpm_out; 722 723 writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret), 724 master->regs + DEVICE_ADDR); 725 master->dev_addr = ret; 726 memset(&info, 0, sizeof(info)); 727 info.dyn_addr = ret; 728 729 ret = i3c_master_set_info(&master->base, &info); 730 if (ret) 731 goto rpm_out; 732 733 dw_i3c_master_set_intr_regs(master); 734 dw_i3c_master_enable(master); 735 736 rpm_out: 737 pm_runtime_put_autosuspend(master->dev); 738 return ret; 739 } 740 741 static void dw_i3c_master_bus_cleanup(struct i3c_master_controller *m) 742 { 743 struct dw_i3c_master *master = to_dw_i3c_master(m); 744 745 dw_i3c_master_disable(master); 746 } 747 748 static enum i3c_error_code dw_i3c_ccc_map_err(u8 dw_err) 749 { 750 switch (dw_err) { 751 case RESPONSE_ERROR_IBA_NACK: 752 return I3C_ERROR_M2; 753 case RESPONSE_ERROR_CRC: 754 case RESPONSE_ERROR_PARITY: 755 case RESPONSE_ERROR_FRAME: 756 case RESPONSE_ERROR_TRANSF_ABORT: 757 return I3C_ERROR_M0; 758 default: 759 return I3C_ERROR_UNKNOWN; 760 } 761 } 762 763 static int dw_i3c_ccc_set(struct dw_i3c_master *master, 764 struct i3c_ccc_cmd *ccc) 765 { 766 struct dw_i3c_cmd *cmd; 767 int ret, pos = 0; 768 769 ccc->err = I3C_ERROR_UNKNOWN; 770 771 if (ccc->id & I3C_CCC_DIRECT) { 772 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); 773 if (pos < 0) 774 return pos; 775 } 776 777 struct dw_i3c_xfer *xfer __free(kfree) = dw_i3c_master_alloc_xfer(master, 1); 778 if (!xfer) 779 return -ENOMEM; 780 781 cmd = xfer->cmds; 782 cmd->tx_buf = ccc->dests[0].payload.data; 783 cmd->tx_len = ccc->dests[0].payload.len; 784 785 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) | 786 COMMAND_PORT_TRANSFER_ARG; 787 788 cmd->cmd_lo = COMMAND_PORT_CP | 789 COMMAND_PORT_DEV_INDEX(pos) | 790 COMMAND_PORT_CMD(ccc->id) | 791 COMMAND_PORT_TOC | 792 COMMAND_PORT_ROC; 793 794 dw_i3c_master_enqueue_xfer(master, xfer); 795 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 796 dw_i3c_master_dequeue_xfer(master, xfer); 797 798 ret = xfer->ret; 799 cmd = &xfer->cmds[0]; 800 ccc->err = dw_i3c_ccc_map_err(cmd->error); 801 802 return ret; 803 } 804 805 static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc) 806 { 807 struct dw_i3c_cmd *cmd; 808 int ret, pos; 809 810 ccc->err = I3C_ERROR_UNKNOWN; 811 812 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); 813 if (pos < 0) 814 return pos; 815 816 struct dw_i3c_xfer *xfer __free(kfree) = dw_i3c_master_alloc_xfer(master, 1); 817 if (!xfer) 818 return -ENOMEM; 819 820 cmd = xfer->cmds; 821 cmd->rx_buf = ccc->dests[0].payload.data; 822 cmd->rx_len = ccc->dests[0].payload.len; 823 824 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) | 825 COMMAND_PORT_TRANSFER_ARG; 826 827 cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER | 828 COMMAND_PORT_CP | 829 COMMAND_PORT_DEV_INDEX(pos) | 830 COMMAND_PORT_CMD(ccc->id) | 831 COMMAND_PORT_TOC | 832 COMMAND_PORT_ROC; 833 834 dw_i3c_master_enqueue_xfer(master, xfer); 835 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 836 dw_i3c_master_dequeue_xfer(master, xfer); 837 838 ret = xfer->ret; 839 cmd = &xfer->cmds[0]; 840 ccc->err = dw_i3c_ccc_map_err(cmd->error); 841 if (!ret) 842 ccc->dests[0].payload.actual_len = cmd->rx_len; 843 844 return ret; 845 } 846 847 static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, 848 struct i3c_ccc_cmd *ccc) 849 { 850 struct dw_i3c_master *master = to_dw_i3c_master(m); 851 int ret = 0; 852 853 if (ccc->id == I3C_CCC_ENTDAA) 854 return -EINVAL; 855 856 ret = pm_runtime_resume_and_get(master->dev); 857 if (ret < 0) { 858 dev_err(master->dev, 859 "<%s> cannot resume i3c bus master, err: %d\n", 860 __func__, ret); 861 return ret; 862 } 863 864 if (ccc->rnw) 865 ret = dw_i3c_ccc_get(master, ccc); 866 else 867 ret = dw_i3c_ccc_set(master, ccc); 868 869 pm_runtime_put_autosuspend(master->dev); 870 return ret; 871 } 872 873 static int dw_i3c_master_daa(struct i3c_master_controller *m) 874 { 875 struct dw_i3c_master *master = to_dw_i3c_master(m); 876 struct dw_i3c_cmd *cmd; 877 u32 olddevs, newdevs; 878 u8 last_addr = 0; 879 int ret, pos; 880 881 struct dw_i3c_xfer *xfer __free(kfree) = dw_i3c_master_alloc_xfer(master, 1); 882 if (!xfer) 883 return -ENOMEM; 884 885 ret = pm_runtime_resume_and_get(master->dev); 886 if (ret < 0) { 887 dev_err(master->dev, 888 "<%s> cannot resume i3c bus master, err: %d\n", 889 __func__, ret); 890 return ret; 891 } 892 893 olddevs = ~(master->free_pos); 894 895 /* Prepare DAT before launching DAA. */ 896 for (pos = 0; pos < master->maxdevs; pos++) { 897 if (olddevs & BIT(pos)) 898 continue; 899 900 ret = i3c_master_get_free_addr(m, last_addr + 1); 901 if (ret < 0) { 902 ret = -ENOSPC; 903 goto rpm_out; 904 } 905 906 master->devs[pos].addr = ret; 907 last_addr = ret; 908 909 ret |= parity8(ret) ? 0 : BIT(7); 910 911 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(ret), 912 master->regs + 913 DEV_ADDR_TABLE_LOC(master->datstartaddr, pos)); 914 915 ret = 0; 916 } 917 918 pos = dw_i3c_master_get_free_pos(master); 919 if (pos < 0) { 920 ret = pos; 921 goto rpm_out; 922 } 923 cmd = &xfer->cmds[0]; 924 cmd->rx_len = master->maxdevs; 925 cmd->cmd_hi = COMMAND_PORT_TRANSFER_ARG; 926 cmd->cmd_lo = COMMAND_PORT_DEV_COUNT(master->maxdevs - pos) | 927 COMMAND_PORT_DEV_INDEX(pos) | 928 COMMAND_PORT_CMD(I3C_CCC_ENTDAA) | 929 COMMAND_PORT_ADDR_ASSGN_CMD | 930 COMMAND_PORT_TOC | 931 COMMAND_PORT_ROC; 932 933 dw_i3c_master_enqueue_xfer(master, xfer); 934 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 935 dw_i3c_master_dequeue_xfer(master, xfer); 936 937 /* 938 * cmd->rx_len holds the number of addresses ENTDAA left unassigned. 939 * On an empty bus rx_len == maxdevs, so avoid GENMASK(-1, 0). 940 */ 941 if (cmd->rx_len >= master->maxdevs) 942 newdevs = 0; 943 else 944 newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0); 945 946 newdevs &= ~olddevs; 947 948 for (pos = 0; pos < master->maxdevs; pos++) { 949 if (newdevs & BIT(pos)) 950 i3c_master_add_i3c_dev_locked(m, master->devs[pos].addr); 951 } 952 953 rpm_out: 954 pm_runtime_put_autosuspend(master->dev); 955 return ret; 956 } 957 958 static int dw_i3c_master_i3c_xfers(struct i3c_dev_desc *dev, 959 struct i3c_xfer *i3c_xfers, 960 int i3c_nxfers, enum i3c_xfer_mode mode) 961 { 962 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 963 struct i3c_master_controller *m = i3c_dev_get_master(dev); 964 struct dw_i3c_master *master = to_dw_i3c_master(m); 965 unsigned int nrxwords = 0, ntxwords = 0; 966 int i, ret = 0; 967 968 if (!i3c_nxfers) 969 return 0; 970 971 if (i3c_nxfers > master->caps.cmdfifodepth) 972 return -EOPNOTSUPP; 973 974 for (i = 0; i < i3c_nxfers; i++) { 975 if (i3c_xfers[i].rnw) 976 nrxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4); 977 else 978 ntxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4); 979 } 980 981 if (ntxwords > master->caps.datafifodepth || 982 nrxwords > master->caps.datafifodepth) 983 return -EOPNOTSUPP; 984 985 struct dw_i3c_xfer *xfer __free(kfree) = dw_i3c_master_alloc_xfer(master, i3c_nxfers); 986 if (!xfer) 987 return -ENOMEM; 988 989 ret = pm_runtime_resume_and_get(master->dev); 990 if (ret < 0) { 991 dev_err(master->dev, 992 "<%s> cannot resume i3c bus master, err: %d\n", 993 __func__, ret); 994 return ret; 995 } 996 997 for (i = 0; i < i3c_nxfers; i++) { 998 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 999 1000 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i3c_xfers[i].len) | 1001 COMMAND_PORT_TRANSFER_ARG; 1002 1003 if (i3c_xfers[i].rnw) { 1004 cmd->rx_buf = i3c_xfers[i].data.in; 1005 cmd->rx_len = i3c_xfers[i].len; 1006 cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER | 1007 COMMAND_PORT_SPEED(dev->info.max_read_ds); 1008 1009 } else { 1010 cmd->tx_buf = i3c_xfers[i].data.out; 1011 cmd->tx_len = i3c_xfers[i].len; 1012 cmd->cmd_lo = 1013 COMMAND_PORT_SPEED(dev->info.max_write_ds); 1014 } 1015 1016 cmd->cmd_lo |= COMMAND_PORT_TID(i) | 1017 COMMAND_PORT_DEV_INDEX(data->index) | 1018 COMMAND_PORT_ROC; 1019 1020 if (i == (i3c_nxfers - 1)) 1021 cmd->cmd_lo |= COMMAND_PORT_TOC; 1022 } 1023 1024 dw_i3c_master_enqueue_xfer(master, xfer); 1025 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 1026 dw_i3c_master_dequeue_xfer(master, xfer); 1027 1028 for (i = 0; i < i3c_nxfers; i++) { 1029 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 1030 1031 if (i3c_xfers[i].rnw) 1032 i3c_xfers[i].len = cmd->rx_len; 1033 } 1034 1035 ret = xfer->ret; 1036 1037 pm_runtime_put_autosuspend(master->dev); 1038 return ret; 1039 } 1040 1041 static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, 1042 u8 old_dyn_addr) 1043 { 1044 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1045 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1046 struct dw_i3c_master *master = to_dw_i3c_master(m); 1047 int pos; 1048 1049 pos = dw_i3c_master_get_free_pos(master); 1050 1051 if (data->index > pos && pos > 0) { 1052 writel(0, 1053 master->regs + 1054 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 1055 1056 master->devs[data->index].addr = 0; 1057 master->free_pos |= BIT(data->index); 1058 1059 data->index = pos; 1060 master->devs[pos].addr = dev->info.dyn_addr; 1061 master->free_pos &= ~BIT(pos); 1062 } 1063 1064 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(dev->info.dyn_addr) | DEV_ADDR_TABLE_SIR_REJECT, 1065 master->regs + 1066 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 1067 1068 master->devs[data->index].addr = dev->info.dyn_addr; 1069 1070 return 0; 1071 } 1072 1073 static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev) 1074 { 1075 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1076 struct dw_i3c_master *master = to_dw_i3c_master(m); 1077 struct dw_i3c_i2c_dev_data *data; 1078 int pos; 1079 1080 pos = dw_i3c_master_get_free_pos(master); 1081 if (pos < 0) 1082 return pos; 1083 1084 data = kzalloc_obj(*data); 1085 if (!data) 1086 return -ENOMEM; 1087 1088 data->index = pos; 1089 master->devs[pos].addr = dev->info.dyn_addr ? : dev->info.static_addr; 1090 master->free_pos &= ~BIT(pos); 1091 i3c_dev_set_master_data(dev, data); 1092 1093 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr) | DEV_ADDR_TABLE_SIR_REJECT, 1094 master->regs + 1095 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 1096 1097 return 0; 1098 } 1099 1100 static void dw_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) 1101 { 1102 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1103 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1104 struct dw_i3c_master *master = to_dw_i3c_master(m); 1105 1106 writel(0, 1107 master->regs + 1108 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 1109 1110 i3c_dev_set_master_data(dev, NULL); 1111 master->devs[data->index].addr = 0; 1112 master->free_pos |= BIT(data->index); 1113 kfree(data); 1114 } 1115 1116 static int dw_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, 1117 struct i2c_msg *i2c_xfers, 1118 int i2c_nxfers) 1119 { 1120 struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 1121 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1122 struct dw_i3c_master *master = to_dw_i3c_master(m); 1123 unsigned int nrxwords = 0, ntxwords = 0; 1124 int i, ret = 0; 1125 1126 if (!i2c_nxfers) 1127 return 0; 1128 1129 if (i2c_nxfers > master->caps.cmdfifodepth) 1130 return -EOPNOTSUPP; 1131 1132 for (i = 0; i < i2c_nxfers; i++) { 1133 if (i2c_xfers[i].flags & I2C_M_RD) 1134 nrxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4); 1135 else 1136 ntxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4); 1137 } 1138 1139 if (ntxwords > master->caps.datafifodepth || 1140 nrxwords > master->caps.datafifodepth) 1141 return -EOPNOTSUPP; 1142 1143 struct dw_i3c_xfer *xfer __free(kfree) = dw_i3c_master_alloc_xfer(master, i2c_nxfers); 1144 if (!xfer) 1145 return -ENOMEM; 1146 1147 ret = pm_runtime_resume_and_get(master->dev); 1148 if (ret < 0) { 1149 dev_err(master->dev, 1150 "<%s> cannot resume i3c bus master, err: %d\n", 1151 __func__, ret); 1152 return ret; 1153 } 1154 1155 for (i = 0; i < i2c_nxfers; i++) { 1156 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 1157 1158 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i2c_xfers[i].len) | 1159 COMMAND_PORT_TRANSFER_ARG; 1160 1161 cmd->cmd_lo = COMMAND_PORT_TID(i) | 1162 COMMAND_PORT_DEV_INDEX(data->index) | 1163 COMMAND_PORT_ROC; 1164 1165 if (i2c_xfers[i].flags & I2C_M_RD) { 1166 cmd->cmd_lo |= COMMAND_PORT_READ_TRANSFER; 1167 cmd->rx_buf = i2c_xfers[i].buf; 1168 cmd->rx_len = i2c_xfers[i].len; 1169 } else { 1170 cmd->tx_buf = i2c_xfers[i].buf; 1171 cmd->tx_len = i2c_xfers[i].len; 1172 } 1173 1174 if (i == (i2c_nxfers - 1)) 1175 cmd->cmd_lo |= COMMAND_PORT_TOC; 1176 } 1177 1178 dw_i3c_master_enqueue_xfer(master, xfer); 1179 if (!wait_for_completion_timeout(&xfer->comp, m->i2c.timeout)) 1180 dw_i3c_master_dequeue_xfer(master, xfer); 1181 1182 ret = xfer->ret; 1183 1184 pm_runtime_put_autosuspend(master->dev); 1185 return ret; 1186 } 1187 1188 static int dw_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) 1189 { 1190 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1191 struct dw_i3c_master *master = to_dw_i3c_master(m); 1192 struct dw_i3c_i2c_dev_data *data; 1193 int pos; 1194 1195 pos = dw_i3c_master_get_free_pos(master); 1196 if (pos < 0) 1197 return pos; 1198 1199 data = kzalloc_obj(*data); 1200 if (!data) 1201 return -ENOMEM; 1202 1203 data->index = pos; 1204 master->devs[pos].addr = dev->addr; 1205 master->devs[pos].is_i2c_addr = true; 1206 master->free_pos &= ~BIT(pos); 1207 i2c_dev_set_master_data(dev, data); 1208 1209 writel(DEV_ADDR_TABLE_LEGACY_I2C_DEV | 1210 DEV_ADDR_TABLE_STATIC_ADDR(dev->addr), 1211 master->regs + 1212 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 1213 1214 return 0; 1215 } 1216 1217 static void dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) 1218 { 1219 struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 1220 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1221 struct dw_i3c_master *master = to_dw_i3c_master(m); 1222 1223 writel(0, 1224 master->regs + 1225 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 1226 1227 i2c_dev_set_master_data(dev, NULL); 1228 master->devs[data->index].addr = 0; 1229 master->free_pos |= BIT(data->index); 1230 kfree(data); 1231 } 1232 1233 static int dw_i3c_master_request_ibi(struct i3c_dev_desc *dev, 1234 const struct i3c_ibi_setup *req) 1235 { 1236 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1237 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1238 struct dw_i3c_master *master = to_dw_i3c_master(m); 1239 1240 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); 1241 if (IS_ERR(data->ibi_pool)) 1242 return PTR_ERR(data->ibi_pool); 1243 1244 guard(spinlock_irqsave)(&master->devs_lock); 1245 master->devs[data->index].ibi_dev = dev; 1246 1247 return 0; 1248 } 1249 1250 static void dw_i3c_master_free_ibi(struct i3c_dev_desc *dev) 1251 { 1252 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1253 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1254 struct dw_i3c_master *master = to_dw_i3c_master(m); 1255 1256 scoped_guard(spinlock_irqsave, &master->devs_lock) { 1257 master->devs[data->index].ibi_dev = NULL; 1258 } 1259 1260 i3c_generic_ibi_free_pool(data->ibi_pool); 1261 data->ibi_pool = NULL; 1262 } 1263 1264 static void dw_i3c_master_enable_sir_signal(struct dw_i3c_master *master, bool enable) 1265 { 1266 u32 reg; 1267 1268 reg = readl(master->regs + INTR_STATUS_EN); 1269 reg &= ~INTR_IBI_THLD_STAT; 1270 if (enable) 1271 reg |= INTR_IBI_THLD_STAT; 1272 writel(reg, master->regs + INTR_STATUS_EN); 1273 1274 reg = readl(master->regs + INTR_SIGNAL_EN); 1275 reg &= ~INTR_IBI_THLD_STAT; 1276 if (enable) 1277 reg |= INTR_IBI_THLD_STAT; 1278 writel(reg, master->regs + INTR_SIGNAL_EN); 1279 } 1280 1281 static void dw_i3c_master_set_sir_enabled(struct dw_i3c_master *master, 1282 struct i3c_dev_desc *dev, 1283 u8 idx, bool enable) 1284 { 1285 u32 dat_entry, reg; 1286 bool global; 1287 u8 dynamic_addr; 1288 1289 dat_entry = DEV_ADDR_TABLE_LOC(master->datstartaddr, idx); 1290 1291 guard(spinlock_irqsave)(&master->devs_lock); 1292 reg = readl(master->regs + dat_entry); 1293 dynamic_addr = DEV_ADDR_TABLE_GET_DYNAMIC_ADDR(reg); 1294 1295 if (!dynamic_addr) 1296 dev_warn(master->dev, 1297 "<%s> unassigned slave device, dynamic addr:%x\n", 1298 __func__, dynamic_addr); 1299 1300 if (enable) { 1301 reg &= ~DEV_ADDR_TABLE_SIR_REJECT; 1302 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) 1303 reg |= DEV_ADDR_TABLE_IBI_MDB; 1304 } else { 1305 reg |= DEV_ADDR_TABLE_SIR_REJECT; 1306 } 1307 master->platform_ops->set_dat_ibi(master, dev, enable, ®); 1308 writel(reg, master->regs + dat_entry); 1309 1310 if (enable) { 1311 global = (master->sir_rej_mask == IBI_REQ_REJECT_ALL); 1312 master->sir_rej_mask &= ~BIT(get_ibi_sir_bit_index(dynamic_addr)); 1313 } else { 1314 bool hj_rejected = !!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_HOT_JOIN_NACK); 1315 1316 master->sir_rej_mask |= BIT(get_ibi_sir_bit_index(dynamic_addr)); 1317 global = (master->sir_rej_mask == IBI_REQ_REJECT_ALL) && hj_rejected; 1318 } 1319 writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT); 1320 1321 if (global) 1322 dw_i3c_master_enable_sir_signal(master, enable); 1323 } 1324 1325 static int dw_i3c_master_enable_hotjoin(struct i3c_master_controller *m) 1326 { 1327 struct dw_i3c_master *master = to_dw_i3c_master(m); 1328 int ret; 1329 1330 ret = pm_runtime_resume_and_get(master->dev); 1331 if (ret < 0) { 1332 dev_err(master->dev, 1333 "<%s> cannot resume i3c bus master, err: %d\n", 1334 __func__, ret); 1335 return ret; 1336 } 1337 1338 dw_i3c_master_enable_sir_signal(master, true); 1339 writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_HOT_JOIN_NACK, 1340 master->regs + DEVICE_CTRL); 1341 1342 return 0; 1343 } 1344 1345 static int dw_i3c_master_disable_hotjoin(struct i3c_master_controller *m) 1346 { 1347 struct dw_i3c_master *master = to_dw_i3c_master(m); 1348 1349 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK, 1350 master->regs + DEVICE_CTRL); 1351 1352 pm_runtime_put_autosuspend(master->dev); 1353 return 0; 1354 } 1355 1356 static int dw_i3c_master_enable_ibi(struct i3c_dev_desc *dev) 1357 { 1358 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1359 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1360 struct dw_i3c_master *master = to_dw_i3c_master(m); 1361 int rc; 1362 1363 rc = pm_runtime_resume_and_get(master->dev); 1364 if (rc < 0) { 1365 dev_err(master->dev, 1366 "<%s> cannot resume i3c bus master, err: %d\n", 1367 __func__, rc); 1368 return rc; 1369 } 1370 1371 dw_i3c_master_set_sir_enabled(master, dev, data->index, true); 1372 1373 rc = i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); 1374 1375 if (rc) { 1376 dw_i3c_master_set_sir_enabled(master, dev, data->index, false); 1377 pm_runtime_put_autosuspend(master->dev); 1378 } 1379 1380 return rc; 1381 } 1382 1383 static int dw_i3c_master_disable_ibi(struct i3c_dev_desc *dev) 1384 { 1385 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1386 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1387 struct dw_i3c_master *master = to_dw_i3c_master(m); 1388 int rc; 1389 1390 rc = i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); 1391 if (rc) 1392 return rc; 1393 1394 dw_i3c_master_set_sir_enabled(master, dev, data->index, false); 1395 1396 pm_runtime_put_autosuspend(master->dev); 1397 return 0; 1398 } 1399 1400 static void dw_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev, 1401 struct i3c_ibi_slot *slot) 1402 { 1403 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1404 1405 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot); 1406 } 1407 1408 static void dw_i3c_master_drain_ibi_queue(struct dw_i3c_master *master, 1409 int len) 1410 { 1411 int i; 1412 1413 for (i = 0; i < DIV_ROUND_UP(len, 4); i++) 1414 readl(master->regs + IBI_QUEUE_STATUS); 1415 } 1416 1417 static void dw_i3c_master_handle_ibi_sir(struct dw_i3c_master *master, 1418 u32 status) 1419 { 1420 struct dw_i3c_i2c_dev_data *data; 1421 struct i3c_ibi_slot *slot; 1422 struct i3c_dev_desc *dev; 1423 u8 addr, len; 1424 int idx; 1425 1426 addr = IBI_QUEUE_IBI_ADDR(status); 1427 len = IBI_QUEUE_STATUS_DATA_LEN(status); 1428 1429 /* 1430 * We be tempted to check the error status in bit 30; however, due 1431 * to the PEC errata workaround on some platform implementations (see 1432 * ast2600_i3c_set_dat_ibi()), those will almost always have a PEC 1433 * error on IBI payload data, as well as losing the last byte of 1434 * payload. 1435 * 1436 * If we implement error status checking on that bit, we may need 1437 * a new platform op to validate it. 1438 */ 1439 1440 guard(spinlock_irqsave)(&master->devs_lock); 1441 idx = dw_i3c_master_get_addr_pos(master, addr); 1442 if (idx < 0) { 1443 dev_dbg_ratelimited(&master->base.dev, 1444 "IBI from unknown addr 0x%x\n", addr); 1445 goto err_drain; 1446 } 1447 1448 dev = master->devs[idx].ibi_dev; 1449 if (!dev || !dev->ibi) { 1450 dev_dbg_ratelimited(&master->base.dev, 1451 "IBI from non-requested dev idx %d\n", idx); 1452 goto err_drain; 1453 } 1454 1455 data = i3c_dev_get_master_data(dev); 1456 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool); 1457 if (!slot) { 1458 dev_dbg_ratelimited(&master->base.dev, 1459 "No IBI slots available\n"); 1460 goto err_drain; 1461 } 1462 1463 if (dev->ibi->max_payload_len < len) { 1464 dev_dbg_ratelimited(&master->base.dev, 1465 "IBI payload len %d greater than max %d\n", 1466 len, dev->ibi->max_payload_len); 1467 goto err_drain; 1468 } 1469 1470 if (len) { 1471 dw_i3c_master_read_ibi_fifo(master, slot->data, len); 1472 slot->len = len; 1473 } 1474 i3c_master_queue_ibi(dev, slot); 1475 1476 return; 1477 1478 err_drain: 1479 dw_i3c_master_drain_ibi_queue(master, len); 1480 } 1481 1482 /* "ibis": referring to In-Band Interrupts, and not 1483 * https://en.wikipedia.org/wiki/Australian_white_ibis. The latter should 1484 * not be handled. 1485 */ 1486 static void dw_i3c_master_irq_handle_ibis(struct dw_i3c_master *master) 1487 { 1488 unsigned int i, len, n_ibis; 1489 u32 reg; 1490 1491 reg = readl(master->regs + QUEUE_STATUS_LEVEL); 1492 if (master->has_ibi_data) 1493 n_ibis = QUEUE_STATUS_IBI_STATUS_CNT(reg); 1494 else 1495 n_ibis = QUEUE_STATUS_IBI_BUF_BLR(reg); 1496 1497 if (!n_ibis) 1498 return; 1499 1500 for (i = 0; i < n_ibis; i++) { 1501 reg = readl(master->regs + IBI_QUEUE_STATUS); 1502 1503 if (IBI_TYPE_SIRQ(reg)) { 1504 dw_i3c_master_handle_ibi_sir(master, reg); 1505 } else if (IBI_TYPE_HJ(reg)) { 1506 i3c_master_queue_hotjoin(&master->base); 1507 } else { 1508 len = IBI_QUEUE_STATUS_DATA_LEN(reg); 1509 dev_info(&master->base.dev, 1510 "unsupported IBI type 0x%lx len %d\n", 1511 IBI_QUEUE_STATUS_IBI_ID(reg), len); 1512 dw_i3c_master_drain_ibi_queue(master, len); 1513 } 1514 } 1515 } 1516 1517 static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id) 1518 { 1519 struct dw_i3c_master *master = dev_id; 1520 u32 status; 1521 1522 status = readl(master->regs + INTR_STATUS); 1523 1524 if (!(status & readl(master->regs + INTR_STATUS_EN))) { 1525 writel(INTR_ALL, master->regs + INTR_STATUS); 1526 return IRQ_NONE; 1527 } 1528 1529 spin_lock(&master->xferqueue.lock); 1530 dw_i3c_master_end_xfer_locked(master, status); 1531 if (status & INTR_TRANSFER_ERR_STAT) 1532 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS); 1533 spin_unlock(&master->xferqueue.lock); 1534 1535 if (status & INTR_IBI_THLD_STAT) 1536 dw_i3c_master_irq_handle_ibis(master); 1537 1538 return IRQ_HANDLED; 1539 } 1540 1541 static int dw_i3c_master_set_speed(struct i3c_master_controller *m, 1542 enum i3c_open_drain_speed speed) 1543 { 1544 struct dw_i3c_master *master = to_dw_i3c_master(m); 1545 unsigned long core_rate; 1546 u32 scl_timing, od_hcnt; 1547 u8 lcnt; 1548 1549 PM_RUNTIME_ACQUIRE_AUTOSUSPEND(master->dev, pm); 1550 if (PM_RUNTIME_ACQUIRE_ERR(&pm)) 1551 return -ENXIO; 1552 1553 switch (speed) { 1554 case I3C_OPEN_DRAIN_SLOW_SPEED: 1555 core_rate = dw_i3c_master_get_core_rate(master); 1556 if (!core_rate) 1557 return -EINVAL; 1558 1559 lcnt = SCL_I3C_TIMING_LCNT(master->i3c_od_timing_normal); 1560 od_hcnt = DIV_ROUND_UP_ULL((u64)I3C_BUS_THIGH_INIT_OD_MIN_NS * 1561 core_rate, NSEC_PER_SEC) - 1; 1562 if (od_hcnt < SCL_I3C_TIMING_CNT_MIN) 1563 od_hcnt = SCL_I3C_TIMING_CNT_MIN; 1564 else if (od_hcnt > U8_MAX) 1565 od_hcnt = U8_MAX; 1566 scl_timing = SCL_I3C_TIMING_HCNT(od_hcnt) | 1567 SCL_I3C_TIMING_LCNT(lcnt); 1568 writel(scl_timing, master->regs + SCL_I3C_OD_TIMING); 1569 master->i3c_od_timing = scl_timing; 1570 break; 1571 1572 case I3C_OPEN_DRAIN_NORMAL_SPEED: 1573 writel(master->i3c_od_timing_normal, 1574 master->regs + SCL_I3C_OD_TIMING); 1575 master->i3c_od_timing = master->i3c_od_timing_normal; 1576 break; 1577 1578 default: 1579 return -EINVAL; 1580 } 1581 1582 return 0; 1583 } 1584 1585 static int dw_i3c_master_set_dev_nack_retry(struct i3c_master_controller *m, 1586 unsigned int dev_nack_retry_cnt) 1587 { 1588 struct dw_i3c_master *master = to_dw_i3c_master(m); 1589 u32 reg; 1590 int i; 1591 1592 if (dev_nack_retry_cnt > DW_I3C_DEV_NACK_RETRY_CNT_MAX) { 1593 dev_err(&master->base.dev, 1594 "Value %u exceeds maximum %d\n", 1595 dev_nack_retry_cnt, DW_I3C_DEV_NACK_RETRY_CNT_MAX); 1596 return -ERANGE; 1597 } 1598 1599 /* 1600 * Update DAT entries for all currently attached devices. 1601 * We directly iterate through the master's device array. 1602 */ 1603 for (i = 0; i < master->maxdevs; i++) { 1604 /* Skip free/empty slots */ 1605 if (master->free_pos & BIT(i)) 1606 continue; 1607 1608 reg = readl(master->regs + 1609 DEV_ADDR_TABLE_LOC(master->datstartaddr, i)); 1610 reg &= ~DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK; 1611 reg |= DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(dev_nack_retry_cnt); 1612 writel(reg, master->regs + 1613 DEV_ADDR_TABLE_LOC(master->datstartaddr, i)); 1614 } 1615 1616 return 0; 1617 } 1618 1619 static const struct i3c_master_controller_ops dw_mipi_i3c_ops = { 1620 .bus_init = dw_i3c_master_bus_init, 1621 .bus_cleanup = dw_i3c_master_bus_cleanup, 1622 .attach_i3c_dev = dw_i3c_master_attach_i3c_dev, 1623 .reattach_i3c_dev = dw_i3c_master_reattach_i3c_dev, 1624 .detach_i3c_dev = dw_i3c_master_detach_i3c_dev, 1625 .do_daa = dw_i3c_master_daa, 1626 .supports_ccc_cmd = dw_i3c_master_supports_ccc_cmd, 1627 .send_ccc_cmd = dw_i3c_master_send_ccc_cmd, 1628 .i3c_xfers = dw_i3c_master_i3c_xfers, 1629 .attach_i2c_dev = dw_i3c_master_attach_i2c_dev, 1630 .detach_i2c_dev = dw_i3c_master_detach_i2c_dev, 1631 .i2c_xfers = dw_i3c_master_i2c_xfers, 1632 .request_ibi = dw_i3c_master_request_ibi, 1633 .free_ibi = dw_i3c_master_free_ibi, 1634 .enable_ibi = dw_i3c_master_enable_ibi, 1635 .disable_ibi = dw_i3c_master_disable_ibi, 1636 .recycle_ibi_slot = dw_i3c_master_recycle_ibi_slot, 1637 .enable_hotjoin = dw_i3c_master_enable_hotjoin, 1638 .disable_hotjoin = dw_i3c_master_disable_hotjoin, 1639 .set_speed = dw_i3c_master_set_speed, 1640 .set_dev_nack_retry = dw_i3c_master_set_dev_nack_retry, 1641 }; 1642 1643 /* default platform ops implementations */ 1644 static int dw_i3c_platform_init_nop(struct dw_i3c_master *i3c) 1645 { 1646 return 0; 1647 } 1648 1649 static void dw_i3c_platform_set_dat_ibi_nop(struct dw_i3c_master *i3c, 1650 struct i3c_dev_desc *dev, 1651 bool enable, u32 *dat) 1652 { 1653 } 1654 1655 static const struct dw_i3c_platform_ops dw_i3c_platform_ops_default = { 1656 .init = dw_i3c_platform_init_nop, 1657 .set_dat_ibi = dw_i3c_platform_set_dat_ibi_nop, 1658 }; 1659 1660 int dw_i3c_common_probe(struct dw_i3c_master *master, 1661 struct platform_device *pdev) 1662 { 1663 int ret, irq; 1664 u32 thld_ctrl; 1665 const struct dw_i3c_drvdata *drvdata; 1666 unsigned long quirks = 0; 1667 1668 if (!master->platform_ops) 1669 master->platform_ops = &dw_i3c_platform_ops_default; 1670 1671 master->dev = &pdev->dev; 1672 1673 if (has_acpi_companion(&pdev->dev)) { 1674 quirks = (unsigned long)device_get_match_data(&pdev->dev); 1675 } else if (pdev->dev.of_node) { 1676 drvdata = device_get_match_data(&pdev->dev); 1677 if (drvdata) 1678 quirks = drvdata->flags; 1679 } 1680 master->quirks = quirks; 1681 1682 master->regs = devm_platform_ioremap_resource(pdev, 0); 1683 if (IS_ERR(master->regs)) 1684 return PTR_ERR(master->regs); 1685 1686 master->core_clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); 1687 if (IS_ERR(master->core_clk)) 1688 return PTR_ERR(master->core_clk); 1689 1690 if (!master->core_clk && !(master->quirks & DW_I3C_ACPI_SKIP_CLK_RST)) { 1691 dev_err(&pdev->dev, "missing core clock\n"); 1692 return -EINVAL; 1693 } 1694 1695 master->pclk = devm_clk_get_optional_enabled(&pdev->dev, "apb"); 1696 if (IS_ERR(master->pclk)) 1697 return PTR_ERR(master->pclk); 1698 1699 master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, 1700 NULL); 1701 if (IS_ERR(master->core_rst)) 1702 return PTR_ERR(master->core_rst); 1703 1704 spin_lock_init(&master->xferqueue.lock); 1705 INIT_LIST_HEAD(&master->xferqueue.list); 1706 1707 spin_lock_init(&master->devs_lock); 1708 1709 writel(INTR_ALL, master->regs + INTR_STATUS); 1710 irq = platform_get_irq(pdev, 0); 1711 ret = devm_request_irq(&pdev->dev, irq, 1712 dw_i3c_master_irq_handler, 0, 1713 dev_name(&pdev->dev), master); 1714 if (ret) 1715 return ret; 1716 1717 platform_set_drvdata(pdev, master); 1718 1719 pm_runtime_set_autosuspend_delay(&pdev->dev, RPM_AUTOSUSPEND_TIMEOUT); 1720 pm_runtime_use_autosuspend(&pdev->dev); 1721 pm_runtime_set_active(&pdev->dev); 1722 pm_runtime_enable(&pdev->dev); 1723 1724 /* Information regarding the FIFOs/QUEUEs depth */ 1725 ret = readl(master->regs + QUEUE_STATUS_LEVEL); 1726 master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret); 1727 1728 ret = readl(master->regs + DATA_BUFFER_STATUS_LEVEL); 1729 master->caps.datafifodepth = DATA_BUFFER_STATUS_LEVEL_TX(ret); 1730 1731 ret = readl(master->regs + DEVICE_ADDR_TABLE_POINTER); 1732 master->datstartaddr = ret; 1733 master->maxdevs = ret >> 16; 1734 master->free_pos = GENMASK(master->maxdevs - 1, 0); 1735 1736 /* 1737 * Detect IBI data capability (IC_HAS_IBI_DATA): write a non-zero value 1738 * to IBI_DATA_THLD and read back. On controllers like Versalnet 1739 * the field is hardwired to 0 and the write is ignored. Restore the 1740 * original register value after detection. 1741 */ 1742 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL); 1743 ret = thld_ctrl | QUEUE_THLD_CTRL_IBI_DATA(2); 1744 writel(ret, master->regs + QUEUE_THLD_CTRL); 1745 ret = readl(master->regs + QUEUE_THLD_CTRL); 1746 if (ret & QUEUE_THLD_CTRL_IBI_DATA_MASK) 1747 master->has_ibi_data = true; 1748 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); 1749 1750 /* Keep controller enabled by preventing runtime suspend */ 1751 if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK) 1752 pm_runtime_get_noresume(&pdev->dev); 1753 1754 device_set_of_node_from_dev(&master->base.i2c.dev, &pdev->dev); 1755 ret = i3c_master_register(&master->base, &pdev->dev, 1756 &dw_mipi_i3c_ops, false); 1757 if (ret) 1758 goto err_disable_pm; 1759 1760 return 0; 1761 1762 err_disable_pm: 1763 if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK) 1764 pm_runtime_put_noidle(&pdev->dev); 1765 pm_runtime_disable(&pdev->dev); 1766 pm_runtime_set_suspended(&pdev->dev); 1767 pm_runtime_dont_use_autosuspend(&pdev->dev); 1768 1769 return ret; 1770 } 1771 EXPORT_SYMBOL_GPL(dw_i3c_common_probe); 1772 1773 void dw_i3c_common_remove(struct dw_i3c_master *master) 1774 { 1775 i3c_master_unregister(&master->base); 1776 1777 /* Balance pm_runtime_get_noresume() from probe() */ 1778 if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK) 1779 pm_runtime_put_noidle(master->dev); 1780 1781 pm_runtime_disable(master->dev); 1782 pm_runtime_set_suspended(master->dev); 1783 pm_runtime_dont_use_autosuspend(master->dev); 1784 } 1785 EXPORT_SYMBOL_GPL(dw_i3c_common_remove); 1786 1787 /* base platform implementation */ 1788 1789 static int dw_i3c_probe(struct platform_device *pdev) 1790 { 1791 struct dw_i3c_master *master; 1792 1793 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 1794 if (!master) 1795 return -ENOMEM; 1796 1797 return dw_i3c_common_probe(master, pdev); 1798 } 1799 1800 static void dw_i3c_remove(struct platform_device *pdev) 1801 { 1802 struct dw_i3c_master *master = platform_get_drvdata(pdev); 1803 1804 dw_i3c_common_remove(master); 1805 } 1806 1807 static void dw_i3c_master_restore_addrs(struct dw_i3c_master *master) 1808 { 1809 u32 pos, reg_val; 1810 1811 writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(master->dev_addr), 1812 master->regs + DEVICE_ADDR); 1813 1814 for (pos = 0; pos < master->maxdevs; pos++) { 1815 if (master->free_pos & BIT(pos)) 1816 continue; 1817 1818 reg_val = readl(master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos)); 1819 1820 if (master->devs[pos].is_i2c_addr) { 1821 reg_val &= ~DEV_ADDR_TABLE_STATIC_MASK; 1822 reg_val |= DEV_ADDR_TABLE_LEGACY_I2C_DEV | 1823 DEV_ADDR_TABLE_STATIC_ADDR(master->devs[pos].addr); 1824 } else { 1825 reg_val &= ~DEV_ADDR_TABLE_DYNAMIC_MASK; 1826 reg_val |= DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr); 1827 } 1828 1829 writel(reg_val, master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos)); 1830 } 1831 } 1832 1833 static void dw_i3c_master_restore_timing_regs(struct dw_i3c_master *master) 1834 { 1835 /* Preserve cached OD timing; it may be the SLOW setting from set_speed(). */ 1836 writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING); 1837 writel(master->bus_free_timing, master->regs + BUS_FREE_TIMING); 1838 writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING); 1839 writel(master->ext_lcnt_timing, master->regs + SCL_EXT_LCNT_TIMING); 1840 1841 if (master->i2c_slv_prsnt) { 1842 writel(master->i2c_fmp_timing, master->regs + SCL_I2C_FMP_TIMING); 1843 writel(master->i2c_fm_timing, master->regs + SCL_I2C_FM_TIMING); 1844 } 1845 } 1846 1847 static int dw_i3c_master_enable_clks(struct dw_i3c_master *master) 1848 { 1849 int ret = 0; 1850 1851 ret = clk_prepare_enable(master->core_clk); 1852 if (ret) 1853 return ret; 1854 1855 ret = clk_prepare_enable(master->pclk); 1856 if (ret) { 1857 clk_disable_unprepare(master->core_clk); 1858 return ret; 1859 } 1860 1861 return 0; 1862 } 1863 1864 static inline void dw_i3c_master_disable_clks(struct dw_i3c_master *master) 1865 { 1866 clk_disable_unprepare(master->pclk); 1867 clk_disable_unprepare(master->core_clk); 1868 } 1869 1870 static int __maybe_unused dw_i3c_master_runtime_suspend(struct device *dev) 1871 { 1872 struct dw_i3c_master *master = dev_get_drvdata(dev); 1873 1874 dw_i3c_master_disable(master); 1875 1876 reset_control_assert(master->core_rst); 1877 dw_i3c_master_disable_clks(master); 1878 pinctrl_pm_select_sleep_state(dev); 1879 return 0; 1880 } 1881 1882 static int __maybe_unused dw_i3c_master_runtime_resume(struct device *dev) 1883 { 1884 struct dw_i3c_master *master = dev_get_drvdata(dev); 1885 1886 pinctrl_pm_select_default_state(dev); 1887 dw_i3c_master_enable_clks(master); 1888 reset_control_deassert(master->core_rst); 1889 1890 dw_i3c_master_set_intr_regs(master); 1891 dw_i3c_master_restore_timing_regs(master); 1892 dw_i3c_master_restore_addrs(master); 1893 1894 dw_i3c_master_enable(master); 1895 return 0; 1896 } 1897 1898 static const struct dev_pm_ops dw_i3c_pm_ops = { 1899 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1900 SET_RUNTIME_PM_OPS(dw_i3c_master_runtime_suspend, dw_i3c_master_runtime_resume, NULL) 1901 }; 1902 1903 static void dw_i3c_shutdown(struct platform_device *pdev) 1904 { 1905 struct dw_i3c_master *master = platform_get_drvdata(pdev); 1906 int ret; 1907 1908 ret = pm_runtime_resume_and_get(master->dev); 1909 if (ret < 0) { 1910 dev_err(master->dev, 1911 "<%s> cannot resume i3c bus master, err: %d\n", 1912 __func__, ret); 1913 return; 1914 } 1915 1916 /* Disable interrupts */ 1917 writel((u32)~INTR_ALL, master->regs + INTR_STATUS_EN); 1918 writel((u32)~INTR_ALL, master->regs + INTR_SIGNAL_EN); 1919 1920 pm_runtime_put_autosuspend(master->dev); 1921 } 1922 1923 static const struct dw_i3c_drvdata altr_agilex5_drvdata = { 1924 .flags = DW_I3C_DISABLE_RUNTIME_PM_QUIRK, 1925 }; 1926 1927 static const struct of_device_id dw_i3c_master_of_match[] = { 1928 { .compatible = "snps,dw-i3c-master-1.00a", }, 1929 { .compatible = "altr,agilex5-dw-i3c-master", 1930 .data = &altr_agilex5_drvdata, 1931 }, 1932 {}, 1933 }; 1934 MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match); 1935 1936 static const struct acpi_device_id dw_i3c_master_acpi_match[] = { 1937 { "AMDI0015", AMD_I3C_OD_PP_TIMING }, 1938 { "NVDA2018", DW_I3C_ACPI_SKIP_CLK_RST }, 1939 { } 1940 }; 1941 MODULE_DEVICE_TABLE(acpi, dw_i3c_master_acpi_match); 1942 1943 static struct platform_driver dw_i3c_driver = { 1944 .probe = dw_i3c_probe, 1945 .remove = dw_i3c_remove, 1946 .shutdown = dw_i3c_shutdown, 1947 .driver = { 1948 .name = "dw-i3c-master", 1949 .of_match_table = dw_i3c_master_of_match, 1950 .acpi_match_table = dw_i3c_master_acpi_match, 1951 .pm = &dw_i3c_pm_ops, 1952 }, 1953 }; 1954 module_platform_driver(dw_i3c_driver); 1955 1956 MODULE_AUTHOR("Vitor Soares <vitor.soares@synopsys.com>"); 1957 MODULE_DESCRIPTION("DesignWare MIPI I3C driver"); 1958 MODULE_LICENSE("GPL v2"); 1959