1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * I3C Controller driver 4 * Copyright 2025 Analog Devices Inc. 5 * Author: Jorge Marques <jorge.marques@analog.com> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/err.h> 12 #include <linux/errno.h> 13 #include <linux/adi-axi-common.h> 14 #include <linux/i3c/master.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 21 #include "../internals.h" 22 23 #define ADI_MAX_DEVS 16 24 #define ADI_HAS_MDB_FROM_BCR(x) (FIELD_GET(BIT(2), (x))) 25 26 #define REG_ENABLE 0x040 27 28 #define REG_PID_L 0x054 29 #define REG_PID_H 0x058 30 #define REG_DCR_BCR_DA 0x05c 31 #define REG_DCR_BCR_DA_GET_DA(x) FIELD_GET(GENMASK(22, 16), (x)) 32 #define REG_DCR_BCR_DA_GET_BCR(x) FIELD_GET(GENMASK(15, 8), (x)) 33 #define REG_DCR_BCR_DA_GET_DCR(x) FIELD_GET(GENMASK(7, 0), (x)) 34 35 #define REG_IRQ_MASK 0x080 36 #define REG_IRQ_PENDING 0x084 37 #define REG_IRQ_PENDING_DAA BIT(7) 38 #define REG_IRQ_PENDING_IBI BIT(6) 39 #define REG_IRQ_PENDING_CMDR BIT(5) 40 41 #define REG_CMD_FIFO 0x0d4 42 #define REG_CMD_FIFO_0_IS_CCC BIT(22) 43 #define REG_CMD_FIFO_0_BCAST BIT(21) 44 #define REG_CMD_FIFO_0_SR BIT(20) 45 #define REG_CMD_FIFO_0_LEN(l) FIELD_PREP(GENMASK(19, 8), (l)) 46 #define REG_CMD_FIFO_0_DEV_ADDR(a) FIELD_PREP(GENMASK(7, 1), (a)) 47 #define REG_CMD_FIFO_0_RNW BIT(0) 48 #define REG_CMD_FIFO_1_CCC(id) FIELD_PREP(GENMASK(7, 0), (id)) 49 50 #define REG_CMD_FIFO_ROOM 0x0c0 51 #define REG_CMDR_FIFO 0x0d8 52 #define REG_CMDR_FIFO_UDA_ERROR 8 53 #define REG_CMDR_FIFO_NACK_RESP 6 54 #define REG_CMDR_FIFO_CE2_ERROR 4 55 #define REG_CMDR_FIFO_CE0_ERROR 1 56 #define REG_CMDR_FIFO_NO_ERROR 0 57 #define REG_CMDR_FIFO_ERROR(x) FIELD_GET(GENMASK(23, 20), (x)) 58 #define REG_CMDR_FIFO_XFER_BYTES(x) FIELD_GET(GENMASK(19, 8), (x)) 59 60 #define REG_SDO_FIFO 0x0dc 61 #define REG_SDO_FIFO_ROOM 0x0c8 62 #define REG_SDI_FIFO 0x0e0 63 #define REG_IBI_FIFO 0x0e4 64 #define REG_FIFO_STATUS 0x0e8 65 #define REG_FIFO_STATUS_CMDR_EMPTY BIT(0) 66 #define REG_FIFO_STATUS_IBI_EMPTY BIT(1) 67 68 #define REG_OPS 0x100 69 #define REG_OPS_PP_SG_MASK GENMASK(6, 5) 70 #define REG_OPS_SET_SG(x) FIELD_PREP(REG_OPS_PP_SG_MASK, (x)) 71 72 #define REG_IBI_CONFIG 0x140 73 #define REG_IBI_CONFIG_ENABLE BIT(0) 74 #define REG_IBI_CONFIG_LISTEN BIT(1) 75 76 #define REG_DEV_CHAR 0x180 77 #define REG_DEV_CHAR_IS_I2C BIT(0) 78 #define REG_DEV_CHAR_IS_ATTACHED BIT(1) 79 #define REG_DEV_CHAR_BCR_IBI(x) FIELD_PREP(GENMASK(3, 2), (x)) 80 #define REG_DEV_CHAR_WEN BIT(8) 81 #define REG_DEV_CHAR_ADDR(x) FIELD_PREP(GENMASK(15, 9), (x)) 82 83 enum speed_grade {PP_SG_UNSET, PP_SG_1MHZ, PP_SG_3MHZ, PP_SG_6MHZ, PP_SG_12MHZ}; 84 85 struct adi_i3c_cmd { 86 u32 cmd0; 87 u32 cmd1; 88 u32 tx_len; 89 const void *tx_buf; 90 u32 rx_len; 91 void *rx_buf; 92 u32 error; 93 }; 94 95 struct adi_i3c_xfer { 96 struct list_head node; 97 struct completion comp; 98 int ret; 99 unsigned int ncmds; 100 unsigned int ncmds_comp; 101 struct adi_i3c_cmd cmds[] __counted_by(ncmds); 102 }; 103 104 struct adi_i3c_master { 105 struct i3c_master_controller base; 106 u32 free_rr_slots; 107 struct { 108 unsigned int num_slots; 109 struct i3c_dev_desc **slots; 110 spinlock_t lock; /* Protect IBI slot access */ 111 } ibi; 112 struct { 113 struct list_head list; 114 struct adi_i3c_xfer *cur; 115 spinlock_t lock; /* Protect transfer */ 116 } xferqueue; 117 void __iomem *regs; 118 struct clk *clk; 119 unsigned long i3c_scl_lim; 120 struct { 121 u8 addrs[ADI_MAX_DEVS]; 122 u8 index; 123 } daa; 124 }; 125 126 static inline struct adi_i3c_master *to_adi_i3c_master(struct i3c_master_controller *master) 127 { 128 return container_of(master, struct adi_i3c_master, base); 129 } 130 131 static void adi_i3c_master_wr_to_tx_fifo(struct adi_i3c_master *master, 132 const u8 *buf, unsigned int nbytes) 133 { 134 unsigned int n, m; 135 136 n = readl(master->regs + REG_SDO_FIFO_ROOM); 137 m = min(n, nbytes); 138 i3c_writel_fifo(master->regs + REG_SDO_FIFO, buf, m); 139 } 140 141 static void adi_i3c_master_rd_from_rx_fifo(struct adi_i3c_master *master, 142 u8 *buf, unsigned int nbytes) 143 { 144 i3c_readl_fifo(master->regs + REG_SDI_FIFO, buf, nbytes); 145 } 146 147 static bool adi_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m, 148 const struct i3c_ccc_cmd *cmd) 149 { 150 if (cmd->ndests > 1) 151 return false; 152 153 switch (cmd->id) { 154 case I3C_CCC_ENEC(true): 155 case I3C_CCC_ENEC(false): 156 case I3C_CCC_DISEC(true): 157 case I3C_CCC_DISEC(false): 158 case I3C_CCC_RSTDAA(true): 159 case I3C_CCC_RSTDAA(false): 160 case I3C_CCC_ENTDAA: 161 case I3C_CCC_SETDASA: 162 case I3C_CCC_SETNEWDA: 163 case I3C_CCC_GETMWL: 164 case I3C_CCC_GETMRL: 165 case I3C_CCC_GETPID: 166 case I3C_CCC_GETBCR: 167 case I3C_CCC_GETDCR: 168 case I3C_CCC_GETSTATUS: 169 case I3C_CCC_GETHDRCAP: 170 return true; 171 default: 172 break; 173 } 174 175 return false; 176 } 177 178 static int adi_i3c_master_disable(struct adi_i3c_master *master) 179 { 180 writel(0, master->regs + REG_IBI_CONFIG); 181 182 return 0; 183 } 184 185 static struct adi_i3c_xfer *adi_i3c_master_alloc_xfer(struct adi_i3c_master *master, 186 unsigned int ncmds) 187 { 188 struct adi_i3c_xfer *xfer; 189 190 xfer = kzalloc_flex(*xfer, cmds, ncmds); 191 if (!xfer) 192 return NULL; 193 194 INIT_LIST_HEAD(&xfer->node); 195 xfer->ncmds = ncmds; 196 xfer->ret = -ETIMEDOUT; 197 198 return xfer; 199 } 200 201 static void adi_i3c_master_start_xfer_locked(struct adi_i3c_master *master) 202 { 203 struct adi_i3c_xfer *xfer = master->xferqueue.cur; 204 unsigned int i, n, m; 205 206 if (!xfer) 207 return; 208 209 for (i = 0; i < xfer->ncmds; i++) { 210 struct adi_i3c_cmd *cmd = &xfer->cmds[i]; 211 212 if (!(cmd->cmd0 & REG_CMD_FIFO_0_RNW)) 213 adi_i3c_master_wr_to_tx_fifo(master, cmd->tx_buf, cmd->tx_len); 214 } 215 216 n = readl(master->regs + REG_CMD_FIFO_ROOM); 217 for (i = 0; i < xfer->ncmds; i++) { 218 struct adi_i3c_cmd *cmd = &xfer->cmds[i]; 219 220 m = cmd->cmd0 & REG_CMD_FIFO_0_IS_CCC ? 2 : 1; 221 if (m > n) 222 break; 223 writel(cmd->cmd0, master->regs + REG_CMD_FIFO); 224 if (cmd->cmd0 & REG_CMD_FIFO_0_IS_CCC) 225 writel(cmd->cmd1, master->regs + REG_CMD_FIFO); 226 n -= m; 227 } 228 } 229 230 static void adi_i3c_master_end_xfer_locked(struct adi_i3c_master *master, 231 u32 pending) 232 { 233 struct adi_i3c_xfer *xfer = master->xferqueue.cur; 234 int i, ret = 0; 235 236 if (!xfer) 237 return; 238 239 while (!(readl(master->regs + REG_FIFO_STATUS) & REG_FIFO_STATUS_CMDR_EMPTY)) { 240 struct adi_i3c_cmd *cmd; 241 u32 cmdr, rx_len; 242 243 cmdr = readl(master->regs + REG_CMDR_FIFO); 244 245 cmd = &xfer->cmds[xfer->ncmds_comp++]; 246 if (cmd->cmd0 & REG_CMD_FIFO_0_RNW) { 247 rx_len = min_t(u32, REG_CMDR_FIFO_XFER_BYTES(cmdr), cmd->rx_len); 248 adi_i3c_master_rd_from_rx_fifo(master, cmd->rx_buf, rx_len); 249 cmd->rx_len = rx_len; 250 } 251 cmd->error = REG_CMDR_FIFO_ERROR(cmdr); 252 } 253 254 for (i = 0; i < xfer->ncmds_comp; i++) { 255 switch (xfer->cmds[i].error) { 256 case REG_CMDR_FIFO_NO_ERROR: 257 break; 258 259 case REG_CMDR_FIFO_CE0_ERROR: 260 case REG_CMDR_FIFO_CE2_ERROR: 261 case REG_CMDR_FIFO_NACK_RESP: 262 case REG_CMDR_FIFO_UDA_ERROR: 263 ret = -EIO; 264 break; 265 266 default: 267 ret = -EINVAL; 268 break; 269 } 270 } 271 272 xfer->ret = ret; 273 274 if (xfer->ncmds_comp != xfer->ncmds) 275 return; 276 277 complete(&xfer->comp); 278 279 xfer = list_first_entry_or_null(&master->xferqueue.list, 280 struct adi_i3c_xfer, node); 281 if (xfer) 282 list_del_init(&xfer->node); 283 284 master->xferqueue.cur = xfer; 285 adi_i3c_master_start_xfer_locked(master); 286 } 287 288 static void adi_i3c_master_queue_xfer(struct adi_i3c_master *master, 289 struct adi_i3c_xfer *xfer) 290 { 291 init_completion(&xfer->comp); 292 guard(spinlock_irqsave)(&master->xferqueue.lock); 293 if (master->xferqueue.cur) { 294 list_add_tail(&xfer->node, &master->xferqueue.list); 295 } else { 296 master->xferqueue.cur = xfer; 297 adi_i3c_master_start_xfer_locked(master); 298 } 299 } 300 301 static void adi_i3c_master_unqueue_xfer(struct adi_i3c_master *master, 302 struct adi_i3c_xfer *xfer) 303 { 304 guard(spinlock_irqsave)(&master->xferqueue.lock); 305 if (master->xferqueue.cur == xfer) 306 master->xferqueue.cur = NULL; 307 else 308 list_del_init(&xfer->node); 309 310 writel(0x01, master->regs + REG_ENABLE); 311 writel(0x00, master->regs + REG_ENABLE); 312 writel(REG_IRQ_PENDING_CMDR, master->regs + REG_IRQ_MASK); 313 } 314 315 static enum i3c_error_code adi_i3c_cmd_get_err(struct adi_i3c_cmd *cmd) 316 { 317 switch (cmd->error) { 318 case REG_CMDR_FIFO_CE0_ERROR: 319 return I3C_ERROR_M0; 320 321 case REG_CMDR_FIFO_CE2_ERROR: 322 case REG_CMDR_FIFO_NACK_RESP: 323 return I3C_ERROR_M2; 324 325 default: 326 break; 327 } 328 329 return I3C_ERROR_UNKNOWN; 330 } 331 332 static int adi_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, 333 struct i3c_ccc_cmd *cmd) 334 { 335 struct adi_i3c_master *master = to_adi_i3c_master(m); 336 struct adi_i3c_cmd *ccmd; 337 338 struct adi_i3c_xfer *xfer __free(kfree) = adi_i3c_master_alloc_xfer(master, 1); 339 if (!xfer) 340 return -ENOMEM; 341 342 ccmd = xfer->cmds; 343 ccmd->cmd1 = REG_CMD_FIFO_1_CCC(cmd->id); 344 ccmd->cmd0 = REG_CMD_FIFO_0_IS_CCC | 345 REG_CMD_FIFO_0_LEN(cmd->dests[0].payload.len); 346 347 if (cmd->id & I3C_CCC_DIRECT) 348 ccmd->cmd0 |= REG_CMD_FIFO_0_DEV_ADDR(cmd->dests[0].addr); 349 350 if (cmd->rnw) { 351 ccmd->cmd0 |= REG_CMD_FIFO_0_RNW; 352 ccmd->rx_buf = cmd->dests[0].payload.data; 353 ccmd->rx_len = cmd->dests[0].payload.len; 354 } else { 355 ccmd->tx_buf = cmd->dests[0].payload.data; 356 ccmd->tx_len = cmd->dests[0].payload.len; 357 } 358 359 adi_i3c_master_queue_xfer(master, xfer); 360 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) 361 adi_i3c_master_unqueue_xfer(master, xfer); 362 363 cmd->err = adi_i3c_cmd_get_err(&xfer->cmds[0]); 364 if (!xfer->ret && cmd->rnw) 365 cmd->dests[0].payload.actual_len = ccmd->rx_len; 366 367 return xfer->ret; 368 } 369 370 static int adi_i3c_master_i3c_xfers(struct i3c_dev_desc *dev, 371 struct i3c_xfer *xfers, 372 int nxfers, enum i3c_xfer_mode mode) 373 { 374 struct i3c_master_controller *m = i3c_dev_get_master(dev); 375 struct adi_i3c_master *master = to_adi_i3c_master(m); 376 int i, ret; 377 378 if (!nxfers) 379 return 0; 380 381 struct adi_i3c_xfer *xfer __free(kfree) = adi_i3c_master_alloc_xfer(master, nxfers); 382 if (!xfer) 383 return -ENOMEM; 384 385 for (i = 0; i < nxfers; i++) { 386 struct adi_i3c_cmd *ccmd = &xfer->cmds[i]; 387 388 ccmd->cmd0 = REG_CMD_FIFO_0_DEV_ADDR(dev->info.dyn_addr); 389 390 if (xfers[i].rnw) { 391 ccmd->cmd0 |= REG_CMD_FIFO_0_RNW; 392 ccmd->rx_buf = xfers[i].data.in; 393 ccmd->rx_len = xfers[i].len; 394 } else { 395 ccmd->tx_buf = xfers[i].data.out; 396 ccmd->tx_len = xfers[i].len; 397 } 398 399 ccmd->cmd0 |= REG_CMD_FIFO_0_LEN(xfers[i].len); 400 401 if (i < nxfers - 1) 402 ccmd->cmd0 |= REG_CMD_FIFO_0_SR; 403 404 if (!i) 405 ccmd->cmd0 |= REG_CMD_FIFO_0_BCAST; 406 } 407 408 adi_i3c_master_queue_xfer(master, xfer); 409 if (!wait_for_completion_timeout(&xfer->comp, 410 msecs_to_jiffies(1000))) 411 adi_i3c_master_unqueue_xfer(master, xfer); 412 413 ret = xfer->ret; 414 415 for (i = 0; i < nxfers; i++) 416 xfers[i].err = adi_i3c_cmd_get_err(&xfer->cmds[i]); 417 418 return ret; 419 } 420 421 struct adi_i3c_i2c_dev_data { 422 struct i3c_generic_ibi_pool *ibi_pool; 423 u16 id; 424 s16 ibi; 425 }; 426 427 static int adi_i3c_master_get_rr_slot(struct adi_i3c_master *master, 428 u8 dyn_addr) 429 { 430 if (!master->free_rr_slots) 431 return -ENOSPC; 432 433 return ffs(master->free_rr_slots) - 1; 434 } 435 436 static int adi_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, u8 dyn_addr) 437 { 438 struct i3c_master_controller *m = i3c_dev_get_master(dev); 439 struct adi_i3c_master *master = to_adi_i3c_master(m); 440 u8 addr; 441 442 addr = dev->info.dyn_addr ? dev->info.dyn_addr : dev->info.static_addr; 443 444 writel(REG_DEV_CHAR_ADDR(dyn_addr), master->regs + REG_DEV_CHAR); 445 writel((readl(master->regs + REG_DEV_CHAR) & 446 ~REG_DEV_CHAR_IS_ATTACHED) | REG_DEV_CHAR_WEN, 447 master->regs + REG_DEV_CHAR); 448 449 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 450 writel(readl(master->regs + REG_DEV_CHAR) | 451 REG_DEV_CHAR_IS_ATTACHED | REG_DEV_CHAR_WEN, 452 master->regs + REG_DEV_CHAR); 453 454 return 0; 455 } 456 457 static int adi_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev) 458 { 459 struct i3c_master_controller *m = i3c_dev_get_master(dev); 460 struct adi_i3c_master *master = to_adi_i3c_master(m); 461 struct adi_i3c_i2c_dev_data *data; 462 int slot; 463 u8 addr; 464 465 data = kzalloc_obj(*data); 466 if (!data) 467 return -ENOMEM; 468 469 slot = adi_i3c_master_get_rr_slot(master, dev->info.dyn_addr); 470 if (slot < 0) { 471 kfree(data); 472 return slot; 473 } 474 475 data->id = slot; 476 i3c_dev_set_master_data(dev, data); 477 master->free_rr_slots &= ~BIT(slot); 478 479 addr = dev->info.dyn_addr ? dev->info.dyn_addr : dev->info.static_addr; 480 481 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 482 writel(readl(master->regs + REG_DEV_CHAR) | 483 REG_DEV_CHAR_IS_ATTACHED | REG_DEV_CHAR_WEN, 484 master->regs + REG_DEV_CHAR); 485 486 return 0; 487 } 488 489 static void adi_i3c_master_sync_dev_char(struct i3c_master_controller *m) 490 { 491 struct adi_i3c_master *master = to_adi_i3c_master(m); 492 struct i3c_dev_desc *i3cdev; 493 u32 bcr_ibi; 494 u8 addr; 495 496 i3c_bus_for_each_i3cdev(&m->bus, i3cdev) { 497 addr = i3cdev->info.dyn_addr ? 498 i3cdev->info.dyn_addr : i3cdev->info.static_addr; 499 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 500 bcr_ibi = FIELD_GET(I3C_BCR_IBI_PAYLOAD | I3C_BCR_IBI_REQ_CAP, (i3cdev->info.bcr)); 501 writel(readl(master->regs + REG_DEV_CHAR) | 502 REG_DEV_CHAR_BCR_IBI(bcr_ibi) | REG_DEV_CHAR_WEN, 503 master->regs + REG_DEV_CHAR); 504 } 505 } 506 507 static void adi_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) 508 { 509 struct i3c_master_controller *m = i3c_dev_get_master(dev); 510 struct adi_i3c_master *master = to_adi_i3c_master(m); 511 struct adi_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 512 u8 addr; 513 514 addr = dev->info.dyn_addr ? dev->info.dyn_addr : dev->info.static_addr; 515 516 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 517 writel((readl(master->regs + REG_DEV_CHAR) & 518 ~REG_DEV_CHAR_IS_ATTACHED) | REG_DEV_CHAR_WEN, 519 master->regs + REG_DEV_CHAR); 520 521 i3c_dev_set_master_data(dev, NULL); 522 master->free_rr_slots |= BIT(data->id); 523 kfree(data); 524 } 525 526 static int adi_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) 527 { 528 struct i3c_master_controller *m = i2c_dev_get_master(dev); 529 struct adi_i3c_master *master = to_adi_i3c_master(m); 530 struct adi_i3c_i2c_dev_data *data; 531 int slot; 532 533 slot = adi_i3c_master_get_rr_slot(master, 0); 534 if (slot < 0) 535 return slot; 536 537 data = kzalloc_obj(*data); 538 if (!data) 539 return -ENOMEM; 540 541 data->id = slot; 542 master->free_rr_slots &= ~BIT(slot); 543 i2c_dev_set_master_data(dev, data); 544 545 writel(REG_DEV_CHAR_ADDR(dev->addr) | 546 REG_DEV_CHAR_IS_I2C | REG_DEV_CHAR_IS_ATTACHED | REG_DEV_CHAR_WEN, 547 master->regs + REG_DEV_CHAR); 548 549 return 0; 550 } 551 552 static void adi_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) 553 { 554 struct i3c_master_controller *m = i2c_dev_get_master(dev); 555 struct adi_i3c_master *master = to_adi_i3c_master(m); 556 struct adi_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 557 558 writel(REG_DEV_CHAR_ADDR(dev->addr) | 559 REG_DEV_CHAR_IS_I2C | REG_DEV_CHAR_WEN, 560 master->regs + REG_DEV_CHAR); 561 562 i2c_dev_set_master_data(dev, NULL); 563 master->free_rr_slots |= BIT(data->id); 564 kfree(data); 565 } 566 567 static void adi_i3c_master_bus_cleanup(struct i3c_master_controller *m) 568 { 569 struct adi_i3c_master *master = to_adi_i3c_master(m); 570 571 adi_i3c_master_disable(master); 572 } 573 574 static void adi_i3c_master_upd_i3c_scl_lim(struct adi_i3c_master *master) 575 { 576 struct i3c_master_controller *m = &master->base; 577 struct i3c_bus *bus = i3c_master_get_bus(m); 578 u8 i3c_scl_lim = 0; 579 struct i3c_dev_desc *dev; 580 u8 pp_sg; 581 582 i3c_bus_for_each_i3cdev(bus, dev) { 583 u8 max_fscl; 584 585 max_fscl = max(I3C_CCC_MAX_SDR_FSCL(dev->info.max_read_ds), 586 I3C_CCC_MAX_SDR_FSCL(dev->info.max_write_ds)); 587 588 switch (max_fscl) { 589 case I3C_SDR1_FSCL_8MHZ: 590 max_fscl = PP_SG_6MHZ; 591 break; 592 case I3C_SDR2_FSCL_6MHZ: 593 max_fscl = PP_SG_3MHZ; 594 break; 595 case I3C_SDR3_FSCL_4MHZ: 596 max_fscl = PP_SG_3MHZ; 597 break; 598 case I3C_SDR4_FSCL_2MHZ: 599 max_fscl = PP_SG_1MHZ; 600 break; 601 case I3C_SDR0_FSCL_MAX: 602 default: 603 max_fscl = PP_SG_12MHZ; 604 break; 605 } 606 607 if (max_fscl && 608 (i3c_scl_lim > max_fscl || !i3c_scl_lim)) 609 i3c_scl_lim = max_fscl; 610 } 611 612 if (!i3c_scl_lim) 613 return; 614 615 master->i3c_scl_lim = i3c_scl_lim - 1; 616 617 pp_sg = readl(master->regs + REG_OPS) & ~REG_OPS_PP_SG_MASK; 618 pp_sg |= REG_OPS_SET_SG(master->i3c_scl_lim); 619 620 writel(pp_sg, master->regs + REG_OPS); 621 } 622 623 static void adi_i3c_master_get_features(struct adi_i3c_master *master, 624 unsigned int slot, 625 struct i3c_device_info *info) 626 { 627 u32 buf; 628 629 /* Dynamic address and PID are for identification only */ 630 memset(info, 0, sizeof(*info)); 631 buf = readl(master->regs + REG_DCR_BCR_DA); 632 info->dyn_addr = REG_DCR_BCR_DA_GET_DA(buf); 633 info->dcr = REG_DCR_BCR_DA_GET_DCR(buf); 634 info->bcr = REG_DCR_BCR_DA_GET_BCR(buf); 635 info->pid = readl(master->regs + REG_PID_L); 636 info->pid |= (u64)readl(master->regs + REG_PID_H) << 32; 637 } 638 639 static int adi_i3c_master_do_daa(struct i3c_master_controller *m) 640 { 641 struct adi_i3c_master *master = to_adi_i3c_master(m); 642 int ret, addr = 0; 643 u32 irq_mask; 644 645 for (u8 i = 0; i < ADI_MAX_DEVS; i++) { 646 addr = i3c_master_get_free_addr(m, addr); 647 if (addr < 0) 648 return addr; 649 master->daa.addrs[i] = addr; 650 } 651 652 irq_mask = readl(master->regs + REG_IRQ_MASK); 653 writel(irq_mask | REG_IRQ_PENDING_DAA, 654 master->regs + REG_IRQ_MASK); 655 656 master->daa.index = 0; 657 ret = i3c_master_entdaa_locked(&master->base); 658 659 writel(irq_mask, master->regs + REG_IRQ_MASK); 660 661 if (ret) 662 return ret; 663 664 /* Add I3C devices discovered */ 665 for (u8 i = 0; i < master->daa.index; i++) 666 i3c_master_add_i3c_dev_locked(m, master->daa.addrs[i]); 667 /* Sync retrieved devs info with the IP */ 668 adi_i3c_master_sync_dev_char(m); 669 670 i3c_master_defslvs_locked(&master->base); 671 672 adi_i3c_master_upd_i3c_scl_lim(master); 673 674 return 0; 675 } 676 677 static int adi_i3c_master_bus_init(struct i3c_master_controller *m) 678 { 679 struct adi_i3c_master *master = to_adi_i3c_master(m); 680 struct i3c_device_info info = { }; 681 int ret; 682 683 ret = i3c_master_get_free_addr(m, 0); 684 if (ret < 0) 685 return ret; 686 687 adi_i3c_master_get_features(master, 0, &info); 688 ret = i3c_master_set_info(&master->base, &info); 689 if (ret) 690 return ret; 691 692 writel(REG_IBI_CONFIG_LISTEN, 693 master->regs + REG_IBI_CONFIG); 694 695 return 0; 696 } 697 698 static void adi_i3c_master_handle_ibi(struct adi_i3c_master *master, 699 u32 raw) 700 { 701 struct adi_i3c_i2c_dev_data *data; 702 struct i3c_ibi_slot *slot; 703 struct i3c_dev_desc *dev; 704 u8 da, id, mdb, len; 705 u8 *buf; 706 707 da = FIELD_GET(GENMASK(23, 17), raw); 708 mdb = FIELD_GET(GENMASK(15, 8), raw); 709 for (id = 0; id < master->ibi.num_slots; id++) { 710 if (master->ibi.slots[id] && 711 master->ibi.slots[id]->info.dyn_addr == da) 712 break; 713 } 714 715 if (id == master->ibi.num_slots) 716 return; 717 718 dev = master->ibi.slots[id]; 719 len = ADI_HAS_MDB_FROM_BCR(dev->info.bcr); 720 data = i3c_dev_get_master_data(dev); 721 722 guard(spinlock)(&master->ibi.lock); 723 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool); 724 if (!slot) 725 return; 726 727 slot->len = len; 728 buf = slot->data; 729 buf[0] = mdb; 730 i3c_master_queue_ibi(dev, slot); 731 } 732 733 static void adi_i3c_master_demux_ibis(struct adi_i3c_master *master) 734 { 735 while (!(readl(master->regs + REG_FIFO_STATUS) & REG_FIFO_STATUS_IBI_EMPTY)) { 736 u32 raw = readl(master->regs + REG_IBI_FIFO); 737 738 adi_i3c_master_handle_ibi(master, raw); 739 } 740 } 741 742 static void adi_i3c_master_handle_da_req(struct adi_i3c_master *master) 743 { 744 u8 payload0[8]; 745 u32 addr; 746 747 adi_i3c_master_rd_from_rx_fifo(master, payload0, 6); 748 addr = master->daa.addrs[master->daa.index++]; 749 addr = (addr << 1) | (parity8(addr) ? 0 : 1); 750 751 writel(addr, master->regs + REG_SDO_FIFO); 752 } 753 754 static irqreturn_t adi_i3c_master_irq(int irq, void *data) 755 { 756 struct adi_i3c_master *master = data; 757 u32 pending; 758 759 pending = readl(master->regs + REG_IRQ_PENDING); 760 writel(pending, master->regs + REG_IRQ_PENDING); 761 if (pending & REG_IRQ_PENDING_CMDR) { 762 scoped_guard(spinlock_irqsave, &master->xferqueue.lock) { 763 adi_i3c_master_end_xfer_locked(master, pending); 764 } 765 } 766 if (pending & REG_IRQ_PENDING_IBI) 767 adi_i3c_master_demux_ibis(master); 768 if (pending & REG_IRQ_PENDING_DAA) 769 adi_i3c_master_handle_da_req(master); 770 771 return IRQ_HANDLED; 772 } 773 774 static int adi_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, 775 struct i2c_msg *xfers, 776 int nxfers) 777 { 778 struct i3c_master_controller *m = i2c_dev_get_master(dev); 779 struct adi_i3c_master *master = to_adi_i3c_master(m); 780 int i; 781 782 if (!nxfers) 783 return 0; 784 for (i = 0; i < nxfers; i++) { 785 if (xfers[i].flags & I2C_M_TEN) 786 return -EOPNOTSUPP; 787 } 788 789 struct adi_i3c_xfer *xfer __free(kfree) = adi_i3c_master_alloc_xfer(master, nxfers); 790 if (!xfer) 791 return -ENOMEM; 792 793 for (i = 0; i < nxfers; i++) { 794 struct adi_i3c_cmd *ccmd = &xfer->cmds[i]; 795 796 ccmd->cmd0 = REG_CMD_FIFO_0_DEV_ADDR(xfers[i].addr); 797 798 if (xfers[i].flags & I2C_M_RD) { 799 ccmd->cmd0 |= REG_CMD_FIFO_0_RNW; 800 ccmd->rx_buf = xfers[i].buf; 801 ccmd->rx_len = xfers[i].len; 802 } else { 803 ccmd->tx_buf = xfers[i].buf; 804 ccmd->tx_len = xfers[i].len; 805 } 806 807 ccmd->cmd0 |= REG_CMD_FIFO_0_LEN(xfers[i].len); 808 } 809 810 adi_i3c_master_queue_xfer(master, xfer); 811 if (!wait_for_completion_timeout(&xfer->comp, 812 m->i2c.timeout)) 813 adi_i3c_master_unqueue_xfer(master, xfer); 814 815 return xfer->ret; 816 } 817 818 static int adi_i3c_master_disable_ibi(struct i3c_dev_desc *dev) 819 { 820 struct i3c_master_controller *m = i3c_dev_get_master(dev); 821 struct adi_i3c_master *master = to_adi_i3c_master(m); 822 struct i3c_dev_desc *i3cdev; 823 u32 enabled = 0; 824 int ret; 825 826 ret = i3c_master_disec_locked(m, dev->info.dyn_addr, 827 I3C_CCC_EVENT_SIR); 828 829 i3c_bus_for_each_i3cdev(&m->bus, i3cdev) { 830 if (dev != i3cdev && i3cdev->ibi) 831 enabled |= i3cdev->ibi->enabled; 832 } 833 if (!enabled) { 834 writel(REG_IBI_CONFIG_LISTEN, 835 master->regs + REG_IBI_CONFIG); 836 writel(readl(master->regs + REG_IRQ_MASK) & ~REG_IRQ_PENDING_IBI, 837 master->regs + REG_IRQ_MASK); 838 } 839 840 return ret; 841 } 842 843 static int adi_i3c_master_enable_ibi(struct i3c_dev_desc *dev) 844 { 845 struct i3c_master_controller *m = i3c_dev_get_master(dev); 846 struct adi_i3c_master *master = to_adi_i3c_master(m); 847 848 writel(REG_IBI_CONFIG_LISTEN | REG_IBI_CONFIG_ENABLE, 849 master->regs + REG_IBI_CONFIG); 850 851 writel(readl(master->regs + REG_IRQ_MASK) | REG_IRQ_PENDING_IBI, 852 master->regs + REG_IRQ_MASK); 853 854 return i3c_master_enec_locked(m, dev->info.dyn_addr, 855 I3C_CCC_EVENT_SIR); 856 } 857 858 static int adi_i3c_master_request_ibi(struct i3c_dev_desc *dev, 859 const struct i3c_ibi_setup *req) 860 { 861 struct i3c_master_controller *m = i3c_dev_get_master(dev); 862 struct adi_i3c_master *master = to_adi_i3c_master(m); 863 struct adi_i3c_i2c_dev_data *data; 864 unsigned int i; 865 866 data = i3c_dev_get_master_data(dev); 867 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); 868 if (IS_ERR(data->ibi_pool)) 869 return PTR_ERR(data->ibi_pool); 870 871 scoped_guard(spinlock_irqsave, &master->ibi.lock) { 872 for (i = 0; i < master->ibi.num_slots; i++) { 873 if (!master->ibi.slots[i]) { 874 data->ibi = i; 875 master->ibi.slots[i] = dev; 876 break; 877 } 878 } 879 } 880 881 if (i < master->ibi.num_slots) 882 return 0; 883 884 i3c_generic_ibi_free_pool(data->ibi_pool); 885 data->ibi_pool = NULL; 886 887 return -ENOSPC; 888 } 889 890 static void adi_i3c_master_free_ibi(struct i3c_dev_desc *dev) 891 { 892 struct i3c_master_controller *m = i3c_dev_get_master(dev); 893 struct adi_i3c_master *master = to_adi_i3c_master(m); 894 struct adi_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 895 896 scoped_guard(spinlock_irqsave, &master->ibi.lock) { 897 master->ibi.slots[data->ibi] = NULL; 898 } 899 900 i3c_generic_ibi_free_pool(data->ibi_pool); 901 } 902 903 static void adi_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev, 904 struct i3c_ibi_slot *slot) 905 { 906 struct adi_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 907 908 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot); 909 } 910 911 static const struct i3c_master_controller_ops adi_i3c_master_ops = { 912 .bus_init = adi_i3c_master_bus_init, 913 .bus_cleanup = adi_i3c_master_bus_cleanup, 914 .attach_i3c_dev = adi_i3c_master_attach_i3c_dev, 915 .reattach_i3c_dev = adi_i3c_master_reattach_i3c_dev, 916 .detach_i3c_dev = adi_i3c_master_detach_i3c_dev, 917 .attach_i2c_dev = adi_i3c_master_attach_i2c_dev, 918 .detach_i2c_dev = adi_i3c_master_detach_i2c_dev, 919 .do_daa = adi_i3c_master_do_daa, 920 .supports_ccc_cmd = adi_i3c_master_supports_ccc_cmd, 921 .send_ccc_cmd = adi_i3c_master_send_ccc_cmd, 922 .i3c_xfers = adi_i3c_master_i3c_xfers, 923 .i2c_xfers = adi_i3c_master_i2c_xfers, 924 .request_ibi = adi_i3c_master_request_ibi, 925 .enable_ibi = adi_i3c_master_enable_ibi, 926 .disable_ibi = adi_i3c_master_disable_ibi, 927 .free_ibi = adi_i3c_master_free_ibi, 928 .recycle_ibi_slot = adi_i3c_master_recycle_ibi_slot, 929 }; 930 931 static const struct of_device_id adi_i3c_master_of_match[] = { 932 { .compatible = "adi,i3c-master-v1" }, 933 {} 934 }; 935 MODULE_DEVICE_TABLE(of, adi_i3c_master_of_match); 936 937 static int adi_i3c_master_probe(struct platform_device *pdev) 938 { 939 struct adi_i3c_master *master; 940 struct clk_bulk_data *clk; 941 unsigned int version; 942 int ret, irq; 943 944 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 945 if (!master) 946 return -ENOMEM; 947 948 master->regs = devm_platform_ioremap_resource(pdev, 0); 949 if (IS_ERR(master->regs)) 950 return PTR_ERR(master->regs); 951 952 ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clk); 953 if (ret < 0) 954 return dev_err_probe(&pdev->dev, ret, 955 "Failed to get clocks\n"); 956 957 irq = platform_get_irq(pdev, 0); 958 if (irq < 0) 959 return irq; 960 961 version = readl(master->regs + ADI_AXI_REG_VERSION); 962 if (ADI_AXI_PCORE_VER_MAJOR(version) != 1) 963 dev_err_probe(&pdev->dev, -ENODEV, "Unsupported peripheral version %u.%u.%u\n", 964 ADI_AXI_PCORE_VER_MAJOR(version), 965 ADI_AXI_PCORE_VER_MINOR(version), 966 ADI_AXI_PCORE_VER_PATCH(version)); 967 968 writel(0x00, master->regs + REG_ENABLE); 969 writel(0x00, master->regs + REG_IRQ_MASK); 970 971 platform_set_drvdata(pdev, master); 972 973 master->free_rr_slots = GENMASK(ADI_MAX_DEVS, 1); 974 spin_lock_init(&master->ibi.lock); 975 master->ibi.num_slots = 15; 976 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots, 977 sizeof(*master->ibi.slots), 978 GFP_KERNEL); 979 if (!master->ibi.slots) 980 return -ENOMEM; 981 982 spin_lock_init(&master->xferqueue.lock); 983 INIT_LIST_HEAD(&master->xferqueue.list); 984 985 ret = devm_request_irq(&pdev->dev, irq, adi_i3c_master_irq, 0, 986 dev_name(&pdev->dev), master); 987 if (ret) 988 return ret; 989 990 writel(REG_IRQ_PENDING_CMDR, master->regs + REG_IRQ_MASK); 991 992 return i3c_master_register(&master->base, &pdev->dev, 993 &adi_i3c_master_ops, false); 994 } 995 996 static void adi_i3c_master_remove(struct platform_device *pdev) 997 { 998 struct adi_i3c_master *master = platform_get_drvdata(pdev); 999 1000 writel(0xff, master->regs + REG_IRQ_PENDING); 1001 writel(0x00, master->regs + REG_IRQ_MASK); 1002 writel(0x01, master->regs + REG_ENABLE); 1003 1004 i3c_master_unregister(&master->base); 1005 } 1006 1007 static struct platform_driver adi_i3c_master = { 1008 .probe = adi_i3c_master_probe, 1009 .remove = adi_i3c_master_remove, 1010 .driver = { 1011 .name = "adi-i3c-master", 1012 .of_match_table = adi_i3c_master_of_match, 1013 }, 1014 }; 1015 module_platform_driver(adi_i3c_master); 1016 1017 MODULE_AUTHOR("Jorge Marques <jorge.marques@analog.com>"); 1018 MODULE_DESCRIPTION("Analog Devices I3C master driver"); 1019 MODULE_LICENSE("GPL"); 1020