1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * I3C Controller driver 4 * Copyright 2025 Analog Devices Inc. 5 * Author: Jorge Marques <jorge.marques@analog.com> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/err.h> 12 #include <linux/errno.h> 13 #include <linux/adi-axi-common.h> 14 #include <linux/i3c/master.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 21 #include "../internals.h" 22 23 #define ADI_MAX_DEVS 16 24 #define ADI_HAS_MDB_FROM_BCR(x) (FIELD_GET(BIT(2), (x))) 25 26 #define REG_ENABLE 0x040 27 28 #define REG_PID_L 0x054 29 #define REG_PID_H 0x058 30 #define REG_DCR_BCR_DA 0x05c 31 #define REG_DCR_BCR_DA_GET_DA(x) FIELD_GET(GENMASK(22, 16), (x)) 32 #define REG_DCR_BCR_DA_GET_BCR(x) FIELD_GET(GENMASK(15, 8), (x)) 33 #define REG_DCR_BCR_DA_GET_DCR(x) FIELD_GET(GENMASK(7, 0), (x)) 34 35 #define REG_IRQ_MASK 0x080 36 #define REG_IRQ_PENDING 0x084 37 #define REG_IRQ_PENDING_DAA BIT(7) 38 #define REG_IRQ_PENDING_IBI BIT(6) 39 #define REG_IRQ_PENDING_CMDR BIT(5) 40 41 #define REG_CMD_FIFO 0x0d4 42 #define REG_CMD_FIFO_0_IS_CCC BIT(22) 43 #define REG_CMD_FIFO_0_BCAST BIT(21) 44 #define REG_CMD_FIFO_0_SR BIT(20) 45 #define REG_CMD_FIFO_0_LEN(l) FIELD_PREP(GENMASK(19, 8), (l)) 46 #define REG_CMD_FIFO_0_DEV_ADDR(a) FIELD_PREP(GENMASK(7, 1), (a)) 47 #define REG_CMD_FIFO_0_RNW BIT(0) 48 #define REG_CMD_FIFO_1_CCC(id) FIELD_PREP(GENMASK(7, 0), (id)) 49 50 #define REG_CMD_FIFO_ROOM 0x0c0 51 #define REG_CMDR_FIFO 0x0d8 52 #define REG_CMDR_FIFO_UDA_ERROR 8 53 #define REG_CMDR_FIFO_NACK_RESP 6 54 #define REG_CMDR_FIFO_CE2_ERROR 4 55 #define REG_CMDR_FIFO_CE0_ERROR 1 56 #define REG_CMDR_FIFO_NO_ERROR 0 57 #define REG_CMDR_FIFO_ERROR(x) FIELD_GET(GENMASK(23, 20), (x)) 58 #define REG_CMDR_FIFO_XFER_BYTES(x) FIELD_GET(GENMASK(19, 8), (x)) 59 60 #define REG_SDO_FIFO 0x0dc 61 #define REG_SDO_FIFO_ROOM 0x0c8 62 #define REG_SDI_FIFO 0x0e0 63 #define REG_IBI_FIFO 0x0e4 64 #define REG_FIFO_STATUS 0x0e8 65 #define REG_FIFO_STATUS_CMDR_EMPTY BIT(0) 66 #define REG_FIFO_STATUS_IBI_EMPTY BIT(1) 67 68 #define REG_OPS 0x100 69 #define REG_OPS_PP_SG_MASK GENMASK(6, 5) 70 #define REG_OPS_SET_SG(x) FIELD_PREP(REG_OPS_PP_SG_MASK, (x)) 71 72 #define REG_IBI_CONFIG 0x140 73 #define REG_IBI_CONFIG_ENABLE BIT(0) 74 #define REG_IBI_CONFIG_LISTEN BIT(1) 75 76 #define REG_DEV_CHAR 0x180 77 #define REG_DEV_CHAR_IS_I2C BIT(0) 78 #define REG_DEV_CHAR_IS_ATTACHED BIT(1) 79 #define REG_DEV_CHAR_BCR_IBI(x) FIELD_PREP(GENMASK(3, 2), (x)) 80 #define REG_DEV_CHAR_WEN BIT(8) 81 #define REG_DEV_CHAR_ADDR(x) FIELD_PREP(GENMASK(15, 9), (x)) 82 83 enum speed_grade {PP_SG_UNSET, PP_SG_1MHZ, PP_SG_3MHZ, PP_SG_6MHZ, PP_SG_12MHZ}; 84 85 struct adi_i3c_cmd { 86 u32 cmd0; 87 u32 cmd1; 88 u32 tx_len; 89 const void *tx_buf; 90 u32 rx_len; 91 void *rx_buf; 92 u32 error; 93 }; 94 95 struct adi_i3c_xfer { 96 struct list_head node; 97 struct completion comp; 98 int ret; 99 unsigned int ncmds; 100 unsigned int ncmds_comp; 101 struct adi_i3c_cmd cmds[] __counted_by(ncmds); 102 }; 103 104 struct adi_i3c_master { 105 struct i3c_master_controller base; 106 u32 free_rr_slots; 107 struct { 108 unsigned int num_slots; 109 struct i3c_dev_desc **slots; 110 spinlock_t lock; /* Protect IBI slot access */ 111 } ibi; 112 struct { 113 struct list_head list; 114 struct adi_i3c_xfer *cur; 115 spinlock_t lock; /* Protect transfer */ 116 } xferqueue; 117 void __iomem *regs; 118 struct clk *clk; 119 unsigned long i3c_scl_lim; 120 struct { 121 u8 addrs[ADI_MAX_DEVS]; 122 u8 index; 123 } daa; 124 }; 125 126 static inline struct adi_i3c_master *to_adi_i3c_master(struct i3c_master_controller *master) 127 { 128 return container_of(master, struct adi_i3c_master, base); 129 } 130 131 static void adi_i3c_master_wr_to_tx_fifo(struct adi_i3c_master *master, 132 const u8 *buf, unsigned int nbytes) 133 { 134 unsigned int n, m; 135 136 n = readl(master->regs + REG_SDO_FIFO_ROOM); 137 m = min(n, nbytes); 138 i3c_writel_fifo(master->regs + REG_SDO_FIFO, buf, m); 139 } 140 141 static void adi_i3c_master_rd_from_rx_fifo(struct adi_i3c_master *master, 142 u8 *buf, unsigned int nbytes) 143 { 144 i3c_readl_fifo(master->regs + REG_SDI_FIFO, buf, nbytes); 145 } 146 147 static bool adi_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m, 148 const struct i3c_ccc_cmd *cmd) 149 { 150 if (cmd->ndests > 1) 151 return false; 152 153 switch (cmd->id) { 154 case I3C_CCC_ENEC(true): 155 case I3C_CCC_ENEC(false): 156 case I3C_CCC_DISEC(true): 157 case I3C_CCC_DISEC(false): 158 case I3C_CCC_RSTDAA(true): 159 case I3C_CCC_RSTDAA(false): 160 case I3C_CCC_ENTDAA: 161 case I3C_CCC_SETDASA: 162 case I3C_CCC_SETNEWDA: 163 case I3C_CCC_GETMWL: 164 case I3C_CCC_GETMRL: 165 case I3C_CCC_GETPID: 166 case I3C_CCC_GETBCR: 167 case I3C_CCC_GETDCR: 168 case I3C_CCC_GETSTATUS: 169 case I3C_CCC_GETHDRCAP: 170 return true; 171 default: 172 break; 173 } 174 175 return false; 176 } 177 178 static int adi_i3c_master_disable(struct adi_i3c_master *master) 179 { 180 writel(0, master->regs + REG_IBI_CONFIG); 181 182 return 0; 183 } 184 185 static struct adi_i3c_xfer *adi_i3c_master_alloc_xfer(struct adi_i3c_master *master, 186 unsigned int ncmds) 187 { 188 struct adi_i3c_xfer *xfer; 189 190 xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL); 191 if (!xfer) 192 return NULL; 193 194 INIT_LIST_HEAD(&xfer->node); 195 xfer->ncmds = ncmds; 196 xfer->ret = -ETIMEDOUT; 197 198 return xfer; 199 } 200 201 static void adi_i3c_master_start_xfer_locked(struct adi_i3c_master *master) 202 { 203 struct adi_i3c_xfer *xfer = master->xferqueue.cur; 204 unsigned int i, n, m; 205 206 if (!xfer) 207 return; 208 209 for (i = 0; i < xfer->ncmds; i++) { 210 struct adi_i3c_cmd *cmd = &xfer->cmds[i]; 211 212 if (!(cmd->cmd0 & REG_CMD_FIFO_0_RNW)) 213 adi_i3c_master_wr_to_tx_fifo(master, cmd->tx_buf, cmd->tx_len); 214 } 215 216 n = readl(master->regs + REG_CMD_FIFO_ROOM); 217 for (i = 0; i < xfer->ncmds; i++) { 218 struct adi_i3c_cmd *cmd = &xfer->cmds[i]; 219 220 m = cmd->cmd0 & REG_CMD_FIFO_0_IS_CCC ? 2 : 1; 221 if (m > n) 222 break; 223 writel(cmd->cmd0, master->regs + REG_CMD_FIFO); 224 if (cmd->cmd0 & REG_CMD_FIFO_0_IS_CCC) 225 writel(cmd->cmd1, master->regs + REG_CMD_FIFO); 226 n -= m; 227 } 228 } 229 230 static void adi_i3c_master_end_xfer_locked(struct adi_i3c_master *master, 231 u32 pending) 232 { 233 struct adi_i3c_xfer *xfer = master->xferqueue.cur; 234 int i, ret = 0; 235 236 if (!xfer) 237 return; 238 239 while (!(readl(master->regs + REG_FIFO_STATUS) & REG_FIFO_STATUS_CMDR_EMPTY)) { 240 struct adi_i3c_cmd *cmd; 241 u32 cmdr, rx_len; 242 243 cmdr = readl(master->regs + REG_CMDR_FIFO); 244 245 cmd = &xfer->cmds[xfer->ncmds_comp++]; 246 if (cmd->cmd0 & REG_CMD_FIFO_0_RNW) { 247 rx_len = min_t(u32, REG_CMDR_FIFO_XFER_BYTES(cmdr), cmd->rx_len); 248 adi_i3c_master_rd_from_rx_fifo(master, cmd->rx_buf, rx_len); 249 } 250 cmd->error = REG_CMDR_FIFO_ERROR(cmdr); 251 } 252 253 for (i = 0; i < xfer->ncmds_comp; i++) { 254 switch (xfer->cmds[i].error) { 255 case REG_CMDR_FIFO_NO_ERROR: 256 break; 257 258 case REG_CMDR_FIFO_CE0_ERROR: 259 case REG_CMDR_FIFO_CE2_ERROR: 260 case REG_CMDR_FIFO_NACK_RESP: 261 case REG_CMDR_FIFO_UDA_ERROR: 262 ret = -EIO; 263 break; 264 265 default: 266 ret = -EINVAL; 267 break; 268 } 269 } 270 271 xfer->ret = ret; 272 273 if (xfer->ncmds_comp != xfer->ncmds) 274 return; 275 276 complete(&xfer->comp); 277 278 xfer = list_first_entry_or_null(&master->xferqueue.list, 279 struct adi_i3c_xfer, node); 280 if (xfer) 281 list_del_init(&xfer->node); 282 283 master->xferqueue.cur = xfer; 284 adi_i3c_master_start_xfer_locked(master); 285 } 286 287 static void adi_i3c_master_queue_xfer(struct adi_i3c_master *master, 288 struct adi_i3c_xfer *xfer) 289 { 290 init_completion(&xfer->comp); 291 guard(spinlock_irqsave)(&master->xferqueue.lock); 292 if (master->xferqueue.cur) { 293 list_add_tail(&xfer->node, &master->xferqueue.list); 294 } else { 295 master->xferqueue.cur = xfer; 296 adi_i3c_master_start_xfer_locked(master); 297 } 298 } 299 300 static void adi_i3c_master_unqueue_xfer(struct adi_i3c_master *master, 301 struct adi_i3c_xfer *xfer) 302 { 303 guard(spinlock_irqsave)(&master->xferqueue.lock); 304 if (master->xferqueue.cur == xfer) 305 master->xferqueue.cur = NULL; 306 else 307 list_del_init(&xfer->node); 308 309 writel(0x01, master->regs + REG_ENABLE); 310 writel(0x00, master->regs + REG_ENABLE); 311 writel(REG_IRQ_PENDING_CMDR, master->regs + REG_IRQ_MASK); 312 } 313 314 static enum i3c_error_code adi_i3c_cmd_get_err(struct adi_i3c_cmd *cmd) 315 { 316 switch (cmd->error) { 317 case REG_CMDR_FIFO_CE0_ERROR: 318 return I3C_ERROR_M0; 319 320 case REG_CMDR_FIFO_CE2_ERROR: 321 case REG_CMDR_FIFO_NACK_RESP: 322 return I3C_ERROR_M2; 323 324 default: 325 break; 326 } 327 328 return I3C_ERROR_UNKNOWN; 329 } 330 331 static int adi_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, 332 struct i3c_ccc_cmd *cmd) 333 { 334 struct adi_i3c_master *master = to_adi_i3c_master(m); 335 struct adi_i3c_xfer *xfer __free(kfree) = NULL; 336 struct adi_i3c_cmd *ccmd; 337 338 xfer = adi_i3c_master_alloc_xfer(master, 1); 339 if (!xfer) 340 return -ENOMEM; 341 342 ccmd = xfer->cmds; 343 ccmd->cmd1 = REG_CMD_FIFO_1_CCC(cmd->id); 344 ccmd->cmd0 = REG_CMD_FIFO_0_IS_CCC | 345 REG_CMD_FIFO_0_LEN(cmd->dests[0].payload.len); 346 347 if (cmd->id & I3C_CCC_DIRECT) 348 ccmd->cmd0 |= REG_CMD_FIFO_0_DEV_ADDR(cmd->dests[0].addr); 349 350 if (cmd->rnw) { 351 ccmd->cmd0 |= REG_CMD_FIFO_0_RNW; 352 ccmd->rx_buf = cmd->dests[0].payload.data; 353 ccmd->rx_len = cmd->dests[0].payload.len; 354 } else { 355 ccmd->tx_buf = cmd->dests[0].payload.data; 356 ccmd->tx_len = cmd->dests[0].payload.len; 357 } 358 359 adi_i3c_master_queue_xfer(master, xfer); 360 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) 361 adi_i3c_master_unqueue_xfer(master, xfer); 362 363 cmd->err = adi_i3c_cmd_get_err(&xfer->cmds[0]); 364 365 return 0; 366 } 367 368 static int adi_i3c_master_priv_xfers(struct i3c_dev_desc *dev, 369 struct i3c_priv_xfer *xfers, 370 int nxfers) 371 { 372 struct i3c_master_controller *m = i3c_dev_get_master(dev); 373 struct adi_i3c_master *master = to_adi_i3c_master(m); 374 struct adi_i3c_xfer *xfer __free(kfree) = NULL; 375 int i, ret; 376 377 if (!nxfers) 378 return 0; 379 380 xfer = adi_i3c_master_alloc_xfer(master, nxfers); 381 if (!xfer) 382 return -ENOMEM; 383 384 for (i = 0; i < nxfers; i++) { 385 struct adi_i3c_cmd *ccmd = &xfer->cmds[i]; 386 387 ccmd->cmd0 = REG_CMD_FIFO_0_DEV_ADDR(dev->info.dyn_addr); 388 389 if (xfers[i].rnw) { 390 ccmd->cmd0 |= REG_CMD_FIFO_0_RNW; 391 ccmd->rx_buf = xfers[i].data.in; 392 ccmd->rx_len = xfers[i].len; 393 } else { 394 ccmd->tx_buf = xfers[i].data.out; 395 ccmd->tx_len = xfers[i].len; 396 } 397 398 ccmd->cmd0 |= REG_CMD_FIFO_0_LEN(xfers[i].len); 399 400 if (i < nxfers - 1) 401 ccmd->cmd0 |= REG_CMD_FIFO_0_SR; 402 403 if (!i) 404 ccmd->cmd0 |= REG_CMD_FIFO_0_BCAST; 405 } 406 407 adi_i3c_master_queue_xfer(master, xfer); 408 if (!wait_for_completion_timeout(&xfer->comp, 409 msecs_to_jiffies(1000))) 410 adi_i3c_master_unqueue_xfer(master, xfer); 411 412 ret = xfer->ret; 413 414 for (i = 0; i < nxfers; i++) 415 xfers[i].err = adi_i3c_cmd_get_err(&xfer->cmds[i]); 416 417 return ret; 418 } 419 420 struct adi_i3c_i2c_dev_data { 421 struct i3c_generic_ibi_pool *ibi_pool; 422 u16 id; 423 s16 ibi; 424 }; 425 426 static int adi_i3c_master_get_rr_slot(struct adi_i3c_master *master, 427 u8 dyn_addr) 428 { 429 if (!master->free_rr_slots) 430 return -ENOSPC; 431 432 return ffs(master->free_rr_slots) - 1; 433 } 434 435 static int adi_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, u8 dyn_addr) 436 { 437 struct i3c_master_controller *m = i3c_dev_get_master(dev); 438 struct adi_i3c_master *master = to_adi_i3c_master(m); 439 u8 addr; 440 441 addr = dev->info.dyn_addr ? dev->info.dyn_addr : dev->info.static_addr; 442 443 writel(REG_DEV_CHAR_ADDR(dyn_addr), master->regs + REG_DEV_CHAR); 444 writel((readl(master->regs + REG_DEV_CHAR) & 445 ~REG_DEV_CHAR_IS_ATTACHED) | REG_DEV_CHAR_WEN, 446 master->regs + REG_DEV_CHAR); 447 448 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 449 writel(readl(master->regs + REG_DEV_CHAR) | 450 REG_DEV_CHAR_IS_ATTACHED | REG_DEV_CHAR_WEN, 451 master->regs + REG_DEV_CHAR); 452 453 return 0; 454 } 455 456 static int adi_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev) 457 { 458 struct i3c_master_controller *m = i3c_dev_get_master(dev); 459 struct adi_i3c_master *master = to_adi_i3c_master(m); 460 struct adi_i3c_i2c_dev_data *data; 461 int slot; 462 u8 addr; 463 464 data = kzalloc(sizeof(*data), GFP_KERNEL); 465 if (!data) 466 return -ENOMEM; 467 468 slot = adi_i3c_master_get_rr_slot(master, dev->info.dyn_addr); 469 if (slot < 0) { 470 kfree(data); 471 return slot; 472 } 473 474 data->id = slot; 475 i3c_dev_set_master_data(dev, data); 476 master->free_rr_slots &= ~BIT(slot); 477 478 addr = dev->info.dyn_addr ? dev->info.dyn_addr : dev->info.static_addr; 479 480 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 481 writel(readl(master->regs + REG_DEV_CHAR) | 482 REG_DEV_CHAR_IS_ATTACHED | REG_DEV_CHAR_WEN, 483 master->regs + REG_DEV_CHAR); 484 485 return 0; 486 } 487 488 static void adi_i3c_master_sync_dev_char(struct i3c_master_controller *m) 489 { 490 struct adi_i3c_master *master = to_adi_i3c_master(m); 491 struct i3c_dev_desc *i3cdev; 492 u32 bcr_ibi; 493 u8 addr; 494 495 i3c_bus_for_each_i3cdev(&m->bus, i3cdev) { 496 addr = i3cdev->info.dyn_addr ? 497 i3cdev->info.dyn_addr : i3cdev->info.static_addr; 498 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 499 bcr_ibi = FIELD_GET(I3C_BCR_IBI_PAYLOAD | I3C_BCR_IBI_REQ_CAP, (i3cdev->info.bcr)); 500 writel(readl(master->regs + REG_DEV_CHAR) | 501 REG_DEV_CHAR_BCR_IBI(bcr_ibi) | REG_DEV_CHAR_WEN, 502 master->regs + REG_DEV_CHAR); 503 } 504 } 505 506 static void adi_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) 507 { 508 struct i3c_master_controller *m = i3c_dev_get_master(dev); 509 struct adi_i3c_master *master = to_adi_i3c_master(m); 510 struct adi_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 511 u8 addr; 512 513 addr = dev->info.dyn_addr ? dev->info.dyn_addr : dev->info.static_addr; 514 515 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 516 writel((readl(master->regs + REG_DEV_CHAR) & 517 ~REG_DEV_CHAR_IS_ATTACHED) | REG_DEV_CHAR_WEN, 518 master->regs + REG_DEV_CHAR); 519 520 i3c_dev_set_master_data(dev, NULL); 521 master->free_rr_slots |= BIT(data->id); 522 kfree(data); 523 } 524 525 static int adi_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) 526 { 527 struct i3c_master_controller *m = i2c_dev_get_master(dev); 528 struct adi_i3c_master *master = to_adi_i3c_master(m); 529 struct adi_i3c_i2c_dev_data *data; 530 int slot; 531 532 slot = adi_i3c_master_get_rr_slot(master, 0); 533 if (slot < 0) 534 return slot; 535 536 data = kzalloc(sizeof(*data), GFP_KERNEL); 537 if (!data) 538 return -ENOMEM; 539 540 data->id = slot; 541 master->free_rr_slots &= ~BIT(slot); 542 i2c_dev_set_master_data(dev, data); 543 544 writel(REG_DEV_CHAR_ADDR(dev->addr) | 545 REG_DEV_CHAR_IS_I2C | REG_DEV_CHAR_IS_ATTACHED | REG_DEV_CHAR_WEN, 546 master->regs + REG_DEV_CHAR); 547 548 return 0; 549 } 550 551 static void adi_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) 552 { 553 struct i3c_master_controller *m = i2c_dev_get_master(dev); 554 struct adi_i3c_master *master = to_adi_i3c_master(m); 555 struct adi_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 556 557 writel(REG_DEV_CHAR_ADDR(dev->addr) | 558 REG_DEV_CHAR_IS_I2C | REG_DEV_CHAR_WEN, 559 master->regs + REG_DEV_CHAR); 560 561 i2c_dev_set_master_data(dev, NULL); 562 master->free_rr_slots |= BIT(data->id); 563 kfree(data); 564 } 565 566 static void adi_i3c_master_bus_cleanup(struct i3c_master_controller *m) 567 { 568 struct adi_i3c_master *master = to_adi_i3c_master(m); 569 570 adi_i3c_master_disable(master); 571 } 572 573 static void adi_i3c_master_upd_i3c_scl_lim(struct adi_i3c_master *master) 574 { 575 struct i3c_master_controller *m = &master->base; 576 struct i3c_bus *bus = i3c_master_get_bus(m); 577 u8 i3c_scl_lim = 0; 578 struct i3c_dev_desc *dev; 579 u8 pp_sg; 580 581 i3c_bus_for_each_i3cdev(bus, dev) { 582 u8 max_fscl; 583 584 max_fscl = max(I3C_CCC_MAX_SDR_FSCL(dev->info.max_read_ds), 585 I3C_CCC_MAX_SDR_FSCL(dev->info.max_write_ds)); 586 587 switch (max_fscl) { 588 case I3C_SDR1_FSCL_8MHZ: 589 max_fscl = PP_SG_6MHZ; 590 break; 591 case I3C_SDR2_FSCL_6MHZ: 592 max_fscl = PP_SG_3MHZ; 593 break; 594 case I3C_SDR3_FSCL_4MHZ: 595 max_fscl = PP_SG_3MHZ; 596 break; 597 case I3C_SDR4_FSCL_2MHZ: 598 max_fscl = PP_SG_1MHZ; 599 break; 600 case I3C_SDR0_FSCL_MAX: 601 default: 602 max_fscl = PP_SG_12MHZ; 603 break; 604 } 605 606 if (max_fscl && 607 (i3c_scl_lim > max_fscl || !i3c_scl_lim)) 608 i3c_scl_lim = max_fscl; 609 } 610 611 if (!i3c_scl_lim) 612 return; 613 614 master->i3c_scl_lim = i3c_scl_lim - 1; 615 616 pp_sg = readl(master->regs + REG_OPS) & ~REG_OPS_PP_SG_MASK; 617 pp_sg |= REG_OPS_SET_SG(master->i3c_scl_lim); 618 619 writel(pp_sg, master->regs + REG_OPS); 620 } 621 622 static void adi_i3c_master_get_features(struct adi_i3c_master *master, 623 unsigned int slot, 624 struct i3c_device_info *info) 625 { 626 u32 buf; 627 628 /* Dynamic address and PID are for identification only */ 629 memset(info, 0, sizeof(*info)); 630 buf = readl(master->regs + REG_DCR_BCR_DA); 631 info->dyn_addr = REG_DCR_BCR_DA_GET_DA(buf); 632 info->dcr = REG_DCR_BCR_DA_GET_DCR(buf); 633 info->bcr = REG_DCR_BCR_DA_GET_BCR(buf); 634 info->pid = readl(master->regs + REG_PID_L); 635 info->pid |= (u64)readl(master->regs + REG_PID_H) << 32; 636 } 637 638 static int adi_i3c_master_do_daa(struct i3c_master_controller *m) 639 { 640 struct adi_i3c_master *master = to_adi_i3c_master(m); 641 int ret, addr = 0; 642 u32 irq_mask; 643 644 for (u8 i = 0; i < ADI_MAX_DEVS; i++) { 645 addr = i3c_master_get_free_addr(m, addr); 646 if (addr < 0) 647 return addr; 648 master->daa.addrs[i] = addr; 649 } 650 651 irq_mask = readl(master->regs + REG_IRQ_MASK); 652 writel(irq_mask | REG_IRQ_PENDING_DAA, 653 master->regs + REG_IRQ_MASK); 654 655 master->daa.index = 0; 656 ret = i3c_master_entdaa_locked(&master->base); 657 658 writel(irq_mask, master->regs + REG_IRQ_MASK); 659 660 /* DAA always finishes with CE2_ERROR or NACK_RESP */ 661 if (ret && ret != I3C_ERROR_M2) 662 return ret; 663 664 /* Add I3C devices discovered */ 665 for (u8 i = 0; i < master->daa.index; i++) 666 i3c_master_add_i3c_dev_locked(m, master->daa.addrs[i]); 667 /* Sync retrieved devs info with the IP */ 668 adi_i3c_master_sync_dev_char(m); 669 670 i3c_master_defslvs_locked(&master->base); 671 672 adi_i3c_master_upd_i3c_scl_lim(master); 673 674 return 0; 675 } 676 677 static int adi_i3c_master_bus_init(struct i3c_master_controller *m) 678 { 679 struct adi_i3c_master *master = to_adi_i3c_master(m); 680 struct i3c_device_info info = { }; 681 int ret; 682 683 ret = i3c_master_get_free_addr(m, 0); 684 if (ret < 0) 685 return ret; 686 687 adi_i3c_master_get_features(master, 0, &info); 688 ret = i3c_master_set_info(&master->base, &info); 689 if (ret) 690 return ret; 691 692 writel(REG_IBI_CONFIG_LISTEN, 693 master->regs + REG_IBI_CONFIG); 694 695 return 0; 696 } 697 698 static void adi_i3c_master_handle_ibi(struct adi_i3c_master *master, 699 u32 raw) 700 { 701 struct adi_i3c_i2c_dev_data *data; 702 struct i3c_ibi_slot *slot; 703 struct i3c_dev_desc *dev; 704 u8 da, id, mdb, len; 705 u8 *buf; 706 707 da = FIELD_GET(GENMASK(23, 17), raw); 708 mdb = FIELD_GET(GENMASK(15, 8), raw); 709 for (id = 0; id < master->ibi.num_slots; id++) { 710 if (master->ibi.slots[id] && 711 master->ibi.slots[id]->info.dyn_addr == da) 712 break; 713 } 714 715 if (id == master->ibi.num_slots) 716 return; 717 718 dev = master->ibi.slots[id]; 719 len = ADI_HAS_MDB_FROM_BCR(dev->info.bcr); 720 data = i3c_dev_get_master_data(dev); 721 722 guard(spinlock)(&master->ibi.lock); 723 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool); 724 if (!slot) 725 return; 726 727 slot->len = len; 728 buf = slot->data; 729 buf[0] = mdb; 730 i3c_master_queue_ibi(dev, slot); 731 } 732 733 static void adi_i3c_master_demux_ibis(struct adi_i3c_master *master) 734 { 735 while (!(readl(master->regs + REG_FIFO_STATUS) & REG_FIFO_STATUS_IBI_EMPTY)) { 736 u32 raw = readl(master->regs + REG_IBI_FIFO); 737 738 adi_i3c_master_handle_ibi(master, raw); 739 } 740 } 741 742 static void adi_i3c_master_handle_da_req(struct adi_i3c_master *master) 743 { 744 u8 payload0[8]; 745 u32 addr; 746 747 adi_i3c_master_rd_from_rx_fifo(master, payload0, 6); 748 addr = master->daa.addrs[master->daa.index++]; 749 addr = (addr << 1) | (parity8(addr) ? 0 : 1); 750 751 writel(addr, master->regs + REG_SDO_FIFO); 752 } 753 754 static irqreturn_t adi_i3c_master_irq(int irq, void *data) 755 { 756 struct adi_i3c_master *master = data; 757 u32 pending; 758 759 pending = readl(master->regs + REG_IRQ_PENDING); 760 writel(pending, master->regs + REG_IRQ_PENDING); 761 if (pending & REG_IRQ_PENDING_CMDR) { 762 scoped_guard(spinlock_irqsave, &master->xferqueue.lock) { 763 adi_i3c_master_end_xfer_locked(master, pending); 764 } 765 } 766 if (pending & REG_IRQ_PENDING_IBI) 767 adi_i3c_master_demux_ibis(master); 768 if (pending & REG_IRQ_PENDING_DAA) 769 adi_i3c_master_handle_da_req(master); 770 771 return IRQ_HANDLED; 772 } 773 774 static int adi_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, 775 struct i2c_msg *xfers, 776 int nxfers) 777 { 778 struct i3c_master_controller *m = i2c_dev_get_master(dev); 779 struct adi_i3c_master *master = to_adi_i3c_master(m); 780 struct adi_i3c_xfer *xfer __free(kfree) = NULL; 781 int i; 782 783 if (!nxfers) 784 return 0; 785 for (i = 0; i < nxfers; i++) { 786 if (xfers[i].flags & I2C_M_TEN) 787 return -EOPNOTSUPP; 788 } 789 xfer = adi_i3c_master_alloc_xfer(master, nxfers); 790 if (!xfer) 791 return -ENOMEM; 792 793 for (i = 0; i < nxfers; i++) { 794 struct adi_i3c_cmd *ccmd = &xfer->cmds[i]; 795 796 ccmd->cmd0 = REG_CMD_FIFO_0_DEV_ADDR(xfers[i].addr); 797 798 if (xfers[i].flags & I2C_M_RD) { 799 ccmd->cmd0 |= REG_CMD_FIFO_0_RNW; 800 ccmd->rx_buf = xfers[i].buf; 801 ccmd->rx_len = xfers[i].len; 802 } else { 803 ccmd->tx_buf = xfers[i].buf; 804 ccmd->tx_len = xfers[i].len; 805 } 806 807 ccmd->cmd0 |= REG_CMD_FIFO_0_LEN(xfers[i].len); 808 } 809 810 adi_i3c_master_queue_xfer(master, xfer); 811 if (!wait_for_completion_timeout(&xfer->comp, 812 m->i2c.timeout)) 813 adi_i3c_master_unqueue_xfer(master, xfer); 814 815 return xfer->ret; 816 } 817 818 static int adi_i3c_master_disable_ibi(struct i3c_dev_desc *dev) 819 { 820 struct i3c_master_controller *m = i3c_dev_get_master(dev); 821 struct adi_i3c_master *master = to_adi_i3c_master(m); 822 struct i3c_dev_desc *i3cdev; 823 u32 enabled = 0; 824 int ret; 825 826 ret = i3c_master_disec_locked(m, dev->info.dyn_addr, 827 I3C_CCC_EVENT_SIR); 828 829 i3c_bus_for_each_i3cdev(&m->bus, i3cdev) { 830 if (dev != i3cdev && i3cdev->ibi) 831 enabled |= i3cdev->ibi->enabled; 832 } 833 if (!enabled) { 834 writel(REG_IBI_CONFIG_LISTEN, 835 master->regs + REG_IBI_CONFIG); 836 writel(readl(master->regs + REG_IRQ_MASK) & ~REG_IRQ_PENDING_IBI, 837 master->regs + REG_IRQ_MASK); 838 } 839 840 return ret; 841 } 842 843 static int adi_i3c_master_enable_ibi(struct i3c_dev_desc *dev) 844 { 845 struct i3c_master_controller *m = i3c_dev_get_master(dev); 846 struct adi_i3c_master *master = to_adi_i3c_master(m); 847 848 writel(REG_IBI_CONFIG_LISTEN | REG_IBI_CONFIG_ENABLE, 849 master->regs + REG_IBI_CONFIG); 850 851 writel(readl(master->regs + REG_IRQ_MASK) | REG_IRQ_PENDING_IBI, 852 master->regs + REG_IRQ_MASK); 853 854 return i3c_master_enec_locked(m, dev->info.dyn_addr, 855 I3C_CCC_EVENT_SIR); 856 } 857 858 static int adi_i3c_master_request_ibi(struct i3c_dev_desc *dev, 859 const struct i3c_ibi_setup *req) 860 { 861 struct i3c_master_controller *m = i3c_dev_get_master(dev); 862 struct adi_i3c_master *master = to_adi_i3c_master(m); 863 struct adi_i3c_i2c_dev_data *data; 864 unsigned int i; 865 866 data = i3c_dev_get_master_data(dev); 867 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); 868 if (IS_ERR(data->ibi_pool)) 869 return PTR_ERR(data->ibi_pool); 870 871 scoped_guard(spinlock_irqsave, &master->ibi.lock) { 872 for (i = 0; i < master->ibi.num_slots; i++) { 873 if (!master->ibi.slots[i]) { 874 data->ibi = i; 875 master->ibi.slots[i] = dev; 876 break; 877 } 878 } 879 } 880 881 if (i < master->ibi.num_slots) 882 return 0; 883 884 i3c_generic_ibi_free_pool(data->ibi_pool); 885 data->ibi_pool = NULL; 886 887 return -ENOSPC; 888 } 889 890 static void adi_i3c_master_free_ibi(struct i3c_dev_desc *dev) 891 { 892 struct i3c_master_controller *m = i3c_dev_get_master(dev); 893 struct adi_i3c_master *master = to_adi_i3c_master(m); 894 struct adi_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 895 896 scoped_guard(spinlock_irqsave, &master->ibi.lock) { 897 master->ibi.slots[data->ibi] = NULL; 898 } 899 900 i3c_generic_ibi_free_pool(data->ibi_pool); 901 } 902 903 static void adi_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev, 904 struct i3c_ibi_slot *slot) 905 { 906 struct adi_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 907 908 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot); 909 } 910 911 static const struct i3c_master_controller_ops adi_i3c_master_ops = { 912 .bus_init = adi_i3c_master_bus_init, 913 .bus_cleanup = adi_i3c_master_bus_cleanup, 914 .attach_i3c_dev = adi_i3c_master_attach_i3c_dev, 915 .reattach_i3c_dev = adi_i3c_master_reattach_i3c_dev, 916 .detach_i3c_dev = adi_i3c_master_detach_i3c_dev, 917 .attach_i2c_dev = adi_i3c_master_attach_i2c_dev, 918 .detach_i2c_dev = adi_i3c_master_detach_i2c_dev, 919 .do_daa = adi_i3c_master_do_daa, 920 .supports_ccc_cmd = adi_i3c_master_supports_ccc_cmd, 921 .send_ccc_cmd = adi_i3c_master_send_ccc_cmd, 922 .priv_xfers = adi_i3c_master_priv_xfers, 923 .i2c_xfers = adi_i3c_master_i2c_xfers, 924 .request_ibi = adi_i3c_master_request_ibi, 925 .enable_ibi = adi_i3c_master_enable_ibi, 926 .disable_ibi = adi_i3c_master_disable_ibi, 927 .free_ibi = adi_i3c_master_free_ibi, 928 .recycle_ibi_slot = adi_i3c_master_recycle_ibi_slot, 929 }; 930 931 static const struct of_device_id adi_i3c_master_of_match[] = { 932 { .compatible = "adi,i3c-master-v1" }, 933 {} 934 }; 935 936 static int adi_i3c_master_probe(struct platform_device *pdev) 937 { 938 struct adi_i3c_master *master; 939 struct clk_bulk_data *clk; 940 unsigned int version; 941 int ret, irq; 942 943 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 944 if (!master) 945 return -ENOMEM; 946 947 master->regs = devm_platform_ioremap_resource(pdev, 0); 948 if (IS_ERR(master->regs)) 949 return PTR_ERR(master->regs); 950 951 ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clk); 952 if (ret < 0) 953 return dev_err_probe(&pdev->dev, ret, 954 "Failed to get clocks\n"); 955 956 irq = platform_get_irq(pdev, 0); 957 if (irq < 0) 958 return irq; 959 960 version = readl(master->regs + ADI_AXI_REG_VERSION); 961 if (ADI_AXI_PCORE_VER_MAJOR(version) != 1) 962 dev_err_probe(&pdev->dev, -ENODEV, "Unsupported peripheral version %u.%u.%u\n", 963 ADI_AXI_PCORE_VER_MAJOR(version), 964 ADI_AXI_PCORE_VER_MINOR(version), 965 ADI_AXI_PCORE_VER_PATCH(version)); 966 967 writel(0x00, master->regs + REG_ENABLE); 968 writel(0x00, master->regs + REG_IRQ_MASK); 969 970 ret = devm_request_irq(&pdev->dev, irq, adi_i3c_master_irq, 0, 971 dev_name(&pdev->dev), master); 972 if (ret) 973 return ret; 974 975 platform_set_drvdata(pdev, master); 976 977 master->free_rr_slots = GENMASK(ADI_MAX_DEVS, 1); 978 979 writel(REG_IRQ_PENDING_CMDR, master->regs + REG_IRQ_MASK); 980 981 spin_lock_init(&master->ibi.lock); 982 master->ibi.num_slots = 15; 983 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots, 984 sizeof(*master->ibi.slots), 985 GFP_KERNEL); 986 if (!master->ibi.slots) 987 return -ENOMEM; 988 989 spin_lock_init(&master->xferqueue.lock); 990 INIT_LIST_HEAD(&master->xferqueue.list); 991 992 return i3c_master_register(&master->base, &pdev->dev, 993 &adi_i3c_master_ops, false); 994 } 995 996 static void adi_i3c_master_remove(struct platform_device *pdev) 997 { 998 struct adi_i3c_master *master = platform_get_drvdata(pdev); 999 1000 writel(0xff, master->regs + REG_IRQ_PENDING); 1001 writel(0x00, master->regs + REG_IRQ_MASK); 1002 writel(0x01, master->regs + REG_ENABLE); 1003 1004 i3c_master_unregister(&master->base); 1005 } 1006 1007 static struct platform_driver adi_i3c_master = { 1008 .probe = adi_i3c_master_probe, 1009 .remove = adi_i3c_master_remove, 1010 .driver = { 1011 .name = "adi-i3c-master", 1012 .of_match_table = adi_i3c_master_of_match, 1013 }, 1014 }; 1015 module_platform_driver(adi_i3c_master); 1016 1017 MODULE_AUTHOR("Jorge Marques <jorge.marques@analog.com>"); 1018 MODULE_DESCRIPTION("Analog Devices I3C master driver"); 1019 MODULE_LICENSE("GPL"); 1020