1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Cadence Design Systems Inc. 4 * 5 * Author: Boris Brezillon <boris.brezillon@bootlin.com> 6 */ 7 8 #include <linux/atomic.h> 9 #include <linux/bug.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/err.h> 13 #include <linux/export.h> 14 #include <linux/kernel.h> 15 #include <linux/list.h> 16 #include <linux/of.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/slab.h> 19 #include <linux/spinlock.h> 20 #include <linux/workqueue.h> 21 22 #include "internals.h" 23 24 static DEFINE_IDR(i3c_bus_idr); 25 static DEFINE_MUTEX(i3c_core_lock); 26 static int __i3c_first_dynamic_bus_num; 27 static BLOCKING_NOTIFIER_HEAD(i3c_bus_notifier); 28 29 /** 30 * i3c_bus_maintenance_lock - Lock the bus for a maintenance operation 31 * @bus: I3C bus to take the lock on 32 * 33 * This function takes the bus lock so that no other operations can occur on 34 * the bus. This is needed for all kind of bus maintenance operation, like 35 * - enabling/disabling slave events 36 * - re-triggering DAA 37 * - changing the dynamic address of a device 38 * - relinquishing mastership 39 * - ... 40 * 41 * The reason for this kind of locking is that we don't want drivers and core 42 * logic to rely on I3C device information that could be changed behind their 43 * back. 44 */ 45 static void i3c_bus_maintenance_lock(struct i3c_bus *bus) 46 { 47 down_write(&bus->lock); 48 } 49 50 /** 51 * i3c_bus_maintenance_unlock - Release the bus lock after a maintenance 52 * operation 53 * @bus: I3C bus to release the lock on 54 * 55 * Should be called when the bus maintenance operation is done. See 56 * i3c_bus_maintenance_lock() for more details on what these maintenance 57 * operations are. 58 */ 59 static void i3c_bus_maintenance_unlock(struct i3c_bus *bus) 60 { 61 up_write(&bus->lock); 62 } 63 64 /** 65 * i3c_bus_normaluse_lock - Lock the bus for a normal operation 66 * @bus: I3C bus to take the lock on 67 * 68 * This function takes the bus lock for any operation that is not a maintenance 69 * operation (see i3c_bus_maintenance_lock() for a non-exhaustive list of 70 * maintenance operations). Basically all communications with I3C devices are 71 * normal operations (HDR, SDR transfers or CCC commands that do not change bus 72 * state or I3C dynamic address). 73 * 74 * Note that this lock is not guaranteeing serialization of normal operations. 75 * In other words, transfer requests passed to the I3C master can be submitted 76 * in parallel and I3C master drivers have to use their own locking to make 77 * sure two different communications are not inter-mixed, or access to the 78 * output/input queue is not done while the engine is busy. 79 */ 80 void i3c_bus_normaluse_lock(struct i3c_bus *bus) 81 { 82 down_read(&bus->lock); 83 } 84 85 /** 86 * i3c_bus_normaluse_unlock - Release the bus lock after a normal operation 87 * @bus: I3C bus to release the lock on 88 * 89 * Should be called when a normal operation is done. See 90 * i3c_bus_normaluse_lock() for more details on what these normal operations 91 * are. 92 */ 93 void i3c_bus_normaluse_unlock(struct i3c_bus *bus) 94 { 95 up_read(&bus->lock); 96 } 97 98 static struct i3c_master_controller * 99 i3c_bus_to_i3c_master(struct i3c_bus *i3cbus) 100 { 101 return container_of(i3cbus, struct i3c_master_controller, bus); 102 } 103 104 static struct i3c_master_controller *dev_to_i3cmaster(struct device *dev) 105 { 106 return container_of(dev, struct i3c_master_controller, dev); 107 } 108 109 static const struct device_type i3c_device_type; 110 111 static struct i3c_bus *dev_to_i3cbus(struct device *dev) 112 { 113 struct i3c_master_controller *master; 114 115 if (dev->type == &i3c_device_type) 116 return dev_to_i3cdev(dev)->bus; 117 118 master = dev_to_i3cmaster(dev); 119 120 return &master->bus; 121 } 122 123 static struct i3c_dev_desc *dev_to_i3cdesc(struct device *dev) 124 { 125 struct i3c_master_controller *master; 126 127 if (dev->type == &i3c_device_type) 128 return dev_to_i3cdev(dev)->desc; 129 130 master = dev_to_i3cmaster(dev); 131 132 return master->this; 133 } 134 135 static ssize_t bcr_show(struct device *dev, 136 struct device_attribute *da, 137 char *buf) 138 { 139 struct i3c_bus *bus = dev_to_i3cbus(dev); 140 struct i3c_dev_desc *desc; 141 ssize_t ret; 142 143 i3c_bus_normaluse_lock(bus); 144 desc = dev_to_i3cdesc(dev); 145 ret = sprintf(buf, "0x%02x\n", desc->info.bcr); 146 i3c_bus_normaluse_unlock(bus); 147 148 return ret; 149 } 150 static DEVICE_ATTR_RO(bcr); 151 152 static ssize_t dcr_show(struct device *dev, 153 struct device_attribute *da, 154 char *buf) 155 { 156 struct i3c_bus *bus = dev_to_i3cbus(dev); 157 struct i3c_dev_desc *desc; 158 ssize_t ret; 159 160 i3c_bus_normaluse_lock(bus); 161 desc = dev_to_i3cdesc(dev); 162 ret = sprintf(buf, "0x%02x\n", desc->info.dcr); 163 i3c_bus_normaluse_unlock(bus); 164 165 return ret; 166 } 167 static DEVICE_ATTR_RO(dcr); 168 169 static ssize_t pid_show(struct device *dev, 170 struct device_attribute *da, 171 char *buf) 172 { 173 struct i3c_bus *bus = dev_to_i3cbus(dev); 174 struct i3c_dev_desc *desc; 175 ssize_t ret; 176 177 i3c_bus_normaluse_lock(bus); 178 desc = dev_to_i3cdesc(dev); 179 ret = sprintf(buf, "%llx\n", desc->info.pid); 180 i3c_bus_normaluse_unlock(bus); 181 182 return ret; 183 } 184 static DEVICE_ATTR_RO(pid); 185 186 static ssize_t dynamic_address_show(struct device *dev, 187 struct device_attribute *da, 188 char *buf) 189 { 190 struct i3c_bus *bus = dev_to_i3cbus(dev); 191 struct i3c_dev_desc *desc; 192 ssize_t ret; 193 194 i3c_bus_normaluse_lock(bus); 195 desc = dev_to_i3cdesc(dev); 196 ret = sprintf(buf, "%02x\n", desc->info.dyn_addr); 197 i3c_bus_normaluse_unlock(bus); 198 199 return ret; 200 } 201 static DEVICE_ATTR_RO(dynamic_address); 202 203 static const char * const hdrcap_strings[] = { 204 "hdr-ddr", "hdr-tsp", "hdr-tsl", 205 }; 206 207 static ssize_t hdrcap_show(struct device *dev, 208 struct device_attribute *da, 209 char *buf) 210 { 211 struct i3c_bus *bus = dev_to_i3cbus(dev); 212 struct i3c_dev_desc *desc; 213 ssize_t offset = 0, ret; 214 unsigned long caps; 215 int mode; 216 217 i3c_bus_normaluse_lock(bus); 218 desc = dev_to_i3cdesc(dev); 219 caps = desc->info.hdr_cap; 220 for_each_set_bit(mode, &caps, 8) { 221 if (mode >= ARRAY_SIZE(hdrcap_strings)) 222 break; 223 224 if (!hdrcap_strings[mode]) 225 continue; 226 227 ret = sprintf(buf + offset, offset ? " %s" : "%s", 228 hdrcap_strings[mode]); 229 if (ret < 0) 230 goto out; 231 232 offset += ret; 233 } 234 235 ret = sprintf(buf + offset, "\n"); 236 if (ret < 0) 237 goto out; 238 239 ret = offset + ret; 240 241 out: 242 i3c_bus_normaluse_unlock(bus); 243 244 return ret; 245 } 246 static DEVICE_ATTR_RO(hdrcap); 247 248 static ssize_t modalias_show(struct device *dev, 249 struct device_attribute *da, char *buf) 250 { 251 struct i3c_device *i3c = dev_to_i3cdev(dev); 252 struct i3c_device_info devinfo; 253 u16 manuf, part, ext; 254 255 i3c_device_get_info(i3c, &devinfo); 256 manuf = I3C_PID_MANUF_ID(devinfo.pid); 257 part = I3C_PID_PART_ID(devinfo.pid); 258 ext = I3C_PID_EXTRA_INFO(devinfo.pid); 259 260 if (I3C_PID_RND_LOWER_32BITS(devinfo.pid)) 261 return sprintf(buf, "i3c:dcr%02Xmanuf%04X", devinfo.dcr, 262 manuf); 263 264 return sprintf(buf, "i3c:dcr%02Xmanuf%04Xpart%04Xext%04X", 265 devinfo.dcr, manuf, part, ext); 266 } 267 static DEVICE_ATTR_RO(modalias); 268 269 static struct attribute *i3c_device_attrs[] = { 270 &dev_attr_bcr.attr, 271 &dev_attr_dcr.attr, 272 &dev_attr_pid.attr, 273 &dev_attr_dynamic_address.attr, 274 &dev_attr_hdrcap.attr, 275 &dev_attr_modalias.attr, 276 NULL, 277 }; 278 ATTRIBUTE_GROUPS(i3c_device); 279 280 static int i3c_device_uevent(const struct device *dev, struct kobj_uevent_env *env) 281 { 282 const struct i3c_device *i3cdev = dev_to_i3cdev(dev); 283 struct i3c_device_info devinfo; 284 u16 manuf, part, ext; 285 286 if (i3cdev->desc) 287 devinfo = i3cdev->desc->info; 288 manuf = I3C_PID_MANUF_ID(devinfo.pid); 289 part = I3C_PID_PART_ID(devinfo.pid); 290 ext = I3C_PID_EXTRA_INFO(devinfo.pid); 291 292 if (I3C_PID_RND_LOWER_32BITS(devinfo.pid)) 293 return add_uevent_var(env, "MODALIAS=i3c:dcr%02Xmanuf%04X", 294 devinfo.dcr, manuf); 295 296 return add_uevent_var(env, 297 "MODALIAS=i3c:dcr%02Xmanuf%04Xpart%04Xext%04X", 298 devinfo.dcr, manuf, part, ext); 299 } 300 301 static const struct device_type i3c_device_type = { 302 .groups = i3c_device_groups, 303 .uevent = i3c_device_uevent, 304 }; 305 306 static int i3c_device_match(struct device *dev, const struct device_driver *drv) 307 { 308 struct i3c_device *i3cdev; 309 const struct i3c_driver *i3cdrv; 310 311 if (dev->type != &i3c_device_type) 312 return 0; 313 314 i3cdev = dev_to_i3cdev(dev); 315 i3cdrv = drv_to_i3cdrv(drv); 316 if (i3c_device_match_id(i3cdev, i3cdrv->id_table)) 317 return 1; 318 319 return 0; 320 } 321 322 static int i3c_device_probe(struct device *dev) 323 { 324 struct i3c_device *i3cdev = dev_to_i3cdev(dev); 325 struct i3c_driver *driver = drv_to_i3cdrv(dev->driver); 326 327 return driver->probe(i3cdev); 328 } 329 330 static void i3c_device_remove(struct device *dev) 331 { 332 struct i3c_device *i3cdev = dev_to_i3cdev(dev); 333 struct i3c_driver *driver = drv_to_i3cdrv(dev->driver); 334 335 if (driver->remove) 336 driver->remove(i3cdev); 337 } 338 339 const struct bus_type i3c_bus_type = { 340 .name = "i3c", 341 .match = i3c_device_match, 342 .probe = i3c_device_probe, 343 .remove = i3c_device_remove, 344 }; 345 EXPORT_SYMBOL_GPL(i3c_bus_type); 346 347 static enum i3c_addr_slot_status 348 i3c_bus_get_addr_slot_status_mask(struct i3c_bus *bus, u16 addr, u32 mask) 349 { 350 unsigned long status; 351 int bitpos = addr * I3C_ADDR_SLOT_STATUS_BITS; 352 353 if (addr > I2C_MAX_ADDR) 354 return I3C_ADDR_SLOT_RSVD; 355 356 status = bus->addrslots[bitpos / BITS_PER_LONG]; 357 status >>= bitpos % BITS_PER_LONG; 358 359 return status & mask; 360 } 361 362 static enum i3c_addr_slot_status 363 i3c_bus_get_addr_slot_status(struct i3c_bus *bus, u16 addr) 364 { 365 return i3c_bus_get_addr_slot_status_mask(bus, addr, I3C_ADDR_SLOT_STATUS_MASK); 366 } 367 368 static void i3c_bus_set_addr_slot_status_mask(struct i3c_bus *bus, u16 addr, 369 enum i3c_addr_slot_status status, u32 mask) 370 { 371 int bitpos = addr * I3C_ADDR_SLOT_STATUS_BITS; 372 unsigned long *ptr; 373 374 if (addr > I2C_MAX_ADDR) 375 return; 376 377 ptr = bus->addrslots + (bitpos / BITS_PER_LONG); 378 *ptr &= ~((unsigned long)mask << (bitpos % BITS_PER_LONG)); 379 *ptr |= ((unsigned long)status & mask) << (bitpos % BITS_PER_LONG); 380 } 381 382 static void i3c_bus_set_addr_slot_status(struct i3c_bus *bus, u16 addr, 383 enum i3c_addr_slot_status status) 384 { 385 i3c_bus_set_addr_slot_status_mask(bus, addr, status, I3C_ADDR_SLOT_STATUS_MASK); 386 } 387 388 static bool i3c_bus_dev_addr_is_avail(struct i3c_bus *bus, u8 addr) 389 { 390 enum i3c_addr_slot_status status; 391 392 status = i3c_bus_get_addr_slot_status(bus, addr); 393 394 return status == I3C_ADDR_SLOT_FREE; 395 } 396 397 /* 398 * ┌────┬─────────────┬───┬─────────┬───┐ 399 * │S/Sr│ 7'h7E RnW=0 │ACK│ ENTDAA │ T ├────┐ 400 * └────┴─────────────┴───┴─────────┴───┘ │ 401 * ┌─────────────────────────────────────────┘ 402 * │ ┌──┬─────────────┬───┬─────────────────┬────────────────┬───┬─────────┐ 403 * └─►│Sr│7'h7E RnW=1 │ACK│48bit UID BCR DCR│Assign 7bit Addr│PAR│ ACK/NACK│ 404 * └──┴─────────────┴───┴─────────────────┴────────────────┴───┴─────────┘ 405 * Some master controllers (such as HCI) need to prepare the entire above transaction before 406 * sending it out to the I3C bus. This means that a 7-bit dynamic address needs to be allocated 407 * before knowing the target device's UID information. 408 * 409 * However, some I3C targets may request specific addresses (called as "init_dyn_addr"), which is 410 * typically specified by the DT-'s assigned-address property. Lower addresses having higher IBI 411 * priority. If it is available, i3c_bus_get_free_addr() preferably return a free address that is 412 * not in the list of desired addresses (called as "init_dyn_addr"). This allows the device with 413 * the "init_dyn_addr" to switch to its "init_dyn_addr" when it hot-joins the I3C bus. Otherwise, 414 * if the "init_dyn_addr" is already in use by another I3C device, the target device will not be 415 * able to switch to its desired address. 416 * 417 * If the previous step fails, fallback returning one of the remaining unassigned address, 418 * regardless of its state in the desired list. 419 */ 420 static int i3c_bus_get_free_addr(struct i3c_bus *bus, u8 start_addr) 421 { 422 enum i3c_addr_slot_status status; 423 u8 addr; 424 425 for (addr = start_addr; addr < I3C_MAX_ADDR; addr++) { 426 status = i3c_bus_get_addr_slot_status_mask(bus, addr, 427 I3C_ADDR_SLOT_EXT_STATUS_MASK); 428 if (status == I3C_ADDR_SLOT_FREE) 429 return addr; 430 } 431 432 for (addr = start_addr; addr < I3C_MAX_ADDR; addr++) { 433 status = i3c_bus_get_addr_slot_status_mask(bus, addr, 434 I3C_ADDR_SLOT_STATUS_MASK); 435 if (status == I3C_ADDR_SLOT_FREE) 436 return addr; 437 } 438 439 return -ENOMEM; 440 } 441 442 static void i3c_bus_init_addrslots(struct i3c_bus *bus) 443 { 444 int i; 445 446 /* Addresses 0 to 7 are reserved. */ 447 for (i = 0; i < 8; i++) 448 i3c_bus_set_addr_slot_status(bus, i, I3C_ADDR_SLOT_RSVD); 449 450 /* 451 * Reserve broadcast address and all addresses that might collide 452 * with the broadcast address when facing a single bit error. 453 */ 454 i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR, 455 I3C_ADDR_SLOT_RSVD); 456 for (i = 0; i < 7; i++) 457 i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR ^ BIT(i), 458 I3C_ADDR_SLOT_RSVD); 459 } 460 461 static void i3c_bus_cleanup(struct i3c_bus *i3cbus) 462 { 463 mutex_lock(&i3c_core_lock); 464 idr_remove(&i3c_bus_idr, i3cbus->id); 465 mutex_unlock(&i3c_core_lock); 466 } 467 468 static int i3c_bus_init(struct i3c_bus *i3cbus, struct device_node *np) 469 { 470 int ret, start, end, id = -1; 471 472 init_rwsem(&i3cbus->lock); 473 INIT_LIST_HEAD(&i3cbus->devs.i2c); 474 INIT_LIST_HEAD(&i3cbus->devs.i3c); 475 i3c_bus_init_addrslots(i3cbus); 476 i3cbus->mode = I3C_BUS_MODE_PURE; 477 478 if (np) 479 id = of_alias_get_id(np, "i3c"); 480 481 mutex_lock(&i3c_core_lock); 482 if (id >= 0) { 483 start = id; 484 end = start + 1; 485 } else { 486 start = __i3c_first_dynamic_bus_num; 487 end = 0; 488 } 489 490 ret = idr_alloc(&i3c_bus_idr, i3cbus, start, end, GFP_KERNEL); 491 mutex_unlock(&i3c_core_lock); 492 493 if (ret < 0) 494 return ret; 495 496 i3cbus->id = ret; 497 498 return 0; 499 } 500 501 void i3c_for_each_bus_locked(int (*fn)(struct i3c_bus *bus, void *data), 502 void *data) 503 { 504 struct i3c_bus *bus; 505 int id; 506 507 mutex_lock(&i3c_core_lock); 508 idr_for_each_entry(&i3c_bus_idr, bus, id) 509 fn(bus, data); 510 mutex_unlock(&i3c_core_lock); 511 } 512 EXPORT_SYMBOL_GPL(i3c_for_each_bus_locked); 513 514 int i3c_register_notifier(struct notifier_block *nb) 515 { 516 return blocking_notifier_chain_register(&i3c_bus_notifier, nb); 517 } 518 EXPORT_SYMBOL_GPL(i3c_register_notifier); 519 520 int i3c_unregister_notifier(struct notifier_block *nb) 521 { 522 return blocking_notifier_chain_unregister(&i3c_bus_notifier, nb); 523 } 524 EXPORT_SYMBOL_GPL(i3c_unregister_notifier); 525 526 static void i3c_bus_notify(struct i3c_bus *bus, unsigned int action) 527 { 528 blocking_notifier_call_chain(&i3c_bus_notifier, action, bus); 529 } 530 531 static const char * const i3c_bus_mode_strings[] = { 532 [I3C_BUS_MODE_PURE] = "pure", 533 [I3C_BUS_MODE_MIXED_FAST] = "mixed-fast", 534 [I3C_BUS_MODE_MIXED_LIMITED] = "mixed-limited", 535 [I3C_BUS_MODE_MIXED_SLOW] = "mixed-slow", 536 }; 537 538 static ssize_t mode_show(struct device *dev, 539 struct device_attribute *da, 540 char *buf) 541 { 542 struct i3c_bus *i3cbus = dev_to_i3cbus(dev); 543 ssize_t ret; 544 545 i3c_bus_normaluse_lock(i3cbus); 546 if (i3cbus->mode < 0 || 547 i3cbus->mode >= ARRAY_SIZE(i3c_bus_mode_strings) || 548 !i3c_bus_mode_strings[i3cbus->mode]) 549 ret = sprintf(buf, "unknown\n"); 550 else 551 ret = sprintf(buf, "%s\n", i3c_bus_mode_strings[i3cbus->mode]); 552 i3c_bus_normaluse_unlock(i3cbus); 553 554 return ret; 555 } 556 static DEVICE_ATTR_RO(mode); 557 558 static ssize_t current_master_show(struct device *dev, 559 struct device_attribute *da, 560 char *buf) 561 { 562 struct i3c_bus *i3cbus = dev_to_i3cbus(dev); 563 ssize_t ret; 564 565 i3c_bus_normaluse_lock(i3cbus); 566 ret = sprintf(buf, "%d-%llx\n", i3cbus->id, 567 i3cbus->cur_master->info.pid); 568 i3c_bus_normaluse_unlock(i3cbus); 569 570 return ret; 571 } 572 static DEVICE_ATTR_RO(current_master); 573 574 static ssize_t i3c_scl_frequency_show(struct device *dev, 575 struct device_attribute *da, 576 char *buf) 577 { 578 struct i3c_bus *i3cbus = dev_to_i3cbus(dev); 579 ssize_t ret; 580 581 i3c_bus_normaluse_lock(i3cbus); 582 ret = sprintf(buf, "%ld\n", i3cbus->scl_rate.i3c); 583 i3c_bus_normaluse_unlock(i3cbus); 584 585 return ret; 586 } 587 static DEVICE_ATTR_RO(i3c_scl_frequency); 588 589 static ssize_t i2c_scl_frequency_show(struct device *dev, 590 struct device_attribute *da, 591 char *buf) 592 { 593 struct i3c_bus *i3cbus = dev_to_i3cbus(dev); 594 ssize_t ret; 595 596 i3c_bus_normaluse_lock(i3cbus); 597 ret = sprintf(buf, "%ld\n", i3cbus->scl_rate.i2c); 598 i3c_bus_normaluse_unlock(i3cbus); 599 600 return ret; 601 } 602 static DEVICE_ATTR_RO(i2c_scl_frequency); 603 604 static int i3c_set_hotjoin(struct i3c_master_controller *master, bool enable) 605 { 606 int ret; 607 608 if (!master || !master->ops) 609 return -EINVAL; 610 611 if (!master->ops->enable_hotjoin || !master->ops->disable_hotjoin) 612 return -EINVAL; 613 614 i3c_bus_normaluse_lock(&master->bus); 615 616 if (enable) 617 ret = master->ops->enable_hotjoin(master); 618 else 619 ret = master->ops->disable_hotjoin(master); 620 621 master->hotjoin = enable; 622 623 i3c_bus_normaluse_unlock(&master->bus); 624 625 return ret; 626 } 627 628 static ssize_t hotjoin_store(struct device *dev, struct device_attribute *attr, 629 const char *buf, size_t count) 630 { 631 struct i3c_bus *i3cbus = dev_to_i3cbus(dev); 632 int ret; 633 bool res; 634 635 if (!i3cbus->cur_master) 636 return -EINVAL; 637 638 if (kstrtobool(buf, &res)) 639 return -EINVAL; 640 641 ret = i3c_set_hotjoin(i3cbus->cur_master->common.master, res); 642 if (ret) 643 return ret; 644 645 return count; 646 } 647 648 /* 649 * i3c_master_enable_hotjoin - Enable hotjoin 650 * @master: I3C master object 651 * 652 * Return: a 0 in case of success, an negative error code otherwise. 653 */ 654 int i3c_master_enable_hotjoin(struct i3c_master_controller *master) 655 { 656 return i3c_set_hotjoin(master, true); 657 } 658 EXPORT_SYMBOL_GPL(i3c_master_enable_hotjoin); 659 660 /* 661 * i3c_master_disable_hotjoin - Disable hotjoin 662 * @master: I3C master object 663 * 664 * Return: a 0 in case of success, an negative error code otherwise. 665 */ 666 int i3c_master_disable_hotjoin(struct i3c_master_controller *master) 667 { 668 return i3c_set_hotjoin(master, false); 669 } 670 EXPORT_SYMBOL_GPL(i3c_master_disable_hotjoin); 671 672 static ssize_t hotjoin_show(struct device *dev, struct device_attribute *da, char *buf) 673 { 674 struct i3c_bus *i3cbus = dev_to_i3cbus(dev); 675 ssize_t ret; 676 677 i3c_bus_normaluse_lock(i3cbus); 678 ret = sysfs_emit(buf, "%d\n", i3cbus->cur_master->common.master->hotjoin); 679 i3c_bus_normaluse_unlock(i3cbus); 680 681 return ret; 682 } 683 684 static DEVICE_ATTR_RW(hotjoin); 685 686 static struct attribute *i3c_masterdev_attrs[] = { 687 &dev_attr_mode.attr, 688 &dev_attr_current_master.attr, 689 &dev_attr_i3c_scl_frequency.attr, 690 &dev_attr_i2c_scl_frequency.attr, 691 &dev_attr_bcr.attr, 692 &dev_attr_dcr.attr, 693 &dev_attr_pid.attr, 694 &dev_attr_dynamic_address.attr, 695 &dev_attr_hdrcap.attr, 696 &dev_attr_hotjoin.attr, 697 NULL, 698 }; 699 ATTRIBUTE_GROUPS(i3c_masterdev); 700 701 static void i3c_masterdev_release(struct device *dev) 702 { 703 struct i3c_master_controller *master = dev_to_i3cmaster(dev); 704 struct i3c_bus *bus = dev_to_i3cbus(dev); 705 706 if (master->wq) 707 destroy_workqueue(master->wq); 708 709 WARN_ON(!list_empty(&bus->devs.i2c) || !list_empty(&bus->devs.i3c)); 710 i3c_bus_cleanup(bus); 711 712 of_node_put(dev->of_node); 713 } 714 715 static const struct device_type i3c_masterdev_type = { 716 .groups = i3c_masterdev_groups, 717 }; 718 719 static int i3c_bus_set_mode(struct i3c_bus *i3cbus, enum i3c_bus_mode mode, 720 unsigned long max_i2c_scl_rate) 721 { 722 struct i3c_master_controller *master = i3c_bus_to_i3c_master(i3cbus); 723 724 i3cbus->mode = mode; 725 726 switch (i3cbus->mode) { 727 case I3C_BUS_MODE_PURE: 728 if (!i3cbus->scl_rate.i3c) 729 i3cbus->scl_rate.i3c = I3C_BUS_I3C_SCL_TYP_RATE; 730 break; 731 case I3C_BUS_MODE_MIXED_FAST: 732 case I3C_BUS_MODE_MIXED_LIMITED: 733 if (!i3cbus->scl_rate.i3c) 734 i3cbus->scl_rate.i3c = I3C_BUS_I3C_SCL_TYP_RATE; 735 if (!i3cbus->scl_rate.i2c) 736 i3cbus->scl_rate.i2c = max_i2c_scl_rate; 737 break; 738 case I3C_BUS_MODE_MIXED_SLOW: 739 if (!i3cbus->scl_rate.i2c) 740 i3cbus->scl_rate.i2c = max_i2c_scl_rate; 741 if (!i3cbus->scl_rate.i3c || 742 i3cbus->scl_rate.i3c > i3cbus->scl_rate.i2c) 743 i3cbus->scl_rate.i3c = i3cbus->scl_rate.i2c; 744 break; 745 default: 746 return -EINVAL; 747 } 748 749 dev_dbg(&master->dev, "i2c-scl = %ld Hz i3c-scl = %ld Hz\n", 750 i3cbus->scl_rate.i2c, i3cbus->scl_rate.i3c); 751 752 /* 753 * I3C/I2C frequency may have been overridden, check that user-provided 754 * values are not exceeding max possible frequency. 755 */ 756 if (i3cbus->scl_rate.i3c > I3C_BUS_I3C_SCL_MAX_RATE || 757 i3cbus->scl_rate.i2c > I3C_BUS_I2C_FM_PLUS_SCL_MAX_RATE) 758 return -EINVAL; 759 760 return 0; 761 } 762 763 static struct i3c_master_controller * 764 i2c_adapter_to_i3c_master(struct i2c_adapter *adap) 765 { 766 return container_of(adap, struct i3c_master_controller, i2c); 767 } 768 769 static struct i2c_adapter * 770 i3c_master_to_i2c_adapter(struct i3c_master_controller *master) 771 { 772 return &master->i2c; 773 } 774 775 static void i3c_master_free_i2c_dev(struct i2c_dev_desc *dev) 776 { 777 kfree(dev); 778 } 779 780 static struct i2c_dev_desc * 781 i3c_master_alloc_i2c_dev(struct i3c_master_controller *master, 782 u16 addr, u8 lvr) 783 { 784 struct i2c_dev_desc *dev; 785 786 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 787 if (!dev) 788 return ERR_PTR(-ENOMEM); 789 790 dev->common.master = master; 791 dev->addr = addr; 792 dev->lvr = lvr; 793 794 return dev; 795 } 796 797 static void *i3c_ccc_cmd_dest_init(struct i3c_ccc_cmd_dest *dest, u8 addr, 798 u16 payloadlen) 799 { 800 dest->addr = addr; 801 dest->payload.len = payloadlen; 802 if (payloadlen) 803 dest->payload.data = kzalloc(payloadlen, GFP_KERNEL); 804 else 805 dest->payload.data = NULL; 806 807 return dest->payload.data; 808 } 809 810 static void i3c_ccc_cmd_dest_cleanup(struct i3c_ccc_cmd_dest *dest) 811 { 812 kfree(dest->payload.data); 813 } 814 815 static void i3c_ccc_cmd_init(struct i3c_ccc_cmd *cmd, bool rnw, u8 id, 816 struct i3c_ccc_cmd_dest *dests, 817 unsigned int ndests) 818 { 819 cmd->rnw = rnw ? 1 : 0; 820 cmd->id = id; 821 cmd->dests = dests; 822 cmd->ndests = ndests; 823 cmd->err = I3C_ERROR_UNKNOWN; 824 } 825 826 static int i3c_master_send_ccc_cmd_locked(struct i3c_master_controller *master, 827 struct i3c_ccc_cmd *cmd) 828 { 829 int ret; 830 831 if (!cmd || !master) 832 return -EINVAL; 833 834 if (WARN_ON(master->init_done && 835 !rwsem_is_locked(&master->bus.lock))) 836 return -EINVAL; 837 838 if (!master->ops->send_ccc_cmd) 839 return -EOPNOTSUPP; 840 841 if ((cmd->id & I3C_CCC_DIRECT) && (!cmd->dests || !cmd->ndests)) 842 return -EINVAL; 843 844 if (master->ops->supports_ccc_cmd && 845 !master->ops->supports_ccc_cmd(master, cmd)) 846 return -EOPNOTSUPP; 847 848 ret = master->ops->send_ccc_cmd(master, cmd); 849 if (ret) { 850 if (cmd->err != I3C_ERROR_UNKNOWN) 851 return cmd->err; 852 853 return ret; 854 } 855 856 return 0; 857 } 858 859 static struct i2c_dev_desc * 860 i3c_master_find_i2c_dev_by_addr(const struct i3c_master_controller *master, 861 u16 addr) 862 { 863 struct i2c_dev_desc *dev; 864 865 i3c_bus_for_each_i2cdev(&master->bus, dev) { 866 if (dev->addr == addr) 867 return dev; 868 } 869 870 return NULL; 871 } 872 873 /** 874 * i3c_master_get_free_addr() - get a free address on the bus 875 * @master: I3C master object 876 * @start_addr: where to start searching 877 * 878 * This function must be called with the bus lock held in write mode. 879 * 880 * Return: the first free address starting at @start_addr (included) or -ENOMEM 881 * if there's no more address available. 882 */ 883 int i3c_master_get_free_addr(struct i3c_master_controller *master, 884 u8 start_addr) 885 { 886 return i3c_bus_get_free_addr(&master->bus, start_addr); 887 } 888 EXPORT_SYMBOL_GPL(i3c_master_get_free_addr); 889 890 static void i3c_device_release(struct device *dev) 891 { 892 struct i3c_device *i3cdev = dev_to_i3cdev(dev); 893 894 WARN_ON(i3cdev->desc); 895 896 of_node_put(i3cdev->dev.of_node); 897 kfree(i3cdev); 898 } 899 900 static void i3c_master_free_i3c_dev(struct i3c_dev_desc *dev) 901 { 902 kfree(dev); 903 } 904 905 static struct i3c_dev_desc * 906 i3c_master_alloc_i3c_dev(struct i3c_master_controller *master, 907 const struct i3c_device_info *info) 908 { 909 struct i3c_dev_desc *dev; 910 911 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 912 if (!dev) 913 return ERR_PTR(-ENOMEM); 914 915 dev->common.master = master; 916 dev->info = *info; 917 mutex_init(&dev->ibi_lock); 918 919 return dev; 920 } 921 922 static int i3c_master_rstdaa_locked(struct i3c_master_controller *master, 923 u8 addr) 924 { 925 enum i3c_addr_slot_status addrstat; 926 struct i3c_ccc_cmd_dest dest; 927 struct i3c_ccc_cmd cmd; 928 int ret; 929 930 if (!master) 931 return -EINVAL; 932 933 addrstat = i3c_bus_get_addr_slot_status(&master->bus, addr); 934 if (addr != I3C_BROADCAST_ADDR && addrstat != I3C_ADDR_SLOT_I3C_DEV) 935 return -EINVAL; 936 937 i3c_ccc_cmd_dest_init(&dest, addr, 0); 938 i3c_ccc_cmd_init(&cmd, false, 939 I3C_CCC_RSTDAA(addr == I3C_BROADCAST_ADDR), 940 &dest, 1); 941 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 942 i3c_ccc_cmd_dest_cleanup(&dest); 943 944 return ret; 945 } 946 947 /** 948 * i3c_master_entdaa_locked() - start a DAA (Dynamic Address Assignment) 949 * procedure 950 * @master: master used to send frames on the bus 951 * 952 * Send a ENTDAA CCC command to start a DAA procedure. 953 * 954 * Note that this function only sends the ENTDAA CCC command, all the logic 955 * behind dynamic address assignment has to be handled in the I3C master 956 * driver. 957 * 958 * This function must be called with the bus lock held in write mode. 959 * 960 * Return: 0 in case of success, a positive I3C error code if the error is 961 * one of the official Mx error codes, and a negative error code otherwise. 962 */ 963 int i3c_master_entdaa_locked(struct i3c_master_controller *master) 964 { 965 struct i3c_ccc_cmd_dest dest; 966 struct i3c_ccc_cmd cmd; 967 int ret; 968 969 i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR, 0); 970 i3c_ccc_cmd_init(&cmd, false, I3C_CCC_ENTDAA, &dest, 1); 971 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 972 i3c_ccc_cmd_dest_cleanup(&dest); 973 974 return ret; 975 } 976 EXPORT_SYMBOL_GPL(i3c_master_entdaa_locked); 977 978 static int i3c_master_enec_disec_locked(struct i3c_master_controller *master, 979 u8 addr, bool enable, u8 evts) 980 { 981 struct i3c_ccc_events *events; 982 struct i3c_ccc_cmd_dest dest; 983 struct i3c_ccc_cmd cmd; 984 int ret; 985 986 events = i3c_ccc_cmd_dest_init(&dest, addr, sizeof(*events)); 987 if (!events) 988 return -ENOMEM; 989 990 events->events = evts; 991 i3c_ccc_cmd_init(&cmd, false, 992 enable ? 993 I3C_CCC_ENEC(addr == I3C_BROADCAST_ADDR) : 994 I3C_CCC_DISEC(addr == I3C_BROADCAST_ADDR), 995 &dest, 1); 996 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 997 i3c_ccc_cmd_dest_cleanup(&dest); 998 999 return ret; 1000 } 1001 1002 /** 1003 * i3c_master_disec_locked() - send a DISEC CCC command 1004 * @master: master used to send frames on the bus 1005 * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR 1006 * @evts: events to disable 1007 * 1008 * Send a DISEC CCC command to disable some or all events coming from a 1009 * specific slave, or all devices if @addr is %I3C_BROADCAST_ADDR. 1010 * 1011 * This function must be called with the bus lock held in write mode. 1012 * 1013 * Return: 0 in case of success, a positive I3C error code if the error is 1014 * one of the official Mx error codes, and a negative error code otherwise. 1015 */ 1016 int i3c_master_disec_locked(struct i3c_master_controller *master, u8 addr, 1017 u8 evts) 1018 { 1019 return i3c_master_enec_disec_locked(master, addr, false, evts); 1020 } 1021 EXPORT_SYMBOL_GPL(i3c_master_disec_locked); 1022 1023 /** 1024 * i3c_master_enec_locked() - send an ENEC CCC command 1025 * @master: master used to send frames on the bus 1026 * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR 1027 * @evts: events to disable 1028 * 1029 * Sends an ENEC CCC command to enable some or all events coming from a 1030 * specific slave, or all devices if @addr is %I3C_BROADCAST_ADDR. 1031 * 1032 * This function must be called with the bus lock held in write mode. 1033 * 1034 * Return: 0 in case of success, a positive I3C error code if the error is 1035 * one of the official Mx error codes, and a negative error code otherwise. 1036 */ 1037 int i3c_master_enec_locked(struct i3c_master_controller *master, u8 addr, 1038 u8 evts) 1039 { 1040 return i3c_master_enec_disec_locked(master, addr, true, evts); 1041 } 1042 EXPORT_SYMBOL_GPL(i3c_master_enec_locked); 1043 1044 /** 1045 * i3c_master_defslvs_locked() - send a DEFSLVS CCC command 1046 * @master: master used to send frames on the bus 1047 * 1048 * Send a DEFSLVS CCC command containing all the devices known to the @master. 1049 * This is useful when you have secondary masters on the bus to propagate 1050 * device information. 1051 * 1052 * This should be called after all I3C devices have been discovered (in other 1053 * words, after the DAA procedure has finished) and instantiated in 1054 * &i3c_master_controller_ops->bus_init(). 1055 * It should also be called if a master ACKed an Hot-Join request and assigned 1056 * a dynamic address to the device joining the bus. 1057 * 1058 * This function must be called with the bus lock held in write mode. 1059 * 1060 * Return: 0 in case of success, a positive I3C error code if the error is 1061 * one of the official Mx error codes, and a negative error code otherwise. 1062 */ 1063 int i3c_master_defslvs_locked(struct i3c_master_controller *master) 1064 { 1065 struct i3c_ccc_defslvs *defslvs; 1066 struct i3c_ccc_dev_desc *desc; 1067 struct i3c_ccc_cmd_dest dest; 1068 struct i3c_dev_desc *i3cdev; 1069 struct i2c_dev_desc *i2cdev; 1070 struct i3c_ccc_cmd cmd; 1071 struct i3c_bus *bus; 1072 bool send = false; 1073 int ndevs = 0, ret; 1074 1075 if (!master) 1076 return -EINVAL; 1077 1078 bus = i3c_master_get_bus(master); 1079 i3c_bus_for_each_i3cdev(bus, i3cdev) { 1080 ndevs++; 1081 1082 if (i3cdev == master->this) 1083 continue; 1084 1085 if (I3C_BCR_DEVICE_ROLE(i3cdev->info.bcr) == 1086 I3C_BCR_I3C_MASTER) 1087 send = true; 1088 } 1089 1090 /* No other master on the bus, skip DEFSLVS. */ 1091 if (!send) 1092 return 0; 1093 1094 i3c_bus_for_each_i2cdev(bus, i2cdev) 1095 ndevs++; 1096 1097 defslvs = i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR, 1098 struct_size(defslvs, slaves, 1099 ndevs - 1)); 1100 if (!defslvs) 1101 return -ENOMEM; 1102 1103 defslvs->count = ndevs; 1104 defslvs->master.bcr = master->this->info.bcr; 1105 defslvs->master.dcr = master->this->info.dcr; 1106 defslvs->master.dyn_addr = master->this->info.dyn_addr << 1; 1107 defslvs->master.static_addr = I3C_BROADCAST_ADDR << 1; 1108 1109 desc = defslvs->slaves; 1110 i3c_bus_for_each_i2cdev(bus, i2cdev) { 1111 desc->lvr = i2cdev->lvr; 1112 desc->static_addr = i2cdev->addr << 1; 1113 desc++; 1114 } 1115 1116 i3c_bus_for_each_i3cdev(bus, i3cdev) { 1117 /* Skip the I3C dev representing this master. */ 1118 if (i3cdev == master->this) 1119 continue; 1120 1121 desc->bcr = i3cdev->info.bcr; 1122 desc->dcr = i3cdev->info.dcr; 1123 desc->dyn_addr = i3cdev->info.dyn_addr << 1; 1124 desc->static_addr = i3cdev->info.static_addr << 1; 1125 desc++; 1126 } 1127 1128 i3c_ccc_cmd_init(&cmd, false, I3C_CCC_DEFSLVS, &dest, 1); 1129 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1130 i3c_ccc_cmd_dest_cleanup(&dest); 1131 1132 return ret; 1133 } 1134 EXPORT_SYMBOL_GPL(i3c_master_defslvs_locked); 1135 1136 static int i3c_master_setda_locked(struct i3c_master_controller *master, 1137 u8 oldaddr, u8 newaddr, bool setdasa) 1138 { 1139 struct i3c_ccc_cmd_dest dest; 1140 struct i3c_ccc_setda *setda; 1141 struct i3c_ccc_cmd cmd; 1142 int ret; 1143 1144 if (!oldaddr || !newaddr) 1145 return -EINVAL; 1146 1147 setda = i3c_ccc_cmd_dest_init(&dest, oldaddr, sizeof(*setda)); 1148 if (!setda) 1149 return -ENOMEM; 1150 1151 setda->addr = newaddr << 1; 1152 i3c_ccc_cmd_init(&cmd, false, 1153 setdasa ? I3C_CCC_SETDASA : I3C_CCC_SETNEWDA, 1154 &dest, 1); 1155 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1156 i3c_ccc_cmd_dest_cleanup(&dest); 1157 1158 return ret; 1159 } 1160 1161 static int i3c_master_setdasa_locked(struct i3c_master_controller *master, 1162 u8 static_addr, u8 dyn_addr) 1163 { 1164 return i3c_master_setda_locked(master, static_addr, dyn_addr, true); 1165 } 1166 1167 static int i3c_master_setnewda_locked(struct i3c_master_controller *master, 1168 u8 oldaddr, u8 newaddr) 1169 { 1170 return i3c_master_setda_locked(master, oldaddr, newaddr, false); 1171 } 1172 1173 static int i3c_master_getmrl_locked(struct i3c_master_controller *master, 1174 struct i3c_device_info *info) 1175 { 1176 struct i3c_ccc_cmd_dest dest; 1177 struct i3c_ccc_mrl *mrl; 1178 struct i3c_ccc_cmd cmd; 1179 int ret; 1180 1181 mrl = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*mrl)); 1182 if (!mrl) 1183 return -ENOMEM; 1184 1185 /* 1186 * When the device does not have IBI payload GETMRL only returns 2 1187 * bytes of data. 1188 */ 1189 if (!(info->bcr & I3C_BCR_IBI_PAYLOAD)) 1190 dest.payload.len -= 1; 1191 1192 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMRL, &dest, 1); 1193 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1194 if (ret) 1195 goto out; 1196 1197 switch (dest.payload.len) { 1198 case 3: 1199 info->max_ibi_len = mrl->ibi_len; 1200 fallthrough; 1201 case 2: 1202 info->max_read_len = be16_to_cpu(mrl->read_len); 1203 break; 1204 default: 1205 ret = -EIO; 1206 goto out; 1207 } 1208 1209 out: 1210 i3c_ccc_cmd_dest_cleanup(&dest); 1211 1212 return ret; 1213 } 1214 1215 static int i3c_master_getmwl_locked(struct i3c_master_controller *master, 1216 struct i3c_device_info *info) 1217 { 1218 struct i3c_ccc_cmd_dest dest; 1219 struct i3c_ccc_mwl *mwl; 1220 struct i3c_ccc_cmd cmd; 1221 int ret; 1222 1223 mwl = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*mwl)); 1224 if (!mwl) 1225 return -ENOMEM; 1226 1227 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMWL, &dest, 1); 1228 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1229 if (ret) 1230 goto out; 1231 1232 if (dest.payload.len != sizeof(*mwl)) { 1233 ret = -EIO; 1234 goto out; 1235 } 1236 1237 info->max_write_len = be16_to_cpu(mwl->len); 1238 1239 out: 1240 i3c_ccc_cmd_dest_cleanup(&dest); 1241 1242 return ret; 1243 } 1244 1245 static int i3c_master_getmxds_locked(struct i3c_master_controller *master, 1246 struct i3c_device_info *info) 1247 { 1248 struct i3c_ccc_getmxds *getmaxds; 1249 struct i3c_ccc_cmd_dest dest; 1250 struct i3c_ccc_cmd cmd; 1251 int ret; 1252 1253 getmaxds = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, 1254 sizeof(*getmaxds)); 1255 if (!getmaxds) 1256 return -ENOMEM; 1257 1258 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMXDS, &dest, 1); 1259 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1260 if (ret) { 1261 /* 1262 * Retry when the device does not support max read turnaround 1263 * while expecting shorter length from this CCC command. 1264 */ 1265 dest.payload.len -= 3; 1266 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1267 if (ret) 1268 goto out; 1269 } 1270 1271 if (dest.payload.len != 2 && dest.payload.len != 5) { 1272 ret = -EIO; 1273 goto out; 1274 } 1275 1276 info->max_read_ds = getmaxds->maxrd; 1277 info->max_write_ds = getmaxds->maxwr; 1278 if (dest.payload.len == 5) 1279 info->max_read_turnaround = getmaxds->maxrdturn[0] | 1280 ((u32)getmaxds->maxrdturn[1] << 8) | 1281 ((u32)getmaxds->maxrdturn[2] << 16); 1282 1283 out: 1284 i3c_ccc_cmd_dest_cleanup(&dest); 1285 1286 return ret; 1287 } 1288 1289 static int i3c_master_gethdrcap_locked(struct i3c_master_controller *master, 1290 struct i3c_device_info *info) 1291 { 1292 struct i3c_ccc_gethdrcap *gethdrcap; 1293 struct i3c_ccc_cmd_dest dest; 1294 struct i3c_ccc_cmd cmd; 1295 int ret; 1296 1297 gethdrcap = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, 1298 sizeof(*gethdrcap)); 1299 if (!gethdrcap) 1300 return -ENOMEM; 1301 1302 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETHDRCAP, &dest, 1); 1303 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1304 if (ret) 1305 goto out; 1306 1307 if (dest.payload.len != 1) { 1308 ret = -EIO; 1309 goto out; 1310 } 1311 1312 info->hdr_cap = gethdrcap->modes; 1313 1314 out: 1315 i3c_ccc_cmd_dest_cleanup(&dest); 1316 1317 return ret; 1318 } 1319 1320 static int i3c_master_getpid_locked(struct i3c_master_controller *master, 1321 struct i3c_device_info *info) 1322 { 1323 struct i3c_ccc_getpid *getpid; 1324 struct i3c_ccc_cmd_dest dest; 1325 struct i3c_ccc_cmd cmd; 1326 int ret, i; 1327 1328 getpid = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getpid)); 1329 if (!getpid) 1330 return -ENOMEM; 1331 1332 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETPID, &dest, 1); 1333 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1334 if (ret) 1335 goto out; 1336 1337 info->pid = 0; 1338 for (i = 0; i < sizeof(getpid->pid); i++) { 1339 int sft = (sizeof(getpid->pid) - i - 1) * 8; 1340 1341 info->pid |= (u64)getpid->pid[i] << sft; 1342 } 1343 1344 out: 1345 i3c_ccc_cmd_dest_cleanup(&dest); 1346 1347 return ret; 1348 } 1349 1350 static int i3c_master_getbcr_locked(struct i3c_master_controller *master, 1351 struct i3c_device_info *info) 1352 { 1353 struct i3c_ccc_getbcr *getbcr; 1354 struct i3c_ccc_cmd_dest dest; 1355 struct i3c_ccc_cmd cmd; 1356 int ret; 1357 1358 getbcr = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getbcr)); 1359 if (!getbcr) 1360 return -ENOMEM; 1361 1362 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETBCR, &dest, 1); 1363 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1364 if (ret) 1365 goto out; 1366 1367 info->bcr = getbcr->bcr; 1368 1369 out: 1370 i3c_ccc_cmd_dest_cleanup(&dest); 1371 1372 return ret; 1373 } 1374 1375 static int i3c_master_getdcr_locked(struct i3c_master_controller *master, 1376 struct i3c_device_info *info) 1377 { 1378 struct i3c_ccc_getdcr *getdcr; 1379 struct i3c_ccc_cmd_dest dest; 1380 struct i3c_ccc_cmd cmd; 1381 int ret; 1382 1383 getdcr = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getdcr)); 1384 if (!getdcr) 1385 return -ENOMEM; 1386 1387 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETDCR, &dest, 1); 1388 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1389 if (ret) 1390 goto out; 1391 1392 info->dcr = getdcr->dcr; 1393 1394 out: 1395 i3c_ccc_cmd_dest_cleanup(&dest); 1396 1397 return ret; 1398 } 1399 1400 static int i3c_master_retrieve_dev_info(struct i3c_dev_desc *dev) 1401 { 1402 struct i3c_master_controller *master = i3c_dev_get_master(dev); 1403 enum i3c_addr_slot_status slot_status; 1404 int ret; 1405 1406 if (!dev->info.dyn_addr) 1407 return -EINVAL; 1408 1409 slot_status = i3c_bus_get_addr_slot_status(&master->bus, 1410 dev->info.dyn_addr); 1411 if (slot_status == I3C_ADDR_SLOT_RSVD || 1412 slot_status == I3C_ADDR_SLOT_I2C_DEV) 1413 return -EINVAL; 1414 1415 ret = i3c_master_getpid_locked(master, &dev->info); 1416 if (ret) 1417 return ret; 1418 1419 ret = i3c_master_getbcr_locked(master, &dev->info); 1420 if (ret) 1421 return ret; 1422 1423 ret = i3c_master_getdcr_locked(master, &dev->info); 1424 if (ret) 1425 return ret; 1426 1427 if (dev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM) { 1428 ret = i3c_master_getmxds_locked(master, &dev->info); 1429 if (ret) 1430 return ret; 1431 } 1432 1433 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) 1434 dev->info.max_ibi_len = 1; 1435 1436 i3c_master_getmrl_locked(master, &dev->info); 1437 i3c_master_getmwl_locked(master, &dev->info); 1438 1439 if (dev->info.bcr & I3C_BCR_HDR_CAP) { 1440 ret = i3c_master_gethdrcap_locked(master, &dev->info); 1441 if (ret && ret != -EOPNOTSUPP) 1442 return ret; 1443 } 1444 1445 return 0; 1446 } 1447 1448 static void i3c_master_put_i3c_addrs(struct i3c_dev_desc *dev) 1449 { 1450 struct i3c_master_controller *master = i3c_dev_get_master(dev); 1451 1452 if (dev->info.static_addr) 1453 i3c_bus_set_addr_slot_status(&master->bus, 1454 dev->info.static_addr, 1455 I3C_ADDR_SLOT_FREE); 1456 1457 if (dev->info.dyn_addr) 1458 i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr, 1459 I3C_ADDR_SLOT_FREE); 1460 1461 if (dev->boardinfo && dev->boardinfo->init_dyn_addr) 1462 i3c_bus_set_addr_slot_status(&master->bus, dev->boardinfo->init_dyn_addr, 1463 I3C_ADDR_SLOT_FREE); 1464 } 1465 1466 static int i3c_master_get_i3c_addrs(struct i3c_dev_desc *dev) 1467 { 1468 struct i3c_master_controller *master = i3c_dev_get_master(dev); 1469 enum i3c_addr_slot_status status; 1470 1471 if (!dev->info.static_addr && !dev->info.dyn_addr) 1472 return 0; 1473 1474 if (dev->info.static_addr) { 1475 status = i3c_bus_get_addr_slot_status(&master->bus, 1476 dev->info.static_addr); 1477 /* Since static address and assigned dynamic address can be 1478 * equal, allow this case to pass. 1479 */ 1480 if (status != I3C_ADDR_SLOT_FREE && 1481 dev->info.static_addr != dev->boardinfo->init_dyn_addr) 1482 return -EBUSY; 1483 1484 i3c_bus_set_addr_slot_status(&master->bus, 1485 dev->info.static_addr, 1486 I3C_ADDR_SLOT_I3C_DEV); 1487 } 1488 1489 /* 1490 * ->init_dyn_addr should have been reserved before that, so, if we're 1491 * trying to apply a pre-reserved dynamic address, we should not try 1492 * to reserve the address slot a second time. 1493 */ 1494 if (dev->info.dyn_addr && 1495 (!dev->boardinfo || 1496 dev->boardinfo->init_dyn_addr != dev->info.dyn_addr)) { 1497 status = i3c_bus_get_addr_slot_status(&master->bus, 1498 dev->info.dyn_addr); 1499 if (status != I3C_ADDR_SLOT_FREE) 1500 goto err_release_static_addr; 1501 1502 i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr, 1503 I3C_ADDR_SLOT_I3C_DEV); 1504 } 1505 1506 return 0; 1507 1508 err_release_static_addr: 1509 if (dev->info.static_addr) 1510 i3c_bus_set_addr_slot_status(&master->bus, 1511 dev->info.static_addr, 1512 I3C_ADDR_SLOT_FREE); 1513 1514 return -EBUSY; 1515 } 1516 1517 static int i3c_master_attach_i3c_dev(struct i3c_master_controller *master, 1518 struct i3c_dev_desc *dev) 1519 { 1520 int ret; 1521 1522 /* 1523 * We don't attach devices to the controller until they are 1524 * addressable on the bus. 1525 */ 1526 if (!dev->info.static_addr && !dev->info.dyn_addr) 1527 return 0; 1528 1529 ret = i3c_master_get_i3c_addrs(dev); 1530 if (ret) 1531 return ret; 1532 1533 /* Do not attach the master device itself. */ 1534 if (master->this != dev && master->ops->attach_i3c_dev) { 1535 ret = master->ops->attach_i3c_dev(dev); 1536 if (ret) { 1537 i3c_master_put_i3c_addrs(dev); 1538 return ret; 1539 } 1540 } 1541 1542 list_add_tail(&dev->common.node, &master->bus.devs.i3c); 1543 1544 return 0; 1545 } 1546 1547 static int i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, 1548 u8 old_dyn_addr) 1549 { 1550 struct i3c_master_controller *master = i3c_dev_get_master(dev); 1551 int ret; 1552 1553 if (dev->info.dyn_addr != old_dyn_addr) { 1554 i3c_bus_set_addr_slot_status(&master->bus, 1555 dev->info.dyn_addr, 1556 I3C_ADDR_SLOT_I3C_DEV); 1557 if (old_dyn_addr) 1558 i3c_bus_set_addr_slot_status(&master->bus, old_dyn_addr, 1559 I3C_ADDR_SLOT_FREE); 1560 } 1561 1562 if (master->ops->reattach_i3c_dev) { 1563 ret = master->ops->reattach_i3c_dev(dev, old_dyn_addr); 1564 if (ret) { 1565 i3c_master_put_i3c_addrs(dev); 1566 return ret; 1567 } 1568 } 1569 1570 return 0; 1571 } 1572 1573 static void i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) 1574 { 1575 struct i3c_master_controller *master = i3c_dev_get_master(dev); 1576 1577 /* Do not detach the master device itself. */ 1578 if (master->this != dev && master->ops->detach_i3c_dev) 1579 master->ops->detach_i3c_dev(dev); 1580 1581 i3c_master_put_i3c_addrs(dev); 1582 list_del(&dev->common.node); 1583 } 1584 1585 static int i3c_master_attach_i2c_dev(struct i3c_master_controller *master, 1586 struct i2c_dev_desc *dev) 1587 { 1588 int ret; 1589 1590 if (master->ops->attach_i2c_dev) { 1591 ret = master->ops->attach_i2c_dev(dev); 1592 if (ret) 1593 return ret; 1594 } 1595 1596 list_add_tail(&dev->common.node, &master->bus.devs.i2c); 1597 1598 return 0; 1599 } 1600 1601 static void i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) 1602 { 1603 struct i3c_master_controller *master = i2c_dev_get_master(dev); 1604 1605 list_del(&dev->common.node); 1606 1607 if (master->ops->detach_i2c_dev) 1608 master->ops->detach_i2c_dev(dev); 1609 } 1610 1611 static int i3c_master_early_i3c_dev_add(struct i3c_master_controller *master, 1612 struct i3c_dev_boardinfo *boardinfo) 1613 { 1614 struct i3c_device_info info = { 1615 .static_addr = boardinfo->static_addr, 1616 .pid = boardinfo->pid, 1617 }; 1618 struct i3c_dev_desc *i3cdev; 1619 int ret; 1620 1621 i3cdev = i3c_master_alloc_i3c_dev(master, &info); 1622 if (IS_ERR(i3cdev)) 1623 return -ENOMEM; 1624 1625 i3cdev->boardinfo = boardinfo; 1626 1627 ret = i3c_master_attach_i3c_dev(master, i3cdev); 1628 if (ret) 1629 goto err_free_dev; 1630 1631 ret = i3c_master_setdasa_locked(master, i3cdev->info.static_addr, 1632 i3cdev->boardinfo->init_dyn_addr); 1633 if (ret) 1634 goto err_detach_dev; 1635 1636 i3cdev->info.dyn_addr = i3cdev->boardinfo->init_dyn_addr; 1637 ret = i3c_master_reattach_i3c_dev(i3cdev, 0); 1638 if (ret) 1639 goto err_rstdaa; 1640 1641 ret = i3c_master_retrieve_dev_info(i3cdev); 1642 if (ret) 1643 goto err_rstdaa; 1644 1645 return 0; 1646 1647 err_rstdaa: 1648 i3c_master_rstdaa_locked(master, i3cdev->boardinfo->init_dyn_addr); 1649 err_detach_dev: 1650 i3c_master_detach_i3c_dev(i3cdev); 1651 err_free_dev: 1652 i3c_master_free_i3c_dev(i3cdev); 1653 1654 return ret; 1655 } 1656 1657 static void 1658 i3c_master_register_new_i3c_devs(struct i3c_master_controller *master) 1659 { 1660 struct i3c_dev_desc *desc; 1661 int ret; 1662 1663 if (!master->init_done) 1664 return; 1665 1666 i3c_bus_for_each_i3cdev(&master->bus, desc) { 1667 if (desc->dev || !desc->info.dyn_addr || desc == master->this) 1668 continue; 1669 1670 desc->dev = kzalloc(sizeof(*desc->dev), GFP_KERNEL); 1671 if (!desc->dev) 1672 continue; 1673 1674 desc->dev->bus = &master->bus; 1675 desc->dev->desc = desc; 1676 desc->dev->dev.parent = &master->dev; 1677 desc->dev->dev.type = &i3c_device_type; 1678 desc->dev->dev.bus = &i3c_bus_type; 1679 desc->dev->dev.release = i3c_device_release; 1680 dev_set_name(&desc->dev->dev, "%d-%llx", master->bus.id, 1681 desc->info.pid); 1682 1683 if (desc->boardinfo) 1684 desc->dev->dev.of_node = desc->boardinfo->of_node; 1685 1686 ret = device_register(&desc->dev->dev); 1687 if (ret) { 1688 dev_err(&master->dev, 1689 "Failed to add I3C device (err = %d)\n", ret); 1690 put_device(&desc->dev->dev); 1691 } 1692 } 1693 } 1694 1695 /** 1696 * i3c_master_do_daa() - do a DAA (Dynamic Address Assignment) 1697 * @master: master doing the DAA 1698 * 1699 * This function is instantiating an I3C device object and adding it to the 1700 * I3C device list. All device information are automatically retrieved using 1701 * standard CCC commands. 1702 * 1703 * The I3C device object is returned in case the master wants to attach 1704 * private data to it using i3c_dev_set_master_data(). 1705 * 1706 * This function must be called with the bus lock held in write mode. 1707 * 1708 * Return: a 0 in case of success, an negative error code otherwise. 1709 */ 1710 int i3c_master_do_daa(struct i3c_master_controller *master) 1711 { 1712 int ret; 1713 1714 i3c_bus_maintenance_lock(&master->bus); 1715 ret = master->ops->do_daa(master); 1716 i3c_bus_maintenance_unlock(&master->bus); 1717 1718 if (ret) 1719 return ret; 1720 1721 i3c_bus_normaluse_lock(&master->bus); 1722 i3c_master_register_new_i3c_devs(master); 1723 i3c_bus_normaluse_unlock(&master->bus); 1724 1725 return 0; 1726 } 1727 EXPORT_SYMBOL_GPL(i3c_master_do_daa); 1728 1729 /** 1730 * i3c_master_dma_map_single() - Map buffer for single DMA transfer 1731 * @dev: device object of a device doing DMA 1732 * @buf: destination/source buffer for DMA 1733 * @len: length of transfer 1734 * @force_bounce: true, force to use a bounce buffer, 1735 * false, function will auto check is a bounce buffer required 1736 * @dir: DMA direction 1737 * 1738 * Map buffer for a DMA transfer and allocate a bounce buffer if required. 1739 * 1740 * Return: I3C DMA transfer descriptor or NULL in case of error. 1741 */ 1742 struct i3c_dma *i3c_master_dma_map_single(struct device *dev, void *buf, 1743 size_t len, bool force_bounce, enum dma_data_direction dir) 1744 { 1745 void *bounce __free(kfree) = NULL; 1746 void *dma_buf = buf; 1747 1748 struct i3c_dma *dma_xfer __free(kfree) = kzalloc(sizeof(*dma_xfer), GFP_KERNEL); 1749 if (!dma_xfer) 1750 return NULL; 1751 1752 dma_xfer->dev = dev; 1753 dma_xfer->buf = buf; 1754 dma_xfer->dir = dir; 1755 dma_xfer->len = len; 1756 dma_xfer->map_len = len; 1757 1758 if (is_vmalloc_addr(buf)) 1759 force_bounce = true; 1760 1761 if (force_bounce) { 1762 dma_xfer->map_len = ALIGN(len, cache_line_size()); 1763 if (dir == DMA_FROM_DEVICE) 1764 bounce = kzalloc(dma_xfer->map_len, GFP_KERNEL); 1765 else 1766 bounce = kmemdup(buf, dma_xfer->map_len, GFP_KERNEL); 1767 if (!bounce) 1768 return NULL; 1769 dma_buf = bounce; 1770 } 1771 1772 dma_xfer->addr = dma_map_single(dev, dma_buf, dma_xfer->map_len, dir); 1773 if (dma_mapping_error(dev, dma_xfer->addr)) 1774 return NULL; 1775 1776 dma_xfer->bounce_buf = no_free_ptr(bounce); 1777 return no_free_ptr(dma_xfer); 1778 } 1779 EXPORT_SYMBOL_GPL(i3c_master_dma_map_single); 1780 1781 /** 1782 * i3c_master_dma_unmap_single() - Unmap buffer after DMA 1783 * @dma_xfer: DMA transfer and mapping descriptor 1784 * 1785 * Unmap buffer and cleanup DMA transfer descriptor. 1786 */ 1787 void i3c_master_dma_unmap_single(struct i3c_dma *dma_xfer) 1788 { 1789 dma_unmap_single(dma_xfer->dev, dma_xfer->addr, 1790 dma_xfer->map_len, dma_xfer->dir); 1791 if (dma_xfer->bounce_buf) { 1792 if (dma_xfer->dir == DMA_FROM_DEVICE) 1793 memcpy(dma_xfer->buf, dma_xfer->bounce_buf, 1794 dma_xfer->len); 1795 kfree(dma_xfer->bounce_buf); 1796 } 1797 kfree(dma_xfer); 1798 } 1799 EXPORT_SYMBOL_GPL(i3c_master_dma_unmap_single); 1800 1801 /** 1802 * i3c_master_set_info() - set master device information 1803 * @master: master used to send frames on the bus 1804 * @info: I3C device information 1805 * 1806 * Set master device info. This should be called from 1807 * &i3c_master_controller_ops->bus_init(). 1808 * 1809 * Not all &i3c_device_info fields are meaningful for a master device. 1810 * Here is a list of fields that should be properly filled: 1811 * 1812 * - &i3c_device_info->dyn_addr 1813 * - &i3c_device_info->bcr 1814 * - &i3c_device_info->dcr 1815 * - &i3c_device_info->pid 1816 * - &i3c_device_info->hdr_cap if %I3C_BCR_HDR_CAP bit is set in 1817 * &i3c_device_info->bcr 1818 * 1819 * This function must be called with the bus lock held in maintenance mode. 1820 * 1821 * Return: 0 if @info contains valid information (not every piece of 1822 * information can be checked, but we can at least make sure @info->dyn_addr 1823 * and @info->bcr are correct), -EINVAL otherwise. 1824 */ 1825 int i3c_master_set_info(struct i3c_master_controller *master, 1826 const struct i3c_device_info *info) 1827 { 1828 struct i3c_dev_desc *i3cdev; 1829 int ret; 1830 1831 if (!i3c_bus_dev_addr_is_avail(&master->bus, info->dyn_addr)) 1832 return -EINVAL; 1833 1834 if (I3C_BCR_DEVICE_ROLE(info->bcr) == I3C_BCR_I3C_MASTER && 1835 master->secondary) 1836 return -EINVAL; 1837 1838 if (master->this) 1839 return -EINVAL; 1840 1841 i3cdev = i3c_master_alloc_i3c_dev(master, info); 1842 if (IS_ERR(i3cdev)) 1843 return PTR_ERR(i3cdev); 1844 1845 master->this = i3cdev; 1846 master->bus.cur_master = master->this; 1847 1848 ret = i3c_master_attach_i3c_dev(master, i3cdev); 1849 if (ret) 1850 goto err_free_dev; 1851 1852 return 0; 1853 1854 err_free_dev: 1855 i3c_master_free_i3c_dev(i3cdev); 1856 1857 return ret; 1858 } 1859 EXPORT_SYMBOL_GPL(i3c_master_set_info); 1860 1861 static void i3c_master_detach_free_devs(struct i3c_master_controller *master) 1862 { 1863 struct i3c_dev_desc *i3cdev, *i3ctmp; 1864 struct i2c_dev_desc *i2cdev, *i2ctmp; 1865 1866 list_for_each_entry_safe(i3cdev, i3ctmp, &master->bus.devs.i3c, 1867 common.node) { 1868 i3c_master_detach_i3c_dev(i3cdev); 1869 1870 if (i3cdev->boardinfo && i3cdev->boardinfo->init_dyn_addr) 1871 i3c_bus_set_addr_slot_status(&master->bus, 1872 i3cdev->boardinfo->init_dyn_addr, 1873 I3C_ADDR_SLOT_FREE); 1874 1875 i3c_master_free_i3c_dev(i3cdev); 1876 } 1877 1878 list_for_each_entry_safe(i2cdev, i2ctmp, &master->bus.devs.i2c, 1879 common.node) { 1880 i3c_master_detach_i2c_dev(i2cdev); 1881 i3c_bus_set_addr_slot_status(&master->bus, 1882 i2cdev->addr, 1883 I3C_ADDR_SLOT_FREE); 1884 i3c_master_free_i2c_dev(i2cdev); 1885 } 1886 } 1887 1888 /** 1889 * i3c_master_bus_init() - initialize an I3C bus 1890 * @master: main master initializing the bus 1891 * 1892 * This function is following all initialisation steps described in the I3C 1893 * specification: 1894 * 1895 * 1. Attach I2C devs to the master so that the master can fill its internal 1896 * device table appropriately 1897 * 1898 * 2. Call &i3c_master_controller_ops->bus_init() method to initialize 1899 * the master controller. That's usually where the bus mode is selected 1900 * (pure bus or mixed fast/slow bus) 1901 * 1902 * 3. Instruct all devices on the bus to drop their dynamic address. This is 1903 * particularly important when the bus was previously configured by someone 1904 * else (for example the bootloader) 1905 * 1906 * 4. Disable all slave events. 1907 * 1908 * 5. Reserve address slots for I3C devices with init_dyn_addr. And if devices 1909 * also have static_addr, try to pre-assign dynamic addresses requested by 1910 * the FW with SETDASA and attach corresponding statically defined I3C 1911 * devices to the master. 1912 * 1913 * 6. Do a DAA (Dynamic Address Assignment) to assign dynamic addresses to all 1914 * remaining I3C devices 1915 * 1916 * Once this is done, all I3C and I2C devices should be usable. 1917 * 1918 * Return: a 0 in case of success, an negative error code otherwise. 1919 */ 1920 static int i3c_master_bus_init(struct i3c_master_controller *master) 1921 { 1922 enum i3c_addr_slot_status status; 1923 struct i2c_dev_boardinfo *i2cboardinfo; 1924 struct i3c_dev_boardinfo *i3cboardinfo; 1925 struct i2c_dev_desc *i2cdev; 1926 int ret; 1927 1928 /* 1929 * First attach all devices with static definitions provided by the 1930 * FW. 1931 */ 1932 list_for_each_entry(i2cboardinfo, &master->boardinfo.i2c, node) { 1933 status = i3c_bus_get_addr_slot_status(&master->bus, 1934 i2cboardinfo->base.addr); 1935 if (status != I3C_ADDR_SLOT_FREE) { 1936 ret = -EBUSY; 1937 goto err_detach_devs; 1938 } 1939 1940 i3c_bus_set_addr_slot_status(&master->bus, 1941 i2cboardinfo->base.addr, 1942 I3C_ADDR_SLOT_I2C_DEV); 1943 1944 i2cdev = i3c_master_alloc_i2c_dev(master, 1945 i2cboardinfo->base.addr, 1946 i2cboardinfo->lvr); 1947 if (IS_ERR(i2cdev)) { 1948 ret = PTR_ERR(i2cdev); 1949 goto err_detach_devs; 1950 } 1951 1952 ret = i3c_master_attach_i2c_dev(master, i2cdev); 1953 if (ret) { 1954 i3c_master_free_i2c_dev(i2cdev); 1955 goto err_detach_devs; 1956 } 1957 } 1958 1959 /* 1960 * Now execute the controller specific ->bus_init() routine, which 1961 * might configure its internal logic to match the bus limitations. 1962 */ 1963 ret = master->ops->bus_init(master); 1964 if (ret) 1965 goto err_detach_devs; 1966 1967 /* 1968 * The master device should have been instantiated in ->bus_init(), 1969 * complain if this was not the case. 1970 */ 1971 if (!master->this) { 1972 dev_err(&master->dev, 1973 "master_set_info() was not called in ->bus_init()\n"); 1974 ret = -EINVAL; 1975 goto err_bus_cleanup; 1976 } 1977 1978 if (master->ops->set_speed) { 1979 ret = master->ops->set_speed(master, I3C_OPEN_DRAIN_SLOW_SPEED); 1980 if (ret) 1981 goto err_bus_cleanup; 1982 } 1983 1984 /* 1985 * Reset all dynamic address that may have been assigned before 1986 * (assigned by the bootloader for example). 1987 */ 1988 ret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR); 1989 if (ret && ret != I3C_ERROR_M2) 1990 goto err_bus_cleanup; 1991 1992 if (master->ops->set_speed) { 1993 ret = master->ops->set_speed(master, I3C_OPEN_DRAIN_NORMAL_SPEED); 1994 if (ret) 1995 goto err_bus_cleanup; 1996 } 1997 1998 /* Disable all slave events before starting DAA. */ 1999 ret = i3c_master_disec_locked(master, I3C_BROADCAST_ADDR, 2000 I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR | 2001 I3C_CCC_EVENT_HJ); 2002 if (ret && ret != I3C_ERROR_M2) 2003 goto err_bus_cleanup; 2004 2005 /* 2006 * Reserve init_dyn_addr first, and then try to pre-assign dynamic 2007 * address and retrieve device information if needed. 2008 * In case pre-assign dynamic address fails, setting dynamic address to 2009 * the requested init_dyn_addr is retried after DAA is done in 2010 * i3c_master_add_i3c_dev_locked(). 2011 */ 2012 list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) { 2013 2014 /* 2015 * We don't reserve a dynamic address for devices that 2016 * don't explicitly request one. 2017 */ 2018 if (!i3cboardinfo->init_dyn_addr) 2019 continue; 2020 2021 ret = i3c_bus_get_addr_slot_status(&master->bus, 2022 i3cboardinfo->init_dyn_addr); 2023 if (ret != I3C_ADDR_SLOT_FREE) { 2024 ret = -EBUSY; 2025 goto err_rstdaa; 2026 } 2027 2028 /* Do not mark as occupied until real device exist in bus */ 2029 i3c_bus_set_addr_slot_status_mask(&master->bus, 2030 i3cboardinfo->init_dyn_addr, 2031 I3C_ADDR_SLOT_EXT_DESIRED, 2032 I3C_ADDR_SLOT_EXT_STATUS_MASK); 2033 2034 /* 2035 * Only try to create/attach devices that have a static 2036 * address. Other devices will be created/attached when 2037 * DAA happens, and the requested dynamic address will 2038 * be set using SETNEWDA once those devices become 2039 * addressable. 2040 */ 2041 2042 if (i3cboardinfo->static_addr) 2043 i3c_master_early_i3c_dev_add(master, i3cboardinfo); 2044 } 2045 2046 ret = i3c_master_do_daa(master); 2047 if (ret) 2048 goto err_rstdaa; 2049 2050 return 0; 2051 2052 err_rstdaa: 2053 i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR); 2054 2055 err_bus_cleanup: 2056 if (master->ops->bus_cleanup) 2057 master->ops->bus_cleanup(master); 2058 2059 err_detach_devs: 2060 i3c_master_detach_free_devs(master); 2061 2062 return ret; 2063 } 2064 2065 static void i3c_master_bus_cleanup(struct i3c_master_controller *master) 2066 { 2067 if (master->ops->bus_cleanup) 2068 master->ops->bus_cleanup(master); 2069 2070 i3c_master_detach_free_devs(master); 2071 } 2072 2073 static void i3c_master_attach_boardinfo(struct i3c_dev_desc *i3cdev) 2074 { 2075 struct i3c_master_controller *master = i3cdev->common.master; 2076 struct i3c_dev_boardinfo *i3cboardinfo; 2077 2078 list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) { 2079 if (i3cdev->info.pid != i3cboardinfo->pid) 2080 continue; 2081 2082 i3cdev->boardinfo = i3cboardinfo; 2083 i3cdev->info.static_addr = i3cboardinfo->static_addr; 2084 return; 2085 } 2086 } 2087 2088 static struct i3c_dev_desc * 2089 i3c_master_search_i3c_dev_duplicate(struct i3c_dev_desc *refdev) 2090 { 2091 struct i3c_master_controller *master = i3c_dev_get_master(refdev); 2092 struct i3c_dev_desc *i3cdev; 2093 2094 i3c_bus_for_each_i3cdev(&master->bus, i3cdev) { 2095 if (i3cdev != refdev && i3cdev->info.pid == refdev->info.pid) 2096 return i3cdev; 2097 } 2098 2099 return NULL; 2100 } 2101 2102 /** 2103 * i3c_master_add_i3c_dev_locked() - add an I3C slave to the bus 2104 * @master: master used to send frames on the bus 2105 * @addr: I3C slave dynamic address assigned to the device 2106 * 2107 * This function is instantiating an I3C device object and adding it to the 2108 * I3C device list. All device information are automatically retrieved using 2109 * standard CCC commands. 2110 * 2111 * The I3C device object is returned in case the master wants to attach 2112 * private data to it using i3c_dev_set_master_data(). 2113 * 2114 * This function must be called with the bus lock held in write mode. 2115 * 2116 * Return: a 0 in case of success, an negative error code otherwise. 2117 */ 2118 int i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master, 2119 u8 addr) 2120 { 2121 struct i3c_device_info info = { .dyn_addr = addr }; 2122 struct i3c_dev_desc *newdev, *olddev; 2123 u8 old_dyn_addr = addr, expected_dyn_addr; 2124 struct i3c_ibi_setup ibireq = { }; 2125 bool enable_ibi = false; 2126 int ret; 2127 2128 if (!master) 2129 return -EINVAL; 2130 2131 newdev = i3c_master_alloc_i3c_dev(master, &info); 2132 if (IS_ERR(newdev)) 2133 return PTR_ERR(newdev); 2134 2135 ret = i3c_master_attach_i3c_dev(master, newdev); 2136 if (ret) 2137 goto err_free_dev; 2138 2139 ret = i3c_master_retrieve_dev_info(newdev); 2140 if (ret) 2141 goto err_detach_dev; 2142 2143 i3c_master_attach_boardinfo(newdev); 2144 2145 olddev = i3c_master_search_i3c_dev_duplicate(newdev); 2146 if (olddev) { 2147 newdev->dev = olddev->dev; 2148 if (newdev->dev) 2149 newdev->dev->desc = newdev; 2150 2151 /* 2152 * We need to restore the IBI state too, so let's save the 2153 * IBI information and try to restore them after olddev has 2154 * been detached+released and its IBI has been stopped and 2155 * the associated resources have been freed. 2156 */ 2157 mutex_lock(&olddev->ibi_lock); 2158 if (olddev->ibi) { 2159 ibireq.handler = olddev->ibi->handler; 2160 ibireq.max_payload_len = olddev->ibi->max_payload_len; 2161 ibireq.num_slots = olddev->ibi->num_slots; 2162 2163 if (olddev->ibi->enabled) 2164 enable_ibi = true; 2165 /* 2166 * The olddev should not receive any commands on the 2167 * i3c bus as it does not exist and has been assigned 2168 * a new address. This will result in NACK or timeout. 2169 * So, update the olddev->ibi->enabled flag to false 2170 * to avoid DISEC with OldAddr. 2171 */ 2172 olddev->ibi->enabled = false; 2173 i3c_dev_free_ibi_locked(olddev); 2174 } 2175 mutex_unlock(&olddev->ibi_lock); 2176 2177 old_dyn_addr = olddev->info.dyn_addr; 2178 2179 i3c_master_detach_i3c_dev(olddev); 2180 i3c_master_free_i3c_dev(olddev); 2181 } 2182 2183 /* 2184 * Depending on our previous state, the expected dynamic address might 2185 * differ: 2186 * - if the device already had a dynamic address assigned, let's try to 2187 * re-apply this one 2188 * - if the device did not have a dynamic address and the firmware 2189 * requested a specific address, pick this one 2190 * - in any other case, keep the address automatically assigned by the 2191 * master 2192 */ 2193 if (old_dyn_addr && old_dyn_addr != newdev->info.dyn_addr) 2194 expected_dyn_addr = old_dyn_addr; 2195 else if (newdev->boardinfo && newdev->boardinfo->init_dyn_addr) 2196 expected_dyn_addr = newdev->boardinfo->init_dyn_addr; 2197 else 2198 expected_dyn_addr = newdev->info.dyn_addr; 2199 2200 if (newdev->info.dyn_addr != expected_dyn_addr && 2201 i3c_bus_get_addr_slot_status(&master->bus, expected_dyn_addr) == I3C_ADDR_SLOT_FREE) { 2202 /* 2203 * Try to apply the expected dynamic address. If it fails, keep 2204 * the address assigned by the master. 2205 */ 2206 ret = i3c_master_setnewda_locked(master, 2207 newdev->info.dyn_addr, 2208 expected_dyn_addr); 2209 if (!ret) { 2210 old_dyn_addr = newdev->info.dyn_addr; 2211 newdev->info.dyn_addr = expected_dyn_addr; 2212 i3c_master_reattach_i3c_dev(newdev, old_dyn_addr); 2213 } else { 2214 dev_err(&master->dev, 2215 "Failed to assign reserved/old address to device %d%llx", 2216 master->bus.id, newdev->info.pid); 2217 } 2218 } 2219 2220 /* 2221 * Now is time to try to restore the IBI setup. If we're lucky, 2222 * everything works as before, otherwise, all we can do is complain. 2223 * FIXME: maybe we should add callback to inform the driver that it 2224 * should request the IBI again instead of trying to hide that from 2225 * him. 2226 */ 2227 if (ibireq.handler) { 2228 mutex_lock(&newdev->ibi_lock); 2229 ret = i3c_dev_request_ibi_locked(newdev, &ibireq); 2230 if (ret) { 2231 dev_err(&master->dev, 2232 "Failed to request IBI on device %d-%llx", 2233 master->bus.id, newdev->info.pid); 2234 } else if (enable_ibi) { 2235 ret = i3c_dev_enable_ibi_locked(newdev); 2236 if (ret) 2237 dev_err(&master->dev, 2238 "Failed to re-enable IBI on device %d-%llx", 2239 master->bus.id, newdev->info.pid); 2240 } 2241 mutex_unlock(&newdev->ibi_lock); 2242 } 2243 2244 return 0; 2245 2246 err_detach_dev: 2247 if (newdev->dev && newdev->dev->desc) 2248 newdev->dev->desc = NULL; 2249 2250 i3c_master_detach_i3c_dev(newdev); 2251 2252 err_free_dev: 2253 i3c_master_free_i3c_dev(newdev); 2254 2255 return ret; 2256 } 2257 EXPORT_SYMBOL_GPL(i3c_master_add_i3c_dev_locked); 2258 2259 #define OF_I3C_REG1_IS_I2C_DEV BIT(31) 2260 2261 static int 2262 of_i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master, 2263 struct device_node *node, u32 *reg) 2264 { 2265 struct i2c_dev_boardinfo *boardinfo; 2266 struct device *dev = &master->dev; 2267 int ret; 2268 2269 boardinfo = devm_kzalloc(dev, sizeof(*boardinfo), GFP_KERNEL); 2270 if (!boardinfo) 2271 return -ENOMEM; 2272 2273 ret = of_i2c_get_board_info(dev, node, &boardinfo->base); 2274 if (ret) 2275 return ret; 2276 2277 /* 2278 * The I3C Specification does not clearly say I2C devices with 10-bit 2279 * address are supported. These devices can't be passed properly through 2280 * DEFSLVS command. 2281 */ 2282 if (boardinfo->base.flags & I2C_CLIENT_TEN) { 2283 dev_err(dev, "I2C device with 10 bit address not supported."); 2284 return -EOPNOTSUPP; 2285 } 2286 2287 /* LVR is encoded in reg[2]. */ 2288 boardinfo->lvr = reg[2]; 2289 2290 list_add_tail(&boardinfo->node, &master->boardinfo.i2c); 2291 of_node_get(node); 2292 2293 return 0; 2294 } 2295 2296 static int 2297 of_i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master, 2298 struct device_node *node, u32 *reg) 2299 { 2300 struct i3c_dev_boardinfo *boardinfo; 2301 struct device *dev = &master->dev; 2302 enum i3c_addr_slot_status addrstatus; 2303 u32 init_dyn_addr = 0; 2304 2305 boardinfo = devm_kzalloc(dev, sizeof(*boardinfo), GFP_KERNEL); 2306 if (!boardinfo) 2307 return -ENOMEM; 2308 2309 if (reg[0]) { 2310 if (reg[0] > I3C_MAX_ADDR) 2311 return -EINVAL; 2312 2313 addrstatus = i3c_bus_get_addr_slot_status(&master->bus, 2314 reg[0]); 2315 if (addrstatus != I3C_ADDR_SLOT_FREE) 2316 return -EINVAL; 2317 } 2318 2319 boardinfo->static_addr = reg[0]; 2320 2321 if (!of_property_read_u32(node, "assigned-address", &init_dyn_addr)) { 2322 if (init_dyn_addr > I3C_MAX_ADDR) 2323 return -EINVAL; 2324 2325 addrstatus = i3c_bus_get_addr_slot_status(&master->bus, 2326 init_dyn_addr); 2327 if (addrstatus != I3C_ADDR_SLOT_FREE) 2328 return -EINVAL; 2329 } 2330 2331 boardinfo->pid = ((u64)reg[1] << 32) | reg[2]; 2332 2333 if ((boardinfo->pid & GENMASK_ULL(63, 48)) || 2334 I3C_PID_RND_LOWER_32BITS(boardinfo->pid)) 2335 return -EINVAL; 2336 2337 boardinfo->init_dyn_addr = init_dyn_addr; 2338 boardinfo->of_node = of_node_get(node); 2339 list_add_tail(&boardinfo->node, &master->boardinfo.i3c); 2340 2341 return 0; 2342 } 2343 2344 static int of_i3c_master_add_dev(struct i3c_master_controller *master, 2345 struct device_node *node) 2346 { 2347 u32 reg[3]; 2348 int ret; 2349 2350 if (!master) 2351 return -EINVAL; 2352 2353 ret = of_property_read_u32_array(node, "reg", reg, ARRAY_SIZE(reg)); 2354 if (ret) 2355 return ret; 2356 2357 /* 2358 * The manufacturer ID can't be 0. If reg[1] == 0 that means we're 2359 * dealing with an I2C device. 2360 */ 2361 if (!reg[1]) 2362 ret = of_i3c_master_add_i2c_boardinfo(master, node, reg); 2363 else 2364 ret = of_i3c_master_add_i3c_boardinfo(master, node, reg); 2365 2366 return ret; 2367 } 2368 2369 static int of_populate_i3c_bus(struct i3c_master_controller *master) 2370 { 2371 struct device *dev = &master->dev; 2372 struct device_node *i3cbus_np = dev->of_node; 2373 struct device_node *node; 2374 int ret; 2375 u32 val; 2376 2377 if (!i3cbus_np) 2378 return 0; 2379 2380 for_each_available_child_of_node(i3cbus_np, node) { 2381 ret = of_i3c_master_add_dev(master, node); 2382 if (ret) { 2383 of_node_put(node); 2384 return ret; 2385 } 2386 } 2387 2388 /* 2389 * The user might want to limit I2C and I3C speed in case some devices 2390 * on the bus are not supporting typical rates, or if the bus topology 2391 * prevents it from using max possible rate. 2392 */ 2393 if (!of_property_read_u32(i3cbus_np, "i2c-scl-hz", &val)) 2394 master->bus.scl_rate.i2c = val; 2395 2396 if (!of_property_read_u32(i3cbus_np, "i3c-scl-hz", &val)) 2397 master->bus.scl_rate.i3c = val; 2398 2399 return 0; 2400 } 2401 2402 static int i3c_master_i2c_adapter_xfer(struct i2c_adapter *adap, 2403 struct i2c_msg *xfers, int nxfers) 2404 { 2405 struct i3c_master_controller *master = i2c_adapter_to_i3c_master(adap); 2406 struct i2c_dev_desc *dev; 2407 int i, ret; 2408 u16 addr; 2409 2410 if (!xfers || !master || nxfers <= 0) 2411 return -EINVAL; 2412 2413 if (!master->ops->i2c_xfers) 2414 return -EOPNOTSUPP; 2415 2416 /* Doing transfers to different devices is not supported. */ 2417 addr = xfers[0].addr; 2418 for (i = 1; i < nxfers; i++) { 2419 if (addr != xfers[i].addr) 2420 return -EOPNOTSUPP; 2421 } 2422 2423 i3c_bus_normaluse_lock(&master->bus); 2424 dev = i3c_master_find_i2c_dev_by_addr(master, addr); 2425 if (!dev) 2426 ret = -ENOENT; 2427 else 2428 ret = master->ops->i2c_xfers(dev, xfers, nxfers); 2429 i3c_bus_normaluse_unlock(&master->bus); 2430 2431 return ret ? ret : nxfers; 2432 } 2433 2434 static u32 i3c_master_i2c_funcs(struct i2c_adapter *adapter) 2435 { 2436 return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C; 2437 } 2438 2439 static u8 i3c_master_i2c_get_lvr(struct i2c_client *client) 2440 { 2441 /* Fall back to no spike filters and FM bus mode. */ 2442 u8 lvr = I3C_LVR_I2C_INDEX(2) | I3C_LVR_I2C_FM_MODE; 2443 u32 reg[3]; 2444 2445 if (!of_property_read_u32_array(client->dev.of_node, "reg", reg, ARRAY_SIZE(reg))) 2446 lvr = reg[2]; 2447 2448 return lvr; 2449 } 2450 2451 static int i3c_master_i2c_attach(struct i2c_adapter *adap, struct i2c_client *client) 2452 { 2453 struct i3c_master_controller *master = i2c_adapter_to_i3c_master(adap); 2454 enum i3c_addr_slot_status status; 2455 struct i2c_dev_desc *i2cdev; 2456 int ret; 2457 2458 /* Already added by board info? */ 2459 if (i3c_master_find_i2c_dev_by_addr(master, client->addr)) 2460 return 0; 2461 2462 status = i3c_bus_get_addr_slot_status(&master->bus, client->addr); 2463 if (status != I3C_ADDR_SLOT_FREE) 2464 return -EBUSY; 2465 2466 i3c_bus_set_addr_slot_status(&master->bus, client->addr, 2467 I3C_ADDR_SLOT_I2C_DEV); 2468 2469 i2cdev = i3c_master_alloc_i2c_dev(master, client->addr, 2470 i3c_master_i2c_get_lvr(client)); 2471 if (IS_ERR(i2cdev)) { 2472 ret = PTR_ERR(i2cdev); 2473 goto out_clear_status; 2474 } 2475 2476 ret = i3c_master_attach_i2c_dev(master, i2cdev); 2477 if (ret) 2478 goto out_free_dev; 2479 2480 return 0; 2481 2482 out_free_dev: 2483 i3c_master_free_i2c_dev(i2cdev); 2484 out_clear_status: 2485 i3c_bus_set_addr_slot_status(&master->bus, client->addr, 2486 I3C_ADDR_SLOT_FREE); 2487 2488 return ret; 2489 } 2490 2491 static int i3c_master_i2c_detach(struct i2c_adapter *adap, struct i2c_client *client) 2492 { 2493 struct i3c_master_controller *master = i2c_adapter_to_i3c_master(adap); 2494 struct i2c_dev_desc *dev; 2495 2496 dev = i3c_master_find_i2c_dev_by_addr(master, client->addr); 2497 if (!dev) 2498 return -ENODEV; 2499 2500 i3c_master_detach_i2c_dev(dev); 2501 i3c_bus_set_addr_slot_status(&master->bus, dev->addr, 2502 I3C_ADDR_SLOT_FREE); 2503 i3c_master_free_i2c_dev(dev); 2504 2505 return 0; 2506 } 2507 2508 static const struct i2c_algorithm i3c_master_i2c_algo = { 2509 .master_xfer = i3c_master_i2c_adapter_xfer, 2510 .functionality = i3c_master_i2c_funcs, 2511 }; 2512 2513 static int i3c_i2c_notifier_call(struct notifier_block *nb, unsigned long action, 2514 void *data) 2515 { 2516 struct i2c_adapter *adap; 2517 struct i2c_client *client; 2518 struct device *dev = data; 2519 struct i3c_master_controller *master; 2520 int ret; 2521 2522 if (dev->type != &i2c_client_type) 2523 return 0; 2524 2525 client = to_i2c_client(dev); 2526 adap = client->adapter; 2527 2528 if (adap->algo != &i3c_master_i2c_algo) 2529 return 0; 2530 2531 master = i2c_adapter_to_i3c_master(adap); 2532 2533 i3c_bus_maintenance_lock(&master->bus); 2534 switch (action) { 2535 case BUS_NOTIFY_ADD_DEVICE: 2536 ret = i3c_master_i2c_attach(adap, client); 2537 break; 2538 case BUS_NOTIFY_DEL_DEVICE: 2539 ret = i3c_master_i2c_detach(adap, client); 2540 break; 2541 default: 2542 ret = -EINVAL; 2543 } 2544 i3c_bus_maintenance_unlock(&master->bus); 2545 2546 return ret; 2547 } 2548 2549 static struct notifier_block i2cdev_notifier = { 2550 .notifier_call = i3c_i2c_notifier_call, 2551 }; 2552 2553 static int i3c_master_i2c_adapter_init(struct i3c_master_controller *master) 2554 { 2555 struct i2c_adapter *adap = i3c_master_to_i2c_adapter(master); 2556 struct i2c_dev_desc *i2cdev; 2557 struct i2c_dev_boardinfo *i2cboardinfo; 2558 int ret, id; 2559 2560 adap->dev.parent = master->dev.parent; 2561 adap->owner = master->dev.parent->driver->owner; 2562 adap->algo = &i3c_master_i2c_algo; 2563 strscpy(adap->name, dev_name(master->dev.parent), sizeof(adap->name)); 2564 adap->timeout = HZ; 2565 adap->retries = 3; 2566 2567 id = of_alias_get_id(master->dev.of_node, "i2c"); 2568 if (id >= 0) { 2569 adap->nr = id; 2570 ret = i2c_add_numbered_adapter(adap); 2571 } else { 2572 ret = i2c_add_adapter(adap); 2573 } 2574 if (ret) 2575 return ret; 2576 2577 /* 2578 * We silently ignore failures here. The bus should keep working 2579 * correctly even if one or more i2c devices are not registered. 2580 */ 2581 list_for_each_entry(i2cboardinfo, &master->boardinfo.i2c, node) { 2582 i2cdev = i3c_master_find_i2c_dev_by_addr(master, 2583 i2cboardinfo->base.addr); 2584 if (WARN_ON(!i2cdev)) 2585 continue; 2586 i2cdev->dev = i2c_new_client_device(adap, &i2cboardinfo->base); 2587 } 2588 2589 return 0; 2590 } 2591 2592 static void i3c_master_i2c_adapter_cleanup(struct i3c_master_controller *master) 2593 { 2594 struct i2c_dev_desc *i2cdev; 2595 2596 i2c_del_adapter(&master->i2c); 2597 2598 i3c_bus_for_each_i2cdev(&master->bus, i2cdev) 2599 i2cdev->dev = NULL; 2600 } 2601 2602 static void i3c_master_unregister_i3c_devs(struct i3c_master_controller *master) 2603 { 2604 struct i3c_dev_desc *i3cdev; 2605 2606 i3c_bus_for_each_i3cdev(&master->bus, i3cdev) { 2607 if (!i3cdev->dev) 2608 continue; 2609 2610 i3cdev->dev->desc = NULL; 2611 if (device_is_registered(&i3cdev->dev->dev)) 2612 device_unregister(&i3cdev->dev->dev); 2613 else 2614 put_device(&i3cdev->dev->dev); 2615 i3cdev->dev = NULL; 2616 } 2617 } 2618 2619 /** 2620 * i3c_master_queue_ibi() - Queue an IBI 2621 * @dev: the device this IBI is coming from 2622 * @slot: the IBI slot used to store the payload 2623 * 2624 * Queue an IBI to the controller workqueue. The IBI handler attached to 2625 * the dev will be called from a workqueue context. 2626 */ 2627 void i3c_master_queue_ibi(struct i3c_dev_desc *dev, struct i3c_ibi_slot *slot) 2628 { 2629 if (!dev->ibi || !slot) 2630 return; 2631 2632 atomic_inc(&dev->ibi->pending_ibis); 2633 queue_work(dev->ibi->wq, &slot->work); 2634 } 2635 EXPORT_SYMBOL_GPL(i3c_master_queue_ibi); 2636 2637 static void i3c_master_handle_ibi(struct work_struct *work) 2638 { 2639 struct i3c_ibi_slot *slot = container_of(work, struct i3c_ibi_slot, 2640 work); 2641 struct i3c_dev_desc *dev = slot->dev; 2642 struct i3c_master_controller *master = i3c_dev_get_master(dev); 2643 struct i3c_ibi_payload payload; 2644 2645 payload.data = slot->data; 2646 payload.len = slot->len; 2647 2648 if (dev->dev) 2649 dev->ibi->handler(dev->dev, &payload); 2650 2651 master->ops->recycle_ibi_slot(dev, slot); 2652 if (atomic_dec_and_test(&dev->ibi->pending_ibis)) 2653 complete(&dev->ibi->all_ibis_handled); 2654 } 2655 2656 static void i3c_master_init_ibi_slot(struct i3c_dev_desc *dev, 2657 struct i3c_ibi_slot *slot) 2658 { 2659 slot->dev = dev; 2660 INIT_WORK(&slot->work, i3c_master_handle_ibi); 2661 } 2662 2663 struct i3c_generic_ibi_slot { 2664 struct list_head node; 2665 struct i3c_ibi_slot base; 2666 }; 2667 2668 struct i3c_generic_ibi_pool { 2669 spinlock_t lock; 2670 unsigned int num_slots; 2671 struct i3c_generic_ibi_slot *slots; 2672 void *payload_buf; 2673 struct list_head free_slots; 2674 struct list_head pending; 2675 }; 2676 2677 /** 2678 * i3c_generic_ibi_free_pool() - Free a generic IBI pool 2679 * @pool: the IBI pool to free 2680 * 2681 * Free all IBI slots allated by a generic IBI pool. 2682 */ 2683 void i3c_generic_ibi_free_pool(struct i3c_generic_ibi_pool *pool) 2684 { 2685 struct i3c_generic_ibi_slot *slot; 2686 unsigned int nslots = 0; 2687 2688 while (!list_empty(&pool->free_slots)) { 2689 slot = list_first_entry(&pool->free_slots, 2690 struct i3c_generic_ibi_slot, node); 2691 list_del(&slot->node); 2692 nslots++; 2693 } 2694 2695 /* 2696 * If the number of freed slots is not equal to the number of allocated 2697 * slots we have a leak somewhere. 2698 */ 2699 WARN_ON(nslots != pool->num_slots); 2700 2701 kfree(pool->payload_buf); 2702 kfree(pool->slots); 2703 kfree(pool); 2704 } 2705 EXPORT_SYMBOL_GPL(i3c_generic_ibi_free_pool); 2706 2707 /** 2708 * i3c_generic_ibi_alloc_pool() - Create a generic IBI pool 2709 * @dev: the device this pool will be used for 2710 * @req: IBI setup request describing what the device driver expects 2711 * 2712 * Create a generic IBI pool based on the information provided in @req. 2713 * 2714 * Return: a valid IBI pool in case of success, an ERR_PTR() otherwise. 2715 */ 2716 struct i3c_generic_ibi_pool * 2717 i3c_generic_ibi_alloc_pool(struct i3c_dev_desc *dev, 2718 const struct i3c_ibi_setup *req) 2719 { 2720 struct i3c_generic_ibi_pool *pool; 2721 struct i3c_generic_ibi_slot *slot; 2722 unsigned int i; 2723 int ret; 2724 2725 pool = kzalloc(sizeof(*pool), GFP_KERNEL); 2726 if (!pool) 2727 return ERR_PTR(-ENOMEM); 2728 2729 spin_lock_init(&pool->lock); 2730 INIT_LIST_HEAD(&pool->free_slots); 2731 INIT_LIST_HEAD(&pool->pending); 2732 2733 pool->slots = kcalloc(req->num_slots, sizeof(*slot), GFP_KERNEL); 2734 if (!pool->slots) { 2735 ret = -ENOMEM; 2736 goto err_free_pool; 2737 } 2738 2739 if (req->max_payload_len) { 2740 pool->payload_buf = kcalloc(req->num_slots, 2741 req->max_payload_len, GFP_KERNEL); 2742 if (!pool->payload_buf) { 2743 ret = -ENOMEM; 2744 goto err_free_pool; 2745 } 2746 } 2747 2748 for (i = 0; i < req->num_slots; i++) { 2749 slot = &pool->slots[i]; 2750 i3c_master_init_ibi_slot(dev, &slot->base); 2751 2752 if (req->max_payload_len) 2753 slot->base.data = pool->payload_buf + 2754 (i * req->max_payload_len); 2755 2756 list_add_tail(&slot->node, &pool->free_slots); 2757 pool->num_slots++; 2758 } 2759 2760 return pool; 2761 2762 err_free_pool: 2763 i3c_generic_ibi_free_pool(pool); 2764 return ERR_PTR(ret); 2765 } 2766 EXPORT_SYMBOL_GPL(i3c_generic_ibi_alloc_pool); 2767 2768 /** 2769 * i3c_generic_ibi_get_free_slot() - Get a free slot from a generic IBI pool 2770 * @pool: the pool to query an IBI slot on 2771 * 2772 * Search for a free slot in a generic IBI pool. 2773 * The slot should be returned to the pool using i3c_generic_ibi_recycle_slot() 2774 * when it's no longer needed. 2775 * 2776 * Return: a pointer to a free slot, or NULL if there's no free slot available. 2777 */ 2778 struct i3c_ibi_slot * 2779 i3c_generic_ibi_get_free_slot(struct i3c_generic_ibi_pool *pool) 2780 { 2781 struct i3c_generic_ibi_slot *slot; 2782 unsigned long flags; 2783 2784 spin_lock_irqsave(&pool->lock, flags); 2785 slot = list_first_entry_or_null(&pool->free_slots, 2786 struct i3c_generic_ibi_slot, node); 2787 if (slot) 2788 list_del(&slot->node); 2789 spin_unlock_irqrestore(&pool->lock, flags); 2790 2791 return slot ? &slot->base : NULL; 2792 } 2793 EXPORT_SYMBOL_GPL(i3c_generic_ibi_get_free_slot); 2794 2795 /** 2796 * i3c_generic_ibi_recycle_slot() - Return a slot to a generic IBI pool 2797 * @pool: the pool to return the IBI slot to 2798 * @s: IBI slot to recycle 2799 * 2800 * Add an IBI slot back to its generic IBI pool. Should be called from the 2801 * master driver struct_master_controller_ops->recycle_ibi() method. 2802 */ 2803 void i3c_generic_ibi_recycle_slot(struct i3c_generic_ibi_pool *pool, 2804 struct i3c_ibi_slot *s) 2805 { 2806 struct i3c_generic_ibi_slot *slot; 2807 unsigned long flags; 2808 2809 if (!s) 2810 return; 2811 2812 slot = container_of(s, struct i3c_generic_ibi_slot, base); 2813 spin_lock_irqsave(&pool->lock, flags); 2814 list_add_tail(&slot->node, &pool->free_slots); 2815 spin_unlock_irqrestore(&pool->lock, flags); 2816 } 2817 EXPORT_SYMBOL_GPL(i3c_generic_ibi_recycle_slot); 2818 2819 static int i3c_master_check_ops(const struct i3c_master_controller_ops *ops) 2820 { 2821 if (!ops || !ops->bus_init || !ops->i3c_xfers || 2822 !ops->send_ccc_cmd || !ops->do_daa || !ops->i2c_xfers) 2823 return -EINVAL; 2824 2825 if (ops->request_ibi && 2826 (!ops->enable_ibi || !ops->disable_ibi || !ops->free_ibi || 2827 !ops->recycle_ibi_slot)) 2828 return -EINVAL; 2829 2830 return 0; 2831 } 2832 2833 /** 2834 * i3c_master_register() - register an I3C master 2835 * @master: master used to send frames on the bus 2836 * @parent: the parent device (the one that provides this I3C master 2837 * controller) 2838 * @ops: the master controller operations 2839 * @secondary: true if you are registering a secondary master. Will return 2840 * -EOPNOTSUPP if set to true since secondary masters are not yet 2841 * supported 2842 * 2843 * This function takes care of everything for you: 2844 * 2845 * - creates and initializes the I3C bus 2846 * - populates the bus with static I2C devs if @parent->of_node is not 2847 * NULL 2848 * - registers all I3C devices added by the controller during bus 2849 * initialization 2850 * - registers the I2C adapter and all I2C devices 2851 * 2852 * Return: 0 in case of success, a negative error code otherwise. 2853 */ 2854 int i3c_master_register(struct i3c_master_controller *master, 2855 struct device *parent, 2856 const struct i3c_master_controller_ops *ops, 2857 bool secondary) 2858 { 2859 unsigned long i2c_scl_rate = I3C_BUS_I2C_FM_PLUS_SCL_MAX_RATE; 2860 struct i3c_bus *i3cbus = i3c_master_get_bus(master); 2861 enum i3c_bus_mode mode = I3C_BUS_MODE_PURE; 2862 struct i2c_dev_boardinfo *i2cbi; 2863 int ret; 2864 2865 /* We do not support secondary masters yet. */ 2866 if (secondary) 2867 return -EOPNOTSUPP; 2868 2869 ret = i3c_master_check_ops(ops); 2870 if (ret) 2871 return ret; 2872 2873 master->dev.parent = parent; 2874 master->dev.of_node = of_node_get(parent->of_node); 2875 master->dev.bus = &i3c_bus_type; 2876 master->dev.type = &i3c_masterdev_type; 2877 master->dev.release = i3c_masterdev_release; 2878 master->ops = ops; 2879 master->secondary = secondary; 2880 INIT_LIST_HEAD(&master->boardinfo.i2c); 2881 INIT_LIST_HEAD(&master->boardinfo.i3c); 2882 2883 device_initialize(&master->dev); 2884 dev_set_name(&master->dev, "i3c-%d", i3cbus->id); 2885 2886 master->dev.dma_mask = parent->dma_mask; 2887 master->dev.coherent_dma_mask = parent->coherent_dma_mask; 2888 master->dev.dma_parms = parent->dma_parms; 2889 2890 ret = i3c_bus_init(i3cbus, master->dev.of_node); 2891 if (ret) 2892 goto err_put_dev; 2893 2894 ret = of_populate_i3c_bus(master); 2895 if (ret) 2896 goto err_put_dev; 2897 2898 list_for_each_entry(i2cbi, &master->boardinfo.i2c, node) { 2899 switch (i2cbi->lvr & I3C_LVR_I2C_INDEX_MASK) { 2900 case I3C_LVR_I2C_INDEX(0): 2901 if (mode < I3C_BUS_MODE_MIXED_FAST) 2902 mode = I3C_BUS_MODE_MIXED_FAST; 2903 break; 2904 case I3C_LVR_I2C_INDEX(1): 2905 if (mode < I3C_BUS_MODE_MIXED_LIMITED) 2906 mode = I3C_BUS_MODE_MIXED_LIMITED; 2907 break; 2908 case I3C_LVR_I2C_INDEX(2): 2909 if (mode < I3C_BUS_MODE_MIXED_SLOW) 2910 mode = I3C_BUS_MODE_MIXED_SLOW; 2911 break; 2912 default: 2913 ret = -EINVAL; 2914 goto err_put_dev; 2915 } 2916 2917 if (i2cbi->lvr & I3C_LVR_I2C_FM_MODE) 2918 i2c_scl_rate = I3C_BUS_I2C_FM_SCL_MAX_RATE; 2919 } 2920 2921 ret = i3c_bus_set_mode(i3cbus, mode, i2c_scl_rate); 2922 if (ret) 2923 goto err_put_dev; 2924 2925 master->wq = alloc_workqueue("%s", WQ_PERCPU, 0, dev_name(parent)); 2926 if (!master->wq) { 2927 ret = -ENOMEM; 2928 goto err_put_dev; 2929 } 2930 2931 ret = i3c_master_bus_init(master); 2932 if (ret) 2933 goto err_put_dev; 2934 2935 ret = device_add(&master->dev); 2936 if (ret) 2937 goto err_cleanup_bus; 2938 2939 /* 2940 * Expose our I3C bus as an I2C adapter so that I2C devices are exposed 2941 * through the I2C subsystem. 2942 */ 2943 ret = i3c_master_i2c_adapter_init(master); 2944 if (ret) 2945 goto err_del_dev; 2946 2947 i3c_bus_notify(i3cbus, I3C_NOTIFY_BUS_ADD); 2948 2949 pm_runtime_no_callbacks(&master->dev); 2950 pm_suspend_ignore_children(&master->dev, true); 2951 pm_runtime_enable(&master->dev); 2952 2953 /* 2954 * We're done initializing the bus and the controller, we can now 2955 * register I3C devices discovered during the initial DAA. 2956 */ 2957 master->init_done = true; 2958 i3c_bus_normaluse_lock(&master->bus); 2959 i3c_master_register_new_i3c_devs(master); 2960 i3c_bus_normaluse_unlock(&master->bus); 2961 2962 return 0; 2963 2964 err_del_dev: 2965 device_del(&master->dev); 2966 2967 err_cleanup_bus: 2968 i3c_master_bus_cleanup(master); 2969 2970 err_put_dev: 2971 put_device(&master->dev); 2972 2973 return ret; 2974 } 2975 EXPORT_SYMBOL_GPL(i3c_master_register); 2976 2977 /** 2978 * i3c_master_unregister() - unregister an I3C master 2979 * @master: master used to send frames on the bus 2980 * 2981 * Basically undo everything done in i3c_master_register(). 2982 */ 2983 void i3c_master_unregister(struct i3c_master_controller *master) 2984 { 2985 i3c_bus_notify(&master->bus, I3C_NOTIFY_BUS_REMOVE); 2986 2987 i3c_master_i2c_adapter_cleanup(master); 2988 i3c_master_unregister_i3c_devs(master); 2989 i3c_master_bus_cleanup(master); 2990 pm_runtime_disable(&master->dev); 2991 device_unregister(&master->dev); 2992 } 2993 EXPORT_SYMBOL_GPL(i3c_master_unregister); 2994 2995 int i3c_dev_setdasa_locked(struct i3c_dev_desc *dev) 2996 { 2997 struct i3c_master_controller *master; 2998 2999 if (!dev) 3000 return -ENOENT; 3001 3002 master = i3c_dev_get_master(dev); 3003 if (!master) 3004 return -EINVAL; 3005 3006 if (!dev->boardinfo || !dev->boardinfo->init_dyn_addr || 3007 !dev->boardinfo->static_addr) 3008 return -EINVAL; 3009 3010 return i3c_master_setdasa_locked(master, dev->info.static_addr, 3011 dev->boardinfo->init_dyn_addr); 3012 } 3013 3014 int i3c_dev_do_xfers_locked(struct i3c_dev_desc *dev, struct i3c_xfer *xfers, 3015 int nxfers, enum i3c_xfer_mode mode) 3016 { 3017 struct i3c_master_controller *master; 3018 3019 if (!dev) 3020 return -ENOENT; 3021 3022 master = i3c_dev_get_master(dev); 3023 if (!master || !xfers) 3024 return -EINVAL; 3025 3026 if (mode != I3C_SDR && !(master->this->info.hdr_cap & BIT(mode))) 3027 return -EOPNOTSUPP; 3028 3029 return master->ops->i3c_xfers(dev, xfers, nxfers, mode); 3030 } 3031 3032 int i3c_dev_disable_ibi_locked(struct i3c_dev_desc *dev) 3033 { 3034 struct i3c_master_controller *master; 3035 int ret; 3036 3037 if (!dev->ibi) 3038 return -EINVAL; 3039 3040 master = i3c_dev_get_master(dev); 3041 ret = master->ops->disable_ibi(dev); 3042 if (ret) 3043 return ret; 3044 3045 reinit_completion(&dev->ibi->all_ibis_handled); 3046 if (atomic_read(&dev->ibi->pending_ibis)) 3047 wait_for_completion(&dev->ibi->all_ibis_handled); 3048 3049 dev->ibi->enabled = false; 3050 3051 return 0; 3052 } 3053 3054 int i3c_dev_enable_ibi_locked(struct i3c_dev_desc *dev) 3055 { 3056 struct i3c_master_controller *master = i3c_dev_get_master(dev); 3057 int ret; 3058 3059 if (!dev->ibi) 3060 return -EINVAL; 3061 3062 ret = master->ops->enable_ibi(dev); 3063 if (!ret) 3064 dev->ibi->enabled = true; 3065 3066 return ret; 3067 } 3068 3069 int i3c_dev_request_ibi_locked(struct i3c_dev_desc *dev, 3070 const struct i3c_ibi_setup *req) 3071 { 3072 struct i3c_master_controller *master = i3c_dev_get_master(dev); 3073 struct i3c_device_ibi_info *ibi; 3074 int ret; 3075 3076 if (!master->ops->request_ibi) 3077 return -EOPNOTSUPP; 3078 3079 if (dev->ibi) 3080 return -EBUSY; 3081 3082 ibi = kzalloc(sizeof(*ibi), GFP_KERNEL); 3083 if (!ibi) 3084 return -ENOMEM; 3085 3086 ibi->wq = alloc_ordered_workqueue(dev_name(i3cdev_to_dev(dev->dev)), WQ_MEM_RECLAIM); 3087 if (!ibi->wq) { 3088 kfree(ibi); 3089 return -ENOMEM; 3090 } 3091 3092 atomic_set(&ibi->pending_ibis, 0); 3093 init_completion(&ibi->all_ibis_handled); 3094 ibi->handler = req->handler; 3095 ibi->max_payload_len = req->max_payload_len; 3096 ibi->num_slots = req->num_slots; 3097 3098 dev->ibi = ibi; 3099 ret = master->ops->request_ibi(dev, req); 3100 if (ret) { 3101 kfree(ibi); 3102 dev->ibi = NULL; 3103 } 3104 3105 return ret; 3106 } 3107 3108 void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev) 3109 { 3110 struct i3c_master_controller *master = i3c_dev_get_master(dev); 3111 3112 if (!dev->ibi) 3113 return; 3114 3115 if (WARN_ON(dev->ibi->enabled)) 3116 WARN_ON(i3c_dev_disable_ibi_locked(dev)); 3117 3118 master->ops->free_ibi(dev); 3119 3120 if (dev->ibi->wq) { 3121 destroy_workqueue(dev->ibi->wq); 3122 dev->ibi->wq = NULL; 3123 } 3124 3125 kfree(dev->ibi); 3126 dev->ibi = NULL; 3127 } 3128 3129 static int __init i3c_init(void) 3130 { 3131 int res; 3132 3133 res = of_alias_get_highest_id("i3c"); 3134 if (res >= 0) { 3135 mutex_lock(&i3c_core_lock); 3136 __i3c_first_dynamic_bus_num = res + 1; 3137 mutex_unlock(&i3c_core_lock); 3138 } 3139 3140 res = bus_register_notifier(&i2c_bus_type, &i2cdev_notifier); 3141 if (res) 3142 return res; 3143 3144 res = bus_register(&i3c_bus_type); 3145 if (res) 3146 goto out_unreg_notifier; 3147 3148 return 0; 3149 3150 out_unreg_notifier: 3151 bus_unregister_notifier(&i2c_bus_type, &i2cdev_notifier); 3152 3153 return res; 3154 } 3155 subsys_initcall(i3c_init); 3156 3157 static void __exit i3c_exit(void) 3158 { 3159 bus_unregister_notifier(&i2c_bus_type, &i2cdev_notifier); 3160 idr_destroy(&i3c_bus_idr); 3161 bus_unregister(&i3c_bus_type); 3162 } 3163 module_exit(i3c_exit); 3164 3165 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>"); 3166 MODULE_DESCRIPTION("I3C core"); 3167 MODULE_LICENSE("GPL v2"); 3168