1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Cadence Design Systems Inc. 4 * 5 * Author: Boris Brezillon <boris.brezillon@bootlin.com> 6 */ 7 8 #include <dt-bindings/i3c/i3c.h> 9 #include <linux/acpi.h> 10 #include <linux/atomic.h> 11 #include <linux/bitfield.h> 12 #include <linux/bitmap.h> 13 #include <linux/bug.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/err.h> 18 #include <linux/export.h> 19 #include <linux/i2c.h> 20 #include <linux/kernel.h> 21 #include <linux/list.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/property.h> 26 #include <linux/slab.h> 27 #include <linux/spinlock.h> 28 #include <linux/workqueue.h> 29 30 #include "internals.h" 31 32 static DEFINE_IDR(i3c_bus_idr); 33 static DEFINE_MUTEX(i3c_core_lock); 34 static int __i3c_first_dynamic_bus_num; 35 static BLOCKING_NOTIFIER_HEAD(i3c_bus_notifier); 36 37 /** 38 * i3c_bus_maintenance_lock - Lock the bus for a maintenance operation 39 * @bus: I3C bus to take the lock on 40 * 41 * This function takes the bus lock so that no other operations can occur on 42 * the bus. This is needed for all kind of bus maintenance operation, like 43 * - enabling/disabling slave events 44 * - re-triggering DAA 45 * - changing the dynamic address of a device 46 * - relinquishing mastership 47 * - ... 48 * 49 * The reason for this kind of locking is that we don't want drivers and core 50 * logic to rely on I3C device information that could be changed behind their 51 * back. 52 */ 53 void i3c_bus_maintenance_lock(struct i3c_bus *bus) 54 { 55 down_write(&bus->lock); 56 } 57 EXPORT_SYMBOL_GPL(i3c_bus_maintenance_lock); 58 59 /** 60 * i3c_bus_maintenance_unlock - Release the bus lock after a maintenance 61 * operation 62 * @bus: I3C bus to release the lock on 63 * 64 * Should be called when the bus maintenance operation is done. See 65 * i3c_bus_maintenance_lock() for more details on what these maintenance 66 * operations are. 67 */ 68 void i3c_bus_maintenance_unlock(struct i3c_bus *bus) 69 { 70 up_write(&bus->lock); 71 } 72 EXPORT_SYMBOL_GPL(i3c_bus_maintenance_unlock); 73 74 /** 75 * i3c_bus_normaluse_lock - Lock the bus for a normal operation 76 * @bus: I3C bus to take the lock on 77 * 78 * This function takes the bus lock for any operation that is not a maintenance 79 * operation (see i3c_bus_maintenance_lock() for a non-exhaustive list of 80 * maintenance operations). Basically all communications with I3C devices are 81 * normal operations (HDR, SDR transfers or CCC commands that do not change bus 82 * state or I3C dynamic address). 83 * 84 * Note that this lock is not guaranteeing serialization of normal operations. 85 * In other words, transfer requests passed to the I3C master can be submitted 86 * in parallel and I3C master drivers have to use their own locking to make 87 * sure two different communications are not inter-mixed, or access to the 88 * output/input queue is not done while the engine is busy. 89 */ 90 void i3c_bus_normaluse_lock(struct i3c_bus *bus) 91 { 92 down_read(&bus->lock); 93 } 94 EXPORT_SYMBOL_GPL(i3c_bus_normaluse_lock); 95 96 /** 97 * i3c_bus_normaluse_unlock - Release the bus lock after a normal operation 98 * @bus: I3C bus to release the lock on 99 * 100 * Should be called when a normal operation is done. See 101 * i3c_bus_normaluse_lock() for more details on what these normal operations 102 * are. 103 */ 104 void i3c_bus_normaluse_unlock(struct i3c_bus *bus) 105 { 106 up_read(&bus->lock); 107 } 108 EXPORT_SYMBOL_GPL(i3c_bus_normaluse_unlock); 109 110 static struct i3c_master_controller *dev_to_i3cmaster(struct device *dev) 111 { 112 return container_of(dev, struct i3c_master_controller, dev); 113 } 114 115 static int __must_check i3c_master_rpm_get(struct i3c_master_controller *master) 116 { 117 int ret = master->rpm_allowed ? pm_runtime_resume_and_get(master->dev.parent) : 0; 118 119 if (ret < 0) { 120 dev_err(master->dev.parent, "runtime resume failed, error %d\n", ret); 121 return ret; 122 } 123 return 0; 124 } 125 126 static void i3c_master_rpm_put(struct i3c_master_controller *master) 127 { 128 if (master->rpm_allowed) 129 pm_runtime_put_autosuspend(master->dev.parent); 130 } 131 132 int i3c_bus_rpm_get(struct i3c_bus *bus) 133 { 134 return i3c_master_rpm_get(i3c_bus_to_i3c_master(bus)); 135 } 136 137 void i3c_bus_rpm_put(struct i3c_bus *bus) 138 { 139 i3c_master_rpm_put(i3c_bus_to_i3c_master(bus)); 140 } 141 142 bool i3c_bus_rpm_ibi_allowed(struct i3c_bus *bus) 143 { 144 return i3c_bus_to_i3c_master(bus)->rpm_ibi_allowed; 145 } 146 147 static const struct device_type i3c_device_type; 148 149 static struct i3c_bus *dev_to_i3cbus(struct device *dev) 150 { 151 struct i3c_master_controller *master; 152 153 if (dev->type == &i3c_device_type) 154 return dev_to_i3cdev(dev)->bus; 155 156 master = dev_to_i3cmaster(dev); 157 158 return &master->bus; 159 } 160 161 static struct i3c_dev_desc *dev_to_i3cdesc(struct device *dev) 162 { 163 struct i3c_master_controller *master; 164 165 if (dev->type == &i3c_device_type) 166 return dev_to_i3cdev(dev)->desc; 167 168 master = dev_to_i3cmaster(dev); 169 170 return master->this; 171 } 172 173 static ssize_t bcr_show(struct device *dev, 174 struct device_attribute *da, 175 char *buf) 176 { 177 struct i3c_bus *bus = dev_to_i3cbus(dev); 178 struct i3c_dev_desc *desc; 179 ssize_t ret; 180 181 i3c_bus_normaluse_lock(bus); 182 desc = dev_to_i3cdesc(dev); 183 ret = sysfs_emit(buf, "0x%02x\n", desc->info.bcr); 184 i3c_bus_normaluse_unlock(bus); 185 186 return ret; 187 } 188 static DEVICE_ATTR_RO(bcr); 189 190 static ssize_t dcr_show(struct device *dev, 191 struct device_attribute *da, 192 char *buf) 193 { 194 struct i3c_bus *bus = dev_to_i3cbus(dev); 195 struct i3c_dev_desc *desc; 196 ssize_t ret; 197 198 i3c_bus_normaluse_lock(bus); 199 desc = dev_to_i3cdesc(dev); 200 ret = sysfs_emit(buf, "0x%02x\n", desc->info.dcr); 201 i3c_bus_normaluse_unlock(bus); 202 203 return ret; 204 } 205 static DEVICE_ATTR_RO(dcr); 206 207 static ssize_t pid_show(struct device *dev, 208 struct device_attribute *da, 209 char *buf) 210 { 211 struct i3c_bus *bus = dev_to_i3cbus(dev); 212 struct i3c_dev_desc *desc; 213 ssize_t ret; 214 215 i3c_bus_normaluse_lock(bus); 216 desc = dev_to_i3cdesc(dev); 217 ret = sysfs_emit(buf, "%llx\n", desc->info.pid); 218 i3c_bus_normaluse_unlock(bus); 219 220 return ret; 221 } 222 static DEVICE_ATTR_RO(pid); 223 224 static ssize_t dynamic_address_show(struct device *dev, 225 struct device_attribute *da, 226 char *buf) 227 { 228 struct i3c_bus *bus = dev_to_i3cbus(dev); 229 struct i3c_dev_desc *desc; 230 ssize_t ret; 231 232 i3c_bus_normaluse_lock(bus); 233 desc = dev_to_i3cdesc(dev); 234 ret = sysfs_emit(buf, "%02x\n", desc->info.dyn_addr); 235 i3c_bus_normaluse_unlock(bus); 236 237 return ret; 238 } 239 static DEVICE_ATTR_RO(dynamic_address); 240 241 static const char * const hdrcap_strings[] = { 242 "hdr-ddr", "hdr-tsp", "hdr-tsl", 243 }; 244 245 static ssize_t hdrcap_show(struct device *dev, 246 struct device_attribute *da, 247 char *buf) 248 { 249 struct i3c_bus *bus = dev_to_i3cbus(dev); 250 struct i3c_dev_desc *desc; 251 ssize_t offset = 0, ret; 252 unsigned long caps; 253 int mode; 254 255 i3c_bus_normaluse_lock(bus); 256 desc = dev_to_i3cdesc(dev); 257 caps = desc->info.hdr_cap; 258 for_each_set_bit(mode, &caps, 8) { 259 if (mode >= ARRAY_SIZE(hdrcap_strings)) 260 break; 261 262 if (!hdrcap_strings[mode]) 263 continue; 264 265 ret = sysfs_emit_at(buf, offset, offset ? " %s" : "%s", 266 hdrcap_strings[mode]); 267 if (ret < 0) 268 goto out; 269 270 offset += ret; 271 } 272 273 ret = sysfs_emit_at(buf, offset, "\n"); 274 if (ret < 0) 275 goto out; 276 277 ret = offset + ret; 278 279 out: 280 i3c_bus_normaluse_unlock(bus); 281 282 return ret; 283 } 284 static DEVICE_ATTR_RO(hdrcap); 285 286 static ssize_t modalias_show(struct device *dev, 287 struct device_attribute *da, char *buf) 288 { 289 struct i3c_device *i3c = dev_to_i3cdev(dev); 290 struct i3c_device_info devinfo; 291 u16 manuf, part, ext; 292 293 i3c_device_get_info(i3c, &devinfo); 294 manuf = I3C_PID_MANUF_ID(devinfo.pid); 295 part = I3C_PID_PART_ID(devinfo.pid); 296 ext = I3C_PID_EXTRA_INFO(devinfo.pid); 297 298 if (I3C_PID_RND_LOWER_32BITS(devinfo.pid)) 299 return sysfs_emit(buf, "i3c:dcr%02Xmanuf%04X\n", devinfo.dcr, 300 manuf); 301 302 return sysfs_emit(buf, "i3c:dcr%02Xmanuf%04Xpart%04Xext%04X\n", 303 devinfo.dcr, manuf, part, ext); 304 } 305 static DEVICE_ATTR_RO(modalias); 306 307 static struct attribute *i3c_device_attrs[] = { 308 &dev_attr_bcr.attr, 309 &dev_attr_dcr.attr, 310 &dev_attr_pid.attr, 311 &dev_attr_dynamic_address.attr, 312 &dev_attr_hdrcap.attr, 313 &dev_attr_modalias.attr, 314 NULL, 315 }; 316 ATTRIBUTE_GROUPS(i3c_device); 317 318 static int i3c_device_uevent(const struct device *dev, struct kobj_uevent_env *env) 319 { 320 const struct i3c_device *i3cdev = dev_to_i3cdev(dev); 321 struct i3c_device_info devinfo; 322 u16 manuf, part, ext; 323 324 i3c_device_get_info(i3cdev, &devinfo); 325 manuf = I3C_PID_MANUF_ID(devinfo.pid); 326 part = I3C_PID_PART_ID(devinfo.pid); 327 ext = I3C_PID_EXTRA_INFO(devinfo.pid); 328 329 if (I3C_PID_RND_LOWER_32BITS(devinfo.pid)) 330 return add_uevent_var(env, "MODALIAS=i3c:dcr%02Xmanuf%04X", 331 devinfo.dcr, manuf); 332 333 return add_uevent_var(env, 334 "MODALIAS=i3c:dcr%02Xmanuf%04Xpart%04Xext%04X", 335 devinfo.dcr, manuf, part, ext); 336 } 337 338 static const struct device_type i3c_device_type = { 339 .groups = i3c_device_groups, 340 .uevent = i3c_device_uevent, 341 }; 342 343 static int i3c_device_match(struct device *dev, const struct device_driver *drv) 344 { 345 struct i3c_device *i3cdev; 346 const struct i3c_driver *i3cdrv; 347 u8 static_addr_method = 0; 348 349 if (dev->type != &i3c_device_type) 350 return 0; 351 352 i3cdev = dev_to_i3cdev(dev); 353 i3cdrv = drv_to_i3cdrv(drv); 354 355 i3c_bus_normaluse_lock(i3cdev->bus); 356 if (i3cdev->desc->boardinfo) 357 static_addr_method = i3cdev->desc->boardinfo->static_addr_method; 358 i3c_bus_normaluse_unlock(i3cdev->bus); 359 360 /* 361 * SETAASA-based devices need not always have a matching ID since 362 * it is not mandatory for such devices to implement deviceinfo 363 * CCC commands. Allow them to register through DT or ACPI. 364 */ 365 if (i3cdrv->id_table && i3c_device_match_id(i3cdev, i3cdrv->id_table)) 366 return 1; 367 368 if (static_addr_method & I3C_ADDR_METHOD_SETAASA) { 369 if (of_driver_match_device(dev, drv)) 370 return 1; 371 if (acpi_driver_match_device(dev, drv)) 372 return 1; 373 } 374 375 return 0; 376 } 377 378 static int i3c_device_probe(struct device *dev) 379 { 380 struct i3c_device *i3cdev = dev_to_i3cdev(dev); 381 struct i3c_driver *driver = drv_to_i3cdrv(dev->driver); 382 383 return driver->probe(i3cdev); 384 } 385 386 static void i3c_device_remove(struct device *dev) 387 { 388 struct i3c_device *i3cdev = dev_to_i3cdev(dev); 389 struct i3c_driver *driver = drv_to_i3cdrv(dev->driver); 390 391 if (driver->remove) 392 driver->remove(i3cdev); 393 } 394 395 static enum i3c_addr_slot_status 396 i3c_bus_get_addr_slot_status_mask(struct i3c_bus *bus, u16 addr, u32 mask) 397 { 398 unsigned long status; 399 int bitpos = addr * I3C_ADDR_SLOT_STATUS_BITS; 400 401 if (addr > I2C_MAX_ADDR) 402 return I3C_ADDR_SLOT_RSVD; 403 404 status = bus->addrslots[bitpos / BITS_PER_LONG]; 405 status >>= bitpos % BITS_PER_LONG; 406 407 return status & mask; 408 } 409 410 /** 411 * i3c_bus_get_addr_slot_status() - Get I3C bus address slot status 412 * @bus: I3C bus. 413 * @addr: I3C address to query. 414 * 415 * Return: Address slot status for @addr. 416 */ 417 enum i3c_addr_slot_status 418 i3c_bus_get_addr_slot_status(struct i3c_bus *bus, u16 addr) 419 { 420 return i3c_bus_get_addr_slot_status_mask(bus, addr, I3C_ADDR_SLOT_STATUS_MASK); 421 } 422 EXPORT_SYMBOL_GPL(i3c_bus_get_addr_slot_status); 423 424 static void i3c_bus_set_addr_slot_status_mask(struct i3c_bus *bus, u16 addr, 425 enum i3c_addr_slot_status status, u32 mask) 426 { 427 int bitpos = addr * I3C_ADDR_SLOT_STATUS_BITS; 428 unsigned long *ptr; 429 430 if (addr > I2C_MAX_ADDR) 431 return; 432 433 ptr = bus->addrslots + (bitpos / BITS_PER_LONG); 434 *ptr &= ~((unsigned long)mask << (bitpos % BITS_PER_LONG)); 435 *ptr |= ((unsigned long)status & mask) << (bitpos % BITS_PER_LONG); 436 } 437 438 /** 439 * i3c_bus_set_addr_slot_status() - Set I3C bus address slot status 440 * @bus: I3C bus. 441 * @addr: I3C address to update. 442 * @status: Address slot status to set. 443 */ 444 void i3c_bus_set_addr_slot_status(struct i3c_bus *bus, u16 addr, 445 enum i3c_addr_slot_status status) 446 { 447 i3c_bus_set_addr_slot_status_mask(bus, addr, status, I3C_ADDR_SLOT_STATUS_MASK); 448 } 449 EXPORT_SYMBOL_GPL(i3c_bus_set_addr_slot_status); 450 451 static bool i3c_bus_dev_addr_is_avail(struct i3c_bus *bus, u8 addr) 452 { 453 enum i3c_addr_slot_status status; 454 455 status = i3c_bus_get_addr_slot_status(bus, addr); 456 457 return status == I3C_ADDR_SLOT_FREE; 458 } 459 460 /* 461 * ┌────┬─────────────┬───┬─────────┬───┐ 462 * │S/Sr│ 7'h7E RnW=0 │ACK│ ENTDAA │ T ├────┐ 463 * └────┴─────────────┴───┴─────────┴───┘ │ 464 * ┌─────────────────────────────────────────┘ 465 * │ ┌──┬─────────────┬───┬─────────────────┬────────────────┬───┬─────────┐ 466 * └─►│Sr│7'h7E RnW=1 │ACK│48bit UID BCR DCR│Assign 7bit Addr│PAR│ ACK/NACK│ 467 * └──┴─────────────┴───┴─────────────────┴────────────────┴───┴─────────┘ 468 * Some master controllers (such as HCI) need to prepare the entire above transaction before 469 * sending it out to the I3C bus. This means that a 7-bit dynamic address needs to be allocated 470 * before knowing the target device's UID information. 471 * 472 * However, some I3C targets may request specific addresses (called as "init_dyn_addr"), which is 473 * typically specified by the DT-'s assigned-address property. Lower addresses having higher IBI 474 * priority. If it is available, i3c_bus_get_free_addr() preferably return a free address that is 475 * not in the list of desired addresses (called as "init_dyn_addr"). This allows the device with 476 * the "init_dyn_addr" to switch to its "init_dyn_addr" when it hot-joins the I3C bus. Otherwise, 477 * if the "init_dyn_addr" is already in use by another I3C device, the target device will not be 478 * able to switch to its desired address. 479 * 480 * If the previous step fails, fallback returning one of the remaining unassigned address, 481 * regardless of its state in the desired list. 482 */ 483 static int i3c_bus_get_free_addr(struct i3c_bus *bus, u8 start_addr) 484 { 485 enum i3c_addr_slot_status status; 486 u8 addr; 487 488 for (addr = start_addr; addr < I3C_MAX_ADDR; addr++) { 489 status = i3c_bus_get_addr_slot_status_mask(bus, addr, 490 I3C_ADDR_SLOT_EXT_STATUS_MASK); 491 if (status == I3C_ADDR_SLOT_FREE) 492 return addr; 493 } 494 495 for (addr = start_addr; addr < I3C_MAX_ADDR; addr++) { 496 status = i3c_bus_get_addr_slot_status_mask(bus, addr, 497 I3C_ADDR_SLOT_STATUS_MASK); 498 if (status == I3C_ADDR_SLOT_FREE) 499 return addr; 500 } 501 502 return -ENOMEM; 503 } 504 505 static void i3c_bus_init_addrslots(struct i3c_bus *bus) 506 { 507 int i; 508 509 /* Addresses 0 to 7 are reserved. */ 510 for (i = 0; i < 8; i++) 511 i3c_bus_set_addr_slot_status(bus, i, I3C_ADDR_SLOT_RSVD); 512 513 /* 514 * Reserve broadcast address and all addresses that might collide 515 * with the broadcast address when facing a single bit error. 516 */ 517 i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR, 518 I3C_ADDR_SLOT_RSVD); 519 for (i = 0; i < 7; i++) 520 i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR ^ BIT(i), 521 I3C_ADDR_SLOT_RSVD); 522 } 523 524 static void i3c_bus_cleanup(struct i3c_bus *i3cbus) 525 { 526 mutex_lock(&i3c_core_lock); 527 idr_remove(&i3c_bus_idr, i3cbus->id); 528 mutex_unlock(&i3c_core_lock); 529 } 530 531 static int i3c_bus_init(struct i3c_bus *i3cbus, struct fwnode_handle *fwnode) 532 { 533 int ret, start, end, id = -1; 534 535 init_rwsem(&i3cbus->lock); 536 INIT_LIST_HEAD(&i3cbus->devs.i2c); 537 INIT_LIST_HEAD(&i3cbus->devs.i3c); 538 i3c_bus_init_addrslots(i3cbus); 539 i3cbus->mode = I3C_BUS_MODE_PURE; 540 541 if (fwnode && is_of_node(fwnode)) 542 id = of_alias_get_id(to_of_node(fwnode), "i3c"); 543 544 mutex_lock(&i3c_core_lock); 545 if (id >= 0) { 546 start = id; 547 end = start + 1; 548 } else { 549 start = __i3c_first_dynamic_bus_num; 550 end = 0; 551 } 552 553 ret = idr_alloc(&i3c_bus_idr, i3cbus, start, end, GFP_KERNEL); 554 mutex_unlock(&i3c_core_lock); 555 556 if (ret < 0) 557 return ret; 558 559 i3cbus->id = ret; 560 561 return 0; 562 } 563 564 void i3c_for_each_bus_locked(int (*fn)(struct i3c_bus *bus, void *data), 565 void *data) 566 { 567 struct i3c_bus *bus; 568 int id; 569 570 mutex_lock(&i3c_core_lock); 571 idr_for_each_entry(&i3c_bus_idr, bus, id) 572 fn(bus, data); 573 mutex_unlock(&i3c_core_lock); 574 } 575 EXPORT_SYMBOL_GPL(i3c_for_each_bus_locked); 576 577 int i3c_register_notifier(struct notifier_block *nb) 578 { 579 return blocking_notifier_chain_register(&i3c_bus_notifier, nb); 580 } 581 EXPORT_SYMBOL_GPL(i3c_register_notifier); 582 583 int i3c_unregister_notifier(struct notifier_block *nb) 584 { 585 return blocking_notifier_chain_unregister(&i3c_bus_notifier, nb); 586 } 587 EXPORT_SYMBOL_GPL(i3c_unregister_notifier); 588 589 static void i3c_bus_notify(struct i3c_bus *bus, unsigned int action) 590 { 591 blocking_notifier_call_chain(&i3c_bus_notifier, action, bus); 592 } 593 594 static const char * const i3c_bus_mode_strings[] = { 595 [I3C_BUS_MODE_PURE] = "pure", 596 [I3C_BUS_MODE_MIXED_FAST] = "mixed-fast", 597 [I3C_BUS_MODE_MIXED_LIMITED] = "mixed-limited", 598 [I3C_BUS_MODE_MIXED_SLOW] = "mixed-slow", 599 }; 600 601 static ssize_t mode_show(struct device *dev, 602 struct device_attribute *da, 603 char *buf) 604 { 605 struct i3c_bus *i3cbus = dev_to_i3cbus(dev); 606 ssize_t ret; 607 608 i3c_bus_normaluse_lock(i3cbus); 609 if (i3cbus->mode < 0 || 610 i3cbus->mode >= ARRAY_SIZE(i3c_bus_mode_strings) || 611 !i3c_bus_mode_strings[i3cbus->mode]) 612 ret = sysfs_emit(buf, "unknown\n"); 613 else 614 ret = sysfs_emit(buf, "%s\n", i3c_bus_mode_strings[i3cbus->mode]); 615 i3c_bus_normaluse_unlock(i3cbus); 616 617 return ret; 618 } 619 static DEVICE_ATTR_RO(mode); 620 621 static ssize_t current_master_show(struct device *dev, 622 struct device_attribute *da, 623 char *buf) 624 { 625 struct i3c_bus *i3cbus = dev_to_i3cbus(dev); 626 ssize_t ret; 627 628 i3c_bus_normaluse_lock(i3cbus); 629 ret = sysfs_emit(buf, "%d-%llx\n", i3cbus->id, 630 i3cbus->cur_master->info.pid); 631 i3c_bus_normaluse_unlock(i3cbus); 632 633 return ret; 634 } 635 static DEVICE_ATTR_RO(current_master); 636 637 static ssize_t i3c_scl_frequency_show(struct device *dev, 638 struct device_attribute *da, 639 char *buf) 640 { 641 struct i3c_bus *i3cbus = dev_to_i3cbus(dev); 642 ssize_t ret; 643 644 i3c_bus_normaluse_lock(i3cbus); 645 ret = sysfs_emit(buf, "%ld\n", i3cbus->scl_rate.i3c); 646 i3c_bus_normaluse_unlock(i3cbus); 647 648 return ret; 649 } 650 static DEVICE_ATTR_RO(i3c_scl_frequency); 651 652 static ssize_t i2c_scl_frequency_show(struct device *dev, 653 struct device_attribute *da, 654 char *buf) 655 { 656 struct i3c_bus *i3cbus = dev_to_i3cbus(dev); 657 ssize_t ret; 658 659 i3c_bus_normaluse_lock(i3cbus); 660 ret = sysfs_emit(buf, "%ld\n", i3cbus->scl_rate.i2c); 661 i3c_bus_normaluse_unlock(i3cbus); 662 663 return ret; 664 } 665 static DEVICE_ATTR_RO(i2c_scl_frequency); 666 667 static void i3c_master_hj_work_fn(struct work_struct *work) 668 { 669 struct i3c_master_controller *master = container_of(work, typeof(*master), hj_work); 670 671 if (!master->shutting_down) 672 i3c_master_do_daa(master); 673 } 674 675 static int i3c_set_hotjoin(struct i3c_master_controller *master, bool enable) 676 { 677 int ret; 678 679 if (!master || !master->ops) 680 return -EINVAL; 681 682 if (!master->ops->enable_hotjoin || !master->ops->disable_hotjoin) 683 return -EINVAL; 684 685 if (enable || master->rpm_ibi_allowed) { 686 ret = i3c_master_rpm_get(master); 687 if (ret) 688 return ret; 689 } 690 691 i3c_bus_maintenance_lock(&master->bus); 692 693 if (master->shutting_down) 694 ret = -ENODEV; 695 else if (enable) 696 ret = master->ops->enable_hotjoin(master); 697 else 698 ret = master->ops->disable_hotjoin(master); 699 700 if (!ret) 701 master->hotjoin = enable; 702 703 i3c_bus_maintenance_unlock(&master->bus); 704 705 if ((enable && ret) || (!enable && !ret) || master->rpm_ibi_allowed) 706 i3c_master_rpm_put(master); 707 708 return ret; 709 } 710 711 static ssize_t hotjoin_store(struct device *dev, struct device_attribute *attr, 712 const char *buf, size_t count) 713 { 714 struct i3c_bus *i3cbus = dev_to_i3cbus(dev); 715 int ret; 716 bool res; 717 718 if (!i3cbus->cur_master) 719 return -EINVAL; 720 721 if (kstrtobool(buf, &res)) 722 return -EINVAL; 723 724 ret = i3c_set_hotjoin(i3cbus->cur_master->common.master, res); 725 if (ret) 726 return ret; 727 728 return count; 729 } 730 731 /* 732 * i3c_master_enable_hotjoin - Enable hotjoin 733 * @master: I3C master object 734 * 735 * Return: a 0 in case of success, an negative error code otherwise. 736 */ 737 int i3c_master_enable_hotjoin(struct i3c_master_controller *master) 738 { 739 return i3c_set_hotjoin(master, true); 740 } 741 EXPORT_SYMBOL_GPL(i3c_master_enable_hotjoin); 742 743 /* 744 * i3c_master_disable_hotjoin - Disable hotjoin 745 * @master: I3C master object 746 * 747 * Return: a 0 in case of success, an negative error code otherwise. 748 */ 749 int i3c_master_disable_hotjoin(struct i3c_master_controller *master) 750 { 751 return i3c_set_hotjoin(master, false); 752 } 753 EXPORT_SYMBOL_GPL(i3c_master_disable_hotjoin); 754 755 /** 756 * i3c_master_queue_hotjoin - Queue DAA processing after a Hot-Join event 757 * @master: I3C master object 758 * 759 * Queue the hot-join worker on the master's workqueue. 760 */ 761 void i3c_master_queue_hotjoin(struct i3c_master_controller *master) 762 { 763 queue_work(master->wq, &master->hj_work); 764 } 765 EXPORT_SYMBOL_GPL(i3c_master_queue_hotjoin); 766 767 static ssize_t hotjoin_show(struct device *dev, struct device_attribute *da, char *buf) 768 { 769 struct i3c_bus *i3cbus = dev_to_i3cbus(dev); 770 ssize_t ret; 771 772 i3c_bus_normaluse_lock(i3cbus); 773 ret = sysfs_emit(buf, "%d\n", i3cbus->cur_master->common.master->hotjoin); 774 i3c_bus_normaluse_unlock(i3cbus); 775 776 return ret; 777 } 778 779 static DEVICE_ATTR_RW(hotjoin); 780 781 static ssize_t dev_nack_retry_count_show(struct device *dev, 782 struct device_attribute *attr, char *buf) 783 { 784 struct i3c_bus *i3cbus = dev_to_i3cbus(dev); 785 ssize_t ret; 786 787 i3c_bus_normaluse_lock(i3cbus); 788 ret = sysfs_emit(buf, "%u\n", dev_to_i3cmaster(dev)->dev_nack_retry_count); 789 i3c_bus_normaluse_unlock(i3cbus); 790 791 return ret; 792 } 793 794 static ssize_t dev_nack_retry_count_store(struct device *dev, 795 struct device_attribute *attr, 796 const char *buf, size_t count) 797 { 798 struct i3c_bus *i3cbus = dev_to_i3cbus(dev); 799 struct i3c_master_controller *master = dev_to_i3cmaster(dev); 800 unsigned int val; 801 int ret; 802 803 ret = kstrtouint(buf, 0, &val); 804 if (ret) 805 return ret; 806 807 ret = i3c_master_rpm_get(master); 808 if (ret) 809 return ret; 810 811 i3c_bus_maintenance_lock(i3cbus); 812 ret = master->ops->set_dev_nack_retry(master, val); 813 if (!ret) 814 master->dev_nack_retry_count = val; 815 i3c_bus_maintenance_unlock(i3cbus); 816 817 i3c_master_rpm_put(master); 818 819 return ret ?: count; 820 } 821 822 static DEVICE_ATTR_RW(dev_nack_retry_count); 823 824 static ssize_t do_daa_store(struct device *dev, 825 struct device_attribute *attr, 826 const char *buf, size_t count) 827 { 828 struct i3c_master_controller *master = dev_to_i3cmaster(dev); 829 bool val; 830 int ret; 831 832 if (kstrtobool(buf, &val)) 833 return -EINVAL; 834 835 if (!val) 836 return -EINVAL; 837 838 if (!master->init_done) 839 return -EAGAIN; 840 841 ret = i3c_master_do_daa(master); 842 if (ret) 843 return ret; 844 845 return count; 846 } 847 848 static DEVICE_ATTR_WO(do_daa); 849 850 static struct attribute *i3c_masterdev_attrs[] = { 851 &dev_attr_mode.attr, 852 &dev_attr_current_master.attr, 853 &dev_attr_i3c_scl_frequency.attr, 854 &dev_attr_i2c_scl_frequency.attr, 855 &dev_attr_bcr.attr, 856 &dev_attr_dcr.attr, 857 &dev_attr_pid.attr, 858 &dev_attr_dynamic_address.attr, 859 &dev_attr_hdrcap.attr, 860 &dev_attr_hotjoin.attr, 861 &dev_attr_do_daa.attr, 862 NULL, 863 }; 864 ATTRIBUTE_GROUPS(i3c_masterdev); 865 866 static void i3c_master_free_i3c_dev(struct i3c_dev_desc *dev) 867 { 868 kfree(dev); 869 } 870 871 static void i3c_masterdev_release(struct device *dev) 872 { 873 struct i3c_master_controller *master = dev_to_i3cmaster(dev); 874 struct i3c_bus *bus = dev_to_i3cbus(dev); 875 876 if (master->wq) 877 destroy_workqueue(master->wq); 878 879 WARN_ON(!list_empty(&bus->devs.i2c) || !list_empty(&bus->devs.i3c)); 880 i3c_bus_cleanup(bus); 881 882 fwnode_handle_put(dev->fwnode); 883 884 i3c_master_free_i3c_dev(master->this); 885 } 886 887 static const struct device_type i3c_masterdev_type = { 888 .groups = i3c_masterdev_groups, 889 }; 890 891 static void i3c_master_shutdown(struct i3c_master_controller *master) 892 { 893 i3c_bus_maintenance_lock(&master->bus); 894 master->shutting_down = true; 895 i3c_bus_maintenance_unlock(&master->bus); 896 897 cancel_work_sync(&master->hj_work); 898 cancel_work_sync(&master->reg_work); 899 } 900 901 static void i3c_device_shutdown(struct device *dev) 902 { 903 if (dev->type == &i3c_masterdev_type) 904 i3c_master_shutdown(dev_to_i3cmaster(dev)); 905 } 906 907 const struct bus_type i3c_bus_type = { 908 .name = "i3c", 909 .match = i3c_device_match, 910 .probe = i3c_device_probe, 911 .remove = i3c_device_remove, 912 .shutdown = i3c_device_shutdown, 913 }; 914 EXPORT_SYMBOL_GPL(i3c_bus_type); 915 916 static int i3c_bus_set_mode(struct i3c_bus *i3cbus, enum i3c_bus_mode mode, 917 unsigned long max_i2c_scl_rate) 918 { 919 struct i3c_master_controller *master = i3c_bus_to_i3c_master(i3cbus); 920 921 i3cbus->mode = mode; 922 923 switch (i3cbus->mode) { 924 case I3C_BUS_MODE_PURE: 925 if (!i3cbus->scl_rate.i3c) 926 i3cbus->scl_rate.i3c = I3C_BUS_I3C_SCL_TYP_RATE; 927 break; 928 case I3C_BUS_MODE_MIXED_FAST: 929 case I3C_BUS_MODE_MIXED_LIMITED: 930 if (!i3cbus->scl_rate.i3c) 931 i3cbus->scl_rate.i3c = I3C_BUS_I3C_SCL_TYP_RATE; 932 if (!i3cbus->scl_rate.i2c) 933 i3cbus->scl_rate.i2c = max_i2c_scl_rate; 934 break; 935 case I3C_BUS_MODE_MIXED_SLOW: 936 if (!i3cbus->scl_rate.i2c) 937 i3cbus->scl_rate.i2c = max_i2c_scl_rate; 938 if (!i3cbus->scl_rate.i3c || 939 i3cbus->scl_rate.i3c > i3cbus->scl_rate.i2c) 940 i3cbus->scl_rate.i3c = i3cbus->scl_rate.i2c; 941 break; 942 default: 943 return -EINVAL; 944 } 945 946 dev_dbg(&master->dev, "i2c-scl = %ld Hz i3c-scl = %ld Hz\n", 947 i3cbus->scl_rate.i2c, i3cbus->scl_rate.i3c); 948 949 /* 950 * I3C/I2C frequency may have been overridden, check that user-provided 951 * values are not exceeding max possible frequency. 952 */ 953 if (i3cbus->scl_rate.i3c > I3C_BUS_I3C_SCL_MAX_RATE || 954 i3cbus->scl_rate.i2c > I3C_BUS_I2C_FM_PLUS_SCL_MAX_RATE) 955 return -EINVAL; 956 957 return 0; 958 } 959 960 /* 961 * I3C v1.1.1 Section 5.1.2.4 Table 9 lists the HDR Modes each Bus 962 * Configuration allows. A Mixed Slow / Limited Bus has Legacy I2C Devices 963 * without a 50 ns spike filter, so there is no way to hide any HDR Mode from 964 * them. Of the two Ternary Modes, only HDR-TSL is defined for a Bus that 965 * also has Legacy I2C Devices; HDR-TSP is defined for a Pure Bus. 966 */ 967 static u32 i3c_bus_hdr_modes(struct i3c_bus *bus) 968 { 969 switch (bus->mode) { 970 case I3C_BUS_MODE_PURE: 971 return BIT(I3C_HDR_DDR) | BIT(I3C_HDR_TSP) | BIT(I3C_HDR_TSL); 972 case I3C_BUS_MODE_MIXED_FAST: 973 return BIT(I3C_HDR_DDR) | BIT(I3C_HDR_TSL); 974 case I3C_BUS_MODE_MIXED_LIMITED: 975 case I3C_BUS_MODE_MIXED_SLOW: 976 break; 977 } 978 979 return 0; 980 } 981 982 static u32 i3c_dev_hdr_modes(struct i3c_dev_desc *dev) 983 { 984 if (!(dev->info.bcr & I3C_BCR_HDR_CAP)) 985 return 0; 986 987 return dev->info.hdr_cap; 988 } 989 990 /** 991 * i3c_dev_supported_xfer_modes_locked() - Get the transfer modes usable with a 992 * device 993 * @dev: I3C device descriptor 994 * 995 * The HDR Modes the controller and @dev both support, restricted to those the 996 * bus configuration allows. SDR is always supported. 997 * 998 * The bus lock must be held in normal use mode. 999 * 1000 * Return: a bit mask of &enum i3c_xfer_mode values. 1001 */ 1002 u32 i3c_dev_supported_xfer_modes_locked(struct i3c_dev_desc *dev) 1003 { 1004 struct i3c_master_controller *master = i3c_dev_get_master(dev); 1005 1006 /* 1007 * master->this->info.bcr is ignored because it describes the master's 1008 * target capability, not its controller capability. 1009 */ 1010 return (master->this->info.hdr_cap & 1011 i3c_bus_hdr_modes(&master->bus) & 1012 i3c_dev_hdr_modes(dev)) | BIT(I3C_SDR); 1013 } 1014 1015 static struct i3c_master_controller * 1016 i2c_adapter_to_i3c_master(struct i2c_adapter *adap) 1017 { 1018 return container_of(adap, struct i3c_master_controller, i2c); 1019 } 1020 1021 static struct i2c_adapter * 1022 i3c_master_to_i2c_adapter(struct i3c_master_controller *master) 1023 { 1024 return &master->i2c; 1025 } 1026 1027 static void i3c_master_free_i2c_dev(struct i2c_dev_desc *dev) 1028 { 1029 kfree(dev); 1030 } 1031 1032 static struct i2c_dev_desc * 1033 i3c_master_alloc_i2c_dev(struct i3c_master_controller *master, 1034 u16 addr, u8 lvr) 1035 { 1036 struct i2c_dev_desc *dev; 1037 1038 dev = kzalloc_obj(*dev); 1039 if (!dev) 1040 return ERR_PTR(-ENOMEM); 1041 1042 dev->common.master = master; 1043 dev->addr = addr; 1044 dev->lvr = lvr; 1045 1046 return dev; 1047 } 1048 1049 static void *i3c_ccc_cmd_dest_init(struct i3c_ccc_cmd_dest *dest, u8 addr, 1050 u16 payloadlen) 1051 { 1052 dest->addr = addr; 1053 dest->payload.len = payloadlen; 1054 dest->payload.actual_len = 0; 1055 dest->payload.optional_bytes = 0; 1056 if (payloadlen) 1057 dest->payload.data = kzalloc(payloadlen, GFP_KERNEL); 1058 else 1059 dest->payload.data = NULL; 1060 1061 return dest->payload.data; 1062 } 1063 1064 static void i3c_ccc_cmd_dest_cleanup(struct i3c_ccc_cmd_dest *dest) 1065 { 1066 kfree(dest->payload.data); 1067 } 1068 1069 static void i3c_ccc_cmd_init_retries(struct i3c_ccc_cmd *cmd, bool rnw, u8 id, 1070 struct i3c_ccc_cmd_dest *dests, 1071 unsigned int ndests, unsigned int retries) 1072 { 1073 cmd->rnw = rnw ? 1 : 0; 1074 cmd->id = id; 1075 cmd->dests = dests; 1076 cmd->ndests = ndests; 1077 cmd->retries = retries; 1078 cmd->err = I3C_ERROR_UNKNOWN; 1079 } 1080 1081 static void i3c_ccc_cmd_init(struct i3c_ccc_cmd *cmd, bool rnw, u8 id, 1082 struct i3c_ccc_cmd_dest *dests, 1083 unsigned int ndests) 1084 { 1085 i3c_ccc_cmd_init_retries(cmd, rnw, id, dests, ndests, 1086 rnw ? I3C_CCC_RETRIES : 0); 1087 } 1088 1089 static int i3c_ccc_validate_payload_len(struct i3c_ccc_cmd *cmd) 1090 { 1091 unsigned int i; 1092 1093 if (!cmd->rnw) 1094 return 0; 1095 1096 for (i = 0; i < cmd->ndests; i++) { 1097 struct i3c_ccc_cmd_payload *p = &cmd->dests[i].payload; 1098 u16 min_len; 1099 1100 if (p->optional_bytes > p->len) 1101 return -EINVAL; 1102 1103 if (p->actual_len > p->len) 1104 return -EIO; 1105 1106 if (!p->len) 1107 continue; 1108 1109 min_len = p->len - p->optional_bytes; 1110 if (p->actual_len < min_len) 1111 return -EIO; 1112 } 1113 1114 return 0; 1115 } 1116 1117 /** 1118 * i3c_master_send_ccc_cmd_locked() - send a CCC (Common Command Codes) 1119 * @master: master used to send frames on the bus 1120 * @cmd: command to send 1121 * 1122 * Return: 0 in case of success, or a negative error code otherwise. 1123 * I3C Mx error codes are stored in cmd->err. 1124 */ 1125 static int i3c_master_send_ccc_cmd_locked(struct i3c_master_controller *master, 1126 struct i3c_ccc_cmd *cmd) 1127 { 1128 unsigned int attempt, max_attempts; 1129 int ret; 1130 1131 if (!cmd || !master) 1132 return -EINVAL; 1133 1134 if (WARN_ON(master->init_done && 1135 !rwsem_is_locked(&master->bus.lock))) 1136 return -EINVAL; 1137 1138 if (!master->ops->send_ccc_cmd) 1139 return -EOPNOTSUPP; 1140 1141 if ((cmd->rnw || (cmd->id & I3C_CCC_DIRECT)) && 1142 (!cmd->dests || !cmd->ndests)) 1143 return -EINVAL; 1144 1145 if (master->ops->supports_ccc_cmd && 1146 !master->ops->supports_ccc_cmd(master, cmd)) 1147 return -EOPNOTSUPP; 1148 1149 max_attempts = cmd->retries + 1; 1150 ret = -EIO; 1151 for (attempt = 0; attempt < max_attempts; attempt++) { 1152 unsigned int i; 1153 1154 if (cmd->rnw) 1155 for (i = 0; i < cmd->ndests; i++) 1156 cmd->dests[i].payload.actual_len = 0; 1157 1158 cmd->err = I3C_ERROR_UNKNOWN; 1159 ret = master->ops->send_ccc_cmd(master, cmd); 1160 if (!ret && cmd->err == I3C_ERROR_UNKNOWN) 1161 break; 1162 } 1163 1164 if (!ret) 1165 ret = i3c_ccc_validate_payload_len(cmd); 1166 1167 return ret; 1168 } 1169 1170 static struct i2c_dev_desc * 1171 i3c_master_find_i2c_dev_by_addr(const struct i3c_master_controller *master, 1172 u16 addr) 1173 { 1174 struct i2c_dev_desc *dev; 1175 1176 i3c_bus_for_each_i2cdev(&master->bus, dev) { 1177 if (dev->addr == addr) 1178 return dev; 1179 } 1180 1181 return NULL; 1182 } 1183 1184 /** 1185 * i3c_master_get_free_addr() - get a free address on the bus 1186 * @master: I3C master object 1187 * @start_addr: where to start searching 1188 * 1189 * This function must be called with the bus lock held in write mode. 1190 * 1191 * Return: the first free address starting at @start_addr (included) or -ENOMEM 1192 * if there's no more address available. 1193 */ 1194 int i3c_master_get_free_addr(struct i3c_master_controller *master, 1195 u8 start_addr) 1196 { 1197 return i3c_bus_get_free_addr(&master->bus, start_addr); 1198 } 1199 EXPORT_SYMBOL_GPL(i3c_master_get_free_addr); 1200 1201 static void i3c_device_release(struct device *dev) 1202 { 1203 struct i3c_device *i3cdev = dev_to_i3cdev(dev); 1204 1205 WARN_ON(i3cdev->desc); 1206 1207 fwnode_handle_put(dev->fwnode); 1208 kfree(i3cdev); 1209 } 1210 1211 static struct i3c_dev_desc * 1212 i3c_master_alloc_i3c_dev(struct i3c_master_controller *master, 1213 const struct i3c_device_info *info) 1214 { 1215 struct i3c_dev_desc *dev; 1216 1217 dev = kzalloc_obj(*dev); 1218 if (!dev) 1219 return ERR_PTR(-ENOMEM); 1220 1221 dev->common.master = master; 1222 dev->info = *info; 1223 mutex_init(&dev->ibi_lock); 1224 1225 return dev; 1226 } 1227 1228 static int i3c_master_rstdaa_locked(struct i3c_master_controller *master, 1229 u8 addr) 1230 { 1231 enum i3c_addr_slot_status addrstat; 1232 struct i3c_ccc_cmd_dest dest; 1233 struct i3c_ccc_cmd cmd; 1234 int ret; 1235 1236 if (!master) 1237 return -EINVAL; 1238 1239 addrstat = i3c_bus_get_addr_slot_status(&master->bus, addr); 1240 if (addr != I3C_BROADCAST_ADDR && addrstat != I3C_ADDR_SLOT_I3C_DEV) 1241 return -EINVAL; 1242 1243 i3c_ccc_cmd_dest_init(&dest, addr, 0); 1244 i3c_ccc_cmd_init(&cmd, false, 1245 I3C_CCC_RSTDAA(addr == I3C_BROADCAST_ADDR), 1246 &dest, 1); 1247 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1248 i3c_ccc_cmd_dest_cleanup(&dest); 1249 1250 /* No active devices on the bus. */ 1251 if (ret && cmd.err == I3C_ERROR_M2) 1252 ret = 0; 1253 1254 return ret; 1255 } 1256 1257 /** 1258 * i3c_master_setaasa_locked() - start a SETAASA procedure (Set All Addresses to Static Address) 1259 * @master: I3C master object 1260 * 1261 * Send a SETAASA CCC command to set all attached I3C devices' dynamic addresses to 1262 * their static address. 1263 * 1264 * This function must be called with the bus lock held in write mode. 1265 * 1266 * First, the SETHID CCC command is sent, followed by the SETAASA CCC. 1267 * 1268 * Return: 0 in case of success, a positive I3C error code if the error is 1269 * one of the official Mx error codes, and a negative error code otherwise. 1270 */ 1271 static int i3c_master_setaasa_locked(struct i3c_master_controller *master) 1272 { 1273 struct i3c_ccc_cmd_dest dest; 1274 struct i3c_ccc_cmd cmd; 1275 int ret; 1276 1277 /* 1278 * Send SETHID CCC command. Though it is a standard CCC command specified 1279 * in JESD300-5, we are not defining a separate macro to be explicit that 1280 * the value falls under the vendor specific range. 1281 */ 1282 i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR, 0); 1283 i3c_ccc_cmd_init(&cmd, false, I3C_CCC_VENDOR(0, true), &dest, 1); 1284 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1285 i3c_ccc_cmd_dest_cleanup(&dest); 1286 if (ret && cmd.err == I3C_ERROR_M2) 1287 ret = 0; 1288 if (ret) 1289 return ret; 1290 1291 /* Send SETAASA CCC command */ 1292 i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR, 0); 1293 i3c_ccc_cmd_init(&cmd, false, I3C_CCC_SETAASA, &dest, 1); 1294 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1295 i3c_ccc_cmd_dest_cleanup(&dest); 1296 if (ret && cmd.err == I3C_ERROR_M2) 1297 ret = 0; 1298 1299 return ret; 1300 } 1301 1302 /** 1303 * i3c_master_entdaa_locked() - start a DAA (Dynamic Address Assignment) 1304 * procedure 1305 * @master: master used to send frames on the bus 1306 * 1307 * Send a ENTDAA CCC command to start a DAA procedure. 1308 * 1309 * Note that this function only sends the ENTDAA CCC command, all the logic 1310 * behind dynamic address assignment has to be handled in the I3C master 1311 * driver. 1312 * 1313 * This function must be called with the bus lock held in write mode. 1314 * 1315 * Return: 0 in case of success, or a negative error code otherwise. 1316 */ 1317 int i3c_master_entdaa_locked(struct i3c_master_controller *master) 1318 { 1319 struct i3c_ccc_cmd_dest dest; 1320 struct i3c_ccc_cmd cmd; 1321 int ret; 1322 1323 i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR, 0); 1324 i3c_ccc_cmd_init(&cmd, false, I3C_CCC_ENTDAA, &dest, 1); 1325 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1326 i3c_ccc_cmd_dest_cleanup(&dest); 1327 1328 /* No active devices need an address. */ 1329 if (ret && cmd.err == I3C_ERROR_M2) 1330 ret = 0; 1331 1332 return ret; 1333 } 1334 EXPORT_SYMBOL_GPL(i3c_master_entdaa_locked); 1335 1336 /** 1337 * i3c_master_enec_disec_locked() - send an ENEC or DISEC CCC command 1338 * @master: master used to send frames on the bus 1339 * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR 1340 * @enable: true to send ENEC, false to send DISEC 1341 * @evts: events to enable or disable 1342 * @suppress_m2: if true, treat an M2 (NACK) error from the CCC as success 1343 * 1344 * Send an ENEC or DISEC CCC command to enable or disable some or all events 1345 * coming from a specific slave, or all devices if @addr is 1346 * %I3C_BROADCAST_ADDR. 1347 * 1348 * When @suppress_m2 is true, a NACK of the broadcast (which can happen when 1349 * no devices are present on the bus) is not reported as an error. This is 1350 * useful for callers that want to configure event reporting unconditionally, 1351 * regardless of whether any devices are currently on the bus. 1352 * 1353 * This function must be called with the bus lock held in write mode. 1354 * 1355 * Return: 0 in case of success, or a negative error code otherwise. 1356 */ 1357 int i3c_master_enec_disec_locked(struct i3c_master_controller *master, u8 addr, 1358 bool enable, u8 evts, bool suppress_m2) 1359 { 1360 struct i3c_ccc_events *events; 1361 struct i3c_ccc_cmd_dest dest; 1362 struct i3c_ccc_cmd cmd; 1363 int ret; 1364 1365 events = i3c_ccc_cmd_dest_init(&dest, addr, sizeof(*events)); 1366 if (!events) 1367 return -ENOMEM; 1368 1369 events->events = evts; 1370 i3c_ccc_cmd_init(&cmd, false, 1371 enable ? 1372 I3C_CCC_ENEC(addr == I3C_BROADCAST_ADDR) : 1373 I3C_CCC_DISEC(addr == I3C_BROADCAST_ADDR), 1374 &dest, 1); 1375 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1376 i3c_ccc_cmd_dest_cleanup(&dest); 1377 1378 if (suppress_m2 && ret && cmd.err == I3C_ERROR_M2) 1379 ret = 0; 1380 1381 return ret; 1382 } 1383 EXPORT_SYMBOL_GPL(i3c_master_enec_disec_locked); 1384 1385 /** 1386 * i3c_master_disec_locked() - send a DISEC CCC command 1387 * @master: master used to send frames on the bus 1388 * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR 1389 * @evts: events to disable 1390 * 1391 * Send a DISEC CCC command to disable some or all events coming from a 1392 * specific slave, or all devices if @addr is %I3C_BROADCAST_ADDR. 1393 * 1394 * This function must be called with the bus lock held in write mode. 1395 * 1396 * Return: 0 in case of success, or a negative error code otherwise. 1397 */ 1398 int i3c_master_disec_locked(struct i3c_master_controller *master, u8 addr, 1399 u8 evts) 1400 { 1401 return i3c_master_enec_disec_locked(master, addr, false, evts, false); 1402 } 1403 EXPORT_SYMBOL_GPL(i3c_master_disec_locked); 1404 1405 /** 1406 * i3c_master_enec_locked() - send an ENEC CCC command 1407 * @master: master used to send frames on the bus 1408 * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR 1409 * @evts: events to disable 1410 * 1411 * Sends an ENEC CCC command to enable some or all events coming from a 1412 * specific slave, or all devices if @addr is %I3C_BROADCAST_ADDR. 1413 * 1414 * This function must be called with the bus lock held in write mode. 1415 * 1416 * Return: 0 in case of success, or a negative error code otherwise. 1417 */ 1418 int i3c_master_enec_locked(struct i3c_master_controller *master, u8 addr, 1419 u8 evts) 1420 { 1421 return i3c_master_enec_disec_locked(master, addr, true, evts, false); 1422 } 1423 EXPORT_SYMBOL_GPL(i3c_master_enec_locked); 1424 1425 /** 1426 * i3c_master_defslvs_locked() - send a DEFSLVS CCC command 1427 * @master: master used to send frames on the bus 1428 * 1429 * Send a DEFSLVS CCC command containing all the devices known to the @master. 1430 * This is useful when you have secondary masters on the bus to propagate 1431 * device information. 1432 * 1433 * This should be called after all I3C devices have been discovered (in other 1434 * words, after the DAA procedure has finished) and instantiated in 1435 * &i3c_master_controller_ops->bus_init(). 1436 * It should also be called if a master ACKed an Hot-Join request and assigned 1437 * a dynamic address to the device joining the bus. 1438 * 1439 * This function must be called with the bus lock held in write mode. 1440 * 1441 * Return: 0 in case of success, or a negative error code otherwise. 1442 */ 1443 int i3c_master_defslvs_locked(struct i3c_master_controller *master) 1444 { 1445 struct i3c_ccc_defslvs *defslvs; 1446 struct i3c_ccc_dev_desc *desc; 1447 struct i3c_ccc_cmd_dest dest; 1448 struct i3c_dev_desc *i3cdev; 1449 struct i2c_dev_desc *i2cdev; 1450 struct i3c_ccc_cmd cmd; 1451 struct i3c_bus *bus; 1452 bool send = false; 1453 int ndevs = 0, ret; 1454 1455 if (!master) 1456 return -EINVAL; 1457 1458 bus = i3c_master_get_bus(master); 1459 i3c_bus_for_each_i3cdev(bus, i3cdev) { 1460 ndevs++; 1461 1462 if (i3cdev == master->this) 1463 continue; 1464 1465 if (I3C_BCR_DEVICE_ROLE(i3cdev->info.bcr) == 1466 I3C_BCR_I3C_MASTER) 1467 send = true; 1468 } 1469 1470 /* No other master on the bus, skip DEFSLVS. */ 1471 if (!send) 1472 return 0; 1473 1474 i3c_bus_for_each_i2cdev(bus, i2cdev) 1475 ndevs++; 1476 1477 defslvs = i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR, 1478 struct_size(defslvs, slaves, 1479 ndevs - 1)); 1480 if (!defslvs) 1481 return -ENOMEM; 1482 1483 defslvs->count = ndevs; 1484 defslvs->master.bcr = master->this->info.bcr; 1485 defslvs->master.dcr = master->this->info.dcr; 1486 defslvs->master.dyn_addr = master->this->info.dyn_addr << 1; 1487 defslvs->master.static_addr = I3C_BROADCAST_ADDR << 1; 1488 1489 desc = defslvs->slaves; 1490 i3c_bus_for_each_i2cdev(bus, i2cdev) { 1491 desc->lvr = i2cdev->lvr; 1492 desc->static_addr = i2cdev->addr << 1; 1493 desc++; 1494 } 1495 1496 i3c_bus_for_each_i3cdev(bus, i3cdev) { 1497 /* Skip the I3C dev representing this master. */ 1498 if (i3cdev == master->this) 1499 continue; 1500 1501 desc->bcr = i3cdev->info.bcr; 1502 desc->dcr = i3cdev->info.dcr; 1503 desc->dyn_addr = i3cdev->info.dyn_addr << 1; 1504 desc->static_addr = i3cdev->info.static_addr << 1; 1505 desc++; 1506 } 1507 1508 i3c_ccc_cmd_init(&cmd, false, I3C_CCC_DEFSLVS, &dest, 1); 1509 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1510 i3c_ccc_cmd_dest_cleanup(&dest); 1511 1512 return ret; 1513 } 1514 EXPORT_SYMBOL_GPL(i3c_master_defslvs_locked); 1515 1516 static int i3c_master_setda_locked(struct i3c_master_controller *master, 1517 u8 oldaddr, u8 newaddr, bool setdasa) 1518 { 1519 struct i3c_ccc_cmd_dest dest; 1520 struct i3c_ccc_setda *setda; 1521 struct i3c_ccc_cmd cmd; 1522 int ret; 1523 1524 if (!oldaddr || !newaddr) 1525 return -EINVAL; 1526 1527 setda = i3c_ccc_cmd_dest_init(&dest, oldaddr, sizeof(*setda)); 1528 if (!setda) 1529 return -ENOMEM; 1530 1531 setda->addr = newaddr << 1; 1532 i3c_ccc_cmd_init(&cmd, false, 1533 setdasa ? I3C_CCC_SETDASA : I3C_CCC_SETNEWDA, 1534 &dest, 1); 1535 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1536 i3c_ccc_cmd_dest_cleanup(&dest); 1537 1538 return ret; 1539 } 1540 1541 static int i3c_master_setdasa_locked(struct i3c_master_controller *master, 1542 u8 static_addr, u8 dyn_addr) 1543 { 1544 return i3c_master_setda_locked(master, static_addr, dyn_addr, true); 1545 } 1546 1547 static int i3c_master_setnewda_locked(struct i3c_master_controller *master, 1548 u8 oldaddr, u8 newaddr) 1549 { 1550 return i3c_master_setda_locked(master, oldaddr, newaddr, false); 1551 } 1552 1553 static int i3c_master_getmrl_locked(struct i3c_master_controller *master, 1554 struct i3c_device_info *info) 1555 { 1556 struct i3c_ccc_cmd_dest dest; 1557 struct i3c_ccc_mrl *mrl; 1558 struct i3c_ccc_cmd cmd; 1559 int ret; 1560 1561 mrl = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*mrl)); 1562 if (!mrl) 1563 return -ENOMEM; 1564 1565 /* 1566 * GETMRL returns 2 bytes (max read length) when the device does not 1567 * advertise IBI payload, or 2 or 3 bytes when it does (the optional 1568 * third byte is max IBI length). Use optional_bytes to allow either 1569 * length when IBI payload is supported. 1570 */ 1571 if (info->bcr & I3C_BCR_IBI_PAYLOAD) 1572 dest.payload.optional_bytes = 1; 1573 else 1574 dest.payload.len -= 1; 1575 1576 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMRL, &dest, 1); 1577 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1578 if (ret) 1579 goto out; 1580 1581 switch (dest.payload.actual_len) { 1582 case 3: 1583 info->max_ibi_len = mrl->ibi_len; 1584 fallthrough; 1585 case 2: 1586 info->max_read_len = be16_to_cpu(mrl->read_len); 1587 break; 1588 default: 1589 ret = -EIO; 1590 goto out; 1591 } 1592 1593 out: 1594 i3c_ccc_cmd_dest_cleanup(&dest); 1595 1596 return ret; 1597 } 1598 1599 static int i3c_master_getmwl_locked(struct i3c_master_controller *master, 1600 struct i3c_device_info *info) 1601 { 1602 struct i3c_ccc_cmd_dest dest; 1603 struct i3c_ccc_mwl *mwl; 1604 struct i3c_ccc_cmd cmd; 1605 int ret; 1606 1607 mwl = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*mwl)); 1608 if (!mwl) 1609 return -ENOMEM; 1610 1611 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMWL, &dest, 1); 1612 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1613 if (ret) 1614 goto out; 1615 1616 if (dest.payload.actual_len != sizeof(*mwl)) { 1617 ret = -EIO; 1618 goto out; 1619 } 1620 1621 info->max_write_len = be16_to_cpu(mwl->len); 1622 1623 out: 1624 i3c_ccc_cmd_dest_cleanup(&dest); 1625 1626 return ret; 1627 } 1628 1629 static int i3c_master_getmxds_locked(struct i3c_master_controller *master, 1630 struct i3c_device_info *info) 1631 { 1632 struct i3c_ccc_getmxds *getmaxds; 1633 struct i3c_ccc_cmd_dest dest; 1634 struct i3c_ccc_cmd cmd; 1635 int ret; 1636 1637 getmaxds = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, 1638 sizeof(*getmaxds)); 1639 if (!getmaxds) 1640 return -ENOMEM; 1641 1642 dest.payload.optional_bytes = 3; 1643 1644 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMXDS, &dest, 1); 1645 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1646 if (ret) { 1647 /* 1648 * optional_bytes = 3 accepts a 2-byte response on the first 1649 * attempt, so this fallback runs only when the 5-byte request 1650 * fails rather than returning a short read. 1651 */ 1652 dest.payload.len -= 3; 1653 dest.payload.optional_bytes = 0; 1654 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMXDS, &dest, 1); 1655 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1656 if (ret) 1657 goto out; 1658 } 1659 1660 if (dest.payload.actual_len != 2 && dest.payload.actual_len != 5) { 1661 ret = -EIO; 1662 goto out; 1663 } 1664 1665 info->max_read_ds = getmaxds->maxrd; 1666 info->max_write_ds = getmaxds->maxwr; 1667 if (dest.payload.actual_len == 5) 1668 info->max_read_turnaround = getmaxds->maxrdturn[0] | 1669 ((u32)getmaxds->maxrdturn[1] << 8) | 1670 ((u32)getmaxds->maxrdturn[2] << 16); 1671 1672 out: 1673 i3c_ccc_cmd_dest_cleanup(&dest); 1674 1675 return ret; 1676 } 1677 1678 static int i3c_master_gethdrcap_locked(struct i3c_master_controller *master, 1679 struct i3c_device_info *info) 1680 { 1681 struct i3c_ccc_gethdrcap *gethdrcap; 1682 struct i3c_ccc_cmd_dest dest; 1683 struct i3c_ccc_cmd cmd; 1684 int ret; 1685 1686 gethdrcap = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, 1687 sizeof(*gethdrcap)); 1688 if (!gethdrcap) 1689 return -ENOMEM; 1690 1691 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETHDRCAP, &dest, 1); 1692 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1693 if (ret) 1694 goto out; 1695 1696 if (dest.payload.actual_len != 1) { 1697 ret = -EIO; 1698 goto out; 1699 } 1700 1701 info->hdr_cap = gethdrcap->modes; 1702 1703 out: 1704 i3c_ccc_cmd_dest_cleanup(&dest); 1705 1706 return ret; 1707 } 1708 1709 static int i3c_master_getpid_locked(struct i3c_master_controller *master, 1710 struct i3c_device_info *info) 1711 { 1712 struct i3c_ccc_getpid *getpid; 1713 struct i3c_ccc_cmd_dest dest; 1714 struct i3c_ccc_cmd cmd; 1715 int ret, i; 1716 1717 getpid = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getpid)); 1718 if (!getpid) 1719 return -ENOMEM; 1720 1721 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETPID, &dest, 1); 1722 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1723 if (ret) 1724 goto out; 1725 1726 info->pid = 0; 1727 for (i = 0; i < sizeof(getpid->pid); i++) { 1728 int sft = (sizeof(getpid->pid) - i - 1) * 8; 1729 1730 info->pid |= (u64)getpid->pid[i] << sft; 1731 } 1732 1733 out: 1734 i3c_ccc_cmd_dest_cleanup(&dest); 1735 1736 return ret; 1737 } 1738 1739 static int i3c_master_getbcr_locked(struct i3c_master_controller *master, 1740 struct i3c_device_info *info) 1741 { 1742 struct i3c_ccc_getbcr *getbcr; 1743 struct i3c_ccc_cmd_dest dest; 1744 struct i3c_ccc_cmd cmd; 1745 int ret; 1746 1747 getbcr = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getbcr)); 1748 if (!getbcr) 1749 return -ENOMEM; 1750 1751 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETBCR, &dest, 1); 1752 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1753 if (ret) 1754 goto out; 1755 1756 info->bcr = getbcr->bcr; 1757 1758 out: 1759 i3c_ccc_cmd_dest_cleanup(&dest); 1760 1761 return ret; 1762 } 1763 1764 static int i3c_master_getdcr_locked(struct i3c_master_controller *master, 1765 struct i3c_device_info *info) 1766 { 1767 struct i3c_ccc_getdcr *getdcr; 1768 struct i3c_ccc_cmd_dest dest; 1769 struct i3c_ccc_cmd cmd; 1770 int ret; 1771 1772 getdcr = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getdcr)); 1773 if (!getdcr) 1774 return -ENOMEM; 1775 1776 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETDCR, &dest, 1); 1777 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1778 if (ret) 1779 goto out; 1780 1781 info->dcr = getdcr->dcr; 1782 1783 out: 1784 i3c_ccc_cmd_dest_cleanup(&dest); 1785 1786 return ret; 1787 } 1788 1789 static int i3c_master_retrieve_dev_info(struct i3c_dev_desc *dev) 1790 { 1791 struct i3c_master_controller *master = i3c_dev_get_master(dev); 1792 enum i3c_addr_slot_status slot_status; 1793 int ret; 1794 1795 if (!dev->info.dyn_addr) 1796 return -EINVAL; 1797 1798 slot_status = i3c_bus_get_addr_slot_status(&master->bus, 1799 dev->info.dyn_addr); 1800 if (slot_status == I3C_ADDR_SLOT_RSVD || 1801 slot_status == I3C_ADDR_SLOT_I2C_DEV) 1802 return -EINVAL; 1803 1804 ret = i3c_master_getpid_locked(master, &dev->info); 1805 if (ret) 1806 return ret; 1807 1808 ret = i3c_master_getbcr_locked(master, &dev->info); 1809 if (ret) 1810 return ret; 1811 1812 ret = i3c_master_getdcr_locked(master, &dev->info); 1813 if (ret) 1814 return ret; 1815 1816 if (dev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM) { 1817 ret = i3c_master_getmxds_locked(master, &dev->info); 1818 if (ret) 1819 return ret; 1820 } 1821 1822 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) 1823 dev->info.max_ibi_len = 1; 1824 1825 i3c_master_getmrl_locked(master, &dev->info); 1826 i3c_master_getmwl_locked(master, &dev->info); 1827 1828 if (dev->info.bcr & I3C_BCR_HDR_CAP) { 1829 ret = i3c_master_gethdrcap_locked(master, &dev->info); 1830 if (ret && ret != -EOPNOTSUPP) 1831 return ret; 1832 } 1833 1834 return 0; 1835 } 1836 1837 static int i3c_master_getstatus_locked(struct i3c_master_controller *master, 1838 u8 addr, u16 *status) 1839 { 1840 struct i3c_ccc_getstatus *getstatus; 1841 struct i3c_ccc_cmd_dest dest; 1842 struct i3c_ccc_cmd cmd; 1843 int ret; 1844 1845 getstatus = i3c_ccc_cmd_dest_init(&dest, addr, sizeof(*getstatus)); 1846 if (!getstatus) 1847 return -ENOMEM; 1848 1849 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETSTATUS, &dest, 1); 1850 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1851 if (ret) 1852 goto out; 1853 1854 if (status) 1855 *status = be16_to_cpu(getstatus->status); 1856 out: 1857 i3c_ccc_cmd_dest_cleanup(&dest); 1858 1859 return ret; 1860 } 1861 1862 /* Values are chosen to give the device plenty of opportunities to respond */ 1863 #define I3C_DEV_PROBE_INITIAL_DELAY_US 20 1864 #define I3C_DEV_PROBE_DELAY_FACTOR 2 1865 #define I3C_DEV_PROBE_CNT 5 1866 1867 static bool i3c_master_i3c_dev_present(struct i3c_master_controller *master, unsigned int addr) 1868 { 1869 int delay = I3C_DEV_PROBE_INITIAL_DELAY_US; 1870 1871 for (int i = 0; i < I3C_DEV_PROBE_CNT; i++) { 1872 if (i) { 1873 fsleep(delay); 1874 delay *= I3C_DEV_PROBE_DELAY_FACTOR; 1875 } 1876 if (!i3c_master_getstatus_locked(master, addr, NULL)) 1877 return true; 1878 } 1879 1880 return false; 1881 } 1882 1883 static void i3c_master_put_i3c_addrs(struct i3c_dev_desc *dev) 1884 { 1885 struct i3c_master_controller *master = i3c_dev_get_master(dev); 1886 1887 if (dev->info.static_addr) 1888 i3c_bus_set_addr_slot_status(&master->bus, 1889 dev->info.static_addr, 1890 I3C_ADDR_SLOT_FREE); 1891 1892 if (dev->info.dyn_addr) 1893 i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr, 1894 I3C_ADDR_SLOT_FREE); 1895 1896 if (dev->boardinfo && dev->boardinfo->init_dyn_addr) 1897 i3c_bus_set_addr_slot_status(&master->bus, dev->boardinfo->init_dyn_addr, 1898 I3C_ADDR_SLOT_FREE); 1899 } 1900 1901 static int i3c_master_get_i3c_addrs(struct i3c_dev_desc *dev) 1902 { 1903 struct i3c_master_controller *master = i3c_dev_get_master(dev); 1904 enum i3c_addr_slot_status status; 1905 1906 if (!dev->info.static_addr && !dev->info.dyn_addr) 1907 return 0; 1908 1909 if (dev->info.static_addr) { 1910 status = i3c_bus_get_addr_slot_status(&master->bus, 1911 dev->info.static_addr); 1912 /* Since static address and assigned dynamic address can be 1913 * equal, allow this case to pass. 1914 */ 1915 if (status != I3C_ADDR_SLOT_FREE && 1916 dev->info.static_addr != dev->boardinfo->init_dyn_addr) 1917 return -EBUSY; 1918 1919 i3c_bus_set_addr_slot_status(&master->bus, 1920 dev->info.static_addr, 1921 I3C_ADDR_SLOT_I3C_DEV); 1922 } 1923 1924 /* 1925 * ->init_dyn_addr should have been reserved before that, so, if we're 1926 * trying to apply a pre-reserved dynamic address, we should not try 1927 * to reserve the address slot a second time. 1928 */ 1929 if (dev->info.dyn_addr && 1930 (!dev->boardinfo || 1931 dev->boardinfo->init_dyn_addr != dev->info.dyn_addr)) { 1932 status = i3c_bus_get_addr_slot_status(&master->bus, 1933 dev->info.dyn_addr); 1934 if (status != I3C_ADDR_SLOT_FREE) 1935 goto err_release_static_addr; 1936 1937 i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr, 1938 I3C_ADDR_SLOT_I3C_DEV); 1939 } 1940 1941 return 0; 1942 1943 err_release_static_addr: 1944 if (dev->info.static_addr) 1945 i3c_bus_set_addr_slot_status(&master->bus, 1946 dev->info.static_addr, 1947 I3C_ADDR_SLOT_FREE); 1948 1949 return -EBUSY; 1950 } 1951 1952 /** 1953 * i3c_master_attach_i3c_dev_controller_locked() - Attach device state to 1954 * controller 1955 * @dev: I3C device descriptor 1956 * 1957 * Invoke the current controller's attach callback without changing address 1958 * slot state or adding the device to the controller's device list. 1959 * 1960 * Context: The caller must hold the bus lock. 1961 * 1962 * Return: 0 on success, or a negative error code returned by the controller. 1963 */ 1964 int i3c_master_attach_i3c_dev_controller_locked(struct i3c_dev_desc *dev) 1965 { 1966 struct i3c_master_controller *master = i3c_dev_get_master(dev); 1967 1968 /* Do not attach the master device itself. */ 1969 if (master->this != dev && master->ops->attach_i3c_dev) 1970 return master->ops->attach_i3c_dev(dev); 1971 1972 return 0; 1973 } 1974 EXPORT_SYMBOL_GPL(i3c_master_attach_i3c_dev_controller_locked); 1975 1976 static int i3c_master_attach_i3c_dev(struct i3c_master_controller *master, 1977 struct i3c_dev_desc *dev) 1978 { 1979 int ret; 1980 1981 /* 1982 * We don't attach devices to the controller until they are 1983 * addressable on the bus. 1984 */ 1985 if (!dev->info.static_addr && !dev->info.dyn_addr) 1986 return 0; 1987 1988 ret = i3c_master_get_i3c_addrs(dev); 1989 if (ret) 1990 return ret; 1991 1992 /* Do not attach the master device itself. */ 1993 ret = i3c_master_attach_i3c_dev_controller_locked(dev); 1994 if (ret) { 1995 i3c_master_put_i3c_addrs(dev); 1996 return ret; 1997 } 1998 1999 list_add_tail(&dev->common.node, &master->bus.devs.i3c); 2000 2001 return 0; 2002 } 2003 2004 /** 2005 * i3c_master_reattach_i3c_dev_controller_locked() - Reattach controller 2006 * device state 2007 * @dev: I3C device descriptor 2008 * @old_dyn_addr: Previous dynamic address 2009 * 2010 * Invoke the current controller's reattach callback without modifying the 2011 * controller's address-slot state. 2012 * 2013 * Context: The caller must hold the bus lock. 2014 * 2015 * Return: 0 on success, or a negative error code returned by the controller. 2016 */ 2017 int i3c_master_reattach_i3c_dev_controller_locked(struct i3c_dev_desc *dev, 2018 u8 old_dyn_addr) 2019 { 2020 struct i3c_master_controller *master = i3c_dev_get_master(dev); 2021 2022 if (master->ops->reattach_i3c_dev) 2023 return master->ops->reattach_i3c_dev(dev, old_dyn_addr); 2024 2025 return 0; 2026 } 2027 EXPORT_SYMBOL_GPL(i3c_master_reattach_i3c_dev_controller_locked); 2028 2029 /** 2030 * i3c_master_reattach_i3c_dev_locked() - reattach an I3C device with a new address 2031 * @dev: I3C device descriptor to reattach 2032 * @old_dyn_addr: previous dynamic address of the device 2033 * 2034 * This function reattaches an existing I3C device to the bus when its dynamic 2035 * address has changed. It updates the bus address slot status accordingly: 2036 * - Marks the new dynamic address as occupied by an I3C device. 2037 * - Frees the old dynamic address slot if applicable. 2038 * 2039 * This function must be called with the bus lock held in write mode. 2040 * 2041 * Return: 0 on success, or a negative error code if reattachment fails 2042 * (e.g. -EBUSY if the new address slot is not free). 2043 */ 2044 int i3c_master_reattach_i3c_dev_locked(struct i3c_dev_desc *dev, 2045 u8 old_dyn_addr) 2046 { 2047 struct i3c_master_controller *master = i3c_dev_get_master(dev); 2048 int ret; 2049 2050 if (dev->info.dyn_addr != old_dyn_addr) { 2051 i3c_bus_set_addr_slot_status(&master->bus, 2052 dev->info.dyn_addr, 2053 I3C_ADDR_SLOT_I3C_DEV); 2054 if (old_dyn_addr) 2055 i3c_bus_set_addr_slot_status(&master->bus, old_dyn_addr, 2056 I3C_ADDR_SLOT_FREE); 2057 } 2058 2059 ret = i3c_master_reattach_i3c_dev_controller_locked(dev, old_dyn_addr); 2060 if (ret) { 2061 i3c_master_put_i3c_addrs(dev); 2062 return ret; 2063 } 2064 2065 return 0; 2066 } 2067 EXPORT_SYMBOL_GPL(i3c_master_reattach_i3c_dev_locked); 2068 2069 /** 2070 * i3c_master_detach_i3c_dev_controller_locked() - Detach device state from 2071 * controller 2072 * @dev: I3C device descriptor 2073 * 2074 * Invoke the current controller's detach callback without releasing address 2075 * slots or removing the device from the controller's device list. 2076 * 2077 * Context: The caller must hold the bus lock. 2078 */ 2079 void i3c_master_detach_i3c_dev_controller_locked(struct i3c_dev_desc *dev) 2080 { 2081 struct i3c_master_controller *master = i3c_dev_get_master(dev); 2082 2083 /* Do not detach the master device itself. */ 2084 if (master->this != dev && master->ops->detach_i3c_dev) 2085 master->ops->detach_i3c_dev(dev); 2086 } 2087 EXPORT_SYMBOL_GPL(i3c_master_detach_i3c_dev_controller_locked); 2088 2089 static void i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) 2090 { 2091 i3c_master_detach_i3c_dev_controller_locked(dev); 2092 2093 i3c_master_put_i3c_addrs(dev); 2094 list_del(&dev->common.node); 2095 } 2096 2097 static int i3c_master_attach_i2c_dev(struct i3c_master_controller *master, 2098 struct i2c_dev_desc *dev) 2099 { 2100 int ret; 2101 2102 if (master->ops->attach_i2c_dev) { 2103 ret = master->ops->attach_i2c_dev(dev); 2104 if (ret) 2105 return ret; 2106 } 2107 2108 list_add_tail(&dev->common.node, &master->bus.devs.i2c); 2109 2110 return 0; 2111 } 2112 2113 static void i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) 2114 { 2115 struct i3c_master_controller *master = i2c_dev_get_master(dev); 2116 2117 list_del(&dev->common.node); 2118 2119 if (master->ops->detach_i2c_dev) 2120 master->ops->detach_i2c_dev(dev); 2121 } 2122 2123 static int i3c_master_early_i3c_dev_add(struct i3c_master_controller *master, 2124 struct i3c_dev_boardinfo *boardinfo) 2125 { 2126 struct i3c_device_info info = { 2127 .static_addr = boardinfo->static_addr, 2128 .pid = boardinfo->pid, 2129 }; 2130 struct i3c_dev_desc *i3cdev; 2131 int ret; 2132 2133 i3cdev = i3c_master_alloc_i3c_dev(master, &info); 2134 if (IS_ERR(i3cdev)) { 2135 ret = -ENOMEM; 2136 goto err_reserve_addr; 2137 } 2138 2139 i3cdev->boardinfo = boardinfo; 2140 2141 ret = i3c_master_attach_i3c_dev(master, i3cdev); 2142 if (ret) 2143 goto err_free_dev; 2144 2145 /* 2146 * For devices using SETAASA instead of ENTDAA, the address is statically 2147 * assigned. Update the dynamic address to the provided static address. 2148 * Reattach the I3C device after updating the dynamic address with the same 2149 * static address. It is not mandatory for such devices to implement CCC 2150 * commands like GETPID, GETDCR etc. Hence, we can return after reattaching. 2151 */ 2152 if (i3cdev->boardinfo->static_addr_method & I3C_ADDR_METHOD_SETAASA) { 2153 i3cdev->info.dyn_addr = i3cdev->boardinfo->static_addr; 2154 ret = i3c_master_reattach_i3c_dev_locked(i3cdev, 0); 2155 if (ret) 2156 goto err_detach_dev; 2157 2158 return 0; 2159 } 2160 2161 ret = i3c_master_setdasa_locked(master, i3cdev->info.static_addr, 2162 i3cdev->boardinfo->init_dyn_addr); 2163 if (ret) 2164 goto err_detach_dev; 2165 2166 i3cdev->info.dyn_addr = i3cdev->boardinfo->init_dyn_addr; 2167 ret = i3c_master_reattach_i3c_dev_locked(i3cdev, 0); 2168 if (ret) 2169 goto err_rstdaa; 2170 2171 ret = i3c_master_retrieve_dev_info(i3cdev); 2172 if (ret) 2173 goto err_rstdaa; 2174 2175 return 0; 2176 2177 err_rstdaa: 2178 i3c_master_rstdaa_locked(master, i3cdev->boardinfo->init_dyn_addr); 2179 err_detach_dev: 2180 i3c_master_detach_i3c_dev(i3cdev); 2181 err_free_dev: 2182 i3c_master_free_i3c_dev(i3cdev); 2183 err_reserve_addr: 2184 /* 2185 * A target using SETAASA may still get the static address on the 2186 * SETAASA broadcast even if attach fails here. Keep the address 2187 * reserved so that it is not assigned to another device during DAA. 2188 */ 2189 if (boardinfo->static_addr_method & I3C_ADDR_METHOD_SETAASA) 2190 i3c_bus_set_addr_slot_status(&master->bus, 2191 boardinfo->static_addr, 2192 I3C_ADDR_SLOT_RSVD); 2193 2194 return ret; 2195 } 2196 2197 static void 2198 i3c_master_register_new_i3c_devs(struct i3c_master_controller *master) 2199 { 2200 struct i3c_device *i3cdev, *tmp; 2201 struct i3c_dev_desc *desc; 2202 LIST_HEAD(i3c_unreg_devs); 2203 int ret; 2204 2205 if (!master->init_done) 2206 return; 2207 2208 i3c_bus_maintenance_lock(&master->bus); 2209 2210 if (master->shutting_down) { 2211 i3c_bus_maintenance_unlock(&master->bus); 2212 return; 2213 } 2214 2215 i3c_bus_for_each_i3cdev(&master->bus, desc) { 2216 if (desc->dev || !desc->info.dyn_addr || desc == master->this) 2217 continue; 2218 2219 desc->dev = kzalloc_obj(*desc->dev); 2220 if (!desc->dev) 2221 continue; 2222 2223 desc->dev->bus = &master->bus; 2224 desc->dev->desc = desc; 2225 desc->dev->dev.parent = &master->dev; 2226 desc->dev->dev.type = &i3c_device_type; 2227 desc->dev->dev.bus = &i3c_bus_type; 2228 desc->dev->dev.release = i3c_device_release; 2229 2230 /* 2231 * For devices without PID (e.g., SETAASA devices), use 2232 * static address for naming instead. 2233 */ 2234 if (desc->info.pid) 2235 dev_set_name(&desc->dev->dev, "%d-%llx", master->bus.id, 2236 desc->info.pid); 2237 else 2238 dev_set_name(&desc->dev->dev, "%d-%02x", master->bus.id, 2239 desc->info.static_addr); 2240 2241 if (desc->boardinfo) 2242 device_set_node(&desc->dev->dev, desc->boardinfo->fwnode); 2243 2244 /* If the device has IBI capability, set as wakeup capable */ 2245 if (master->ibi_wakeup && (desc->info.bcr & I3C_BCR_IBI_REQ_CAP)) 2246 device_set_wakeup_capable(&desc->dev->dev, true); 2247 2248 list_add_tail(&desc->dev->node, &i3c_unreg_devs); 2249 } 2250 2251 i3c_bus_maintenance_unlock(&master->bus); 2252 2253 list_for_each_entry_safe(i3cdev, tmp, &i3c_unreg_devs, node) { 2254 ret = device_register(&i3cdev->dev); 2255 if (ret) 2256 dev_err(&master->dev, "Failed to add I3C device (err = %d)\n", ret); 2257 else 2258 list_del_init(&i3cdev->node); 2259 } 2260 2261 i3c_bus_maintenance_lock(&master->bus); 2262 2263 list_for_each_entry_safe(i3cdev, tmp, &i3c_unreg_devs, node) { 2264 list_del(&i3cdev->node); 2265 desc = i3cdev->desc; 2266 i3cdev->desc = NULL; 2267 put_device(&i3cdev->dev); 2268 desc->dev = NULL; 2269 } 2270 2271 i3c_bus_maintenance_unlock(&master->bus); 2272 } 2273 2274 static void i3c_master_reg_work_fn(struct work_struct *work) 2275 { 2276 struct i3c_master_controller *master = container_of(work, typeof(*master), reg_work); 2277 2278 i3c_master_register_new_i3c_devs(master); 2279 } 2280 2281 /** 2282 * i3c_master_has_wakeup_enabled_devs() - check if any device can wake the system 2283 * @master: I3C master controller 2284 * 2285 * Iterate over devices on the bus and return true if any device has 2286 * system wakeup enabled and IBI enabled. 2287 * 2288 * Whether a device is enabled for system wakeup is user space policy, 2289 * settable at any time through the device's power/wakeup sysfs attribute, 2290 * so the answer is only stable once user space is frozen. Call this from 2291 * a system suspend callback. 2292 * 2293 * Return: true if any device may wake the system via IBI, false otherwise. 2294 */ 2295 bool i3c_master_has_wakeup_enabled_devs(struct i3c_master_controller *master) 2296 { 2297 struct i3c_dev_desc *desc; 2298 bool wakeup = false; 2299 2300 i3c_bus_normaluse_lock(&master->bus); 2301 i3c_bus_for_each_i3cdev(&master->bus, desc) { 2302 if (!desc->dev || desc == master->this || !device_may_wakeup(&desc->dev->dev)) 2303 continue; 2304 guard(mutex)(&desc->ibi_lock); 2305 if (desc->ibi && desc->ibi->enabled) { 2306 wakeup = true; 2307 break; 2308 } 2309 } 2310 i3c_bus_normaluse_unlock(&master->bus); 2311 2312 return wakeup; 2313 } 2314 EXPORT_SYMBOL_GPL(i3c_master_has_wakeup_enabled_devs); 2315 2316 /** 2317 * i3c_master_dma_map_single() - Map buffer for single DMA transfer 2318 * @dev: device object of a device doing DMA 2319 * @buf: destination/source buffer for DMA 2320 * @len: length of transfer 2321 * @force_bounce: true, force to use a bounce buffer, 2322 * false, function will auto check is a bounce buffer required 2323 * @dir: DMA direction 2324 * 2325 * Map buffer for a DMA transfer and allocate a bounce buffer if required. 2326 * 2327 * Return: I3C DMA transfer descriptor or NULL in case of error. 2328 */ 2329 struct i3c_dma *i3c_master_dma_map_single(struct device *dev, void *buf, 2330 size_t len, bool force_bounce, enum dma_data_direction dir) 2331 { 2332 void *bounce __free(kfree) = NULL; 2333 void *dma_buf = buf; 2334 2335 struct i3c_dma *dma_xfer __free(kfree) = kzalloc_obj(*dma_xfer); 2336 if (!dma_xfer) 2337 return NULL; 2338 2339 dma_xfer->dev = dev; 2340 dma_xfer->buf = buf; 2341 dma_xfer->dir = dir; 2342 dma_xfer->len = len; 2343 dma_xfer->map_len = len; 2344 2345 if (is_vmalloc_addr(buf)) 2346 force_bounce = true; 2347 2348 if (force_bounce) { 2349 dma_xfer->map_len = ALIGN(len, cache_line_size()); 2350 bounce = kzalloc(dma_xfer->map_len, GFP_KERNEL); 2351 if (!bounce) 2352 return NULL; 2353 if (dir != DMA_FROM_DEVICE) 2354 memcpy(bounce, buf, len); 2355 dma_buf = bounce; 2356 } 2357 2358 dma_xfer->addr = dma_map_single(dev, dma_buf, dma_xfer->map_len, dir); 2359 if (dma_mapping_error(dev, dma_xfer->addr)) 2360 return NULL; 2361 2362 dma_xfer->bounce_buf = no_free_ptr(bounce); 2363 return no_free_ptr(dma_xfer); 2364 } 2365 EXPORT_SYMBOL_GPL(i3c_master_dma_map_single); 2366 2367 /** 2368 * i3c_master_dma_unmap_single() - Unmap buffer after DMA 2369 * @dma_xfer: DMA transfer and mapping descriptor 2370 * 2371 * Unmap buffer and cleanup DMA transfer descriptor. 2372 */ 2373 void i3c_master_dma_unmap_single(struct i3c_dma *dma_xfer) 2374 { 2375 dma_unmap_single(dma_xfer->dev, dma_xfer->addr, 2376 dma_xfer->map_len, dma_xfer->dir); 2377 if (dma_xfer->bounce_buf) { 2378 if (dma_xfer->dir == DMA_FROM_DEVICE) 2379 memcpy(dma_xfer->buf, dma_xfer->bounce_buf, 2380 dma_xfer->len); 2381 kfree(dma_xfer->bounce_buf); 2382 } 2383 kfree(dma_xfer); 2384 } 2385 EXPORT_SYMBOL_GPL(i3c_master_dma_unmap_single); 2386 2387 /** 2388 * i3c_master_set_info() - set master device information 2389 * @master: master used to send frames on the bus 2390 * @info: I3C device information 2391 * 2392 * Set master device info. This should be called from 2393 * &i3c_master_controller_ops->bus_init(). 2394 * 2395 * Not all &i3c_device_info fields are meaningful for a master device. 2396 * Here is a list of fields that should be properly filled: 2397 * 2398 * - &i3c_device_info->dyn_addr 2399 * - &i3c_device_info->bcr 2400 * - &i3c_device_info->dcr 2401 * - &i3c_device_info->pid 2402 * - &i3c_device_info->hdr_cap if %I3C_BCR_HDR_CAP bit is set in 2403 * &i3c_device_info->bcr 2404 * 2405 * This function must be called with the bus lock held in maintenance mode. 2406 * 2407 * Return: 0 if @info contains valid information (not every piece of 2408 * information can be checked, but we can at least make sure @info->dyn_addr 2409 * and @info->bcr are correct), -EINVAL otherwise. 2410 */ 2411 int i3c_master_set_info(struct i3c_master_controller *master, 2412 const struct i3c_device_info *info) 2413 { 2414 struct i3c_dev_desc *i3cdev; 2415 int ret; 2416 2417 if (!i3c_bus_dev_addr_is_avail(&master->bus, info->dyn_addr)) 2418 return -EINVAL; 2419 2420 if (I3C_BCR_DEVICE_ROLE(info->bcr) == I3C_BCR_I3C_MASTER && 2421 master->secondary) 2422 return -EINVAL; 2423 2424 if (master->this) 2425 return -EINVAL; 2426 2427 i3cdev = i3c_master_alloc_i3c_dev(master, info); 2428 if (IS_ERR(i3cdev)) 2429 return PTR_ERR(i3cdev); 2430 2431 master->this = i3cdev; 2432 master->bus.cur_master = master->this; 2433 2434 ret = i3c_master_attach_i3c_dev(master, i3cdev); 2435 if (ret) 2436 goto err_free_dev; 2437 2438 return 0; 2439 2440 err_free_dev: 2441 master->bus.cur_master = NULL; 2442 master->this = NULL; 2443 i3c_master_free_i3c_dev(i3cdev); 2444 2445 return ret; 2446 } 2447 EXPORT_SYMBOL_GPL(i3c_master_set_info); 2448 2449 static void i3c_master_detach_free_devs(struct i3c_master_controller *master) 2450 { 2451 struct i3c_dev_desc *i3cdev, *i3ctmp; 2452 struct i2c_dev_desc *i2cdev, *i2ctmp; 2453 2454 list_for_each_entry_safe(i3cdev, i3ctmp, &master->bus.devs.i3c, 2455 common.node) { 2456 i3c_master_detach_i3c_dev(i3cdev); 2457 2458 if (i3cdev->boardinfo && i3cdev->boardinfo->init_dyn_addr) 2459 i3c_bus_set_addr_slot_status(&master->bus, 2460 i3cdev->boardinfo->init_dyn_addr, 2461 I3C_ADDR_SLOT_FREE); 2462 2463 if (i3cdev != master->this) 2464 i3c_master_free_i3c_dev(i3cdev); 2465 } 2466 2467 list_for_each_entry_safe(i2cdev, i2ctmp, &master->bus.devs.i2c, 2468 common.node) { 2469 i3c_master_detach_i2c_dev(i2cdev); 2470 i3c_bus_set_addr_slot_status(&master->bus, 2471 i2cdev->addr, 2472 I3C_ADDR_SLOT_FREE); 2473 i3c_master_free_i2c_dev(i2cdev); 2474 } 2475 } 2476 2477 /** 2478 * i3c_master_bus_init() - initialize an I3C bus 2479 * @master: main master initializing the bus 2480 * 2481 * This function is following all initialisation steps described in the I3C 2482 * specification: 2483 * 2484 * 1. Attach I2C devs to the master so that the master can fill its internal 2485 * device table appropriately 2486 * 2487 * 2. Call &i3c_master_controller_ops->bus_init() method to initialize 2488 * the master controller. That's usually where the bus mode is selected 2489 * (pure bus or mixed fast/slow bus) 2490 * 2491 * 3. Instruct all devices on the bus to drop their dynamic address. This is 2492 * particularly important when the bus was previously configured by someone 2493 * else (for example the bootloader) 2494 * 2495 * 4. Disable all slave events. 2496 * 2497 * 5. Reserve address slots for I3C devices with init_dyn_addr. And if devices 2498 * also have static_addr, try to pre-assign dynamic addresses requested by 2499 * the FW with SETDASA and attach corresponding statically defined I3C 2500 * devices to the master. 2501 * 2502 * 6. Do a DAA (Dynamic Address Assignment) to assign dynamic addresses to all 2503 * remaining I3C devices 2504 * 2505 * Once this is done, all I3C and I2C devices should be usable. 2506 * 2507 * Return: a 0 in case of success, an negative error code otherwise. 2508 */ 2509 static int i3c_master_bus_init(struct i3c_master_controller *master) 2510 { 2511 enum i3c_addr_slot_status status; 2512 struct i2c_dev_boardinfo *i2cboardinfo; 2513 struct i3c_dev_boardinfo *i3cboardinfo; 2514 struct i2c_dev_desc *i2cdev; 2515 int ret; 2516 2517 /* 2518 * First attach all devices with static definitions provided by the 2519 * FW. 2520 */ 2521 list_for_each_entry(i2cboardinfo, &master->boardinfo.i2c, node) { 2522 status = i3c_bus_get_addr_slot_status(&master->bus, 2523 i2cboardinfo->base.addr); 2524 if (status != I3C_ADDR_SLOT_FREE) { 2525 ret = -EBUSY; 2526 goto err_detach_devs; 2527 } 2528 2529 i3c_bus_set_addr_slot_status(&master->bus, 2530 i2cboardinfo->base.addr, 2531 I3C_ADDR_SLOT_I2C_DEV); 2532 2533 i2cdev = i3c_master_alloc_i2c_dev(master, 2534 i2cboardinfo->base.addr, 2535 i2cboardinfo->lvr); 2536 if (IS_ERR(i2cdev)) { 2537 ret = PTR_ERR(i2cdev); 2538 goto err_detach_devs; 2539 } 2540 2541 ret = i3c_master_attach_i2c_dev(master, i2cdev); 2542 if (ret) { 2543 i3c_master_free_i2c_dev(i2cdev); 2544 goto err_detach_devs; 2545 } 2546 } 2547 2548 /* 2549 * Now execute the controller specific ->bus_init() routine, which 2550 * might configure its internal logic to match the bus limitations. 2551 */ 2552 ret = master->ops->bus_init(master); 2553 if (ret) 2554 goto err_detach_devs; 2555 2556 /* 2557 * The master device should have been instantiated in ->bus_init(), 2558 * complain if this was not the case. 2559 */ 2560 if (!master->this) { 2561 dev_err(&master->dev, 2562 "master_set_info() was not called in ->bus_init()\n"); 2563 ret = -EINVAL; 2564 goto err_bus_cleanup; 2565 } 2566 2567 if (master->ops->set_speed) { 2568 ret = master->ops->set_speed(master, I3C_OPEN_DRAIN_SLOW_SPEED); 2569 if (ret) 2570 goto err_bus_cleanup; 2571 } 2572 2573 /* 2574 * Reset all dynamic address that may have been assigned before 2575 * (assigned by the bootloader for example). 2576 */ 2577 ret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR); 2578 if (ret) 2579 goto err_bus_cleanup; 2580 2581 if (master->ops->set_speed) { 2582 ret = master->ops->set_speed(master, I3C_OPEN_DRAIN_NORMAL_SPEED); 2583 if (ret) 2584 goto err_bus_cleanup; 2585 } 2586 2587 /* 2588 * Disable all slave events before starting DAA. When no active device 2589 * is on the bus, returns Mx error code M2, this error is ignored. 2590 */ 2591 ret = i3c_master_enec_disec_locked(master, I3C_BROADCAST_ADDR, false, 2592 I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR | 2593 I3C_CCC_EVENT_HJ, true); 2594 if (ret) 2595 goto err_bus_cleanup; 2596 2597 /* 2598 * Reserve init_dyn_addr first, and then try to pre-assign dynamic 2599 * address and retrieve device information if needed. 2600 * In case pre-assign dynamic address fails, setting dynamic address to 2601 * the requested init_dyn_addr is retried after DAA is done in 2602 * i3c_master_add_i3c_dev_locked(). 2603 */ 2604 list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) { 2605 2606 /* 2607 * We don't reserve a dynamic address for devices that 2608 * don't explicitly request one. 2609 */ 2610 if (!i3cboardinfo->init_dyn_addr) 2611 continue; 2612 2613 ret = i3c_bus_get_addr_slot_status(&master->bus, 2614 i3cboardinfo->init_dyn_addr); 2615 if (ret != I3C_ADDR_SLOT_FREE) { 2616 ret = -EBUSY; 2617 goto err_rstdaa; 2618 } 2619 2620 /* Do not mark as occupied until real device exist in bus */ 2621 i3c_bus_set_addr_slot_status_mask(&master->bus, 2622 i3cboardinfo->init_dyn_addr, 2623 I3C_ADDR_SLOT_EXT_DESIRED, 2624 I3C_ADDR_SLOT_EXT_STATUS_MASK); 2625 2626 /* 2627 * Only try to create/attach devices that have a static 2628 * address. Other devices will be created/attached when 2629 * DAA happens, and the requested dynamic address will 2630 * be set using SETNEWDA once those devices become 2631 * addressable. 2632 */ 2633 2634 if (i3cboardinfo->static_addr) 2635 i3c_master_early_i3c_dev_add(master, i3cboardinfo); 2636 } 2637 2638 /* 2639 * SETAASA is a broadcast CCC. Issue it after SETDASA so that devices 2640 * configured for SETDASA (or supporting both methods) are assigned 2641 * first, matching MIPI DISCO guidance to prefer SETDASA when both are 2642 * available. Targets that already have a dynamic address ignore the 2643 * later SETAASA broadcast. 2644 */ 2645 if (master->addr_method & I3C_ADDR_METHOD_SETAASA) { 2646 ret = i3c_master_setaasa_locked(master); 2647 if (ret) 2648 goto err_rstdaa; 2649 } 2650 2651 ret = i3c_master_do_daa(master); 2652 if (ret) 2653 goto err_rstdaa; 2654 2655 return 0; 2656 2657 err_rstdaa: 2658 i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR); 2659 2660 err_bus_cleanup: 2661 if (master->ops->bus_cleanup) 2662 master->ops->bus_cleanup(master); 2663 2664 err_detach_devs: 2665 i3c_master_detach_free_devs(master); 2666 2667 return ret; 2668 } 2669 2670 static void i3c_master_bus_cleanup(struct i3c_master_controller *master) 2671 { 2672 if (master->ops->bus_cleanup) { 2673 int ret = i3c_master_rpm_get(master); 2674 2675 if (ret) { 2676 dev_err(&master->dev, 2677 "runtime resume error: master bus_cleanup() not done\n"); 2678 } else { 2679 master->ops->bus_cleanup(master); 2680 i3c_master_rpm_put(master); 2681 } 2682 } 2683 2684 i3c_master_detach_free_devs(master); 2685 } 2686 2687 static void i3c_master_attach_boardinfo(struct i3c_dev_desc *i3cdev) 2688 { 2689 struct i3c_master_controller *master = i3cdev->common.master; 2690 struct i3c_dev_boardinfo *i3cboardinfo; 2691 2692 list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) { 2693 /* 2694 * For devices without PID (e.g., SETAASA devices), match by 2695 * static address. For devices with PID, match by PID. 2696 */ 2697 if (i3cboardinfo->pid) { 2698 if (i3cdev->info.pid != i3cboardinfo->pid) 2699 continue; 2700 } else { 2701 if (!i3cboardinfo->static_addr || 2702 i3cdev->info.static_addr != i3cboardinfo->static_addr) 2703 continue; 2704 } 2705 2706 i3cdev->boardinfo = i3cboardinfo; 2707 i3cdev->info.static_addr = i3cboardinfo->static_addr; 2708 return; 2709 } 2710 } 2711 2712 static struct i3c_dev_desc * 2713 i3c_master_search_i3c_dev_duplicate(struct i3c_dev_desc *refdev) 2714 { 2715 struct i3c_master_controller *master = i3c_dev_get_master(refdev); 2716 struct i3c_dev_desc *i3cdev; 2717 2718 if (!refdev->info.pid) 2719 return NULL; 2720 2721 i3c_bus_for_each_i3cdev(&master->bus, i3cdev) { 2722 if (i3cdev != refdev && i3cdev->info.pid && 2723 i3cdev->info.pid == refdev->info.pid && 2724 i3cdev != master->this) 2725 return i3cdev; 2726 } 2727 2728 return NULL; 2729 } 2730 2731 /** 2732 * __i3c_master_add_i3c_dev_locked() - add an I3C slave to the bus 2733 * @master: master used to send frames on the bus 2734 * @addr: I3C slave dynamic address assigned to the device 2735 * @probe: probe to see if the device is really present at @addr 2736 * 2737 * This function instantiates an I3C device object and adds it to the I3C device 2738 * list. All device information is retrieved using standard CCC commands. 2739 * 2740 * This function must be called with the bus lock held in write mode. 2741 */ 2742 static void __i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master, 2743 u8 addr, bool probe) 2744 { 2745 struct i3c_device_info info = { .dyn_addr = addr }; 2746 struct i3c_dev_desc *newdev, *olddev; 2747 u8 old_dyn_addr = addr, expected_dyn_addr; 2748 struct i3c_ibi_setup ibireq = { }; 2749 bool enable_ibi = false; 2750 bool no_dev = false; 2751 int ret; 2752 2753 newdev = i3c_master_alloc_i3c_dev(master, &info); 2754 if (IS_ERR(newdev)) { 2755 ret = PTR_ERR(newdev); 2756 goto err_prevent_addr_reuse; 2757 } 2758 2759 ret = i3c_master_attach_i3c_dev(master, newdev); 2760 if (ret) 2761 goto err_free_dev; 2762 2763 /* 2764 * When a dynamic address is first assigned, there is no need to check 2765 * whether it is still assigned, however, if adding the device fails, 2766 * it will be attempted again later, at which point the address may 2767 * have been lost (e.g. due to power management), so for that case, 2768 * probe to see if the device is still present at the assigned address. 2769 */ 2770 if (probe && !i3c_master_i3c_dev_present(master, addr)) { 2771 no_dev = true; 2772 goto err_detach_dev; 2773 } 2774 2775 ret = i3c_master_retrieve_dev_info(newdev); 2776 if (ret) 2777 goto err_detach_dev; 2778 2779 i3c_master_attach_boardinfo(newdev); 2780 2781 olddev = i3c_master_search_i3c_dev_duplicate(newdev); 2782 if (olddev) { 2783 newdev->dev = olddev->dev; 2784 if (newdev->dev) 2785 newdev->dev->desc = newdev; 2786 2787 /* 2788 * We need to restore the IBI state too, so let's save the 2789 * IBI information and try to restore them after olddev has 2790 * been detached+released and its IBI has been stopped and 2791 * the associated resources have been freed. 2792 */ 2793 mutex_lock(&olddev->ibi_lock); 2794 if (olddev->ibi) { 2795 ibireq.handler = olddev->ibi->handler; 2796 ibireq.max_payload_len = olddev->ibi->max_payload_len; 2797 ibireq.num_slots = olddev->ibi->num_slots; 2798 2799 if (olddev->ibi->enabled) 2800 enable_ibi = true; 2801 /* 2802 * The olddev should not receive any commands on the 2803 * i3c bus as it does not exist and has been assigned 2804 * a new address. This will result in NACK or timeout. 2805 * So, update the olddev->ibi->enabled flag to false 2806 * to avoid DISEC with OldAddr. 2807 */ 2808 olddev->ibi->enabled = false; 2809 i3c_dev_free_ibi_locked(olddev); 2810 } 2811 mutex_unlock(&olddev->ibi_lock); 2812 2813 old_dyn_addr = olddev->info.dyn_addr; 2814 2815 i3c_master_detach_i3c_dev(olddev); 2816 i3c_master_free_i3c_dev(olddev); 2817 } 2818 2819 /* 2820 * Depending on our previous state, the expected dynamic address might 2821 * differ: 2822 * - if the device already had a dynamic address assigned, let's try to 2823 * re-apply this one 2824 * - if the device did not have a dynamic address and the firmware 2825 * requested a specific address, pick this one 2826 * - in any other case, keep the address automatically assigned by the 2827 * master 2828 */ 2829 if (old_dyn_addr && old_dyn_addr != newdev->info.dyn_addr) 2830 expected_dyn_addr = old_dyn_addr; 2831 else if (newdev->boardinfo && newdev->boardinfo->init_dyn_addr) 2832 expected_dyn_addr = newdev->boardinfo->init_dyn_addr; 2833 else 2834 expected_dyn_addr = newdev->info.dyn_addr; 2835 2836 if (newdev->info.dyn_addr != expected_dyn_addr && 2837 i3c_bus_get_addr_slot_status(&master->bus, expected_dyn_addr) == I3C_ADDR_SLOT_FREE) { 2838 /* 2839 * Try to apply the expected dynamic address. If it fails, keep 2840 * the address assigned by the master. 2841 */ 2842 ret = i3c_master_setnewda_locked(master, 2843 newdev->info.dyn_addr, 2844 expected_dyn_addr); 2845 if (!ret) { 2846 old_dyn_addr = newdev->info.dyn_addr; 2847 newdev->info.dyn_addr = expected_dyn_addr; 2848 i3c_master_reattach_i3c_dev_locked(newdev, old_dyn_addr); 2849 } else { 2850 dev_err(&master->dev, 2851 "Failed to assign reserved/old address to device %d%llx", 2852 master->bus.id, newdev->info.pid); 2853 } 2854 } 2855 2856 /* 2857 * Now is time to try to restore the IBI setup. If we're lucky, 2858 * everything works as before, otherwise, all we can do is complain. 2859 * FIXME: maybe we should add callback to inform the driver that it 2860 * should request the IBI again instead of trying to hide that from 2861 * him. 2862 */ 2863 if (ibireq.handler) { 2864 mutex_lock(&newdev->ibi_lock); 2865 ret = i3c_dev_request_ibi_locked(newdev, &ibireq); 2866 if (ret) { 2867 dev_err(&master->dev, 2868 "Failed to request IBI on device %d-%llx", 2869 master->bus.id, newdev->info.pid); 2870 } else if (enable_ibi) { 2871 ret = i3c_dev_enable_ibi_locked(newdev); 2872 if (ret) 2873 dev_err(&master->dev, 2874 "Failed to re-enable IBI on device %d-%llx", 2875 master->bus.id, newdev->info.pid); 2876 } 2877 mutex_unlock(&newdev->ibi_lock); 2878 } 2879 2880 return; 2881 2882 err_detach_dev: 2883 if (newdev->dev && newdev->dev->desc) 2884 newdev->dev->desc = NULL; 2885 2886 i3c_master_detach_i3c_dev(newdev); 2887 2888 err_free_dev: 2889 i3c_master_free_i3c_dev(newdev); 2890 2891 err_prevent_addr_reuse: 2892 if (no_dev) 2893 return; 2894 /* 2895 * Although the device has not been added, the address has been 2896 * assigned. Prevent the address from being used again. 2897 */ 2898 if (i3c_bus_get_addr_slot_status(&master->bus, addr) == I3C_ADDR_SLOT_FREE) 2899 i3c_bus_set_addr_slot_status(&master->bus, addr, I3C_ADDR_SLOT_I3C_DEV); 2900 2901 dev_err(&master->dev, "Failed to add I3C device at address %u, error %d\n", addr, ret); 2902 } 2903 2904 /** 2905 * i3c_master_add_i3c_dev_locked() - add an I3C slave to the bus 2906 * @master: master used to send frames on the bus 2907 * @addr: I3C slave dynamic address assigned to the device 2908 * 2909 * This function instantiates an I3C device object and adds it to the 2910 * I3C device list. All device information is automatically retrieved using 2911 * standard CCC commands. 2912 * 2913 * This function must be called with the bus lock held in write mode. 2914 */ 2915 void i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master, u8 addr) 2916 { 2917 __i3c_master_add_i3c_dev_locked(master, addr, false); 2918 } 2919 EXPORT_SYMBOL_GPL(i3c_master_add_i3c_dev_locked); 2920 2921 static void i3c_master_reconcile_dyn_addrs(struct i3c_master_controller *master) 2922 { 2923 DECLARE_BITMAP(dev_dyn_addrs, I2C_MAX_ADDR + 1); 2924 enum i3c_addr_slot_status status; 2925 struct i3c_dev_desc *desc; 2926 2927 /* Mark all devices' dynamic and static addresses in the bitmap */ 2928 bitmap_zero(dev_dyn_addrs, I2C_MAX_ADDR + 1); 2929 i3c_bus_for_each_i3cdev(&master->bus, desc) { 2930 if (desc->info.static_addr) 2931 __set_bit(desc->info.static_addr, dev_dyn_addrs); 2932 __set_bit(desc->info.dyn_addr, dev_dyn_addrs); 2933 } 2934 /* Reconcile the bitmap with the bus address slot status */ 2935 for (unsigned int addr = 0; addr <= I2C_MAX_ADDR; addr++) { 2936 status = i3c_bus_get_addr_slot_status(&master->bus, addr); 2937 if (status != I3C_ADDR_SLOT_I3C_DEV || test_bit(addr, dev_dyn_addrs)) 2938 continue; 2939 i3c_bus_set_addr_slot_status(&master->bus, addr, I3C_ADDR_SLOT_FREE); 2940 /* Try to add the device, but probe to see if it is really present */ 2941 __i3c_master_add_i3c_dev_locked(master, addr, true); 2942 } 2943 } 2944 2945 /** 2946 * i3c_master_supports_ccc_cmd() - check CCC command support 2947 * @master: I3C master controller 2948 * @cmd: CCC command to verify 2949 * 2950 * Return: true if @cmd is supported, false otherwise. 2951 */ 2952 bool i3c_master_supports_ccc_cmd(struct i3c_master_controller *master, 2953 const struct i3c_ccc_cmd *cmd) 2954 { 2955 if (!master || !cmd) 2956 return false; 2957 2958 if (!master->ops->send_ccc_cmd) 2959 return false; 2960 2961 if (!master->ops->supports_ccc_cmd) 2962 return true; 2963 2964 return master->ops->supports_ccc_cmd(master, cmd); 2965 } 2966 EXPORT_SYMBOL_GPL(i3c_master_supports_ccc_cmd); 2967 2968 /** 2969 * i3c_master_send_ccc_cmd() - send a CCC command 2970 * @master: I3C master controller issuing the command 2971 * @cmd: CCC command to be sent 2972 * 2973 * This function sends a Common Command Code (CCC) command to devices on the 2974 * I3C bus. It acquires the bus maintenance lock, executes the command, and 2975 * then releases the lock to ensure safe access to the bus. 2976 * 2977 * Return: 0 on success, or a negative error code on failure. 2978 */ 2979 int i3c_master_send_ccc_cmd(struct i3c_master_controller *master, 2980 struct i3c_ccc_cmd *cmd) 2981 { 2982 int ret; 2983 2984 ret = i3c_master_rpm_get(master); 2985 if (ret) 2986 return ret; 2987 2988 i3c_bus_maintenance_lock(&master->bus); 2989 ret = i3c_master_send_ccc_cmd_locked(master, cmd); 2990 i3c_bus_maintenance_unlock(&master->bus); 2991 2992 i3c_master_rpm_put(master); 2993 2994 return ret; 2995 } 2996 EXPORT_SYMBOL_GPL(i3c_master_send_ccc_cmd); 2997 2998 /** 2999 * i3c_master_do_daa_ext() - Dynamic Address Assignment (extended version) 3000 * @master: controller 3001 * @rstdaa: whether to first perform Reset of Dynamic Addresses (RSTDAA) 3002 * 3003 * Perform Dynamic Address Assignment with optional support for System 3004 * Hibernation (@rstdaa is true). 3005 * 3006 * After System Hibernation, Dynamic Addresses can have been reassigned at boot 3007 * time to different values. A simple strategy is followed to handle that. 3008 * Perform a Reset of Dynamic Addresses (RSTDAA) followed by the normal DAA 3009 * procedure which has provision for reassigning addresses that differ from the 3010 * previously recorded addresses. 3011 * 3012 * Return: a 0 in case of success, an negative error code otherwise. 3013 */ 3014 int i3c_master_do_daa_ext(struct i3c_master_controller *master, bool rstdaa) 3015 { 3016 int rstret = 0; 3017 int ret; 3018 3019 ret = i3c_master_rpm_get(master); 3020 if (ret) 3021 return ret; 3022 3023 i3c_bus_maintenance_lock(&master->bus); 3024 3025 if (master->shutting_down) { 3026 ret = -ENODEV; 3027 } else { 3028 if (rstdaa) 3029 rstret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR); 3030 ret = master->ops->do_daa(master); 3031 /* 3032 * Handle cases where a dynamic address was assigned but the 3033 * device was not successfully added. 3034 */ 3035 i3c_master_reconcile_dyn_addrs(master); 3036 } 3037 3038 i3c_bus_maintenance_unlock(&master->bus); 3039 3040 if (ret) 3041 goto out; 3042 3043 queue_work(master->wq, &master->reg_work); 3044 out: 3045 i3c_master_rpm_put(master); 3046 3047 return rstret ?: ret; 3048 } 3049 EXPORT_SYMBOL_GPL(i3c_master_do_daa_ext); 3050 3051 /** 3052 * i3c_master_do_daa() - do a DAA (Dynamic Address Assignment) 3053 * @master: master doing the DAA 3054 * 3055 * This function instantiates I3C device objects and adds them to the 3056 * I3C device list. All device information is automatically retrieved using 3057 * standard CCC commands. 3058 * 3059 * Return: a 0 in case of success, an negative error code otherwise. 3060 */ 3061 int i3c_master_do_daa(struct i3c_master_controller *master) 3062 { 3063 return i3c_master_do_daa_ext(master, false); 3064 } 3065 EXPORT_SYMBOL_GPL(i3c_master_do_daa); 3066 3067 #define OF_I3C_REG1_IS_I2C_DEV BIT(31) 3068 3069 #ifdef CONFIG_ACPI 3070 static int i3c_acpi_get_i2c_resource(struct acpi_resource *ares, void *data) 3071 { 3072 struct i2c_dev_boardinfo *boardinfo = data; 3073 struct acpi_resource_i2c_serialbus *sb; 3074 3075 if (boardinfo->base.addr || !i2c_acpi_get_i2c_resource(ares, &sb)) 3076 return 1; 3077 3078 boardinfo->base.addr = sb->slave_address; 3079 if (sb->access_mode == ACPI_I2C_10BIT_MODE) 3080 boardinfo->base.flags |= I2C_CLIENT_TEN; 3081 3082 boardinfo->lvr = sb->lvr; 3083 3084 return 1; 3085 } 3086 3087 static int i3c_acpi_add_i2c_boardinfo(struct i2c_dev_boardinfo *boardinfo, 3088 struct fwnode_handle *fwnode) 3089 { 3090 struct acpi_device *adev = to_acpi_device_node(fwnode); 3091 LIST_HEAD(resources); 3092 int ret; 3093 3094 boardinfo->base.fwnode = acpi_fwnode_handle(adev); 3095 acpi_set_modalias(adev, dev_name(&adev->dev), boardinfo->base.type, 3096 sizeof(boardinfo->base.type)); 3097 3098 ret = acpi_dev_get_resources(adev, &resources, 3099 i3c_acpi_get_i2c_resource, boardinfo); 3100 if (ret < 0) 3101 return ret; 3102 3103 acpi_dev_free_resource_list(&resources); 3104 3105 if (!boardinfo->base.addr) 3106 return -ENODEV; 3107 3108 return 0; 3109 } 3110 #else 3111 static inline int i3c_acpi_add_i2c_boardinfo(struct i2c_dev_boardinfo *boardinfo, 3112 struct fwnode_handle *fwnode) 3113 { 3114 return -ENODEV; 3115 } 3116 #endif 3117 3118 static int 3119 i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master, 3120 struct fwnode_handle *fwnode, u32 *reg) 3121 { 3122 struct i2c_dev_boardinfo *boardinfo; 3123 struct device *dev = &master->dev; 3124 int ret; 3125 3126 boardinfo = devm_kzalloc_obj(dev, *boardinfo); 3127 if (!boardinfo) 3128 return -ENOMEM; 3129 3130 if (is_of_node(fwnode)) { 3131 ret = of_i2c_get_board_info(dev, to_of_node(fwnode), &boardinfo->base); 3132 if (ret) 3133 return ret; 3134 3135 /* LVR is encoded in reg[2] for Device Tree. */ 3136 boardinfo->lvr = reg[2]; 3137 } else if (is_acpi_device_node(fwnode)) { 3138 ret = i3c_acpi_add_i2c_boardinfo(boardinfo, fwnode); 3139 if (ret) { 3140 devm_kfree(dev, boardinfo); 3141 return ret; 3142 } 3143 } else { 3144 return -EINVAL; 3145 } 3146 3147 /* 3148 * The I3C Specification does not clearly say I2C devices with 10-bit 3149 * address are supported. These devices can't be passed properly through 3150 * DEFSLVS command. 3151 */ 3152 if (boardinfo->base.flags & I2C_CLIENT_TEN) { 3153 dev_err(dev, "I2C device with 10 bit address not supported.\n"); 3154 return -EOPNOTSUPP; 3155 } 3156 3157 list_add_tail(&boardinfo->node, &master->boardinfo.i2c); 3158 fwnode_handle_get(fwnode); 3159 3160 return 0; 3161 } 3162 3163 static int 3164 i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master, 3165 struct fwnode_handle *fwnode, u32 *reg) 3166 { 3167 struct i3c_dev_boardinfo *boardinfo; 3168 struct device *dev = &master->dev; 3169 enum i3c_addr_slot_status addrstatus; 3170 u32 init_dyn_addr = 0, static_addr_method = 0; 3171 3172 boardinfo = devm_kzalloc_obj(dev, *boardinfo); 3173 if (!boardinfo) 3174 return -ENOMEM; 3175 3176 if (reg[0]) { 3177 if (reg[0] > I3C_MAX_ADDR) 3178 return -EINVAL; 3179 3180 addrstatus = i3c_bus_get_addr_slot_status(&master->bus, 3181 reg[0]); 3182 if (addrstatus != I3C_ADDR_SLOT_FREE) 3183 return -EINVAL; 3184 } 3185 3186 boardinfo->static_addr = reg[0]; 3187 3188 if (!fwnode_property_read_u32(fwnode, "mipi-i3c-static-method", &static_addr_method)) 3189 boardinfo->static_addr_method = static_addr_method & 3190 (I3C_ADDR_METHOD_SETDASA | I3C_ADDR_METHOD_SETAASA); 3191 3192 if (!fwnode_property_read_u32(fwnode, "assigned-address", &init_dyn_addr)) { 3193 /* 3194 * When a device advertises both SETDASA and SETAASA, an explicit 3195 * dynamic address selects SETDASA (MIPI DISCO prefers it); drop 3196 * SETAASA so it is not used for this device. 3197 */ 3198 if (boardinfo->static_addr_method & I3C_ADDR_METHOD_SETDASA) 3199 boardinfo->static_addr_method &= ~I3C_ADDR_METHOD_SETAASA; 3200 3201 if (init_dyn_addr > I3C_MAX_ADDR) 3202 return -EINVAL; 3203 3204 addrstatus = i3c_bus_get_addr_slot_status(&master->bus, 3205 init_dyn_addr); 3206 if (addrstatus != I3C_ADDR_SLOT_FREE) 3207 return -EINVAL; 3208 } 3209 3210 if (boardinfo->static_addr_method & I3C_ADDR_METHOD_SETAASA) { 3211 /* For SETAASA, static address is taken as the dynamic address. */ 3212 init_dyn_addr = boardinfo->static_addr; 3213 } 3214 3215 /* Update the address methods required for device discovery */ 3216 master->addr_method |= boardinfo->static_addr_method; 3217 3218 boardinfo->pid = ((u64)reg[1] << 32) | reg[2]; 3219 3220 /* For SETAASA devices, validate the static address instead of PID */ 3221 if (boardinfo->static_addr_method & I3C_ADDR_METHOD_SETAASA) { 3222 if (!boardinfo->static_addr) 3223 return -EINVAL; 3224 } else { 3225 if (!I3C_PID_MANUF_ID(boardinfo->pid) || 3226 (boardinfo->pid & GENMASK_ULL(63, 48)) || 3227 I3C_PID_RND_LOWER_32BITS(boardinfo->pid)) 3228 return -EINVAL; 3229 } 3230 3231 boardinfo->init_dyn_addr = init_dyn_addr; 3232 boardinfo->fwnode = fwnode_handle_get(fwnode); 3233 list_add_tail(&boardinfo->node, &master->boardinfo.i3c); 3234 3235 return 0; 3236 } 3237 3238 static int i3c_master_add_of_dev(struct i3c_master_controller *master, 3239 struct fwnode_handle *fwnode) 3240 { 3241 u32 reg[3]; 3242 int ret; 3243 3244 if (!master) 3245 return -EINVAL; 3246 3247 ret = fwnode_property_read_u32_array(fwnode, "reg", reg, ARRAY_SIZE(reg)); 3248 if (ret) 3249 return ret; 3250 3251 /* 3252 * I3C device should have either the manufacturer ID specified or the 3253 * address discovery method specified. Else treat it as an I2C device. 3254 */ 3255 if (!reg[1] && !fwnode_property_present(fwnode, "mipi-i3c-static-method")) 3256 ret = i3c_master_add_i2c_boardinfo(master, fwnode, reg); 3257 else 3258 ret = i3c_master_add_i3c_boardinfo(master, fwnode, reg); 3259 3260 return ret; 3261 } 3262 3263 #define I3C_ACPI_ADR_PID GENMASK_U64(47, 0) 3264 /* 3265 * Zero-based instance number of the Bus Controller to which the Target is 3266 * connected. 3267 */ 3268 #define I3C_ACPI_ADR_INSTANCE GENMASK_U64(51, 48) 3269 3270 #ifdef CONFIG_ACPI 3271 static int i3c_master_add_acpi_dev(struct i3c_master_controller *master, 3272 struct fwnode_handle *fwnode) 3273 { 3274 struct acpi_device *adev = to_acpi_device_node(fwnode); 3275 acpi_bus_address adr; 3276 u32 reg[3] = { 0 }; 3277 u64 pid; 3278 int ret; 3279 3280 /* 3281 * If the ACPI table entry has _ADR method, it's an I3C device. 3282 * Otherwise it may be an I2C device described by an I2cSerialBus 3283 * resource. If no I2cSerialBus resource is found, ignore the entry. 3284 */ 3285 if (!acpi_has_method(adev->handle, "_ADR")) { 3286 ret = i3c_master_add_i2c_boardinfo(master, fwnode, reg); 3287 if (ret == -ENODEV) 3288 return 0; 3289 3290 return ret; 3291 } 3292 3293 adr = acpi_device_adr(adev); 3294 3295 /* Match the multi-bus instance number */ 3296 if (FIELD_GET(I3C_ACPI_ADR_INSTANCE, adr) != master->instance) 3297 return 0; 3298 3299 /* For I3C devices, _ADR will have the 48 bit PID of the device */ 3300 pid = FIELD_GET(I3C_ACPI_ADR_PID, adr); 3301 3302 reg[1] = upper_32_bits(pid); 3303 reg[2] = lower_32_bits(pid); 3304 3305 fwnode_property_read_u32(fwnode, "mipi-i3c-static-address", ®[0]); 3306 3307 return i3c_master_add_i3c_boardinfo(master, fwnode, reg); 3308 } 3309 3310 static u8 i3c_acpi_i2c_get_lvr(struct i2c_client *client) 3311 { 3312 struct acpi_device *adev = to_acpi_device_node(client->dev.fwnode); 3313 struct i2c_dev_boardinfo boardinfo = {}; 3314 LIST_HEAD(resources); 3315 int ret; 3316 u8 lvr; 3317 3318 lvr = I3C_LVR_I2C_INDEX(2) | I3C_LVR_I2C_FM_MODE; 3319 3320 ret = acpi_dev_get_resources(adev, &resources, 3321 i3c_acpi_get_i2c_resource, &boardinfo); 3322 if (ret < 0) 3323 return lvr; 3324 3325 if (boardinfo.base.addr) 3326 lvr = boardinfo.lvr; 3327 3328 acpi_dev_free_resource_list(&resources); 3329 3330 return lvr; 3331 } 3332 #else 3333 static inline int i3c_master_add_acpi_dev(struct i3c_master_controller *master, 3334 struct fwnode_handle *fwnode) 3335 { 3336 return -ENODEV; 3337 } 3338 3339 static inline u8 i3c_acpi_i2c_get_lvr(struct i2c_client *client) 3340 { 3341 return I3C_LVR_I2C_INDEX(2) | I3C_LVR_I2C_FM_MODE; 3342 } 3343 #endif 3344 3345 static int fwnode_populate_i3c_bus(struct i3c_master_controller *master) 3346 { 3347 struct device *dev = &master->dev; 3348 struct fwnode_handle *fwnode = dev_fwnode(dev); 3349 int ret; 3350 u32 val; 3351 3352 if (!fwnode) 3353 return 0; 3354 3355 fwnode_for_each_available_child_node_scoped(fwnode, child) { 3356 if (is_of_node(child)) 3357 ret = i3c_master_add_of_dev(master, child); 3358 else if (is_acpi_device_node(child)) 3359 ret = i3c_master_add_acpi_dev(master, child); 3360 else 3361 continue; 3362 3363 if (ret) 3364 return ret; 3365 } 3366 3367 /* 3368 * The user might want to limit I2C and I3C speed in case some devices 3369 * on the bus are not supporting typical rates, or if the bus topology 3370 * prevents it from using max possible rate. 3371 */ 3372 if (!device_property_read_u32(dev, "i2c-scl-hz", &val)) 3373 master->bus.scl_rate.i2c = val; 3374 3375 if (!device_property_read_u32(dev, "i3c-scl-hz", &val)) 3376 master->bus.scl_rate.i3c = val; 3377 3378 return 0; 3379 } 3380 3381 static int i3c_master_i2c_adapter_xfer(struct i2c_adapter *adap, 3382 struct i2c_msg *xfers, int nxfers) 3383 { 3384 struct i3c_master_controller *master = i2c_adapter_to_i3c_master(adap); 3385 struct i2c_dev_desc *dev; 3386 int i, ret; 3387 u16 addr; 3388 3389 if (!xfers || !master || nxfers <= 0) 3390 return -EINVAL; 3391 3392 if (!master->ops->i2c_xfers) 3393 return -EOPNOTSUPP; 3394 3395 /* Doing transfers to different devices is not supported. */ 3396 addr = xfers[0].addr; 3397 for (i = 1; i < nxfers; i++) { 3398 if (addr != xfers[i].addr) 3399 return -EOPNOTSUPP; 3400 } 3401 3402 ret = i3c_master_rpm_get(master); 3403 if (ret) 3404 return ret; 3405 3406 i3c_bus_normaluse_lock(&master->bus); 3407 dev = i3c_master_find_i2c_dev_by_addr(master, addr); 3408 if (!dev) 3409 ret = -ENOENT; 3410 else 3411 ret = master->ops->i2c_xfers(dev, xfers, nxfers); 3412 i3c_bus_normaluse_unlock(&master->bus); 3413 3414 i3c_master_rpm_put(master); 3415 3416 return ret ? ret : nxfers; 3417 } 3418 3419 static u32 i3c_master_i2c_funcs(struct i2c_adapter *adapter) 3420 { 3421 return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C; 3422 } 3423 3424 static u8 i3c_master_i2c_get_lvr(struct i2c_client *client) 3425 { 3426 /* Fall back to no spike filters and FM bus mode. */ 3427 u8 lvr = I3C_LVR_I2C_INDEX(2) | I3C_LVR_I2C_FM_MODE; 3428 u32 reg[3]; 3429 3430 if (is_of_node(client->dev.fwnode)) { 3431 if (!fwnode_property_read_u32_array(client->dev.fwnode, "reg", 3432 reg, ARRAY_SIZE(reg))) 3433 lvr = reg[2]; 3434 } else if (is_acpi_device_node(client->dev.fwnode)) { 3435 lvr = i3c_acpi_i2c_get_lvr(client); 3436 } 3437 3438 return lvr; 3439 } 3440 3441 static int i3c_master_i2c_attach(struct i2c_adapter *adap, struct i2c_client *client) 3442 { 3443 struct i3c_master_controller *master = i2c_adapter_to_i3c_master(adap); 3444 enum i3c_addr_slot_status status; 3445 struct i2c_dev_desc *i2cdev; 3446 int ret; 3447 3448 /* Already added by board info? */ 3449 if (i3c_master_find_i2c_dev_by_addr(master, client->addr)) 3450 return 0; 3451 3452 status = i3c_bus_get_addr_slot_status(&master->bus, client->addr); 3453 if (status != I3C_ADDR_SLOT_FREE) 3454 return -EBUSY; 3455 3456 i3c_bus_set_addr_slot_status(&master->bus, client->addr, 3457 I3C_ADDR_SLOT_I2C_DEV); 3458 3459 i2cdev = i3c_master_alloc_i2c_dev(master, client->addr, 3460 i3c_master_i2c_get_lvr(client)); 3461 if (IS_ERR(i2cdev)) { 3462 ret = PTR_ERR(i2cdev); 3463 goto out_clear_status; 3464 } 3465 3466 ret = i3c_master_attach_i2c_dev(master, i2cdev); 3467 if (ret) 3468 goto out_free_dev; 3469 3470 return 0; 3471 3472 out_free_dev: 3473 i3c_master_free_i2c_dev(i2cdev); 3474 out_clear_status: 3475 i3c_bus_set_addr_slot_status(&master->bus, client->addr, 3476 I3C_ADDR_SLOT_FREE); 3477 3478 return ret; 3479 } 3480 3481 static int i3c_master_i2c_detach(struct i2c_adapter *adap, struct i2c_client *client) 3482 { 3483 struct i3c_master_controller *master = i2c_adapter_to_i3c_master(adap); 3484 struct i2c_dev_desc *dev; 3485 3486 dev = i3c_master_find_i2c_dev_by_addr(master, client->addr); 3487 if (!dev) 3488 return -ENODEV; 3489 3490 i3c_master_detach_i2c_dev(dev); 3491 i3c_bus_set_addr_slot_status(&master->bus, dev->addr, 3492 I3C_ADDR_SLOT_FREE); 3493 i3c_master_free_i2c_dev(dev); 3494 3495 return 0; 3496 } 3497 3498 static const struct i2c_algorithm i3c_master_i2c_algo = { 3499 .master_xfer = i3c_master_i2c_adapter_xfer, 3500 .functionality = i3c_master_i2c_funcs, 3501 }; 3502 3503 static int i3c_i2c_notifier_call(struct notifier_block *nb, unsigned long action, 3504 void *data) 3505 { 3506 struct i2c_adapter *adap; 3507 struct i2c_client *client; 3508 struct device *dev = data; 3509 struct i3c_master_controller *master; 3510 int ret; 3511 3512 if (dev->type != &i2c_client_type) 3513 return 0; 3514 3515 client = to_i2c_client(dev); 3516 adap = client->adapter; 3517 3518 if (adap->algo != &i3c_master_i2c_algo) 3519 return 0; 3520 3521 master = i2c_adapter_to_i3c_master(adap); 3522 3523 ret = i3c_master_rpm_get(master); 3524 if (ret) 3525 return ret; 3526 3527 i3c_bus_maintenance_lock(&master->bus); 3528 switch (action) { 3529 case BUS_NOTIFY_ADD_DEVICE: 3530 ret = i3c_master_i2c_attach(adap, client); 3531 break; 3532 case BUS_NOTIFY_DEL_DEVICE: 3533 ret = i3c_master_i2c_detach(adap, client); 3534 break; 3535 default: 3536 ret = -EINVAL; 3537 } 3538 i3c_bus_maintenance_unlock(&master->bus); 3539 3540 i3c_master_rpm_put(master); 3541 3542 return ret; 3543 } 3544 3545 static struct notifier_block i2cdev_notifier = { 3546 .notifier_call = i3c_i2c_notifier_call, 3547 }; 3548 3549 static int i3c_master_i2c_adapter_init(struct i3c_master_controller *master) 3550 { 3551 struct i2c_adapter *adap = i3c_master_to_i2c_adapter(master); 3552 struct i2c_dev_desc *i2cdev; 3553 struct i2c_dev_boardinfo *i2cboardinfo; 3554 struct fwnode_handle *fwnode = dev_fwnode(&master->dev); 3555 int ret, id = -1; 3556 3557 adap->dev.parent = master->dev.parent; 3558 adap->owner = master->dev.parent->driver->owner; 3559 adap->algo = &i3c_master_i2c_algo; 3560 strscpy(adap->name, dev_name(master->dev.parent), sizeof(adap->name)); 3561 adap->timeout = HZ; 3562 adap->retries = 3; 3563 3564 if (fwnode && is_of_node(fwnode)) 3565 id = of_alias_get_id(to_of_node(fwnode), "i2c"); 3566 3567 if (id >= 0) { 3568 adap->nr = id; 3569 ret = i2c_add_numbered_adapter(adap); 3570 } else { 3571 ret = i2c_add_adapter(adap); 3572 } 3573 if (ret) 3574 return ret; 3575 3576 /* 3577 * We silently ignore failures here. The bus should keep working 3578 * correctly even if one or more i2c devices are not registered. 3579 */ 3580 list_for_each_entry(i2cboardinfo, &master->boardinfo.i2c, node) { 3581 i2cdev = i3c_master_find_i2c_dev_by_addr(master, 3582 i2cboardinfo->base.addr); 3583 if (WARN_ON(!i2cdev)) 3584 continue; 3585 i2cdev->dev = i2c_new_client_device(adap, &i2cboardinfo->base); 3586 } 3587 3588 return 0; 3589 } 3590 3591 static void i3c_master_i2c_adapter_cleanup(struct i3c_master_controller *master) 3592 { 3593 struct i2c_dev_desc *i2cdev; 3594 3595 i2c_del_adapter(&master->i2c); 3596 3597 i3c_bus_for_each_i2cdev(&master->bus, i2cdev) 3598 i2cdev->dev = NULL; 3599 } 3600 3601 static void i3c_master_unregister_i3c_devs(struct i3c_master_controller *master) 3602 { 3603 struct i3c_dev_desc *i3cdev; 3604 3605 i3c_bus_for_each_i3cdev(&master->bus, i3cdev) { 3606 if (!i3cdev->dev) 3607 continue; 3608 3609 if (device_is_registered(&i3cdev->dev->dev)) { 3610 get_device(&i3cdev->dev->dev); 3611 device_unregister(&i3cdev->dev->dev); 3612 } 3613 i3cdev->dev->desc = NULL; 3614 put_device(&i3cdev->dev->dev); 3615 i3cdev->dev = NULL; 3616 } 3617 } 3618 3619 /* Approximate time for IBI handler to run */ 3620 #define I3C_WAKEUP_PROCESSING_TIME_MS 100 3621 3622 /** 3623 * i3c_master_queue_ibi() - Queue an IBI 3624 * @dev: the device this IBI is coming from 3625 * @slot: the IBI slot used to store the payload 3626 * 3627 * Queue an IBI to the controller workqueue. The IBI handler attached to 3628 * the dev will be called from a workqueue context. 3629 */ 3630 void i3c_master_queue_ibi(struct i3c_dev_desc *dev, struct i3c_ibi_slot *slot) 3631 { 3632 if (!dev->ibi || !slot) 3633 return; 3634 3635 if (device_may_wakeup(&dev->dev->dev)) 3636 pm_wakeup_event(&dev->dev->dev, I3C_WAKEUP_PROCESSING_TIME_MS); 3637 3638 atomic_inc(&dev->ibi->pending_ibis); 3639 queue_work(dev->ibi->wq, &slot->work); 3640 } 3641 EXPORT_SYMBOL_GPL(i3c_master_queue_ibi); 3642 3643 static void i3c_master_handle_ibi(struct work_struct *work) 3644 { 3645 struct i3c_ibi_slot *slot = container_of(work, struct i3c_ibi_slot, 3646 work); 3647 struct i3c_dev_desc *dev = slot->dev; 3648 struct i3c_ibi_payload payload; 3649 3650 payload.data = slot->data; 3651 payload.len = slot->len; 3652 3653 if (dev->dev) 3654 dev->ibi->handler(dev->dev, &payload); 3655 3656 i3c_dev_recycle_ibi_slot_controller(dev, slot); 3657 if (atomic_dec_and_test(&dev->ibi->pending_ibis)) 3658 complete(&dev->ibi->all_ibis_handled); 3659 } 3660 3661 static void i3c_master_init_ibi_slot(struct i3c_dev_desc *dev, 3662 struct i3c_ibi_slot *slot) 3663 { 3664 slot->dev = dev; 3665 INIT_WORK(&slot->work, i3c_master_handle_ibi); 3666 } 3667 3668 struct i3c_generic_ibi_slot { 3669 struct list_head node; 3670 struct i3c_ibi_slot base; 3671 }; 3672 3673 struct i3c_generic_ibi_pool { 3674 spinlock_t lock; 3675 unsigned int num_slots; 3676 void *payload_buf; 3677 struct list_head free_slots; 3678 struct list_head pending; 3679 struct i3c_generic_ibi_slot slots[] __counted_by(num_slots); 3680 }; 3681 3682 /** 3683 * i3c_generic_ibi_free_pool() - Free a generic IBI pool 3684 * @pool: the IBI pool to free 3685 * 3686 * Free all IBI slots allated by a generic IBI pool. 3687 */ 3688 void i3c_generic_ibi_free_pool(struct i3c_generic_ibi_pool *pool) 3689 { 3690 struct i3c_generic_ibi_slot *slot; 3691 unsigned int nslots = 0; 3692 3693 while (!list_empty(&pool->free_slots)) { 3694 slot = list_first_entry(&pool->free_slots, 3695 struct i3c_generic_ibi_slot, node); 3696 list_del(&slot->node); 3697 nslots++; 3698 } 3699 3700 /* 3701 * If the number of freed slots is not equal to the number of allocated 3702 * slots we have a leak somewhere. 3703 */ 3704 WARN_ON(nslots != pool->num_slots); 3705 3706 kfree(pool->payload_buf); 3707 kfree(pool); 3708 } 3709 EXPORT_SYMBOL_GPL(i3c_generic_ibi_free_pool); 3710 3711 /** 3712 * i3c_generic_ibi_alloc_pool() - Create a generic IBI pool 3713 * @dev: the device this pool will be used for 3714 * @req: IBI setup request describing what the device driver expects 3715 * 3716 * Create a generic IBI pool based on the information provided in @req. 3717 * 3718 * Return: a valid IBI pool in case of success, an ERR_PTR() otherwise. 3719 */ 3720 struct i3c_generic_ibi_pool * 3721 i3c_generic_ibi_alloc_pool(struct i3c_dev_desc *dev, 3722 const struct i3c_ibi_setup *req) 3723 { 3724 struct i3c_generic_ibi_pool *pool; 3725 struct i3c_generic_ibi_slot *slot; 3726 unsigned int i; 3727 int ret; 3728 3729 pool = kzalloc_flex(*pool, slots, req->num_slots); 3730 if (!pool) 3731 return ERR_PTR(-ENOMEM); 3732 3733 pool->num_slots = req->num_slots; 3734 3735 spin_lock_init(&pool->lock); 3736 INIT_LIST_HEAD(&pool->free_slots); 3737 INIT_LIST_HEAD(&pool->pending); 3738 3739 if (req->max_payload_len) { 3740 pool->payload_buf = kcalloc(req->num_slots, 3741 req->max_payload_len, GFP_KERNEL); 3742 if (!pool->payload_buf) { 3743 ret = -ENOMEM; 3744 goto err_free_pool; 3745 } 3746 } 3747 3748 for (i = 0; i < req->num_slots; i++) { 3749 slot = &pool->slots[i]; 3750 i3c_master_init_ibi_slot(dev, &slot->base); 3751 3752 if (req->max_payload_len) 3753 slot->base.data = pool->payload_buf + 3754 (i * req->max_payload_len); 3755 3756 list_add_tail(&slot->node, &pool->free_slots); 3757 } 3758 3759 return pool; 3760 3761 err_free_pool: 3762 i3c_generic_ibi_free_pool(pool); 3763 return ERR_PTR(ret); 3764 } 3765 EXPORT_SYMBOL_GPL(i3c_generic_ibi_alloc_pool); 3766 3767 /** 3768 * i3c_dev_recycle_ibi_slot_controller() - Recycle an IBI slot through 3769 * the current controller 3770 * @dev: I3C device descriptor 3771 * @slot: IBI slot to recycle 3772 * 3773 * Invoke the current controller's IBI slot recycling callback. 3774 * 3775 * Context: Called from the generic IBI work handler in workqueue context. 3776 * No bus lock is taken here: the controller owns its IBI pool and is 3777 * responsible for synchronizing access to it. The generic pool 3778 * implementation uses its own spinlock. 3779 */ 3780 void i3c_dev_recycle_ibi_slot_controller(struct i3c_dev_desc *dev, 3781 struct i3c_ibi_slot *slot) 3782 { 3783 struct i3c_master_controller *master = i3c_dev_get_master(dev); 3784 3785 if (master->ops->recycle_ibi_slot) 3786 master->ops->recycle_ibi_slot(dev, slot); 3787 } 3788 EXPORT_SYMBOL_GPL(i3c_dev_recycle_ibi_slot_controller); 3789 3790 /** 3791 * i3c_generic_ibi_get_free_slot() - Get a free slot from a generic IBI pool 3792 * @pool: the pool to query an IBI slot on 3793 * 3794 * Search for a free slot in a generic IBI pool. 3795 * The slot should be returned to the pool using i3c_generic_ibi_recycle_slot() 3796 * when it's no longer needed. 3797 * 3798 * Return: a pointer to a free slot, or NULL if there's no free slot available. 3799 */ 3800 struct i3c_ibi_slot * 3801 i3c_generic_ibi_get_free_slot(struct i3c_generic_ibi_pool *pool) 3802 { 3803 struct i3c_generic_ibi_slot *slot; 3804 unsigned long flags; 3805 3806 spin_lock_irqsave(&pool->lock, flags); 3807 slot = list_first_entry_or_null(&pool->free_slots, 3808 struct i3c_generic_ibi_slot, node); 3809 if (slot) 3810 list_del(&slot->node); 3811 spin_unlock_irqrestore(&pool->lock, flags); 3812 3813 return slot ? &slot->base : NULL; 3814 } 3815 EXPORT_SYMBOL_GPL(i3c_generic_ibi_get_free_slot); 3816 3817 /** 3818 * i3c_generic_ibi_recycle_slot() - Return a slot to a generic IBI pool 3819 * @pool: the pool to return the IBI slot to 3820 * @s: IBI slot to recycle 3821 * 3822 * Add an IBI slot back to its generic IBI pool. Should be called from the 3823 * master driver struct_master_controller_ops->recycle_ibi() method. 3824 */ 3825 void i3c_generic_ibi_recycle_slot(struct i3c_generic_ibi_pool *pool, 3826 struct i3c_ibi_slot *s) 3827 { 3828 struct i3c_generic_ibi_slot *slot; 3829 unsigned long flags; 3830 3831 if (!s) 3832 return; 3833 3834 slot = container_of(s, struct i3c_generic_ibi_slot, base); 3835 spin_lock_irqsave(&pool->lock, flags); 3836 list_add_tail(&slot->node, &pool->free_slots); 3837 spin_unlock_irqrestore(&pool->lock, flags); 3838 } 3839 EXPORT_SYMBOL_GPL(i3c_generic_ibi_recycle_slot); 3840 3841 static int i3c_master_check_ops(const struct i3c_master_controller_ops *ops) 3842 { 3843 if (!ops || !ops->bus_init || !ops->i3c_xfers || 3844 !ops->send_ccc_cmd || !ops->do_daa || !ops->i2c_xfers) 3845 return -EINVAL; 3846 3847 if (ops->request_ibi && 3848 (!ops->enable_ibi || !ops->disable_ibi || !ops->free_ibi || 3849 !ops->recycle_ibi_slot)) 3850 return -EINVAL; 3851 3852 return 0; 3853 } 3854 3855 /** 3856 * i3c_master_register_fwnode() - register an I3C master with a custom fwnode 3857 * @master: master used to send frames on the bus 3858 * @parent: the parent device providing this I3C master controller 3859 * @fwnode: firmware node describing this I3C bus, or NULL 3860 * @ops: the master controller operations 3861 * @secondary: true if registering a secondary master 3862 * 3863 * This helper is useful for virtual I3C masters whose firmware node is not 3864 * the same as @parent's firmware node. 3865 * 3866 * Return: 0 in case of success, a negative error code otherwise. 3867 */ 3868 int i3c_master_register_fwnode(struct i3c_master_controller *master, 3869 struct device *parent, 3870 struct fwnode_handle *fwnode, 3871 const struct i3c_master_controller_ops *ops, 3872 bool secondary) 3873 { 3874 unsigned long i2c_scl_rate = I3C_BUS_I2C_FM_PLUS_SCL_MAX_RATE; 3875 struct i3c_bus *i3cbus = i3c_master_get_bus(master); 3876 enum i3c_bus_mode mode = I3C_BUS_MODE_PURE; 3877 struct i2c_dev_boardinfo *i2cbi; 3878 int ret; 3879 3880 /* We do not support secondary masters yet. */ 3881 if (secondary) 3882 return -EOPNOTSUPP; 3883 3884 ret = i3c_master_check_ops(ops); 3885 if (ret) 3886 return ret; 3887 3888 master->dev.parent = parent; 3889 device_set_node(&master->dev, fwnode_handle_get(fwnode)); 3890 master->dev.bus = &i3c_bus_type; 3891 master->dev.type = &i3c_masterdev_type; 3892 master->dev.release = i3c_masterdev_release; 3893 master->ops = ops; 3894 master->secondary = secondary; 3895 master->addr_method = I3C_ADDR_METHOD_SETDASA; 3896 INIT_LIST_HEAD(&master->boardinfo.i2c); 3897 INIT_LIST_HEAD(&master->boardinfo.i3c); 3898 3899 ret = i3c_master_rpm_get(master); 3900 if (ret) 3901 return ret; 3902 3903 device_initialize(&master->dev); 3904 3905 master->dev.dma_mask = parent->dma_mask; 3906 master->dev.coherent_dma_mask = parent->coherent_dma_mask; 3907 master->dev.dma_parms = parent->dma_parms; 3908 3909 ret = i3c_bus_init(i3cbus, dev_fwnode(&master->dev)); 3910 if (ret) 3911 goto err_put_dev; 3912 3913 dev_set_name(&master->dev, "i3c-%d", i3cbus->id); 3914 3915 ret = fwnode_populate_i3c_bus(master); 3916 if (ret) 3917 goto err_put_dev; 3918 3919 list_for_each_entry(i2cbi, &master->boardinfo.i2c, node) { 3920 switch (i2cbi->lvr & I3C_LVR_I2C_INDEX_MASK) { 3921 case I3C_LVR_I2C_INDEX(0): 3922 if (mode < I3C_BUS_MODE_MIXED_FAST) 3923 mode = I3C_BUS_MODE_MIXED_FAST; 3924 break; 3925 case I3C_LVR_I2C_INDEX(1): 3926 if (mode < I3C_BUS_MODE_MIXED_LIMITED) 3927 mode = I3C_BUS_MODE_MIXED_LIMITED; 3928 break; 3929 case I3C_LVR_I2C_INDEX(2): 3930 if (mode < I3C_BUS_MODE_MIXED_SLOW) 3931 mode = I3C_BUS_MODE_MIXED_SLOW; 3932 break; 3933 default: 3934 ret = -EINVAL; 3935 goto err_put_dev; 3936 } 3937 3938 if (i2cbi->lvr & I3C_LVR_I2C_FM_MODE) 3939 i2c_scl_rate = I3C_BUS_I2C_FM_SCL_MAX_RATE; 3940 } 3941 3942 ret = i3c_bus_set_mode(i3cbus, mode, i2c_scl_rate); 3943 if (ret) 3944 goto err_put_dev; 3945 3946 master->wq = alloc_workqueue("%s", WQ_PERCPU | WQ_FREEZABLE, 0, dev_name(parent)); 3947 if (!master->wq) { 3948 ret = -ENOMEM; 3949 goto err_put_dev; 3950 } 3951 INIT_WORK(&master->hj_work, i3c_master_hj_work_fn); 3952 INIT_WORK(&master->reg_work, i3c_master_reg_work_fn); 3953 3954 ret = i3c_master_bus_init(master); 3955 if (ret) 3956 goto err_put_dev; 3957 3958 ret = device_add(&master->dev); 3959 if (ret) 3960 goto err_cleanup_bus; 3961 3962 /* 3963 * Expose our I3C bus as an I2C adapter so that I2C devices are exposed 3964 * through the I2C subsystem. 3965 */ 3966 ret = i3c_master_i2c_adapter_init(master); 3967 if (ret) 3968 goto err_del_dev; 3969 3970 i3c_bus_notify(i3cbus, I3C_NOTIFY_BUS_ADD); 3971 3972 pm_runtime_no_callbacks(&master->dev); 3973 pm_suspend_ignore_children(&master->dev, true); 3974 pm_runtime_enable(&master->dev); 3975 3976 /* 3977 * We're done initializing the bus and the controller, we can now 3978 * register I3C devices discovered during the initial DAA. Device 3979 * registration is done via reg_work because that keeps a single 3980 * registration code path and ensures the worker is the only writer 3981 * of desc->dev. Flush the work to preserve synchronous probe-time 3982 * behavior. 3983 */ 3984 master->init_done = true; 3985 queue_work(master->wq, &master->reg_work); 3986 flush_work(&master->reg_work); 3987 3988 if (master->ops->set_dev_nack_retry) 3989 device_create_file(&master->dev, &dev_attr_dev_nack_retry_count); 3990 3991 i3c_master_rpm_put(master); 3992 3993 return 0; 3994 3995 err_del_dev: 3996 device_del(&master->dev); 3997 3998 err_cleanup_bus: 3999 i3c_master_bus_cleanup(master); 4000 4001 err_put_dev: 4002 i3c_master_rpm_put(master); 4003 put_device(&master->dev); 4004 4005 return ret; 4006 } 4007 EXPORT_SYMBOL_GPL(i3c_master_register_fwnode); 4008 4009 /** 4010 * i3c_master_register() - register an I3C master 4011 * @master: master used to send frames on the bus 4012 * @parent: the parent device (the one that provides this I3C master 4013 * controller) 4014 * @ops: the master controller operations 4015 * @secondary: true if you are registering a secondary master. Will return 4016 * -EOPNOTSUPP if set to true since secondary masters are not yet 4017 * supported 4018 * 4019 * This function takes care of everything for you: 4020 * 4021 * - creates and initializes the I3C bus 4022 * - populates the bus with static I2C devs if @parent->of_node is not 4023 * NULL 4024 * - registers all I3C devices added by the controller during bus 4025 * initialization 4026 * - registers the I2C adapter and all I2C devices 4027 * 4028 * Return: 0 in case of success, a negative error code otherwise. 4029 */ 4030 int i3c_master_register(struct i3c_master_controller *master, 4031 struct device *parent, 4032 const struct i3c_master_controller_ops *ops, 4033 bool secondary) 4034 { 4035 return i3c_master_register_fwnode(master, parent, 4036 dev_fwnode(parent), 4037 ops, secondary); 4038 } 4039 EXPORT_SYMBOL_GPL(i3c_master_register); 4040 4041 /** 4042 * i3c_master_unregister() - unregister an I3C master 4043 * @master: master used to send frames on the bus 4044 * 4045 * Basically undo everything done in i3c_master_register(). 4046 */ 4047 void i3c_master_unregister(struct i3c_master_controller *master) 4048 { 4049 i3c_bus_notify(&master->bus, I3C_NOTIFY_BUS_REMOVE); 4050 i3c_master_shutdown(master); 4051 4052 if (master->ops->set_dev_nack_retry) 4053 device_remove_file(&master->dev, &dev_attr_dev_nack_retry_count); 4054 4055 i3c_master_i2c_adapter_cleanup(master); 4056 i3c_master_unregister_i3c_devs(master); 4057 i3c_master_bus_cleanup(master); 4058 pm_runtime_disable(&master->dev); 4059 device_unregister(&master->dev); 4060 } 4061 EXPORT_SYMBOL_GPL(i3c_master_unregister); 4062 4063 int i3c_dev_setdasa_locked(struct i3c_dev_desc *dev) 4064 { 4065 struct i3c_master_controller *master; 4066 4067 if (!dev) 4068 return -ENOENT; 4069 4070 master = i3c_dev_get_master(dev); 4071 if (!master) 4072 return -EINVAL; 4073 4074 if (!dev->boardinfo || !dev->boardinfo->init_dyn_addr || 4075 !dev->boardinfo->static_addr) 4076 return -EINVAL; 4077 4078 return i3c_master_setdasa_locked(master, dev->info.static_addr, 4079 dev->boardinfo->init_dyn_addr); 4080 } 4081 4082 int i3c_dev_do_xfers_locked(struct i3c_dev_desc *dev, struct i3c_xfer *xfers, 4083 int nxfers, enum i3c_xfer_mode mode) 4084 { 4085 struct i3c_master_controller *master; 4086 4087 if (!dev) 4088 return -ENOENT; 4089 4090 master = i3c_dev_get_master(dev); 4091 if (!master || !xfers) 4092 return -EINVAL; 4093 4094 if (mode != I3C_SDR && !(i3c_dev_supported_xfer_modes_locked(dev) & BIT(mode))) 4095 return -EOPNOTSUPP; 4096 4097 return master->ops->i3c_xfers(dev, xfers, nxfers, mode); 4098 } 4099 EXPORT_SYMBOL_GPL(i3c_dev_do_xfers_locked); 4100 4101 /** 4102 * i3c_dev_disable_ibi_controller_locked() - Disable IBI in the controller 4103 * @dev: I3C device descriptor 4104 * 4105 * Invoke the current controller's IBI disable callback without waiting for 4106 * pending IBIs or updating the generic IBI enabled state. 4107 * 4108 * Context: The caller must serialize access to @dev->ibi and the generic 4109 * IBI lifecycle. 4110 * 4111 * Return: 0 on success, or a negative error code. 4112 */ 4113 int i3c_dev_disable_ibi_controller_locked(struct i3c_dev_desc *dev) 4114 { 4115 struct i3c_master_controller *master = i3c_dev_get_master(dev); 4116 4117 if (!dev->ibi) 4118 return -EINVAL; 4119 4120 if (!master->ops->disable_ibi) 4121 return -EOPNOTSUPP; 4122 4123 return master->ops->disable_ibi(dev); 4124 } 4125 EXPORT_SYMBOL_GPL(i3c_dev_disable_ibi_controller_locked); 4126 4127 /** 4128 * i3c_dev_disable_ibi_locked() - Disable IBIs coming from a specific device 4129 * @dev: device on which IBIs should be disabled 4130 * 4131 * This function disable IBIs coming from a specific device and wait for 4132 * all pending IBIs to be processed. 4133 * 4134 * Context: Must be called with mutex_lock(&dev->desc->ibi_lock) held. 4135 * Return: 0 in case of success, a negative error core otherwise. 4136 */ 4137 int i3c_dev_disable_ibi_locked(struct i3c_dev_desc *dev) 4138 { 4139 int ret; 4140 4141 ret = i3c_dev_disable_ibi_controller_locked(dev); 4142 if (ret) 4143 return ret; 4144 4145 reinit_completion(&dev->ibi->all_ibis_handled); 4146 if (atomic_read(&dev->ibi->pending_ibis)) 4147 wait_for_completion(&dev->ibi->all_ibis_handled); 4148 4149 dev->ibi->enabled = false; 4150 4151 return 0; 4152 } 4153 EXPORT_SYMBOL_GPL(i3c_dev_disable_ibi_locked); 4154 4155 /** 4156 * i3c_dev_enable_ibi_controller_locked() - Enable controller IBI resources 4157 * @dev: I3C device descriptor 4158 * 4159 * Invoke the current controller's IBI enable callback without updating the 4160 * generic IBI enabled state. 4161 * 4162 * Context: The caller must serialize access to @dev->ibi and the generic 4163 * IBI lifecycle. 4164 * 4165 * Return: 0 on success, or a negative error code. 4166 */ 4167 int i3c_dev_enable_ibi_controller_locked(struct i3c_dev_desc *dev) 4168 { 4169 struct i3c_master_controller *master = i3c_dev_get_master(dev); 4170 4171 if (!dev->ibi) 4172 return -EINVAL; 4173 4174 if (!master->ops->enable_ibi) 4175 return -EOPNOTSUPP; 4176 4177 return master->ops->enable_ibi(dev); 4178 } 4179 EXPORT_SYMBOL_GPL(i3c_dev_enable_ibi_controller_locked); 4180 4181 /** 4182 * i3c_dev_enable_ibi_locked() - Enable IBIs from a specific device (lock held) 4183 * @dev: device on which IBIs should be enabled 4184 * 4185 * This function enable IBIs coming from a specific device and wait for 4186 * all pending IBIs to be processed. This should be called on a device 4187 * where i3c_device_request_ibi() has succeeded. 4188 * 4189 * Note that IBIs from this device might be received before this function 4190 * returns to its caller. 4191 * 4192 * Context: Must be called with mutex_lock(&dev->desc->ibi_lock) held. 4193 * Return: 0 on success, or a negative error code on failure. 4194 */ 4195 int i3c_dev_enable_ibi_locked(struct i3c_dev_desc *dev) 4196 { 4197 int ret; 4198 4199 ret = i3c_dev_enable_ibi_controller_locked(dev); 4200 if (!ret) 4201 dev->ibi->enabled = true; 4202 4203 return ret; 4204 } 4205 EXPORT_SYMBOL_GPL(i3c_dev_enable_ibi_locked); 4206 4207 /** 4208 * i3c_dev_request_ibi_controller_locked() - Request controller IBI resources 4209 * @dev: I3C device descriptor 4210 * @req: IBI setup request 4211 * 4212 * Invoke the current controller's IBI request callback without allocating the 4213 * generic IBI object or workqueue. The caller must ensure that @dev->ibi has 4214 * already been initialized. 4215 * 4216 * Context: The caller must serialize access to @dev->ibi and the generic 4217 * IBI lifecycle. 4218 * 4219 * Return: 0 on success, or a negative error code. 4220 */ 4221 int i3c_dev_request_ibi_controller_locked(struct i3c_dev_desc *dev, 4222 const struct i3c_ibi_setup *req) 4223 { 4224 struct i3c_master_controller *master = i3c_dev_get_master(dev); 4225 4226 if (!dev->ibi) 4227 return -EINVAL; 4228 4229 if (!master->ops->request_ibi) 4230 return -EOPNOTSUPP; 4231 4232 return master->ops->request_ibi(dev, req); 4233 } 4234 EXPORT_SYMBOL_GPL(i3c_dev_request_ibi_controller_locked); 4235 4236 /** 4237 * i3c_dev_request_ibi_locked() - Request an IBI 4238 * @dev: device for which we should enable IBIs 4239 * @req: setup requested for this IBI 4240 * 4241 * This function is responsible for pre-allocating all resources needed to 4242 * process IBIs coming from @dev. When this function returns, the IBI is not 4243 * enabled until i3c_device_enable_ibi() is called. 4244 * 4245 * Context: Must be called with mutex_lock(&dev->desc->ibi_lock) held. 4246 * Return: 0 in case of success, a negative error core otherwise. 4247 */ 4248 int i3c_dev_request_ibi_locked(struct i3c_dev_desc *dev, 4249 const struct i3c_ibi_setup *req) 4250 { 4251 struct i3c_master_controller *master = i3c_dev_get_master(dev); 4252 struct i3c_device_ibi_info *ibi; 4253 int ret; 4254 4255 if (!master->ops->request_ibi) 4256 return -EOPNOTSUPP; 4257 4258 if (dev->ibi) 4259 return -EBUSY; 4260 4261 ibi = kzalloc_obj(*ibi); 4262 if (!ibi) 4263 return -ENOMEM; 4264 4265 ibi->wq = alloc_ordered_workqueue(dev_name(i3cdev_to_dev(dev->dev)), 4266 WQ_MEM_RECLAIM | WQ_HIGHPRI); 4267 if (!ibi->wq) { 4268 kfree(ibi); 4269 return -ENOMEM; 4270 } 4271 4272 atomic_set(&ibi->pending_ibis, 0); 4273 init_completion(&ibi->all_ibis_handled); 4274 ibi->handler = req->handler; 4275 ibi->max_payload_len = req->max_payload_len; 4276 ibi->num_slots = req->num_slots; 4277 4278 dev->ibi = ibi; 4279 ret = i3c_dev_request_ibi_controller_locked(dev, req); 4280 if (ret) { 4281 /* 4282 * The controller request callback failed, so tear down the 4283 * workqueue allocated above before freeing the IBI object. 4284 * This is the owner of the workqueue, so it must destroy it 4285 * here to avoid leaking it on the error path. 4286 */ 4287 destroy_workqueue(ibi->wq); 4288 kfree(ibi); 4289 dev->ibi = NULL; 4290 } 4291 4292 return ret; 4293 } 4294 EXPORT_SYMBOL_GPL(i3c_dev_request_ibi_locked); 4295 4296 /** 4297 * i3c_dev_free_ibi_controller_locked() - Free controller IBI resources 4298 * @dev: I3C device descriptor 4299 * 4300 * Invoke the current controller's IBI free callback without destroying the 4301 * generic IBI workqueue or freeing @dev->ibi. 4302 * 4303 * Context: The caller must serialize access to @dev->ibi and the generic 4304 * IBI lifecycle. 4305 */ 4306 void i3c_dev_free_ibi_controller_locked(struct i3c_dev_desc *dev) 4307 { 4308 struct i3c_master_controller *master = i3c_dev_get_master(dev); 4309 4310 if (!dev->ibi) 4311 return; 4312 4313 master->ops->free_ibi(dev); 4314 } 4315 EXPORT_SYMBOL_GPL(i3c_dev_free_ibi_controller_locked); 4316 4317 /** 4318 * i3c_dev_free_ibi_locked() - Free all resources needed for IBI handling 4319 * @dev: device on which you want to release IBI resources 4320 * 4321 * This function is responsible for de-allocating resources previously 4322 * allocated by i3c_device_request_ibi(). It should be called after disabling 4323 * IBIs with i3c_device_disable_ibi(). 4324 * 4325 * Context: Must be called with mutex_lock(&dev->desc->ibi_lock) held. 4326 */ 4327 void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev) 4328 { 4329 struct i3c_master_controller *master = i3c_dev_get_master(dev); 4330 4331 if (!dev->ibi) 4332 return; 4333 4334 if (dev->ibi->enabled) { 4335 int ret; 4336 4337 dev_err(&master->dev, "Freeing IBI that is still enabled\n"); 4338 ret = i3c_master_rpm_get(master); 4339 if (!ret) { 4340 ret = i3c_dev_disable_ibi_locked(dev); 4341 i3c_master_rpm_put(master); 4342 } 4343 if (ret) 4344 dev_err(&master->dev, "Failed to disable IBI before freeing\n"); 4345 } 4346 4347 i3c_dev_free_ibi_controller_locked(dev); 4348 4349 if (dev->ibi->wq) { 4350 destroy_workqueue(dev->ibi->wq); 4351 dev->ibi->wq = NULL; 4352 } 4353 4354 kfree(dev->ibi); 4355 dev->ibi = NULL; 4356 } 4357 EXPORT_SYMBOL_GPL(i3c_dev_free_ibi_locked); 4358 4359 static int __init i3c_init(void) 4360 { 4361 int res; 4362 4363 res = of_alias_get_highest_id("i3c"); 4364 if (res >= 0) { 4365 mutex_lock(&i3c_core_lock); 4366 __i3c_first_dynamic_bus_num = res + 1; 4367 mutex_unlock(&i3c_core_lock); 4368 } 4369 4370 res = bus_register_notifier(&i2c_bus_type, &i2cdev_notifier); 4371 if (res) 4372 return res; 4373 4374 res = bus_register(&i3c_bus_type); 4375 if (res) 4376 goto out_unreg_notifier; 4377 4378 return 0; 4379 4380 out_unreg_notifier: 4381 bus_unregister_notifier(&i2c_bus_type, &i2cdev_notifier); 4382 4383 return res; 4384 } 4385 subsys_initcall(i3c_init); 4386 4387 static void __exit i3c_exit(void) 4388 { 4389 bus_unregister_notifier(&i2c_bus_type, &i2cdev_notifier); 4390 idr_destroy(&i3c_bus_idr); 4391 bus_unregister(&i3c_bus_type); 4392 } 4393 module_exit(i3c_exit); 4394 4395 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>"); 4396 MODULE_DESCRIPTION("I3C core"); 4397 MODULE_LICENSE("GPL v2"); 4398