1 /* 2 * Copyright (c) 2003-2015 Broadcom Corporation 3 * 4 * This file is licensed under the terms of the GNU General Public 5 * License version 2. This program is licensed "as is" without any 6 * warranty of any kind, whether express or implied. 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/i2c.h> 13 #include <linux/i2c-smbus.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/delay.h> 21 22 #define XLP9XX_I2C_DIV 0x0 23 #define XLP9XX_I2C_CTRL 0x1 24 #define XLP9XX_I2C_CMD 0x2 25 #define XLP9XX_I2C_STATUS 0x3 26 #define XLP9XX_I2C_MTXFIFO 0x4 27 #define XLP9XX_I2C_MRXFIFO 0x5 28 #define XLP9XX_I2C_MFIFOCTRL 0x6 29 #define XLP9XX_I2C_STXFIFO 0x7 30 #define XLP9XX_I2C_SRXFIFO 0x8 31 #define XLP9XX_I2C_SFIFOCTRL 0x9 32 #define XLP9XX_I2C_SLAVEADDR 0xA 33 #define XLP9XX_I2C_OWNADDR 0xB 34 #define XLP9XX_I2C_FIFOWCNT 0xC 35 #define XLP9XX_I2C_INTEN 0xD 36 #define XLP9XX_I2C_INTST 0xE 37 #define XLP9XX_I2C_WAITCNT 0xF 38 #define XLP9XX_I2C_TIMEOUT 0X10 39 #define XLP9XX_I2C_GENCALLADDR 0x11 40 41 #define XLP9XX_I2C_STATUS_BUSY BIT(0) 42 43 #define XLP9XX_I2C_CMD_START BIT(7) 44 #define XLP9XX_I2C_CMD_STOP BIT(6) 45 #define XLP9XX_I2C_CMD_READ BIT(5) 46 #define XLP9XX_I2C_CMD_WRITE BIT(4) 47 #define XLP9XX_I2C_CMD_ACK BIT(3) 48 49 #define XLP9XX_I2C_CTRL_MCTLEN_SHIFT 16 50 #define XLP9XX_I2C_CTRL_MCTLEN_MASK 0xffff0000 51 #define XLP9XX_I2C_CTRL_RST BIT(8) 52 #define XLP9XX_I2C_CTRL_EN BIT(6) 53 #define XLP9XX_I2C_CTRL_MASTER BIT(4) 54 #define XLP9XX_I2C_CTRL_FIFORD BIT(1) 55 #define XLP9XX_I2C_CTRL_ADDMODE BIT(0) 56 57 #define XLP9XX_I2C_INTEN_NACKADDR BIT(25) 58 #define XLP9XX_I2C_INTEN_SADDR BIT(13) 59 #define XLP9XX_I2C_INTEN_DATADONE BIT(12) 60 #define XLP9XX_I2C_INTEN_ARLOST BIT(11) 61 #define XLP9XX_I2C_INTEN_MFIFOFULL BIT(4) 62 #define XLP9XX_I2C_INTEN_MFIFOEMTY BIT(3) 63 #define XLP9XX_I2C_INTEN_MFIFOHI BIT(2) 64 #define XLP9XX_I2C_INTEN_BUSERR BIT(0) 65 66 #define XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT 8 67 #define XLP9XX_I2C_MFIFOCTRL_LOTH_SHIFT 0 68 #define XLP9XX_I2C_MFIFOCTRL_RST BIT(16) 69 70 #define XLP9XX_I2C_SLAVEADDR_RW BIT(0) 71 #define XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT 1 72 73 #define XLP9XX_I2C_IP_CLK_FREQ 133000000UL 74 #define XLP9XX_I2C_DEFAULT_FREQ 100000 75 #define XLP9XX_I2C_HIGH_FREQ 400000 76 #define XLP9XX_I2C_FIFO_SIZE 0x80U 77 #define XLP9XX_I2C_TIMEOUT_MS 1000 78 #define XLP9XX_I2C_BUSY_TIMEOUT 50 79 80 #define XLP9XX_I2C_FIFO_WCNT_MASK 0xff 81 #define XLP9XX_I2C_STATUS_ERRMASK (XLP9XX_I2C_INTEN_ARLOST | \ 82 XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_BUSERR) 83 84 struct xlp9xx_i2c_dev { 85 struct device *dev; 86 struct i2c_adapter adapter; 87 struct completion msg_complete; 88 struct i2c_smbus_alert_setup alert_data; 89 struct i2c_client *ara; 90 int irq; 91 bool msg_read; 92 bool len_recv; 93 bool client_pec; 94 u32 __iomem *base; 95 u32 msg_buf_remaining; 96 u32 msg_len; 97 u32 ip_clk_hz; 98 u32 clk_hz; 99 u32 msg_err; 100 u8 *msg_buf; 101 }; 102 103 static inline void xlp9xx_write_i2c_reg(struct xlp9xx_i2c_dev *priv, 104 unsigned long reg, u32 val) 105 { 106 writel(val, priv->base + reg); 107 } 108 109 static inline u32 xlp9xx_read_i2c_reg(struct xlp9xx_i2c_dev *priv, 110 unsigned long reg) 111 { 112 return readl(priv->base + reg); 113 } 114 115 static void xlp9xx_i2c_mask_irq(struct xlp9xx_i2c_dev *priv, u32 mask) 116 { 117 u32 inten; 118 119 inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) & ~mask; 120 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten); 121 } 122 123 static void xlp9xx_i2c_unmask_irq(struct xlp9xx_i2c_dev *priv, u32 mask) 124 { 125 u32 inten; 126 127 inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) | mask; 128 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten); 129 } 130 131 static void xlp9xx_i2c_update_rx_fifo_thres(struct xlp9xx_i2c_dev *priv) 132 { 133 u32 thres; 134 135 if (priv->len_recv) 136 /* interrupt after the first read to examine 137 * the length byte before proceeding further 138 */ 139 thres = 1; 140 else if (priv->msg_buf_remaining > XLP9XX_I2C_FIFO_SIZE) 141 thres = XLP9XX_I2C_FIFO_SIZE; 142 else 143 thres = priv->msg_buf_remaining; 144 145 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL, 146 thres << XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT); 147 } 148 149 static void xlp9xx_i2c_fill_tx_fifo(struct xlp9xx_i2c_dev *priv) 150 { 151 u32 len, i; 152 u8 *buf = priv->msg_buf; 153 154 len = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE); 155 for (i = 0; i < len; i++) 156 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MTXFIFO, buf[i]); 157 priv->msg_buf_remaining -= len; 158 priv->msg_buf += len; 159 } 160 161 static void xlp9xx_i2c_update_rlen(struct xlp9xx_i2c_dev *priv) 162 { 163 u32 val, len; 164 165 /* 166 * Update receive length. Re-read len to get the latest value, 167 * and then add 4 to have a minimum value that can be safely 168 * written. This is to account for the byte read above, the 169 * transfer in progress and any delays in the register I/O 170 */ 171 val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL); 172 len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) & 173 XLP9XX_I2C_FIFO_WCNT_MASK; 174 len = max_t(u32, priv->msg_len, len + 4); 175 if (len >= I2C_SMBUS_BLOCK_MAX + 2) 176 return; 177 val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) | 178 (len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT); 179 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val); 180 } 181 182 static void xlp9xx_i2c_drain_rx_fifo(struct xlp9xx_i2c_dev *priv) 183 { 184 u32 len, i; 185 u8 rlen, *buf = priv->msg_buf; 186 187 len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) & 188 XLP9XX_I2C_FIFO_WCNT_MASK; 189 if (!len) 190 return; 191 if (priv->len_recv) { 192 /* read length byte */ 193 rlen = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO); 194 if (rlen > I2C_SMBUS_BLOCK_MAX || rlen == 0) { 195 rlen = 0; /*abort transfer */ 196 priv->msg_buf_remaining = 0; 197 priv->msg_len = 0; 198 } else { 199 *buf++ = rlen; 200 if (priv->client_pec) 201 ++rlen; /* account for error check byte */ 202 /* update remaining bytes and message length */ 203 priv->msg_buf_remaining = rlen; 204 priv->msg_len = rlen + 1; 205 } 206 xlp9xx_i2c_update_rlen(priv); 207 priv->len_recv = false; 208 } else { 209 len = min(priv->msg_buf_remaining, len); 210 for (i = 0; i < len; i++, buf++) 211 *buf = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO); 212 213 priv->msg_buf_remaining -= len; 214 } 215 216 priv->msg_buf = buf; 217 218 if (priv->msg_buf_remaining) 219 xlp9xx_i2c_update_rx_fifo_thres(priv); 220 } 221 222 static irqreturn_t xlp9xx_i2c_isr(int irq, void *dev_id) 223 { 224 struct xlp9xx_i2c_dev *priv = dev_id; 225 u32 status; 226 227 status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTST); 228 if (status == 0) 229 return IRQ_NONE; 230 231 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTST, status); 232 if (status & XLP9XX_I2C_STATUS_ERRMASK) { 233 priv->msg_err = status; 234 goto xfer_done; 235 } 236 237 /* SADDR ACK for SMBUS_QUICK */ 238 if ((status & XLP9XX_I2C_INTEN_SADDR) && (priv->msg_len == 0)) 239 goto xfer_done; 240 241 if (!priv->msg_read) { 242 if (status & XLP9XX_I2C_INTEN_MFIFOEMTY) { 243 /* TX FIFO got empty, fill it up again */ 244 if (priv->msg_buf_remaining) 245 xlp9xx_i2c_fill_tx_fifo(priv); 246 else 247 xlp9xx_i2c_mask_irq(priv, 248 XLP9XX_I2C_INTEN_MFIFOEMTY); 249 } 250 } else { 251 if (status & (XLP9XX_I2C_INTEN_DATADONE | 252 XLP9XX_I2C_INTEN_MFIFOHI)) { 253 /* data is in FIFO, read it */ 254 if (priv->msg_buf_remaining) 255 xlp9xx_i2c_drain_rx_fifo(priv); 256 } 257 } 258 259 /* Transfer complete */ 260 if (status & XLP9XX_I2C_INTEN_DATADONE) 261 goto xfer_done; 262 263 return IRQ_HANDLED; 264 265 xfer_done: 266 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0); 267 complete(&priv->msg_complete); 268 return IRQ_HANDLED; 269 } 270 271 static int xlp9xx_i2c_check_bus_status(struct xlp9xx_i2c_dev *priv) 272 { 273 u32 status; 274 u32 busy_timeout = XLP9XX_I2C_BUSY_TIMEOUT; 275 276 while (busy_timeout) { 277 status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_STATUS); 278 if ((status & XLP9XX_I2C_STATUS_BUSY) == 0) 279 break; 280 281 busy_timeout--; 282 usleep_range(1000, 1100); 283 } 284 285 if (!busy_timeout) 286 return -EIO; 287 288 return 0; 289 } 290 291 static int xlp9xx_i2c_init(struct xlp9xx_i2c_dev *priv) 292 { 293 u32 prescale; 294 295 /* 296 * The controller uses 5 * SCL clock internally. 297 * So prescale value should be divided by 5. 298 */ 299 prescale = DIV_ROUND_UP(priv->ip_clk_hz, priv->clk_hz); 300 prescale = ((prescale - 8) / 5) - 1; 301 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_RST); 302 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_EN | 303 XLP9XX_I2C_CTRL_MASTER); 304 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_DIV, prescale); 305 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0); 306 307 return 0; 308 } 309 310 static int xlp9xx_i2c_xfer_msg(struct xlp9xx_i2c_dev *priv, struct i2c_msg *msg, 311 int last_msg) 312 { 313 unsigned long timeleft; 314 u32 intr_mask, cmd, val, len; 315 316 priv->msg_buf = msg->buf; 317 priv->msg_buf_remaining = priv->msg_len = msg->len; 318 priv->msg_err = 0; 319 priv->msg_read = (msg->flags & I2C_M_RD); 320 reinit_completion(&priv->msg_complete); 321 322 /* Reset FIFO */ 323 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL, 324 XLP9XX_I2C_MFIFOCTRL_RST); 325 326 /* set slave addr */ 327 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_SLAVEADDR, 328 (msg->addr << XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT) | 329 (priv->msg_read ? XLP9XX_I2C_SLAVEADDR_RW : 0)); 330 331 /* Build control word for transfer */ 332 val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL); 333 if (!priv->msg_read) 334 val &= ~XLP9XX_I2C_CTRL_FIFORD; 335 else 336 val |= XLP9XX_I2C_CTRL_FIFORD; /* read */ 337 338 if (msg->flags & I2C_M_TEN) 339 val |= XLP9XX_I2C_CTRL_ADDMODE; /* 10-bit address mode*/ 340 else 341 val &= ~XLP9XX_I2C_CTRL_ADDMODE; 342 343 priv->len_recv = msg->flags & I2C_M_RECV_LEN; 344 len = priv->len_recv ? I2C_SMBUS_BLOCK_MAX + 2 : msg->len; 345 priv->client_pec = msg->flags & I2C_CLIENT_PEC; 346 347 /* set FIFO threshold if reading */ 348 if (priv->msg_read) 349 xlp9xx_i2c_update_rx_fifo_thres(priv); 350 351 /* set data length to be transferred */ 352 val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) | 353 (len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT); 354 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val); 355 356 /* fill fifo during tx */ 357 if (!priv->msg_read) 358 xlp9xx_i2c_fill_tx_fifo(priv); 359 360 /* set interrupt mask */ 361 intr_mask = (XLP9XX_I2C_INTEN_ARLOST | XLP9XX_I2C_INTEN_BUSERR | 362 XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_DATADONE); 363 364 if (priv->msg_read) { 365 intr_mask |= XLP9XX_I2C_INTEN_MFIFOHI; 366 if (msg->len == 0) 367 intr_mask |= XLP9XX_I2C_INTEN_SADDR; 368 } else { 369 if (msg->len == 0) 370 intr_mask |= XLP9XX_I2C_INTEN_SADDR; 371 else 372 intr_mask |= XLP9XX_I2C_INTEN_MFIFOEMTY; 373 } 374 xlp9xx_i2c_unmask_irq(priv, intr_mask); 375 376 /* set cmd reg */ 377 cmd = XLP9XX_I2C_CMD_START; 378 if (msg->len) 379 cmd |= (priv->msg_read ? 380 XLP9XX_I2C_CMD_READ : XLP9XX_I2C_CMD_WRITE); 381 if (last_msg) 382 cmd |= XLP9XX_I2C_CMD_STOP; 383 384 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, cmd); 385 386 timeleft = msecs_to_jiffies(XLP9XX_I2C_TIMEOUT_MS); 387 timeleft = wait_for_completion_timeout(&priv->msg_complete, timeleft); 388 389 if (priv->msg_err & XLP9XX_I2C_INTEN_BUSERR) { 390 dev_dbg(priv->dev, "transfer error %x!\n", priv->msg_err); 391 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, XLP9XX_I2C_CMD_STOP); 392 return -EIO; 393 } else if (priv->msg_err & XLP9XX_I2C_INTEN_NACKADDR) { 394 return -ENXIO; 395 } 396 397 if (timeleft == 0) { 398 dev_dbg(priv->dev, "i2c transfer timed out!\n"); 399 xlp9xx_i2c_init(priv); 400 return -ETIMEDOUT; 401 } 402 403 /* update msg->len with actual received length */ 404 if (msg->flags & I2C_M_RECV_LEN) { 405 if (!priv->msg_len) 406 return -EPROTO; 407 msg->len = priv->msg_len; 408 } 409 return 0; 410 } 411 412 static int xlp9xx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 413 int num) 414 { 415 int i, ret; 416 struct xlp9xx_i2c_dev *priv = i2c_get_adapdata(adap); 417 418 ret = xlp9xx_i2c_check_bus_status(priv); 419 if (ret) { 420 xlp9xx_i2c_init(priv); 421 ret = xlp9xx_i2c_check_bus_status(priv); 422 if (ret) 423 return ret; 424 } 425 426 for (i = 0; i < num; i++) { 427 ret = xlp9xx_i2c_xfer_msg(priv, &msgs[i], i == num - 1); 428 if (ret != 0) 429 return ret; 430 } 431 432 return num; 433 } 434 435 static u32 xlp9xx_i2c_functionality(struct i2c_adapter *adapter) 436 { 437 return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_READ_BLOCK_DATA | 438 I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR; 439 } 440 441 static const struct i2c_algorithm xlp9xx_i2c_algo = { 442 .master_xfer = xlp9xx_i2c_xfer, 443 .functionality = xlp9xx_i2c_functionality, 444 }; 445 446 static int xlp9xx_i2c_get_frequency(struct platform_device *pdev, 447 struct xlp9xx_i2c_dev *priv) 448 { 449 struct clk *clk; 450 u32 freq; 451 int err; 452 453 clk = devm_clk_get(&pdev->dev, NULL); 454 if (IS_ERR(clk)) { 455 priv->ip_clk_hz = XLP9XX_I2C_IP_CLK_FREQ; 456 dev_dbg(&pdev->dev, "using default input frequency %u\n", 457 priv->ip_clk_hz); 458 } else { 459 priv->ip_clk_hz = clk_get_rate(clk); 460 } 461 462 err = device_property_read_u32(&pdev->dev, "clock-frequency", &freq); 463 if (err) { 464 freq = XLP9XX_I2C_DEFAULT_FREQ; 465 dev_dbg(&pdev->dev, "using default frequency %u\n", freq); 466 } else if (freq == 0 || freq > XLP9XX_I2C_HIGH_FREQ) { 467 dev_warn(&pdev->dev, "invalid frequency %u, using default\n", 468 freq); 469 freq = XLP9XX_I2C_DEFAULT_FREQ; 470 } 471 priv->clk_hz = freq; 472 473 return 0; 474 } 475 476 static int xlp9xx_i2c_smbus_setup(struct xlp9xx_i2c_dev *priv, 477 struct platform_device *pdev) 478 { 479 if (!priv->alert_data.irq) 480 return -EINVAL; 481 482 priv->ara = i2c_setup_smbus_alert(&priv->adapter, &priv->alert_data); 483 if (!priv->ara) 484 return -ENODEV; 485 486 return 0; 487 } 488 489 static int xlp9xx_i2c_probe(struct platform_device *pdev) 490 { 491 struct xlp9xx_i2c_dev *priv; 492 struct resource *res; 493 int err = 0; 494 495 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 496 if (!priv) 497 return -ENOMEM; 498 499 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 500 priv->base = devm_ioremap_resource(&pdev->dev, res); 501 if (IS_ERR(priv->base)) 502 return PTR_ERR(priv->base); 503 504 priv->irq = platform_get_irq(pdev, 0); 505 if (priv->irq <= 0) { 506 dev_err(&pdev->dev, "invalid irq!\n"); 507 return priv->irq; 508 } 509 /* SMBAlert irq */ 510 priv->alert_data.irq = platform_get_irq(pdev, 1); 511 if (priv->alert_data.irq <= 0) 512 priv->alert_data.irq = 0; 513 514 xlp9xx_i2c_get_frequency(pdev, priv); 515 xlp9xx_i2c_init(priv); 516 517 err = devm_request_irq(&pdev->dev, priv->irq, xlp9xx_i2c_isr, 0, 518 pdev->name, priv); 519 if (err) { 520 dev_err(&pdev->dev, "IRQ request failed!\n"); 521 return err; 522 } 523 524 init_completion(&priv->msg_complete); 525 priv->adapter.dev.parent = &pdev->dev; 526 priv->adapter.algo = &xlp9xx_i2c_algo; 527 priv->adapter.class = I2C_CLASS_HWMON; 528 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev)); 529 priv->adapter.dev.of_node = pdev->dev.of_node; 530 priv->dev = &pdev->dev; 531 532 snprintf(priv->adapter.name, sizeof(priv->adapter.name), "xlp9xx-i2c"); 533 i2c_set_adapdata(&priv->adapter, priv); 534 535 err = i2c_add_adapter(&priv->adapter); 536 if (err) 537 return err; 538 539 err = xlp9xx_i2c_smbus_setup(priv, pdev); 540 if (err) 541 dev_dbg(&pdev->dev, "No active SMBus alert %d\n", err); 542 543 platform_set_drvdata(pdev, priv); 544 dev_dbg(&pdev->dev, "I2C bus:%d added\n", priv->adapter.nr); 545 546 return 0; 547 } 548 549 static int xlp9xx_i2c_remove(struct platform_device *pdev) 550 { 551 struct xlp9xx_i2c_dev *priv; 552 553 priv = platform_get_drvdata(pdev); 554 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0); 555 synchronize_irq(priv->irq); 556 i2c_del_adapter(&priv->adapter); 557 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, 0); 558 559 return 0; 560 } 561 562 static const struct of_device_id xlp9xx_i2c_of_match[] = { 563 { .compatible = "netlogic,xlp980-i2c", }, 564 { /* sentinel */ }, 565 }; 566 MODULE_DEVICE_TABLE(of, xlp9xx_i2c_of_match); 567 568 #ifdef CONFIG_ACPI 569 static const struct acpi_device_id xlp9xx_i2c_acpi_ids[] = { 570 {"BRCM9007", 0}, 571 {"CAV9007", 0}, 572 {} 573 }; 574 MODULE_DEVICE_TABLE(acpi, xlp9xx_i2c_acpi_ids); 575 #endif 576 577 static struct platform_driver xlp9xx_i2c_driver = { 578 .probe = xlp9xx_i2c_probe, 579 .remove = xlp9xx_i2c_remove, 580 .driver = { 581 .name = "xlp9xx-i2c", 582 .of_match_table = xlp9xx_i2c_of_match, 583 .acpi_match_table = ACPI_PTR(xlp9xx_i2c_acpi_ids), 584 }, 585 }; 586 587 module_platform_driver(xlp9xx_i2c_driver); 588 589 MODULE_AUTHOR("Subhendu Sekhar Behera <sbehera@broadcom.com>"); 590 MODULE_DESCRIPTION("XLP9XX/5XX I2C Bus Controller Driver"); 591 MODULE_LICENSE("GPL v2"); 592