1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright(c) 2024 Shanghai Zhaoxin Semiconductor Corporation. 4 * All rights reserved. 5 */ 6 7 #include <linux/acpi.h> 8 #include "i2c-viai2c-common.h" 9 10 /* 11 * registers 12 */ 13 /* Zhaoxin specific register bit fields */ 14 /* REG_CR Bit fields */ 15 #define ZXI2C_CR_MST_RST BIT(7) 16 #define ZXI2C_CR_FIFO_MODE BIT(14) 17 /* REG_ISR/IMR Bit fields */ 18 #define ZXI2C_IRQ_FIFONACK BIT(4) 19 #define ZXI2C_IRQ_FIFOEND BIT(3) 20 #define ZXI2C_IRQ_MASK (VIAI2C_ISR_MASK_ALL \ 21 | ZXI2C_IRQ_FIFOEND \ 22 | ZXI2C_IRQ_FIFONACK) 23 /* Zhaoxin specific registers */ 24 #define ZXI2C_REG_CLK 0x10 25 #define ZXI2C_CLK_50M BIT(0) 26 #define ZXI2C_REG_REV 0x11 27 #define ZXI2C_REG_HCR 0x12 28 #define ZXI2C_HCR_RST_FIFO GENMASK(1, 0) 29 #define ZXI2C_REG_HTDR 0x13 30 #define ZXI2C_REG_HRDR 0x14 31 #define ZXI2C_REG_HTLR 0x15 32 #define ZXI2C_REG_HRLR 0x16 33 #define ZXI2C_REG_HWCNTR 0x18 34 #define ZXI2C_REG_HRCNTR 0x19 35 36 /* parameters Constants */ 37 #define ZXI2C_GOLD_FSTP_100K 0xF3 38 #define ZXI2C_GOLD_FSTP_400K 0x38 39 #define ZXI2C_GOLD_FSTP_1M 0x13 40 #define ZXI2C_GOLD_FSTP_3400K 0x37 41 #define ZXI2C_HS_MASTER_CODE (0x08 << 8) 42 43 #define ZXI2C_FIFO_SIZE 32 44 45 struct viai2c_zhaoxin { 46 u8 hrv; 47 u16 tr; 48 u16 mcr; 49 u16 xfer_len; 50 }; 51 52 /* 'irq == true' means in interrupt context */ 53 int viai2c_fifo_irq_xfer(struct viai2c *i2c, bool irq) 54 { 55 u16 i; 56 u8 tmp; 57 struct i2c_msg *msg = i2c->msg; 58 void __iomem *base = i2c->base; 59 bool read = !!(msg->flags & I2C_M_RD); 60 struct viai2c_zhaoxin *priv = i2c->pltfm_priv; 61 62 if (irq) { 63 /* get the received data */ 64 if (read) 65 for (i = 0; i < priv->xfer_len; i++) 66 msg->buf[i2c->xfered_len + i] = ioread8(base + ZXI2C_REG_HRDR); 67 68 i2c->xfered_len += priv->xfer_len; 69 if (i2c->xfered_len == msg->len) 70 return 1; 71 } 72 73 /* reset fifo buffer */ 74 tmp = ioread8(base + ZXI2C_REG_HCR); 75 iowrite8(tmp | ZXI2C_HCR_RST_FIFO, base + ZXI2C_REG_HCR); 76 77 /* set xfer len */ 78 priv->xfer_len = min_t(u16, msg->len - i2c->xfered_len, ZXI2C_FIFO_SIZE); 79 if (read) { 80 iowrite8(priv->xfer_len - 1, base + ZXI2C_REG_HRLR); 81 } else { 82 iowrite8(priv->xfer_len - 1, base + ZXI2C_REG_HTLR); 83 /* set write data */ 84 for (i = 0; i < priv->xfer_len; i++) 85 iowrite8(msg->buf[i2c->xfered_len + i], base + ZXI2C_REG_HTDR); 86 } 87 88 /* prepare to stop transmission */ 89 if (priv->hrv && msg->len == (i2c->xfered_len + priv->xfer_len)) { 90 tmp = ioread8(base + VIAI2C_REG_CR); 91 tmp |= read ? VIAI2C_CR_RX_END : VIAI2C_CR_TX_END; 92 iowrite8(tmp, base + VIAI2C_REG_CR); 93 } 94 95 if (irq) { 96 /* continue transmission */ 97 tmp = ioread8(base + VIAI2C_REG_CR); 98 iowrite8(tmp |= VIAI2C_CR_CPU_RDY, base + VIAI2C_REG_CR); 99 } else { 100 u16 tcr_val = i2c->tcr; 101 102 /* start transmission */ 103 tcr_val |= read ? VIAI2C_TCR_READ : 0; 104 writew(tcr_val | msg->addr, base + VIAI2C_REG_TCR); 105 } 106 107 return 0; 108 } 109 110 static int zxi2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 111 { 112 u8 tmp; 113 int ret; 114 struct viai2c *i2c = (struct viai2c *)i2c_get_adapdata(adap); 115 struct viai2c_zhaoxin *priv = i2c->pltfm_priv; 116 void __iomem *base = i2c->base; 117 118 ret = viai2c_wait_bus_not_busy(i2c); 119 if (ret) 120 return ret; 121 122 tmp = ioread8(base + VIAI2C_REG_CR); 123 tmp &= ~(VIAI2C_CR_RX_END | VIAI2C_CR_TX_END); 124 125 if (num == 1 && msgs->len >= 2 && (priv->hrv || msgs->len <= ZXI2C_FIFO_SIZE)) { 126 /* enable fifo mode */ 127 iowrite16(ZXI2C_CR_FIFO_MODE | tmp, base + VIAI2C_REG_CR); 128 /* clear irq status */ 129 iowrite8(ZXI2C_IRQ_MASK, base + VIAI2C_REG_ISR); 130 /* enable fifo irq */ 131 iowrite8(VIAI2C_ISR_NACK_ADDR | ZXI2C_IRQ_FIFOEND, base + VIAI2C_REG_IMR); 132 133 i2c->msg = msgs; 134 i2c->mode = VIAI2C_FIFO_MODE; 135 priv->xfer_len = 0; 136 i2c->xfered_len = 0; 137 138 viai2c_fifo_irq_xfer(i2c, 0); 139 140 if (!wait_for_completion_timeout(&i2c->complete, VIAI2C_TIMEOUT)) 141 return -ETIMEDOUT; 142 143 ret = i2c->ret; 144 } else { 145 /* enable byte mode */ 146 iowrite16(tmp, base + VIAI2C_REG_CR); 147 /* clear irq status */ 148 iowrite8(ZXI2C_IRQ_MASK, base + VIAI2C_REG_ISR); 149 /* enable byte irq */ 150 iowrite8(VIAI2C_ISR_NACK_ADDR | VIAI2C_IMR_BYTE, base + VIAI2C_REG_IMR); 151 152 ret = viai2c_xfer(adap, msgs, num); 153 if (ret == -ETIMEDOUT) 154 iowrite16(tmp | VIAI2C_CR_END_MASK, base + VIAI2C_REG_CR); 155 } 156 /* dis interrupt */ 157 iowrite8(0, base + VIAI2C_REG_IMR); 158 159 return ret; 160 } 161 162 static u32 zxi2c_func(struct i2c_adapter *adap) 163 { 164 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 165 } 166 167 static const struct i2c_algorithm zxi2c_algorithm = { 168 .master_xfer = zxi2c_master_xfer, 169 .functionality = zxi2c_func, 170 }; 171 172 static const struct i2c_adapter_quirks zxi2c_quirks = { 173 .flags = I2C_AQ_NO_ZERO_LEN | I2C_AQ_COMB_WRITE_THEN_READ, 174 }; 175 176 static const u32 zxi2c_speed_params_table[][3] = { 177 /* speed, ZXI2C_TCR, ZXI2C_FSTP */ 178 { I2C_MAX_STANDARD_MODE_FREQ, 0, ZXI2C_GOLD_FSTP_100K }, 179 { I2C_MAX_FAST_MODE_FREQ, VIAI2C_TCR_FAST, ZXI2C_GOLD_FSTP_400K }, 180 { I2C_MAX_FAST_MODE_PLUS_FREQ, VIAI2C_TCR_FAST, ZXI2C_GOLD_FSTP_1M }, 181 { I2C_MAX_HIGH_SPEED_MODE_FREQ, VIAI2C_TCR_HS_MODE | VIAI2C_TCR_FAST, 182 ZXI2C_GOLD_FSTP_3400K }, 183 }; 184 185 static void zxi2c_set_bus_speed(struct viai2c *i2c) 186 { 187 struct viai2c_zhaoxin *priv = i2c->pltfm_priv; 188 189 iowrite16(priv->tr, i2c->base + VIAI2C_REG_TR); 190 iowrite8(ZXI2C_CLK_50M, i2c->base + ZXI2C_REG_CLK); 191 iowrite16(priv->mcr, i2c->base + VIAI2C_REG_MCR); 192 } 193 194 static void zxi2c_get_bus_speed(struct viai2c *i2c) 195 { 196 u8 i, count; 197 u8 fstp; 198 const u32 *params; 199 struct viai2c_zhaoxin *priv = i2c->pltfm_priv; 200 u32 acpi_speed = i2c_acpi_find_bus_speed(i2c->dev); 201 202 count = ARRAY_SIZE(zxi2c_speed_params_table); 203 for (i = 0; i < count; i++) 204 if (acpi_speed == zxi2c_speed_params_table[i][0]) 205 break; 206 /* if not found, use 400k as default */ 207 i = i < count ? i : 1; 208 209 params = zxi2c_speed_params_table[i]; 210 fstp = ioread8(i2c->base + VIAI2C_REG_TR); 211 if (abs(fstp - params[2]) > 0x10) { 212 /* 213 * if BIOS setting value far from golden value, 214 * use golden value and warn user 215 */ 216 dev_warn(i2c->dev, "FW FSTP[%x] might cause wrong timings, dropped\n", fstp); 217 priv->tr = params[2] | 0xff00; 218 } else { 219 priv->tr = fstp | 0xff00; 220 } 221 222 i2c->tcr = params[1]; 223 priv->mcr = ioread16(i2c->base + VIAI2C_REG_MCR); 224 /* for Hs-mode, use 0x80 as master code */ 225 if (params[0] == I2C_MAX_HIGH_SPEED_MODE_FREQ) 226 priv->mcr |= ZXI2C_HS_MASTER_CODE; 227 228 dev_info(i2c->dev, "speed mode is %s\n", i2c_freq_mode_string(params[0])); 229 } 230 231 static int zxi2c_probe(struct platform_device *pdev) 232 { 233 int error; 234 struct viai2c *i2c; 235 struct i2c_adapter *adap; 236 struct viai2c_zhaoxin *priv; 237 238 error = viai2c_init(pdev, &i2c, VIAI2C_PLAT_ZHAOXIN); 239 if (error) 240 return error; 241 242 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 243 if (!priv) 244 return -ENOMEM; 245 i2c->pltfm_priv = priv; 246 247 zxi2c_get_bus_speed(i2c); 248 zxi2c_set_bus_speed(i2c); 249 250 priv->hrv = ioread8(i2c->base + ZXI2C_REG_REV); 251 252 adap = &i2c->adapter; 253 adap->owner = THIS_MODULE; 254 adap->algo = &zxi2c_algorithm; 255 adap->quirks = &zxi2c_quirks; 256 adap->dev.parent = &pdev->dev; 257 ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev)); 258 snprintf(adap->name, sizeof(adap->name), "zhaoxin-%s-%s", 259 dev_name(pdev->dev.parent), dev_name(i2c->dev)); 260 i2c_set_adapdata(adap, i2c); 261 262 return devm_i2c_add_adapter(&pdev->dev, adap); 263 } 264 265 static int __maybe_unused zxi2c_resume(struct device *dev) 266 { 267 struct viai2c *i2c = dev_get_drvdata(dev); 268 269 iowrite8(ZXI2C_CR_MST_RST, i2c->base + VIAI2C_REG_CR); 270 zxi2c_set_bus_speed(i2c); 271 272 return 0; 273 } 274 275 static const struct dev_pm_ops zxi2c_pm = { 276 SET_SYSTEM_SLEEP_PM_OPS(NULL, zxi2c_resume) 277 }; 278 279 static const struct acpi_device_id zxi2c_acpi_match[] = { 280 {"IIC1D17", 0 }, 281 { } 282 }; 283 MODULE_DEVICE_TABLE(acpi, zxi2c_acpi_match); 284 285 static struct platform_driver zxi2c_driver = { 286 .probe = zxi2c_probe, 287 .driver = { 288 .name = "i2c_zhaoxin", 289 .acpi_match_table = zxi2c_acpi_match, 290 .pm = &zxi2c_pm, 291 }, 292 }; 293 294 module_platform_driver(zxi2c_driver); 295 296 MODULE_AUTHOR("HansHu@zhaoxin.com"); 297 MODULE_DESCRIPTION("Shanghai Zhaoxin IIC driver"); 298 MODULE_LICENSE("GPL"); 299