1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/i2c.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 13 #define UNIPHIER_I2C_DTRM 0x00 /* TX register */ 14 #define UNIPHIER_I2C_DTRM_IRQEN BIT(11) /* enable interrupt */ 15 #define UNIPHIER_I2C_DTRM_STA BIT(10) /* start condition */ 16 #define UNIPHIER_I2C_DTRM_STO BIT(9) /* stop condition */ 17 #define UNIPHIER_I2C_DTRM_NACK BIT(8) /* do not return ACK */ 18 #define UNIPHIER_I2C_DTRM_RD BIT(0) /* read transaction */ 19 #define UNIPHIER_I2C_DREC 0x04 /* RX register */ 20 #define UNIPHIER_I2C_DREC_MST BIT(14) /* 1 = master, 0 = slave */ 21 #define UNIPHIER_I2C_DREC_TX BIT(13) /* 1 = transmit, 0 = receive */ 22 #define UNIPHIER_I2C_DREC_STS BIT(12) /* stop condition detected */ 23 #define UNIPHIER_I2C_DREC_LRB BIT(11) /* no ACK */ 24 #define UNIPHIER_I2C_DREC_LAB BIT(9) /* arbitration lost */ 25 #define UNIPHIER_I2C_DREC_BBN BIT(8) /* bus not busy */ 26 #define UNIPHIER_I2C_MYAD 0x08 /* slave address */ 27 #define UNIPHIER_I2C_CLK 0x0c /* clock frequency control */ 28 #define UNIPHIER_I2C_BRST 0x10 /* bus reset */ 29 #define UNIPHIER_I2C_BRST_FOEN BIT(1) /* normal operation */ 30 #define UNIPHIER_I2C_BRST_RSCL BIT(0) /* release SCL */ 31 #define UNIPHIER_I2C_HOLD 0x14 /* hold time control */ 32 #define UNIPHIER_I2C_BSTS 0x18 /* bus status monitor */ 33 #define UNIPHIER_I2C_BSTS_SDA BIT(1) /* readback of SDA line */ 34 #define UNIPHIER_I2C_BSTS_SCL BIT(0) /* readback of SCL line */ 35 #define UNIPHIER_I2C_NOISE 0x1c /* noise filter control */ 36 #define UNIPHIER_I2C_SETUP 0x20 /* setup time control */ 37 38 struct uniphier_i2c_priv { 39 struct completion comp; 40 struct i2c_adapter adap; 41 void __iomem *membase; 42 struct clk *clk; 43 unsigned int busy_cnt; 44 unsigned int clk_cycle; 45 }; 46 47 static irqreturn_t uniphier_i2c_interrupt(int irq, void *dev_id) 48 { 49 struct uniphier_i2c_priv *priv = dev_id; 50 51 /* 52 * This hardware uses edge triggered interrupt. Do not touch the 53 * hardware registers in this handler to make sure to catch the next 54 * interrupt edge. Just send a complete signal and return. 55 */ 56 complete(&priv->comp); 57 58 return IRQ_HANDLED; 59 } 60 61 static int uniphier_i2c_xfer_byte(struct i2c_adapter *adap, u32 txdata, 62 u32 *rxdatap) 63 { 64 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap); 65 unsigned long time_left; 66 u32 rxdata; 67 68 reinit_completion(&priv->comp); 69 70 txdata |= UNIPHIER_I2C_DTRM_IRQEN; 71 writel(txdata, priv->membase + UNIPHIER_I2C_DTRM); 72 73 time_left = wait_for_completion_timeout(&priv->comp, adap->timeout); 74 if (unlikely(!time_left)) { 75 dev_err(&adap->dev, "transaction timeout\n"); 76 return -ETIMEDOUT; 77 } 78 79 rxdata = readl(priv->membase + UNIPHIER_I2C_DREC); 80 if (rxdatap) 81 *rxdatap = rxdata; 82 83 return 0; 84 } 85 86 static int uniphier_i2c_send_byte(struct i2c_adapter *adap, u32 txdata) 87 { 88 u32 rxdata; 89 int ret; 90 91 ret = uniphier_i2c_xfer_byte(adap, txdata, &rxdata); 92 if (ret) 93 return ret; 94 95 if (unlikely(rxdata & UNIPHIER_I2C_DREC_LAB)) 96 return -EAGAIN; 97 98 if (unlikely(rxdata & UNIPHIER_I2C_DREC_LRB)) 99 return -ENXIO; 100 101 return 0; 102 } 103 104 static int uniphier_i2c_tx(struct i2c_adapter *adap, u16 addr, u16 len, 105 const u8 *buf) 106 { 107 int ret; 108 109 ret = uniphier_i2c_send_byte(adap, addr << 1 | 110 UNIPHIER_I2C_DTRM_STA | 111 UNIPHIER_I2C_DTRM_NACK); 112 if (ret) 113 return ret; 114 115 while (len--) { 116 ret = uniphier_i2c_send_byte(adap, 117 UNIPHIER_I2C_DTRM_NACK | *buf++); 118 if (ret) 119 return ret; 120 } 121 122 return 0; 123 } 124 125 static int uniphier_i2c_rx(struct i2c_adapter *adap, u16 addr, u16 len, 126 u8 *buf) 127 { 128 int ret; 129 130 ret = uniphier_i2c_send_byte(adap, addr << 1 | 131 UNIPHIER_I2C_DTRM_STA | 132 UNIPHIER_I2C_DTRM_NACK | 133 UNIPHIER_I2C_DTRM_RD); 134 if (ret) 135 return ret; 136 137 while (len--) { 138 u32 rxdata; 139 140 ret = uniphier_i2c_xfer_byte(adap, 141 len ? 0 : UNIPHIER_I2C_DTRM_NACK, 142 &rxdata); 143 if (ret) 144 return ret; 145 *buf++ = rxdata; 146 } 147 148 return 0; 149 } 150 151 static int uniphier_i2c_stop(struct i2c_adapter *adap) 152 { 153 return uniphier_i2c_send_byte(adap, UNIPHIER_I2C_DTRM_STO | 154 UNIPHIER_I2C_DTRM_NACK); 155 } 156 157 static int uniphier_i2c_master_xfer_one(struct i2c_adapter *adap, 158 struct i2c_msg *msg, bool stop) 159 { 160 bool is_read = msg->flags & I2C_M_RD; 161 bool recovery = false; 162 int ret; 163 164 if (is_read) 165 ret = uniphier_i2c_rx(adap, msg->addr, msg->len, msg->buf); 166 else 167 ret = uniphier_i2c_tx(adap, msg->addr, msg->len, msg->buf); 168 169 if (ret == -EAGAIN) /* could not acquire bus. bail out without STOP */ 170 return ret; 171 172 if (ret == -ETIMEDOUT) { 173 /* This error is fatal. Needs recovery. */ 174 stop = false; 175 recovery = true; 176 } 177 178 if (stop) { 179 int ret2 = uniphier_i2c_stop(adap); 180 181 if (ret2) { 182 /* Failed to issue STOP. The bus needs recovery. */ 183 recovery = true; 184 ret = ret ?: ret2; 185 } 186 } 187 188 if (recovery) 189 i2c_recover_bus(adap); 190 191 return ret; 192 } 193 194 static int uniphier_i2c_check_bus_busy(struct i2c_adapter *adap) 195 { 196 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap); 197 198 if (!(readl(priv->membase + UNIPHIER_I2C_DREC) & 199 UNIPHIER_I2C_DREC_BBN)) { 200 if (priv->busy_cnt++ > 3) { 201 /* 202 * If bus busy continues too long, it is probably 203 * in a wrong state. Try bus recovery. 204 */ 205 i2c_recover_bus(adap); 206 priv->busy_cnt = 0; 207 } 208 209 return -EAGAIN; 210 } 211 212 priv->busy_cnt = 0; 213 return 0; 214 } 215 216 static int uniphier_i2c_master_xfer(struct i2c_adapter *adap, 217 struct i2c_msg *msgs, int num) 218 { 219 struct i2c_msg *msg, *emsg = msgs + num; 220 int ret; 221 222 ret = uniphier_i2c_check_bus_busy(adap); 223 if (ret) 224 return ret; 225 226 for (msg = msgs; msg < emsg; msg++) { 227 /* Emit STOP if it is the last message or I2C_M_STOP is set. */ 228 bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP); 229 230 ret = uniphier_i2c_master_xfer_one(adap, msg, stop); 231 if (ret) 232 return ret; 233 } 234 235 return num; 236 } 237 238 static u32 uniphier_i2c_functionality(struct i2c_adapter *adap) 239 { 240 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 241 } 242 243 static const struct i2c_algorithm uniphier_i2c_algo = { 244 .master_xfer = uniphier_i2c_master_xfer, 245 .functionality = uniphier_i2c_functionality, 246 }; 247 248 static void uniphier_i2c_reset(struct uniphier_i2c_priv *priv, bool reset_on) 249 { 250 u32 val = UNIPHIER_I2C_BRST_RSCL; 251 252 val |= reset_on ? 0 : UNIPHIER_I2C_BRST_FOEN; 253 writel(val, priv->membase + UNIPHIER_I2C_BRST); 254 } 255 256 static int uniphier_i2c_get_scl(struct i2c_adapter *adap) 257 { 258 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap); 259 260 return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) & 261 UNIPHIER_I2C_BSTS_SCL); 262 } 263 264 static void uniphier_i2c_set_scl(struct i2c_adapter *adap, int val) 265 { 266 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap); 267 268 writel(val ? UNIPHIER_I2C_BRST_RSCL : 0, 269 priv->membase + UNIPHIER_I2C_BRST); 270 } 271 272 static int uniphier_i2c_get_sda(struct i2c_adapter *adap) 273 { 274 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap); 275 276 return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) & 277 UNIPHIER_I2C_BSTS_SDA); 278 } 279 280 static void uniphier_i2c_unprepare_recovery(struct i2c_adapter *adap) 281 { 282 uniphier_i2c_reset(i2c_get_adapdata(adap), false); 283 } 284 285 static struct i2c_bus_recovery_info uniphier_i2c_bus_recovery_info = { 286 .recover_bus = i2c_generic_scl_recovery, 287 .get_scl = uniphier_i2c_get_scl, 288 .set_scl = uniphier_i2c_set_scl, 289 .get_sda = uniphier_i2c_get_sda, 290 .unprepare_recovery = uniphier_i2c_unprepare_recovery, 291 }; 292 293 static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv) 294 { 295 unsigned int cyc = priv->clk_cycle; 296 297 uniphier_i2c_reset(priv, true); 298 299 /* 300 * Bit30-16: clock cycles of tLOW. 301 * Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us 302 * Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us 303 * "tLow/tHIGH = 5/4" meets both. 304 */ 305 writel((cyc * 5 / 9 << 16) | cyc, priv->membase + UNIPHIER_I2C_CLK); 306 307 uniphier_i2c_reset(priv, false); 308 } 309 310 static int uniphier_i2c_probe(struct platform_device *pdev) 311 { 312 struct device *dev = &pdev->dev; 313 struct uniphier_i2c_priv *priv; 314 u32 bus_speed; 315 unsigned long clk_rate; 316 int irq, ret; 317 318 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 319 if (!priv) 320 return -ENOMEM; 321 322 priv->membase = devm_platform_ioremap_resource(pdev, 0); 323 if (IS_ERR(priv->membase)) 324 return PTR_ERR(priv->membase); 325 326 irq = platform_get_irq(pdev, 0); 327 if (irq < 0) 328 return irq; 329 330 if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed)) 331 bus_speed = I2C_MAX_STANDARD_MODE_FREQ; 332 333 if (!bus_speed || bus_speed > I2C_MAX_FAST_MODE_FREQ) { 334 dev_err(dev, "invalid clock-frequency %d\n", bus_speed); 335 return -EINVAL; 336 } 337 338 priv->clk = devm_clk_get(dev, NULL); 339 if (IS_ERR(priv->clk)) { 340 dev_err(dev, "failed to get clock\n"); 341 return PTR_ERR(priv->clk); 342 } 343 344 ret = clk_prepare_enable(priv->clk); 345 if (ret) 346 return ret; 347 348 clk_rate = clk_get_rate(priv->clk); 349 if (!clk_rate) { 350 dev_err(dev, "input clock rate should not be zero\n"); 351 ret = -EINVAL; 352 goto disable_clk; 353 } 354 355 priv->clk_cycle = clk_rate / bus_speed; 356 init_completion(&priv->comp); 357 priv->adap.owner = THIS_MODULE; 358 priv->adap.algo = &uniphier_i2c_algo; 359 priv->adap.dev.parent = dev; 360 priv->adap.dev.of_node = dev->of_node; 361 strlcpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name)); 362 priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info; 363 i2c_set_adapdata(&priv->adap, priv); 364 platform_set_drvdata(pdev, priv); 365 366 uniphier_i2c_hw_init(priv); 367 368 ret = devm_request_irq(dev, irq, uniphier_i2c_interrupt, 0, pdev->name, 369 priv); 370 if (ret) { 371 dev_err(dev, "failed to request irq %d\n", irq); 372 goto disable_clk; 373 } 374 375 ret = i2c_add_adapter(&priv->adap); 376 disable_clk: 377 if (ret) 378 clk_disable_unprepare(priv->clk); 379 380 return ret; 381 } 382 383 static int uniphier_i2c_remove(struct platform_device *pdev) 384 { 385 struct uniphier_i2c_priv *priv = platform_get_drvdata(pdev); 386 387 i2c_del_adapter(&priv->adap); 388 clk_disable_unprepare(priv->clk); 389 390 return 0; 391 } 392 393 static int __maybe_unused uniphier_i2c_suspend(struct device *dev) 394 { 395 struct uniphier_i2c_priv *priv = dev_get_drvdata(dev); 396 397 clk_disable_unprepare(priv->clk); 398 399 return 0; 400 } 401 402 static int __maybe_unused uniphier_i2c_resume(struct device *dev) 403 { 404 struct uniphier_i2c_priv *priv = dev_get_drvdata(dev); 405 int ret; 406 407 ret = clk_prepare_enable(priv->clk); 408 if (ret) 409 return ret; 410 411 uniphier_i2c_hw_init(priv); 412 413 return 0; 414 } 415 416 static const struct dev_pm_ops uniphier_i2c_pm_ops = { 417 SET_SYSTEM_SLEEP_PM_OPS(uniphier_i2c_suspend, uniphier_i2c_resume) 418 }; 419 420 static const struct of_device_id uniphier_i2c_match[] = { 421 { .compatible = "socionext,uniphier-i2c" }, 422 { /* sentinel */ } 423 }; 424 MODULE_DEVICE_TABLE(of, uniphier_i2c_match); 425 426 static struct platform_driver uniphier_i2c_drv = { 427 .probe = uniphier_i2c_probe, 428 .remove = uniphier_i2c_remove, 429 .driver = { 430 .name = "uniphier-i2c", 431 .of_match_table = uniphier_i2c_match, 432 .pm = &uniphier_i2c_pm_ops, 433 }, 434 }; 435 module_platform_driver(uniphier_i2c_drv); 436 437 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); 438 MODULE_DESCRIPTION("UniPhier I2C bus driver"); 439 MODULE_LICENSE("GPL"); 440