1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/i2c.h> 8 #include <linux/iopoll.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 14 #define UNIPHIER_FI2C_CR 0x00 /* control register */ 15 #define UNIPHIER_FI2C_CR_MST BIT(3) /* master mode */ 16 #define UNIPHIER_FI2C_CR_STA BIT(2) /* start condition */ 17 #define UNIPHIER_FI2C_CR_STO BIT(1) /* stop condition */ 18 #define UNIPHIER_FI2C_CR_NACK BIT(0) /* do not return ACK */ 19 #define UNIPHIER_FI2C_DTTX 0x04 /* TX FIFO */ 20 #define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (slave addr) */ 21 #define UNIPHIER_FI2C_DTTX_RD BIT(0) /* read transaction */ 22 #define UNIPHIER_FI2C_DTRX 0x04 /* RX FIFO */ 23 #define UNIPHIER_FI2C_SLAD 0x0c /* slave address */ 24 #define UNIPHIER_FI2C_CYC 0x10 /* clock cycle control */ 25 #define UNIPHIER_FI2C_LCTL 0x14 /* clock low period control */ 26 #define UNIPHIER_FI2C_SSUT 0x18 /* restart/stop setup time control */ 27 #define UNIPHIER_FI2C_DSUT 0x1c /* data setup time control */ 28 #define UNIPHIER_FI2C_INT 0x20 /* interrupt status */ 29 #define UNIPHIER_FI2C_IE 0x24 /* interrupt enable */ 30 #define UNIPHIER_FI2C_IC 0x28 /* interrupt clear */ 31 #define UNIPHIER_FI2C_INT_TE BIT(9) /* TX FIFO empty */ 32 #define UNIPHIER_FI2C_INT_RF BIT(8) /* RX FIFO full */ 33 #define UNIPHIER_FI2C_INT_TC BIT(7) /* send complete (STOP) */ 34 #define UNIPHIER_FI2C_INT_RC BIT(6) /* receive complete (STOP) */ 35 #define UNIPHIER_FI2C_INT_TB BIT(5) /* sent specified bytes */ 36 #define UNIPHIER_FI2C_INT_RB BIT(4) /* received specified bytes */ 37 #define UNIPHIER_FI2C_INT_NA BIT(2) /* no ACK */ 38 #define UNIPHIER_FI2C_INT_AL BIT(1) /* arbitration lost */ 39 #define UNIPHIER_FI2C_SR 0x2c /* status register */ 40 #define UNIPHIER_FI2C_SR_DB BIT(12) /* device busy */ 41 #define UNIPHIER_FI2C_SR_STS BIT(11) /* stop condition detected */ 42 #define UNIPHIER_FI2C_SR_BB BIT(8) /* bus busy */ 43 #define UNIPHIER_FI2C_SR_RFF BIT(3) /* RX FIFO full */ 44 #define UNIPHIER_FI2C_SR_RNE BIT(2) /* RX FIFO not empty */ 45 #define UNIPHIER_FI2C_SR_TNF BIT(1) /* TX FIFO not full */ 46 #define UNIPHIER_FI2C_SR_TFE BIT(0) /* TX FIFO empty */ 47 #define UNIPHIER_FI2C_RST 0x34 /* reset control */ 48 #define UNIPHIER_FI2C_RST_TBRST BIT(2) /* clear TX FIFO */ 49 #define UNIPHIER_FI2C_RST_RBRST BIT(1) /* clear RX FIFO */ 50 #define UNIPHIER_FI2C_RST_RST BIT(0) /* forcible bus reset */ 51 #define UNIPHIER_FI2C_BM 0x38 /* bus monitor */ 52 #define UNIPHIER_FI2C_BM_SDAO BIT(3) /* output for SDA line */ 53 #define UNIPHIER_FI2C_BM_SDAS BIT(2) /* readback of SDA line */ 54 #define UNIPHIER_FI2C_BM_SCLO BIT(1) /* output for SCL line */ 55 #define UNIPHIER_FI2C_BM_SCLS BIT(0) /* readback of SCL line */ 56 #define UNIPHIER_FI2C_NOISE 0x3c /* noise filter control */ 57 #define UNIPHIER_FI2C_TBC 0x40 /* TX byte count setting */ 58 #define UNIPHIER_FI2C_RBC 0x44 /* RX byte count setting */ 59 #define UNIPHIER_FI2C_TBCM 0x48 /* TX byte count monitor */ 60 #define UNIPHIER_FI2C_RBCM 0x4c /* RX byte count monitor */ 61 #define UNIPHIER_FI2C_BRST 0x50 /* bus reset */ 62 #define UNIPHIER_FI2C_BRST_FOEN BIT(1) /* normal operation */ 63 #define UNIPHIER_FI2C_BRST_RSCL BIT(0) /* release SCL */ 64 65 #define UNIPHIER_FI2C_INT_FAULTS \ 66 (UNIPHIER_FI2C_INT_NA | UNIPHIER_FI2C_INT_AL) 67 #define UNIPHIER_FI2C_INT_STOP \ 68 (UNIPHIER_FI2C_INT_TC | UNIPHIER_FI2C_INT_RC) 69 70 #define UNIPHIER_FI2C_RD BIT(0) 71 #define UNIPHIER_FI2C_STOP BIT(1) 72 #define UNIPHIER_FI2C_MANUAL_NACK BIT(2) 73 #define UNIPHIER_FI2C_BYTE_WISE BIT(3) 74 #define UNIPHIER_FI2C_DEFER_STOP_COMP BIT(4) 75 76 #define UNIPHIER_FI2C_FIFO_SIZE 8 77 78 struct uniphier_fi2c_priv { 79 struct completion comp; 80 struct i2c_adapter adap; 81 void __iomem *membase; 82 struct clk *clk; 83 unsigned int len; 84 u8 *buf; 85 u32 enabled_irqs; 86 int error; 87 unsigned int flags; 88 unsigned int busy_cnt; 89 unsigned int clk_cycle; 90 spinlock_t lock; /* IRQ synchronization */ 91 }; 92 93 static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv, 94 bool first) 95 { 96 int fifo_space = UNIPHIER_FI2C_FIFO_SIZE; 97 98 /* 99 * TX-FIFO stores slave address in it for the first access. 100 * Decrement the counter. 101 */ 102 if (first) 103 fifo_space--; 104 105 while (priv->len) { 106 if (fifo_space-- <= 0) 107 break; 108 109 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); 110 priv->len--; 111 } 112 } 113 114 static void uniphier_fi2c_drain_rxfifo(struct uniphier_fi2c_priv *priv) 115 { 116 int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ? 117 1 : UNIPHIER_FI2C_FIFO_SIZE; 118 119 while (priv->len) { 120 if (fifo_left-- <= 0) 121 break; 122 123 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX); 124 priv->len--; 125 } 126 } 127 128 static void uniphier_fi2c_set_irqs(struct uniphier_fi2c_priv *priv) 129 { 130 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE); 131 } 132 133 static void uniphier_fi2c_clear_irqs(struct uniphier_fi2c_priv *priv, 134 u32 mask) 135 { 136 writel(mask, priv->membase + UNIPHIER_FI2C_IC); 137 } 138 139 static void uniphier_fi2c_stop(struct uniphier_fi2c_priv *priv) 140 { 141 priv->enabled_irqs |= UNIPHIER_FI2C_INT_STOP; 142 uniphier_fi2c_set_irqs(priv); 143 writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO, 144 priv->membase + UNIPHIER_FI2C_CR); 145 } 146 147 static irqreturn_t uniphier_fi2c_interrupt(int irq, void *dev_id) 148 { 149 struct uniphier_fi2c_priv *priv = dev_id; 150 u32 irq_status; 151 152 spin_lock(&priv->lock); 153 154 irq_status = readl(priv->membase + UNIPHIER_FI2C_INT); 155 irq_status &= priv->enabled_irqs; 156 157 if (irq_status & UNIPHIER_FI2C_INT_STOP) 158 goto complete; 159 160 if (unlikely(irq_status & UNIPHIER_FI2C_INT_AL)) { 161 priv->error = -EAGAIN; 162 goto complete; 163 } 164 165 if (unlikely(irq_status & UNIPHIER_FI2C_INT_NA)) { 166 priv->error = -ENXIO; 167 if (priv->flags & UNIPHIER_FI2C_RD) { 168 /* 169 * work around a hardware bug: 170 * The receive-completed interrupt is never set even if 171 * STOP condition is detected after the address phase 172 * of read transaction fails to get ACK. 173 * To avoid time-out error, we issue STOP here, 174 * but do not wait for its completion. 175 * It should be checked after exiting this handler. 176 */ 177 uniphier_fi2c_stop(priv); 178 priv->flags |= UNIPHIER_FI2C_DEFER_STOP_COMP; 179 goto complete; 180 } 181 goto stop; 182 } 183 184 if (irq_status & UNIPHIER_FI2C_INT_TE) { 185 if (!priv->len) 186 goto data_done; 187 188 uniphier_fi2c_fill_txfifo(priv, false); 189 goto handled; 190 } 191 192 if (irq_status & (UNIPHIER_FI2C_INT_RF | UNIPHIER_FI2C_INT_RB)) { 193 uniphier_fi2c_drain_rxfifo(priv); 194 /* 195 * If the number of bytes to read is multiple of the FIFO size 196 * (msg->len == 8, 16, 24, ...), the INT_RF bit is set a little 197 * earlier than INT_RB. We wait for INT_RB to confirm the 198 * completion of the current message. 199 */ 200 if (!priv->len && (irq_status & UNIPHIER_FI2C_INT_RB)) 201 goto data_done; 202 203 if (unlikely(priv->flags & UNIPHIER_FI2C_MANUAL_NACK)) { 204 if (priv->len <= UNIPHIER_FI2C_FIFO_SIZE && 205 !(priv->flags & UNIPHIER_FI2C_BYTE_WISE)) { 206 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RB; 207 uniphier_fi2c_set_irqs(priv); 208 priv->flags |= UNIPHIER_FI2C_BYTE_WISE; 209 } 210 if (priv->len <= 1) 211 writel(UNIPHIER_FI2C_CR_MST | 212 UNIPHIER_FI2C_CR_NACK, 213 priv->membase + UNIPHIER_FI2C_CR); 214 } 215 216 goto handled; 217 } 218 219 spin_unlock(&priv->lock); 220 221 return IRQ_NONE; 222 223 data_done: 224 if (priv->flags & UNIPHIER_FI2C_STOP) { 225 stop: 226 uniphier_fi2c_stop(priv); 227 } else { 228 complete: 229 priv->enabled_irqs = 0; 230 uniphier_fi2c_set_irqs(priv); 231 complete(&priv->comp); 232 } 233 234 handled: 235 /* 236 * This controller makes a pause while any bit of the IRQ status is 237 * asserted. Clear the asserted bit to kick the controller just before 238 * exiting the handler. 239 */ 240 uniphier_fi2c_clear_irqs(priv, irq_status); 241 242 spin_unlock(&priv->lock); 243 244 return IRQ_HANDLED; 245 } 246 247 static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr, 248 bool repeat) 249 { 250 priv->enabled_irqs |= UNIPHIER_FI2C_INT_TE; 251 uniphier_fi2c_set_irqs(priv); 252 253 /* do not use TX byte counter */ 254 writel(0, priv->membase + UNIPHIER_FI2C_TBC); 255 /* set slave address */ 256 writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1, 257 priv->membase + UNIPHIER_FI2C_DTTX); 258 /* 259 * First chunk of data. For a repeated START condition, do not write 260 * data to the TX fifo here to avoid the timing issue. 261 */ 262 if (!repeat) 263 uniphier_fi2c_fill_txfifo(priv, true); 264 } 265 266 static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr) 267 { 268 priv->flags |= UNIPHIER_FI2C_RD; 269 270 if (likely(priv->len < 256)) { 271 /* 272 * If possible, use RX byte counter. 273 * It can automatically handle NACK for the last byte. 274 */ 275 writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC); 276 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF | 277 UNIPHIER_FI2C_INT_RB; 278 } else { 279 /* 280 * The byte counter can not count over 256. In this case, 281 * do not use it at all. Drain data when FIFO gets full, 282 * but treat the last portion as a special case. 283 */ 284 writel(0, priv->membase + UNIPHIER_FI2C_RBC); 285 priv->flags |= UNIPHIER_FI2C_MANUAL_NACK; 286 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF; 287 } 288 289 uniphier_fi2c_set_irqs(priv); 290 291 /* set slave address with RD bit */ 292 writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1, 293 priv->membase + UNIPHIER_FI2C_DTTX); 294 } 295 296 static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv) 297 { 298 writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST); 299 } 300 301 static void uniphier_fi2c_prepare_operation(struct uniphier_fi2c_priv *priv) 302 { 303 writel(UNIPHIER_FI2C_BRST_FOEN | UNIPHIER_FI2C_BRST_RSCL, 304 priv->membase + UNIPHIER_FI2C_BRST); 305 } 306 307 static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv) 308 { 309 uniphier_fi2c_reset(priv); 310 i2c_recover_bus(&priv->adap); 311 } 312 313 static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap, 314 struct i2c_msg *msg, bool repeat, 315 bool stop) 316 { 317 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 318 bool is_read = msg->flags & I2C_M_RD; 319 unsigned long time_left, flags; 320 321 priv->len = msg->len; 322 priv->buf = msg->buf; 323 priv->enabled_irqs = UNIPHIER_FI2C_INT_FAULTS; 324 priv->error = 0; 325 priv->flags = 0; 326 327 if (stop) 328 priv->flags |= UNIPHIER_FI2C_STOP; 329 330 reinit_completion(&priv->comp); 331 uniphier_fi2c_clear_irqs(priv, U32_MAX); 332 writel(UNIPHIER_FI2C_RST_TBRST | UNIPHIER_FI2C_RST_RBRST, 333 priv->membase + UNIPHIER_FI2C_RST); /* reset TX/RX FIFO */ 334 335 spin_lock_irqsave(&priv->lock, flags); 336 337 if (is_read) 338 uniphier_fi2c_rx_init(priv, msg->addr); 339 else 340 uniphier_fi2c_tx_init(priv, msg->addr, repeat); 341 342 /* 343 * For a repeated START condition, writing a slave address to the FIFO 344 * kicks the controller. So, the UNIPHIER_FI2C_CR register should be 345 * written only for a non-repeated START condition. 346 */ 347 if (!repeat) 348 writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STA, 349 priv->membase + UNIPHIER_FI2C_CR); 350 351 spin_unlock_irqrestore(&priv->lock, flags); 352 353 time_left = wait_for_completion_timeout(&priv->comp, adap->timeout); 354 355 spin_lock_irqsave(&priv->lock, flags); 356 priv->enabled_irqs = 0; 357 uniphier_fi2c_set_irqs(priv); 358 spin_unlock_irqrestore(&priv->lock, flags); 359 360 if (!time_left) { 361 dev_err(&adap->dev, "transaction timeout.\n"); 362 uniphier_fi2c_recover(priv); 363 return -ETIMEDOUT; 364 } 365 366 if (unlikely(priv->flags & UNIPHIER_FI2C_DEFER_STOP_COMP)) { 367 u32 status; 368 int ret; 369 370 ret = readl_poll_timeout(priv->membase + UNIPHIER_FI2C_SR, 371 status, 372 (status & UNIPHIER_FI2C_SR_STS) && 373 !(status & UNIPHIER_FI2C_SR_BB), 374 1, 20); 375 if (ret) { 376 dev_err(&adap->dev, 377 "stop condition was not completed.\n"); 378 uniphier_fi2c_recover(priv); 379 return ret; 380 } 381 } 382 383 return priv->error; 384 } 385 386 static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap) 387 { 388 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 389 390 if (readl(priv->membase + UNIPHIER_FI2C_SR) & UNIPHIER_FI2C_SR_DB) { 391 if (priv->busy_cnt++ > 3) { 392 /* 393 * If bus busy continues too long, it is probably 394 * in a wrong state. Try bus recovery. 395 */ 396 uniphier_fi2c_recover(priv); 397 priv->busy_cnt = 0; 398 } 399 400 return -EAGAIN; 401 } 402 403 priv->busy_cnt = 0; 404 return 0; 405 } 406 407 static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap, 408 struct i2c_msg *msgs, int num) 409 { 410 struct i2c_msg *msg, *emsg = msgs + num; 411 bool repeat = false; 412 int ret; 413 414 ret = uniphier_fi2c_check_bus_busy(adap); 415 if (ret) 416 return ret; 417 418 for (msg = msgs; msg < emsg; msg++) { 419 /* Emit STOP if it is the last message or I2C_M_STOP is set. */ 420 bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP); 421 422 ret = uniphier_fi2c_master_xfer_one(adap, msg, repeat, stop); 423 if (ret) 424 return ret; 425 426 repeat = !stop; 427 } 428 429 return num; 430 } 431 432 static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap) 433 { 434 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 435 } 436 437 static const struct i2c_algorithm uniphier_fi2c_algo = { 438 .master_xfer = uniphier_fi2c_master_xfer, 439 .functionality = uniphier_fi2c_functionality, 440 }; 441 442 static int uniphier_fi2c_get_scl(struct i2c_adapter *adap) 443 { 444 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 445 446 return !!(readl(priv->membase + UNIPHIER_FI2C_BM) & 447 UNIPHIER_FI2C_BM_SCLS); 448 } 449 450 static void uniphier_fi2c_set_scl(struct i2c_adapter *adap, int val) 451 { 452 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 453 454 writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0, 455 priv->membase + UNIPHIER_FI2C_BRST); 456 } 457 458 static int uniphier_fi2c_get_sda(struct i2c_adapter *adap) 459 { 460 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 461 462 return !!(readl(priv->membase + UNIPHIER_FI2C_BM) & 463 UNIPHIER_FI2C_BM_SDAS); 464 } 465 466 static void uniphier_fi2c_unprepare_recovery(struct i2c_adapter *adap) 467 { 468 uniphier_fi2c_prepare_operation(i2c_get_adapdata(adap)); 469 } 470 471 static struct i2c_bus_recovery_info uniphier_fi2c_bus_recovery_info = { 472 .recover_bus = i2c_generic_scl_recovery, 473 .get_scl = uniphier_fi2c_get_scl, 474 .set_scl = uniphier_fi2c_set_scl, 475 .get_sda = uniphier_fi2c_get_sda, 476 .unprepare_recovery = uniphier_fi2c_unprepare_recovery, 477 }; 478 479 static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv) 480 { 481 unsigned int cyc = priv->clk_cycle; 482 u32 tmp; 483 484 tmp = readl(priv->membase + UNIPHIER_FI2C_CR); 485 tmp |= UNIPHIER_FI2C_CR_MST; 486 writel(tmp, priv->membase + UNIPHIER_FI2C_CR); 487 488 uniphier_fi2c_reset(priv); 489 490 /* 491 * Standard-mode: tLOW + tHIGH = 10 us 492 * Fast-mode: tLOW + tHIGH = 2.5 us 493 */ 494 writel(cyc, priv->membase + UNIPHIER_FI2C_CYC); 495 /* 496 * Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us, tBUF = 4.7 us 497 * Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us, tBUF = 1.3 us 498 * "tLow/tHIGH = 5/4" meets both. 499 */ 500 writel(cyc * 5 / 9, priv->membase + UNIPHIER_FI2C_LCTL); 501 /* 502 * Standard-mode: tHD;STA = 4.0 us, tSU;STA = 4.7 us, tSU;STO = 4.0 us 503 * Fast-mode: tHD;STA = 0.6 us, tSU;STA = 0.6 us, tSU;STO = 0.6 us 504 */ 505 writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT); 506 /* 507 * Standard-mode: tSU;DAT = 250 ns 508 * Fast-mode: tSU;DAT = 100 ns 509 */ 510 writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT); 511 512 uniphier_fi2c_prepare_operation(priv); 513 } 514 515 static int uniphier_fi2c_probe(struct platform_device *pdev) 516 { 517 struct device *dev = &pdev->dev; 518 struct uniphier_fi2c_priv *priv; 519 u32 bus_speed; 520 unsigned long clk_rate; 521 int irq, ret; 522 523 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 524 if (!priv) 525 return -ENOMEM; 526 527 priv->membase = devm_platform_ioremap_resource(pdev, 0); 528 if (IS_ERR(priv->membase)) 529 return PTR_ERR(priv->membase); 530 531 irq = platform_get_irq(pdev, 0); 532 if (irq < 0) 533 return irq; 534 535 if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed)) 536 bus_speed = I2C_MAX_STANDARD_MODE_FREQ; 537 538 if (!bus_speed || bus_speed > I2C_MAX_FAST_MODE_FREQ) { 539 dev_err(dev, "invalid clock-frequency %d\n", bus_speed); 540 return -EINVAL; 541 } 542 543 priv->clk = devm_clk_get_enabled(dev, NULL); 544 if (IS_ERR(priv->clk)) { 545 dev_err(dev, "failed to enable clock\n"); 546 return PTR_ERR(priv->clk); 547 } 548 549 clk_rate = clk_get_rate(priv->clk); 550 if (!clk_rate) { 551 dev_err(dev, "input clock rate should not be zero\n"); 552 return -EINVAL; 553 } 554 555 priv->clk_cycle = clk_rate / bus_speed; 556 init_completion(&priv->comp); 557 spin_lock_init(&priv->lock); 558 priv->adap.owner = THIS_MODULE; 559 priv->adap.algo = &uniphier_fi2c_algo; 560 priv->adap.dev.parent = dev; 561 priv->adap.dev.of_node = dev->of_node; 562 strscpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name)); 563 priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info; 564 i2c_set_adapdata(&priv->adap, priv); 565 platform_set_drvdata(pdev, priv); 566 567 uniphier_fi2c_hw_init(priv); 568 569 ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0, 570 pdev->name, priv); 571 if (ret) { 572 dev_err(dev, "failed to request irq %d\n", irq); 573 return ret; 574 } 575 576 return i2c_add_adapter(&priv->adap); 577 } 578 579 static void uniphier_fi2c_remove(struct platform_device *pdev) 580 { 581 struct uniphier_fi2c_priv *priv = platform_get_drvdata(pdev); 582 583 i2c_del_adapter(&priv->adap); 584 } 585 586 static int __maybe_unused uniphier_fi2c_suspend(struct device *dev) 587 { 588 struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev); 589 590 clk_disable_unprepare(priv->clk); 591 592 return 0; 593 } 594 595 static int __maybe_unused uniphier_fi2c_resume(struct device *dev) 596 { 597 struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev); 598 int ret; 599 600 ret = clk_prepare_enable(priv->clk); 601 if (ret) 602 return ret; 603 604 uniphier_fi2c_hw_init(priv); 605 606 return 0; 607 } 608 609 static const struct dev_pm_ops uniphier_fi2c_pm_ops = { 610 SET_SYSTEM_SLEEP_PM_OPS(uniphier_fi2c_suspend, uniphier_fi2c_resume) 611 }; 612 613 static const struct of_device_id uniphier_fi2c_match[] = { 614 { .compatible = "socionext,uniphier-fi2c" }, 615 { /* sentinel */ } 616 }; 617 MODULE_DEVICE_TABLE(of, uniphier_fi2c_match); 618 619 static struct platform_driver uniphier_fi2c_drv = { 620 .probe = uniphier_fi2c_probe, 621 .remove_new = uniphier_fi2c_remove, 622 .driver = { 623 .name = "uniphier-fi2c", 624 .of_match_table = uniphier_fi2c_match, 625 .pm = &uniphier_fi2c_pm_ops, 626 }, 627 }; 628 module_platform_driver(uniphier_fi2c_drv); 629 630 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); 631 MODULE_DESCRIPTION("UniPhier FIFO-builtin I2C bus driver"); 632 MODULE_LICENSE("GPL"); 633