1 /* 2 * drivers/i2c/busses/i2c-tegra.c 3 * 4 * Copyright (C) 2010 Google, Inc. 5 * Author: Colin Cross <ccross@android.com> 6 * 7 * This software is licensed under the terms of the GNU General Public 8 * License version 2, as published by the Free Software Foundation, and 9 * may be copied, distributed, and modified under those terms. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/err.h> 23 #include <linux/i2c.h> 24 #include <linux/io.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 #include <linux/i2c-tegra.h> 29 #include <linux/of_i2c.h> 30 #include <linux/module.h> 31 32 #include <asm/unaligned.h> 33 34 #include <mach/clk.h> 35 36 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000)) 37 #define BYTES_PER_FIFO_WORD 4 38 39 #define I2C_CNFG 0x000 40 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 41 #define I2C_CNFG_PACKET_MODE_EN (1<<10) 42 #define I2C_CNFG_NEW_MASTER_FSM (1<<11) 43 #define I2C_STATUS 0x01C 44 #define I2C_SL_CNFG 0x020 45 #define I2C_SL_CNFG_NACK (1<<1) 46 #define I2C_SL_CNFG_NEWSL (1<<2) 47 #define I2C_SL_ADDR1 0x02c 48 #define I2C_SL_ADDR2 0x030 49 #define I2C_TX_FIFO 0x050 50 #define I2C_RX_FIFO 0x054 51 #define I2C_PACKET_TRANSFER_STATUS 0x058 52 #define I2C_FIFO_CONTROL 0x05c 53 #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1) 54 #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0) 55 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5 56 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2 57 #define I2C_FIFO_STATUS 0x060 58 #define I2C_FIFO_STATUS_TX_MASK 0xF0 59 #define I2C_FIFO_STATUS_TX_SHIFT 4 60 #define I2C_FIFO_STATUS_RX_MASK 0x0F 61 #define I2C_FIFO_STATUS_RX_SHIFT 0 62 #define I2C_INT_MASK 0x064 63 #define I2C_INT_STATUS 0x068 64 #define I2C_INT_PACKET_XFER_COMPLETE (1<<7) 65 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6) 66 #define I2C_INT_TX_FIFO_OVERFLOW (1<<5) 67 #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4) 68 #define I2C_INT_NO_ACK (1<<3) 69 #define I2C_INT_ARBITRATION_LOST (1<<2) 70 #define I2C_INT_TX_FIFO_DATA_REQ (1<<1) 71 #define I2C_INT_RX_FIFO_DATA_REQ (1<<0) 72 #define I2C_CLK_DIVISOR 0x06c 73 74 #define DVC_CTRL_REG1 0x000 75 #define DVC_CTRL_REG1_INTR_EN (1<<10) 76 #define DVC_CTRL_REG2 0x004 77 #define DVC_CTRL_REG3 0x008 78 #define DVC_CTRL_REG3_SW_PROG (1<<26) 79 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30) 80 #define DVC_STATUS 0x00c 81 #define DVC_STATUS_I2C_DONE_INTR (1<<30) 82 83 #define I2C_ERR_NONE 0x00 84 #define I2C_ERR_NO_ACK 0x01 85 #define I2C_ERR_ARBITRATION_LOST 0x02 86 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04 87 88 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 89 #define PACKET_HEADER0_PACKET_ID_SHIFT 16 90 #define PACKET_HEADER0_CONT_ID_SHIFT 12 91 #define PACKET_HEADER0_PROTOCOL_I2C (1<<4) 92 93 #define I2C_HEADER_HIGHSPEED_MODE (1<<22) 94 #define I2C_HEADER_CONT_ON_NAK (1<<21) 95 #define I2C_HEADER_SEND_START_BYTE (1<<20) 96 #define I2C_HEADER_READ (1<<19) 97 #define I2C_HEADER_10BIT_ADDR (1<<18) 98 #define I2C_HEADER_IE_ENABLE (1<<17) 99 #define I2C_HEADER_REPEAT_START (1<<16) 100 #define I2C_HEADER_MASTER_ADDR_SHIFT 12 101 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 102 103 /** 104 * struct tegra_i2c_dev - per device i2c context 105 * @dev: device reference for power management 106 * @adapter: core i2c layer adapter information 107 * @clk: clock reference for i2c controller 108 * @i2c_clk: clock reference for i2c bus 109 * @iomem: memory resource for registers 110 * @base: ioremapped registers cookie 111 * @cont_id: i2c controller id, used for for packet header 112 * @irq: irq number of transfer complete interrupt 113 * @is_dvc: identifies the DVC i2c controller, has a different register layout 114 * @msg_complete: transfer completion notifier 115 * @msg_err: error code for completed message 116 * @msg_buf: pointer to current message data 117 * @msg_buf_remaining: size of unsent data in the message buffer 118 * @msg_read: identifies read transfers 119 * @bus_clk_rate: current i2c bus clock rate 120 * @is_suspended: prevents i2c controller accesses after suspend is called 121 */ 122 struct tegra_i2c_dev { 123 struct device *dev; 124 struct i2c_adapter adapter; 125 struct clk *clk; 126 struct clk *i2c_clk; 127 struct resource *iomem; 128 void __iomem *base; 129 int cont_id; 130 int irq; 131 bool irq_disabled; 132 int is_dvc; 133 struct completion msg_complete; 134 int msg_err; 135 u8 *msg_buf; 136 size_t msg_buf_remaining; 137 int msg_read; 138 unsigned long bus_clk_rate; 139 bool is_suspended; 140 }; 141 142 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg) 143 { 144 writel(val, i2c_dev->base + reg); 145 } 146 147 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 148 { 149 return readl(i2c_dev->base + reg); 150 } 151 152 /* 153 * i2c_writel and i2c_readl will offset the register if necessary to talk 154 * to the I2C block inside the DVC block 155 */ 156 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, 157 unsigned long reg) 158 { 159 if (i2c_dev->is_dvc) 160 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 161 return reg; 162 } 163 164 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 165 unsigned long reg) 166 { 167 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 168 } 169 170 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 171 { 172 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 173 } 174 175 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 176 unsigned long reg, int len) 177 { 178 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 179 } 180 181 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 182 unsigned long reg, int len) 183 { 184 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 185 } 186 187 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 188 { 189 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); 190 int_mask &= ~mask; 191 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 192 } 193 194 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 195 { 196 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); 197 int_mask |= mask; 198 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 199 } 200 201 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 202 { 203 unsigned long timeout = jiffies + HZ; 204 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL); 205 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH; 206 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); 207 208 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) & 209 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) { 210 if (time_after(jiffies, timeout)) { 211 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); 212 return -ETIMEDOUT; 213 } 214 msleep(1); 215 } 216 return 0; 217 } 218 219 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 220 { 221 u32 val; 222 int rx_fifo_avail; 223 u8 *buf = i2c_dev->msg_buf; 224 size_t buf_remaining = i2c_dev->msg_buf_remaining; 225 int words_to_transfer; 226 227 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 228 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >> 229 I2C_FIFO_STATUS_RX_SHIFT; 230 231 /* Rounds down to not include partial word at the end of buf */ 232 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 233 if (words_to_transfer > rx_fifo_avail) 234 words_to_transfer = rx_fifo_avail; 235 236 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 237 238 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 239 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 240 rx_fifo_avail -= words_to_transfer; 241 242 /* 243 * If there is a partial word at the end of buf, handle it manually to 244 * prevent overwriting past the end of buf 245 */ 246 if (rx_fifo_avail > 0 && buf_remaining > 0) { 247 BUG_ON(buf_remaining > 3); 248 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 249 memcpy(buf, &val, buf_remaining); 250 buf_remaining = 0; 251 rx_fifo_avail--; 252 } 253 254 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0); 255 i2c_dev->msg_buf_remaining = buf_remaining; 256 i2c_dev->msg_buf = buf; 257 return 0; 258 } 259 260 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 261 { 262 u32 val; 263 int tx_fifo_avail; 264 u8 *buf = i2c_dev->msg_buf; 265 size_t buf_remaining = i2c_dev->msg_buf_remaining; 266 int words_to_transfer; 267 268 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 269 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >> 270 I2C_FIFO_STATUS_TX_SHIFT; 271 272 /* Rounds down to not include partial word at the end of buf */ 273 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 274 275 /* It's very common to have < 4 bytes, so optimize that case. */ 276 if (words_to_transfer) { 277 if (words_to_transfer > tx_fifo_avail) 278 words_to_transfer = tx_fifo_avail; 279 280 /* 281 * Update state before writing to FIFO. If this casues us 282 * to finish writing all bytes (AKA buf_remaining goes to 0) we 283 * have a potential for an interrupt (PACKET_XFER_COMPLETE is 284 * not maskable). We need to make sure that the isr sees 285 * buf_remaining as 0 and doesn't call us back re-entrantly. 286 */ 287 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 288 tx_fifo_avail -= words_to_transfer; 289 i2c_dev->msg_buf_remaining = buf_remaining; 290 i2c_dev->msg_buf = buf + 291 words_to_transfer * BYTES_PER_FIFO_WORD; 292 barrier(); 293 294 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 295 296 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 297 } 298 299 /* 300 * If there is a partial word at the end of buf, handle it manually to 301 * prevent reading past the end of buf, which could cross a page 302 * boundary and fault. 303 */ 304 if (tx_fifo_avail > 0 && buf_remaining > 0) { 305 BUG_ON(buf_remaining > 3); 306 memcpy(&val, buf, buf_remaining); 307 308 /* Again update before writing to FIFO to make sure isr sees. */ 309 i2c_dev->msg_buf_remaining = 0; 310 i2c_dev->msg_buf = NULL; 311 barrier(); 312 313 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 314 } 315 316 return 0; 317 } 318 319 /* 320 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 321 * block. This block is identical to the rest of the I2C blocks, except that 322 * it only supports master mode, it has registers moved around, and it needs 323 * some extra init to get it into I2C mode. The register moves are handled 324 * by i2c_readl and i2c_writel 325 */ 326 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 327 { 328 u32 val = 0; 329 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 330 val |= DVC_CTRL_REG3_SW_PROG; 331 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 332 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 333 334 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 335 val |= DVC_CTRL_REG1_INTR_EN; 336 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 337 } 338 339 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 340 { 341 u32 val; 342 int err = 0; 343 344 clk_enable(i2c_dev->clk); 345 346 tegra_periph_reset_assert(i2c_dev->clk); 347 udelay(2); 348 tegra_periph_reset_deassert(i2c_dev->clk); 349 350 if (i2c_dev->is_dvc) 351 tegra_dvc_init(i2c_dev); 352 353 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 354 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); 355 i2c_writel(i2c_dev, val, I2C_CNFG); 356 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 357 clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8); 358 359 if (!i2c_dev->is_dvc) { 360 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 361 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 362 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 363 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 364 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 365 366 } 367 368 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT | 369 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT; 370 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); 371 372 if (tegra_i2c_flush_fifos(i2c_dev)) 373 err = -ETIMEDOUT; 374 375 clk_disable(i2c_dev->clk); 376 377 if (i2c_dev->irq_disabled) { 378 i2c_dev->irq_disabled = 0; 379 enable_irq(i2c_dev->irq); 380 } 381 382 return err; 383 } 384 385 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 386 { 387 u32 status; 388 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 389 struct tegra_i2c_dev *i2c_dev = dev_id; 390 391 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 392 393 if (status == 0) { 394 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n", 395 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 396 i2c_readl(i2c_dev, I2C_STATUS), 397 i2c_readl(i2c_dev, I2C_CNFG)); 398 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 399 400 if (!i2c_dev->irq_disabled) { 401 disable_irq_nosync(i2c_dev->irq); 402 i2c_dev->irq_disabled = 1; 403 } 404 405 complete(&i2c_dev->msg_complete); 406 goto err; 407 } 408 409 if (unlikely(status & status_err)) { 410 if (status & I2C_INT_NO_ACK) 411 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 412 if (status & I2C_INT_ARBITRATION_LOST) 413 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 414 complete(&i2c_dev->msg_complete); 415 goto err; 416 } 417 418 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 419 if (i2c_dev->msg_buf_remaining) 420 tegra_i2c_empty_rx_fifo(i2c_dev); 421 else 422 BUG(); 423 } 424 425 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 426 if (i2c_dev->msg_buf_remaining) 427 tegra_i2c_fill_tx_fifo(i2c_dev); 428 else 429 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ); 430 } 431 432 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 433 BUG_ON(i2c_dev->msg_buf_remaining); 434 complete(&i2c_dev->msg_complete); 435 } 436 437 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 438 if (i2c_dev->is_dvc) 439 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 440 return IRQ_HANDLED; 441 err: 442 /* An error occurred, mask all interrupts */ 443 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | 444 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ | 445 I2C_INT_RX_FIFO_DATA_REQ); 446 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 447 if (i2c_dev->is_dvc) 448 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 449 return IRQ_HANDLED; 450 } 451 452 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 453 struct i2c_msg *msg, int stop) 454 { 455 u32 packet_header; 456 u32 int_mask; 457 int ret; 458 459 tegra_i2c_flush_fifos(i2c_dev); 460 i2c_writel(i2c_dev, 0xFF, I2C_INT_STATUS); 461 462 if (msg->len == 0) 463 return -EINVAL; 464 465 i2c_dev->msg_buf = msg->buf; 466 i2c_dev->msg_buf_remaining = msg->len; 467 i2c_dev->msg_err = I2C_ERR_NONE; 468 i2c_dev->msg_read = (msg->flags & I2C_M_RD); 469 INIT_COMPLETION(i2c_dev->msg_complete); 470 471 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | 472 PACKET_HEADER0_PROTOCOL_I2C | 473 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | 474 (1 << PACKET_HEADER0_PACKET_ID_SHIFT); 475 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 476 477 packet_header = msg->len - 1; 478 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 479 480 packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 481 packet_header |= I2C_HEADER_IE_ENABLE; 482 if (!stop) 483 packet_header |= I2C_HEADER_REPEAT_START; 484 if (msg->flags & I2C_M_TEN) 485 packet_header |= I2C_HEADER_10BIT_ADDR; 486 if (msg->flags & I2C_M_IGNORE_NAK) 487 packet_header |= I2C_HEADER_CONT_ON_NAK; 488 if (msg->flags & I2C_M_RD) 489 packet_header |= I2C_HEADER_READ; 490 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 491 492 if (!(msg->flags & I2C_M_RD)) 493 tegra_i2c_fill_tx_fifo(i2c_dev); 494 495 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 496 if (msg->flags & I2C_M_RD) 497 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 498 else if (i2c_dev->msg_buf_remaining) 499 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 500 tegra_i2c_unmask_irq(i2c_dev, int_mask); 501 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", 502 i2c_readl(i2c_dev, I2C_INT_MASK)); 503 504 ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT); 505 tegra_i2c_mask_irq(i2c_dev, int_mask); 506 507 if (WARN_ON(ret == 0)) { 508 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); 509 510 tegra_i2c_init(i2c_dev); 511 return -ETIMEDOUT; 512 } 513 514 dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n", 515 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err); 516 517 if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) 518 return 0; 519 520 tegra_i2c_init(i2c_dev); 521 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 522 if (msg->flags & I2C_M_IGNORE_NAK) 523 return 0; 524 return -EREMOTEIO; 525 } 526 527 return -EIO; 528 } 529 530 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 531 int num) 532 { 533 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 534 int i; 535 int ret = 0; 536 537 if (i2c_dev->is_suspended) 538 return -EBUSY; 539 540 clk_enable(i2c_dev->clk); 541 for (i = 0; i < num; i++) { 542 int stop = (i == (num - 1)) ? 1 : 0; 543 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], stop); 544 if (ret) 545 break; 546 } 547 clk_disable(i2c_dev->clk); 548 return ret ?: i; 549 } 550 551 static u32 tegra_i2c_func(struct i2c_adapter *adap) 552 { 553 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 554 } 555 556 static const struct i2c_algorithm tegra_i2c_algo = { 557 .master_xfer = tegra_i2c_xfer, 558 .functionality = tegra_i2c_func, 559 }; 560 561 static int tegra_i2c_probe(struct platform_device *pdev) 562 { 563 struct tegra_i2c_dev *i2c_dev; 564 struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data; 565 struct resource *res; 566 struct resource *iomem; 567 struct clk *clk; 568 struct clk *i2c_clk; 569 const unsigned int *prop; 570 void __iomem *base; 571 int irq; 572 int ret = 0; 573 574 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 575 if (!res) { 576 dev_err(&pdev->dev, "no mem resource\n"); 577 return -EINVAL; 578 } 579 iomem = request_mem_region(res->start, resource_size(res), pdev->name); 580 if (!iomem) { 581 dev_err(&pdev->dev, "I2C region already claimed\n"); 582 return -EBUSY; 583 } 584 585 base = ioremap(iomem->start, resource_size(iomem)); 586 if (!base) { 587 dev_err(&pdev->dev, "Cannot ioremap I2C region\n"); 588 return -ENOMEM; 589 } 590 591 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 592 if (!res) { 593 dev_err(&pdev->dev, "no irq resource\n"); 594 ret = -EINVAL; 595 goto err_iounmap; 596 } 597 irq = res->start; 598 599 clk = clk_get(&pdev->dev, NULL); 600 if (IS_ERR(clk)) { 601 dev_err(&pdev->dev, "missing controller clock"); 602 ret = PTR_ERR(clk); 603 goto err_release_region; 604 } 605 606 i2c_clk = clk_get(&pdev->dev, "i2c"); 607 if (IS_ERR(i2c_clk)) { 608 dev_err(&pdev->dev, "missing bus clock"); 609 ret = PTR_ERR(i2c_clk); 610 goto err_clk_put; 611 } 612 613 i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev), GFP_KERNEL); 614 if (!i2c_dev) { 615 ret = -ENOMEM; 616 goto err_i2c_clk_put; 617 } 618 619 i2c_dev->base = base; 620 i2c_dev->clk = clk; 621 i2c_dev->i2c_clk = i2c_clk; 622 i2c_dev->iomem = iomem; 623 i2c_dev->adapter.algo = &tegra_i2c_algo; 624 i2c_dev->irq = irq; 625 i2c_dev->cont_id = pdev->id; 626 i2c_dev->dev = &pdev->dev; 627 628 i2c_dev->bus_clk_rate = 100000; /* default clock rate */ 629 if (pdata) { 630 i2c_dev->bus_clk_rate = pdata->bus_clk_rate; 631 632 } else if (i2c_dev->dev->of_node) { /* if there is a device tree node ... */ 633 prop = of_get_property(i2c_dev->dev->of_node, 634 "clock-frequency", NULL); 635 if (prop) 636 i2c_dev->bus_clk_rate = be32_to_cpup(prop); 637 } 638 639 if (pdev->id == 3) 640 i2c_dev->is_dvc = 1; 641 init_completion(&i2c_dev->msg_complete); 642 643 platform_set_drvdata(pdev, i2c_dev); 644 645 ret = tegra_i2c_init(i2c_dev); 646 if (ret) { 647 dev_err(&pdev->dev, "Failed to initialize i2c controller"); 648 goto err_free; 649 } 650 651 ret = request_irq(i2c_dev->irq, tegra_i2c_isr, 0, pdev->name, i2c_dev); 652 if (ret) { 653 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); 654 goto err_free; 655 } 656 657 clk_enable(i2c_dev->i2c_clk); 658 659 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 660 i2c_dev->adapter.owner = THIS_MODULE; 661 i2c_dev->adapter.class = I2C_CLASS_HWMON; 662 strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter", 663 sizeof(i2c_dev->adapter.name)); 664 i2c_dev->adapter.algo = &tegra_i2c_algo; 665 i2c_dev->adapter.dev.parent = &pdev->dev; 666 i2c_dev->adapter.nr = pdev->id; 667 i2c_dev->adapter.dev.of_node = pdev->dev.of_node; 668 669 ret = i2c_add_numbered_adapter(&i2c_dev->adapter); 670 if (ret) { 671 dev_err(&pdev->dev, "Failed to add I2C adapter\n"); 672 goto err_free_irq; 673 } 674 675 of_i2c_register_devices(&i2c_dev->adapter); 676 677 return 0; 678 err_free_irq: 679 free_irq(i2c_dev->irq, i2c_dev); 680 err_free: 681 kfree(i2c_dev); 682 err_i2c_clk_put: 683 clk_put(i2c_clk); 684 err_clk_put: 685 clk_put(clk); 686 err_release_region: 687 release_mem_region(iomem->start, resource_size(iomem)); 688 err_iounmap: 689 iounmap(base); 690 return ret; 691 } 692 693 static int tegra_i2c_remove(struct platform_device *pdev) 694 { 695 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 696 i2c_del_adapter(&i2c_dev->adapter); 697 free_irq(i2c_dev->irq, i2c_dev); 698 clk_put(i2c_dev->i2c_clk); 699 clk_put(i2c_dev->clk); 700 release_mem_region(i2c_dev->iomem->start, 701 resource_size(i2c_dev->iomem)); 702 iounmap(i2c_dev->base); 703 kfree(i2c_dev); 704 return 0; 705 } 706 707 #ifdef CONFIG_PM 708 static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state) 709 { 710 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 711 712 i2c_lock_adapter(&i2c_dev->adapter); 713 i2c_dev->is_suspended = true; 714 i2c_unlock_adapter(&i2c_dev->adapter); 715 716 return 0; 717 } 718 719 static int tegra_i2c_resume(struct platform_device *pdev) 720 { 721 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 722 int ret; 723 724 i2c_lock_adapter(&i2c_dev->adapter); 725 726 ret = tegra_i2c_init(i2c_dev); 727 728 if (ret) { 729 i2c_unlock_adapter(&i2c_dev->adapter); 730 return ret; 731 } 732 733 i2c_dev->is_suspended = false; 734 735 i2c_unlock_adapter(&i2c_dev->adapter); 736 737 return 0; 738 } 739 #endif 740 741 #if defined(CONFIG_OF) 742 /* Match table for of_platform binding */ 743 static const struct of_device_id tegra_i2c_of_match[] __devinitconst = { 744 { .compatible = "nvidia,tegra20-i2c", }, 745 {}, 746 }; 747 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 748 #else 749 #define tegra_i2c_of_match NULL 750 #endif 751 752 static struct platform_driver tegra_i2c_driver = { 753 .probe = tegra_i2c_probe, 754 .remove = tegra_i2c_remove, 755 #ifdef CONFIG_PM 756 .suspend = tegra_i2c_suspend, 757 .resume = tegra_i2c_resume, 758 #endif 759 .driver = { 760 .name = "tegra-i2c", 761 .owner = THIS_MODULE, 762 .of_match_table = tegra_i2c_of_match, 763 }, 764 }; 765 766 static int __init tegra_i2c_init_driver(void) 767 { 768 return platform_driver_register(&tegra_i2c_driver); 769 } 770 771 static void __exit tegra_i2c_exit_driver(void) 772 { 773 platform_driver_unregister(&tegra_i2c_driver); 774 } 775 776 subsys_initcall(tegra_i2c_init_driver); 777 module_exit(tegra_i2c_exit_driver); 778 779 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver"); 780 MODULE_AUTHOR("Colin Cross"); 781 MODULE_LICENSE("GPL v2"); 782