1 /* 2 * drivers/i2c/busses/i2c-tegra.c 3 * 4 * Copyright (C) 2010 Google, Inc. 5 * Author: Colin Cross <ccross@android.com> 6 * 7 * This software is licensed under the terms of the GNU General Public 8 * License version 2, as published by the Free Software Foundation, and 9 * may be copied, distributed, and modified under those terms. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/err.h> 23 #include <linux/i2c.h> 24 #include <linux/io.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 #include <linux/i2c-tegra.h> 29 #include <linux/of_i2c.h> 30 #include <linux/module.h> 31 32 #include <asm/unaligned.h> 33 34 #include <mach/clk.h> 35 36 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000)) 37 #define BYTES_PER_FIFO_WORD 4 38 39 #define I2C_CNFG 0x000 40 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 41 #define I2C_CNFG_PACKET_MODE_EN (1<<10) 42 #define I2C_CNFG_NEW_MASTER_FSM (1<<11) 43 #define I2C_STATUS 0x01C 44 #define I2C_SL_CNFG 0x020 45 #define I2C_SL_CNFG_NACK (1<<1) 46 #define I2C_SL_CNFG_NEWSL (1<<2) 47 #define I2C_SL_ADDR1 0x02c 48 #define I2C_SL_ADDR2 0x030 49 #define I2C_TX_FIFO 0x050 50 #define I2C_RX_FIFO 0x054 51 #define I2C_PACKET_TRANSFER_STATUS 0x058 52 #define I2C_FIFO_CONTROL 0x05c 53 #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1) 54 #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0) 55 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5 56 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2 57 #define I2C_FIFO_STATUS 0x060 58 #define I2C_FIFO_STATUS_TX_MASK 0xF0 59 #define I2C_FIFO_STATUS_TX_SHIFT 4 60 #define I2C_FIFO_STATUS_RX_MASK 0x0F 61 #define I2C_FIFO_STATUS_RX_SHIFT 0 62 #define I2C_INT_MASK 0x064 63 #define I2C_INT_STATUS 0x068 64 #define I2C_INT_PACKET_XFER_COMPLETE (1<<7) 65 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6) 66 #define I2C_INT_TX_FIFO_OVERFLOW (1<<5) 67 #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4) 68 #define I2C_INT_NO_ACK (1<<3) 69 #define I2C_INT_ARBITRATION_LOST (1<<2) 70 #define I2C_INT_TX_FIFO_DATA_REQ (1<<1) 71 #define I2C_INT_RX_FIFO_DATA_REQ (1<<0) 72 #define I2C_CLK_DIVISOR 0x06c 73 74 #define DVC_CTRL_REG1 0x000 75 #define DVC_CTRL_REG1_INTR_EN (1<<10) 76 #define DVC_CTRL_REG2 0x004 77 #define DVC_CTRL_REG3 0x008 78 #define DVC_CTRL_REG3_SW_PROG (1<<26) 79 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30) 80 #define DVC_STATUS 0x00c 81 #define DVC_STATUS_I2C_DONE_INTR (1<<30) 82 83 #define I2C_ERR_NONE 0x00 84 #define I2C_ERR_NO_ACK 0x01 85 #define I2C_ERR_ARBITRATION_LOST 0x02 86 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04 87 88 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 89 #define PACKET_HEADER0_PACKET_ID_SHIFT 16 90 #define PACKET_HEADER0_CONT_ID_SHIFT 12 91 #define PACKET_HEADER0_PROTOCOL_I2C (1<<4) 92 93 #define I2C_HEADER_HIGHSPEED_MODE (1<<22) 94 #define I2C_HEADER_CONT_ON_NAK (1<<21) 95 #define I2C_HEADER_SEND_START_BYTE (1<<20) 96 #define I2C_HEADER_READ (1<<19) 97 #define I2C_HEADER_10BIT_ADDR (1<<18) 98 #define I2C_HEADER_IE_ENABLE (1<<17) 99 #define I2C_HEADER_REPEAT_START (1<<16) 100 #define I2C_HEADER_CONTINUE_XFER (1<<15) 101 #define I2C_HEADER_MASTER_ADDR_SHIFT 12 102 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 103 /* 104 * msg_end_type: The bus control which need to be send at end of transfer. 105 * @MSG_END_STOP: Send stop pulse at end of transfer. 106 * @MSG_END_REPEAT_START: Send repeat start at end of transfer. 107 * @MSG_END_CONTINUE: The following on message is coming and so do not send 108 * stop or repeat start. 109 */ 110 enum msg_end_type { 111 MSG_END_STOP, 112 MSG_END_REPEAT_START, 113 MSG_END_CONTINUE, 114 }; 115 116 /** 117 * struct tegra_i2c_dev - per device i2c context 118 * @dev: device reference for power management 119 * @adapter: core i2c layer adapter information 120 * @clk: clock reference for i2c controller 121 * @i2c_clk: clock reference for i2c bus 122 * @base: ioremapped registers cookie 123 * @cont_id: i2c controller id, used for for packet header 124 * @irq: irq number of transfer complete interrupt 125 * @is_dvc: identifies the DVC i2c controller, has a different register layout 126 * @msg_complete: transfer completion notifier 127 * @msg_err: error code for completed message 128 * @msg_buf: pointer to current message data 129 * @msg_buf_remaining: size of unsent data in the message buffer 130 * @msg_read: identifies read transfers 131 * @bus_clk_rate: current i2c bus clock rate 132 * @is_suspended: prevents i2c controller accesses after suspend is called 133 */ 134 struct tegra_i2c_dev { 135 struct device *dev; 136 struct i2c_adapter adapter; 137 struct clk *clk; 138 struct clk *i2c_clk; 139 void __iomem *base; 140 int cont_id; 141 int irq; 142 bool irq_disabled; 143 int is_dvc; 144 struct completion msg_complete; 145 int msg_err; 146 u8 *msg_buf; 147 size_t msg_buf_remaining; 148 int msg_read; 149 unsigned long bus_clk_rate; 150 bool is_suspended; 151 }; 152 153 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg) 154 { 155 writel(val, i2c_dev->base + reg); 156 } 157 158 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 159 { 160 return readl(i2c_dev->base + reg); 161 } 162 163 /* 164 * i2c_writel and i2c_readl will offset the register if necessary to talk 165 * to the I2C block inside the DVC block 166 */ 167 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, 168 unsigned long reg) 169 { 170 if (i2c_dev->is_dvc) 171 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 172 return reg; 173 } 174 175 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 176 unsigned long reg) 177 { 178 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 179 180 /* Read back register to make sure that register writes completed */ 181 if (reg != I2C_TX_FIFO) 182 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 183 } 184 185 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 186 { 187 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 188 } 189 190 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 191 unsigned long reg, int len) 192 { 193 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 194 } 195 196 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 197 unsigned long reg, int len) 198 { 199 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 200 } 201 202 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 203 { 204 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); 205 int_mask &= ~mask; 206 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 207 } 208 209 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 210 { 211 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); 212 int_mask |= mask; 213 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 214 } 215 216 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 217 { 218 unsigned long timeout = jiffies + HZ; 219 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL); 220 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH; 221 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); 222 223 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) & 224 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) { 225 if (time_after(jiffies, timeout)) { 226 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); 227 return -ETIMEDOUT; 228 } 229 msleep(1); 230 } 231 return 0; 232 } 233 234 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 235 { 236 u32 val; 237 int rx_fifo_avail; 238 u8 *buf = i2c_dev->msg_buf; 239 size_t buf_remaining = i2c_dev->msg_buf_remaining; 240 int words_to_transfer; 241 242 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 243 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >> 244 I2C_FIFO_STATUS_RX_SHIFT; 245 246 /* Rounds down to not include partial word at the end of buf */ 247 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 248 if (words_to_transfer > rx_fifo_avail) 249 words_to_transfer = rx_fifo_avail; 250 251 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 252 253 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 254 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 255 rx_fifo_avail -= words_to_transfer; 256 257 /* 258 * If there is a partial word at the end of buf, handle it manually to 259 * prevent overwriting past the end of buf 260 */ 261 if (rx_fifo_avail > 0 && buf_remaining > 0) { 262 BUG_ON(buf_remaining > 3); 263 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 264 memcpy(buf, &val, buf_remaining); 265 buf_remaining = 0; 266 rx_fifo_avail--; 267 } 268 269 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0); 270 i2c_dev->msg_buf_remaining = buf_remaining; 271 i2c_dev->msg_buf = buf; 272 return 0; 273 } 274 275 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 276 { 277 u32 val; 278 int tx_fifo_avail; 279 u8 *buf = i2c_dev->msg_buf; 280 size_t buf_remaining = i2c_dev->msg_buf_remaining; 281 int words_to_transfer; 282 283 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 284 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >> 285 I2C_FIFO_STATUS_TX_SHIFT; 286 287 /* Rounds down to not include partial word at the end of buf */ 288 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 289 290 /* It's very common to have < 4 bytes, so optimize that case. */ 291 if (words_to_transfer) { 292 if (words_to_transfer > tx_fifo_avail) 293 words_to_transfer = tx_fifo_avail; 294 295 /* 296 * Update state before writing to FIFO. If this casues us 297 * to finish writing all bytes (AKA buf_remaining goes to 0) we 298 * have a potential for an interrupt (PACKET_XFER_COMPLETE is 299 * not maskable). We need to make sure that the isr sees 300 * buf_remaining as 0 and doesn't call us back re-entrantly. 301 */ 302 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 303 tx_fifo_avail -= words_to_transfer; 304 i2c_dev->msg_buf_remaining = buf_remaining; 305 i2c_dev->msg_buf = buf + 306 words_to_transfer * BYTES_PER_FIFO_WORD; 307 barrier(); 308 309 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 310 311 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 312 } 313 314 /* 315 * If there is a partial word at the end of buf, handle it manually to 316 * prevent reading past the end of buf, which could cross a page 317 * boundary and fault. 318 */ 319 if (tx_fifo_avail > 0 && buf_remaining > 0) { 320 BUG_ON(buf_remaining > 3); 321 memcpy(&val, buf, buf_remaining); 322 323 /* Again update before writing to FIFO to make sure isr sees. */ 324 i2c_dev->msg_buf_remaining = 0; 325 i2c_dev->msg_buf = NULL; 326 barrier(); 327 328 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 329 } 330 331 return 0; 332 } 333 334 /* 335 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 336 * block. This block is identical to the rest of the I2C blocks, except that 337 * it only supports master mode, it has registers moved around, and it needs 338 * some extra init to get it into I2C mode. The register moves are handled 339 * by i2c_readl and i2c_writel 340 */ 341 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 342 { 343 u32 val = 0; 344 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 345 val |= DVC_CTRL_REG3_SW_PROG; 346 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 347 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 348 349 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 350 val |= DVC_CTRL_REG1_INTR_EN; 351 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 352 } 353 354 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 355 { 356 u32 val; 357 int err = 0; 358 359 clk_prepare_enable(i2c_dev->clk); 360 361 tegra_periph_reset_assert(i2c_dev->clk); 362 udelay(2); 363 tegra_periph_reset_deassert(i2c_dev->clk); 364 365 if (i2c_dev->is_dvc) 366 tegra_dvc_init(i2c_dev); 367 368 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 369 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); 370 i2c_writel(i2c_dev, val, I2C_CNFG); 371 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 372 clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8); 373 374 if (!i2c_dev->is_dvc) { 375 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 376 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 377 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 378 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 379 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 380 381 } 382 383 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT | 384 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT; 385 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); 386 387 if (tegra_i2c_flush_fifos(i2c_dev)) 388 err = -ETIMEDOUT; 389 390 clk_disable_unprepare(i2c_dev->clk); 391 392 if (i2c_dev->irq_disabled) { 393 i2c_dev->irq_disabled = 0; 394 enable_irq(i2c_dev->irq); 395 } 396 397 return err; 398 } 399 400 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 401 { 402 u32 status; 403 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 404 struct tegra_i2c_dev *i2c_dev = dev_id; 405 406 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 407 408 if (status == 0) { 409 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n", 410 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 411 i2c_readl(i2c_dev, I2C_STATUS), 412 i2c_readl(i2c_dev, I2C_CNFG)); 413 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 414 415 if (!i2c_dev->irq_disabled) { 416 disable_irq_nosync(i2c_dev->irq); 417 i2c_dev->irq_disabled = 1; 418 } 419 goto err; 420 } 421 422 if (unlikely(status & status_err)) { 423 if (status & I2C_INT_NO_ACK) 424 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 425 if (status & I2C_INT_ARBITRATION_LOST) 426 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 427 goto err; 428 } 429 430 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 431 if (i2c_dev->msg_buf_remaining) 432 tegra_i2c_empty_rx_fifo(i2c_dev); 433 else 434 BUG(); 435 } 436 437 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 438 if (i2c_dev->msg_buf_remaining) 439 tegra_i2c_fill_tx_fifo(i2c_dev); 440 else 441 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ); 442 } 443 444 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 445 if (i2c_dev->is_dvc) 446 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 447 448 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 449 BUG_ON(i2c_dev->msg_buf_remaining); 450 complete(&i2c_dev->msg_complete); 451 } 452 return IRQ_HANDLED; 453 err: 454 /* An error occurred, mask all interrupts */ 455 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | 456 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ | 457 I2C_INT_RX_FIFO_DATA_REQ); 458 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 459 if (i2c_dev->is_dvc) 460 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 461 462 complete(&i2c_dev->msg_complete); 463 return IRQ_HANDLED; 464 } 465 466 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 467 struct i2c_msg *msg, enum msg_end_type end_state) 468 { 469 u32 packet_header; 470 u32 int_mask; 471 int ret; 472 473 tegra_i2c_flush_fifos(i2c_dev); 474 475 if (msg->len == 0) 476 return -EINVAL; 477 478 i2c_dev->msg_buf = msg->buf; 479 i2c_dev->msg_buf_remaining = msg->len; 480 i2c_dev->msg_err = I2C_ERR_NONE; 481 i2c_dev->msg_read = (msg->flags & I2C_M_RD); 482 INIT_COMPLETION(i2c_dev->msg_complete); 483 484 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | 485 PACKET_HEADER0_PROTOCOL_I2C | 486 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | 487 (1 << PACKET_HEADER0_PACKET_ID_SHIFT); 488 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 489 490 packet_header = msg->len - 1; 491 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 492 493 packet_header = I2C_HEADER_IE_ENABLE; 494 if (end_state == MSG_END_CONTINUE) 495 packet_header |= I2C_HEADER_CONTINUE_XFER; 496 else if (end_state == MSG_END_REPEAT_START) 497 packet_header |= I2C_HEADER_REPEAT_START; 498 if (msg->flags & I2C_M_TEN) { 499 packet_header |= msg->addr; 500 packet_header |= I2C_HEADER_10BIT_ADDR; 501 } else { 502 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 503 } 504 if (msg->flags & I2C_M_IGNORE_NAK) 505 packet_header |= I2C_HEADER_CONT_ON_NAK; 506 if (msg->flags & I2C_M_RD) 507 packet_header |= I2C_HEADER_READ; 508 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 509 510 if (!(msg->flags & I2C_M_RD)) 511 tegra_i2c_fill_tx_fifo(i2c_dev); 512 513 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 514 if (msg->flags & I2C_M_RD) 515 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 516 else if (i2c_dev->msg_buf_remaining) 517 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 518 tegra_i2c_unmask_irq(i2c_dev, int_mask); 519 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", 520 i2c_readl(i2c_dev, I2C_INT_MASK)); 521 522 ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT); 523 tegra_i2c_mask_irq(i2c_dev, int_mask); 524 525 if (WARN_ON(ret == 0)) { 526 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); 527 528 tegra_i2c_init(i2c_dev); 529 return -ETIMEDOUT; 530 } 531 532 dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n", 533 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err); 534 535 if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) 536 return 0; 537 538 /* 539 * NACK interrupt is generated before the I2C controller generates the 540 * STOP condition on the bus. So wait for 2 clock periods before resetting 541 * the controller so that STOP condition has been delivered properly. 542 */ 543 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) 544 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); 545 546 tegra_i2c_init(i2c_dev); 547 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 548 if (msg->flags & I2C_M_IGNORE_NAK) 549 return 0; 550 return -EREMOTEIO; 551 } 552 553 return -EIO; 554 } 555 556 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 557 int num) 558 { 559 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 560 int i; 561 int ret = 0; 562 563 if (i2c_dev->is_suspended) 564 return -EBUSY; 565 566 clk_prepare_enable(i2c_dev->clk); 567 for (i = 0; i < num; i++) { 568 enum msg_end_type end_type = MSG_END_STOP; 569 if (i < (num - 1)) { 570 if (msgs[i + 1].flags & I2C_M_NOSTART) 571 end_type = MSG_END_CONTINUE; 572 else 573 end_type = MSG_END_REPEAT_START; 574 } 575 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 576 if (ret) 577 break; 578 } 579 clk_disable_unprepare(i2c_dev->clk); 580 return ret ?: i; 581 } 582 583 static u32 tegra_i2c_func(struct i2c_adapter *adap) 584 { 585 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | 586 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART; 587 } 588 589 static const struct i2c_algorithm tegra_i2c_algo = { 590 .master_xfer = tegra_i2c_xfer, 591 .functionality = tegra_i2c_func, 592 }; 593 594 static int __devinit tegra_i2c_probe(struct platform_device *pdev) 595 { 596 struct tegra_i2c_dev *i2c_dev; 597 struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data; 598 struct resource *res; 599 struct clk *clk; 600 struct clk *i2c_clk; 601 const unsigned int *prop; 602 void __iomem *base; 603 int irq; 604 int ret = 0; 605 606 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 607 if (!res) { 608 dev_err(&pdev->dev, "no mem resource\n"); 609 return -EINVAL; 610 } 611 612 base = devm_request_and_ioremap(&pdev->dev, res); 613 if (!base) { 614 dev_err(&pdev->dev, "Cannot request/ioremap I2C registers\n"); 615 return -EADDRNOTAVAIL; 616 } 617 618 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 619 if (!res) { 620 dev_err(&pdev->dev, "no irq resource\n"); 621 return -EINVAL; 622 } 623 irq = res->start; 624 625 clk = devm_clk_get(&pdev->dev, NULL); 626 if (IS_ERR(clk)) { 627 dev_err(&pdev->dev, "missing controller clock"); 628 return PTR_ERR(clk); 629 } 630 631 i2c_clk = devm_clk_get(&pdev->dev, "i2c"); 632 if (IS_ERR(i2c_clk)) { 633 dev_err(&pdev->dev, "missing bus clock"); 634 return PTR_ERR(i2c_clk); 635 } 636 637 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 638 if (!i2c_dev) { 639 dev_err(&pdev->dev, "Could not allocate struct tegra_i2c_dev"); 640 return -ENOMEM; 641 } 642 643 i2c_dev->base = base; 644 i2c_dev->clk = clk; 645 i2c_dev->i2c_clk = i2c_clk; 646 i2c_dev->adapter.algo = &tegra_i2c_algo; 647 i2c_dev->irq = irq; 648 i2c_dev->cont_id = pdev->id; 649 i2c_dev->dev = &pdev->dev; 650 651 i2c_dev->bus_clk_rate = 100000; /* default clock rate */ 652 if (pdata) { 653 i2c_dev->bus_clk_rate = pdata->bus_clk_rate; 654 655 } else if (i2c_dev->dev->of_node) { /* if there is a device tree node ... */ 656 prop = of_get_property(i2c_dev->dev->of_node, 657 "clock-frequency", NULL); 658 if (prop) 659 i2c_dev->bus_clk_rate = be32_to_cpup(prop); 660 } 661 662 if (pdev->dev.of_node) 663 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, 664 "nvidia,tegra20-i2c-dvc"); 665 else if (pdev->id == 3) 666 i2c_dev->is_dvc = 1; 667 init_completion(&i2c_dev->msg_complete); 668 669 platform_set_drvdata(pdev, i2c_dev); 670 671 ret = tegra_i2c_init(i2c_dev); 672 if (ret) { 673 dev_err(&pdev->dev, "Failed to initialize i2c controller"); 674 return ret; 675 } 676 677 ret = devm_request_irq(&pdev->dev, i2c_dev->irq, 678 tegra_i2c_isr, 0, pdev->name, i2c_dev); 679 if (ret) { 680 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); 681 return ret; 682 } 683 684 clk_prepare_enable(i2c_dev->i2c_clk); 685 686 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 687 i2c_dev->adapter.owner = THIS_MODULE; 688 i2c_dev->adapter.class = I2C_CLASS_HWMON; 689 strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter", 690 sizeof(i2c_dev->adapter.name)); 691 i2c_dev->adapter.algo = &tegra_i2c_algo; 692 i2c_dev->adapter.dev.parent = &pdev->dev; 693 i2c_dev->adapter.nr = pdev->id; 694 i2c_dev->adapter.dev.of_node = pdev->dev.of_node; 695 696 ret = i2c_add_numbered_adapter(&i2c_dev->adapter); 697 if (ret) { 698 dev_err(&pdev->dev, "Failed to add I2C adapter\n"); 699 clk_disable_unprepare(i2c_dev->i2c_clk); 700 return ret; 701 } 702 703 of_i2c_register_devices(&i2c_dev->adapter); 704 705 return 0; 706 } 707 708 static int __devexit tegra_i2c_remove(struct platform_device *pdev) 709 { 710 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 711 i2c_del_adapter(&i2c_dev->adapter); 712 return 0; 713 } 714 715 #ifdef CONFIG_PM_SLEEP 716 static int tegra_i2c_suspend(struct device *dev) 717 { 718 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 719 720 i2c_lock_adapter(&i2c_dev->adapter); 721 i2c_dev->is_suspended = true; 722 i2c_unlock_adapter(&i2c_dev->adapter); 723 724 return 0; 725 } 726 727 static int tegra_i2c_resume(struct device *dev) 728 { 729 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 730 int ret; 731 732 i2c_lock_adapter(&i2c_dev->adapter); 733 734 ret = tegra_i2c_init(i2c_dev); 735 736 if (ret) { 737 i2c_unlock_adapter(&i2c_dev->adapter); 738 return ret; 739 } 740 741 i2c_dev->is_suspended = false; 742 743 i2c_unlock_adapter(&i2c_dev->adapter); 744 745 return 0; 746 } 747 748 static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume); 749 #define TEGRA_I2C_PM (&tegra_i2c_pm) 750 #else 751 #define TEGRA_I2C_PM NULL 752 #endif 753 754 #if defined(CONFIG_OF) 755 /* Match table for of_platform binding */ 756 static const struct of_device_id tegra_i2c_of_match[] __devinitconst = { 757 { .compatible = "nvidia,tegra20-i2c", }, 758 { .compatible = "nvidia,tegra20-i2c-dvc", }, 759 {}, 760 }; 761 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 762 #endif 763 764 static struct platform_driver tegra_i2c_driver = { 765 .probe = tegra_i2c_probe, 766 .remove = __devexit_p(tegra_i2c_remove), 767 .driver = { 768 .name = "tegra-i2c", 769 .owner = THIS_MODULE, 770 .of_match_table = of_match_ptr(tegra_i2c_of_match), 771 .pm = TEGRA_I2C_PM, 772 }, 773 }; 774 775 static int __init tegra_i2c_init_driver(void) 776 { 777 return platform_driver_register(&tegra_i2c_driver); 778 } 779 780 static void __exit tegra_i2c_exit_driver(void) 781 { 782 platform_driver_unregister(&tegra_i2c_driver); 783 } 784 785 subsys_initcall(tegra_i2c_init_driver); 786 module_exit(tegra_i2c_exit_driver); 787 788 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver"); 789 MODULE_AUTHOR("Colin Cross"); 790 MODULE_LICENSE("GPL v2"); 791