1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/i2c/busses/i2c-tegra.c 4 * 5 * Copyright (C) 2010 Google, Inc. 6 * Author: Colin Cross <ccross@android.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/dmaengine.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/irq.h> 22 #include <linux/kernel.h> 23 #include <linux/ktime.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/reset.h> 30 31 #define BYTES_PER_FIFO_WORD 4 32 33 #define I2C_CNFG 0x000 34 #define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12) 35 #define I2C_CNFG_PACKET_MODE_EN BIT(10) 36 #define I2C_CNFG_NEW_MASTER_FSM BIT(11) 37 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) 38 #define I2C_STATUS 0x01c 39 #define I2C_SL_CNFG 0x020 40 #define I2C_SL_CNFG_NACK BIT(1) 41 #define I2C_SL_CNFG_NEWSL BIT(2) 42 #define I2C_SL_ADDR1 0x02c 43 #define I2C_SL_ADDR2 0x030 44 #define I2C_TLOW_SEXT 0x034 45 #define I2C_TX_FIFO 0x050 46 #define I2C_RX_FIFO 0x054 47 #define I2C_PACKET_TRANSFER_STATUS 0x058 48 #define I2C_FIFO_CONTROL 0x05c 49 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 50 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 51 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5) 52 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2) 53 #define I2C_FIFO_STATUS 0x060 54 #define I2C_FIFO_STATUS_TX GENMASK(7, 4) 55 #define I2C_FIFO_STATUS_RX GENMASK(3, 0) 56 #define I2C_INT_MASK 0x064 57 #define I2C_INT_STATUS 0x068 58 #define I2C_INT_BUS_CLR_DONE BIT(11) 59 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 60 #define I2C_INT_NO_ACK BIT(3) 61 #define I2C_INT_ARBITRATION_LOST BIT(2) 62 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) 63 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) 64 #define I2C_CLK_DIVISOR 0x06c 65 #define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16) 66 #define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0) 67 68 #define DVC_CTRL_REG1 0x000 69 #define DVC_CTRL_REG1_INTR_EN BIT(10) 70 #define DVC_CTRL_REG3 0x008 71 #define DVC_CTRL_REG3_SW_PROG BIT(26) 72 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30) 73 #define DVC_STATUS 0x00c 74 #define DVC_STATUS_I2C_DONE_INTR BIT(30) 75 76 #define I2C_ERR_NONE 0x00 77 #define I2C_ERR_NO_ACK BIT(0) 78 #define I2C_ERR_ARBITRATION_LOST BIT(1) 79 #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2) 80 #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3) 81 82 #define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28) 83 #define PACKET_HEADER0_PACKET_ID GENMASK(23, 16) 84 #define PACKET_HEADER0_CONT_ID GENMASK(15, 12) 85 #define PACKET_HEADER0_PROTOCOL GENMASK(7, 4) 86 #define PACKET_HEADER0_PROTOCOL_I2C 1 87 88 #define I2C_HEADER_CONT_ON_NAK BIT(21) 89 #define I2C_HEADER_READ BIT(19) 90 #define I2C_HEADER_10BIT_ADDR BIT(18) 91 #define I2C_HEADER_IE_ENABLE BIT(17) 92 #define I2C_HEADER_REPEAT_START BIT(16) 93 #define I2C_HEADER_CONTINUE_XFER BIT(15) 94 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 95 96 #define I2C_BUS_CLEAR_CNFG 0x084 97 #define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16) 98 #define I2C_BC_STOP_COND BIT(2) 99 #define I2C_BC_TERMINATE BIT(1) 100 #define I2C_BC_ENABLE BIT(0) 101 #define I2C_BUS_CLEAR_STATUS 0x088 102 #define I2C_BC_STATUS BIT(0) 103 104 #define I2C_CONFIG_LOAD 0x08c 105 #define I2C_MSTR_CONFIG_LOAD BIT(0) 106 107 #define I2C_CLKEN_OVERRIDE 0x090 108 #define I2C_MST_CORE_CLKEN_OVR BIT(0) 109 110 #define I2C_INTERFACE_TIMING_0 0x094 111 #define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8) 112 #define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0) 113 #define I2C_INTERFACE_TIMING_1 0x098 114 #define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24) 115 #define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 116 #define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 117 #define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 118 119 #define I2C_HS_INTERFACE_TIMING_0 0x09c 120 #define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8) 121 #define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0) 122 #define I2C_HS_INTERFACE_TIMING_1 0x0a0 123 #define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 124 #define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 125 #define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 126 127 #define I2C_MST_FIFO_CONTROL 0x0b4 128 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) 129 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) 130 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4) 131 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16) 132 133 #define I2C_MST_FIFO_STATUS 0x0b8 134 #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) 135 #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) 136 137 /* configuration load timeout in microseconds */ 138 #define I2C_CONFIG_LOAD_TIMEOUT 1000000 139 140 /* packet header size in bytes */ 141 #define I2C_PACKET_HEADER_SIZE 12 142 143 /* 144 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to 145 * avoid DMA overhead, otherwise external APB DMA controller will be used. 146 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include 147 * I2C_PACKET_HEADER_SIZE. 148 */ 149 #define I2C_PIO_MODE_PREFERRED_LEN 32 150 151 /* 152 * msg_end_type: The bus control which needs to be sent at end of transfer. 153 * @MSG_END_STOP: Send stop pulse. 154 * @MSG_END_REPEAT_START: Send repeat-start. 155 * @MSG_END_CONTINUE: Don't send stop or repeat-start. 156 */ 157 enum msg_end_type { 158 MSG_END_STOP, 159 MSG_END_REPEAT_START, 160 MSG_END_CONTINUE, 161 }; 162 163 /** 164 * struct tegra_i2c_hw_feature : per hardware generation features 165 * @has_continue_xfer_support: continue-transfer supported 166 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer 167 * completion interrupt on per packet basis. 168 * @has_config_load_reg: Has the config load register to load the new 169 * configuration. 170 * @clk_divisor_hs_mode: Clock divisor in HS mode. 171 * @clk_divisor_std_mode: Clock divisor in standard mode. It is 172 * applicable if there is no fast clock source i.e. single clock 173 * source. 174 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is 175 * applicable if there is no fast clock source i.e. single clock 176 * source. 177 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is 178 * applicable if there is no fast clock source (i.e. single 179 * clock source). 180 * @has_multi_master_mode: The I2C controller supports running in single-master 181 * or multi-master mode. 182 * @has_slcg_override_reg: The I2C controller supports a register that 183 * overrides the second level clock gating. 184 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that 185 * provides additional features and allows for longer messages to 186 * be transferred in one go. 187 * @quirks: I2C adapter quirks for limiting write/read transfer size and not 188 * allowing 0 length transfers. 189 * @supports_bus_clear: Bus Clear support to recover from bus hang during 190 * SDA stuck low from device for some unknown reasons. 191 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip. 192 * @tlow_std_mode: Low period of the clock in standard mode. 193 * @thigh_std_mode: High period of the clock in standard mode. 194 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes. 195 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes. 196 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions 197 * in standard mode. 198 * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop 199 * conditions in fast/fast-plus modes. 200 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions 201 * in HS mode. 202 * @has_interface_timing_reg: Has interface timing register to program the tuned 203 * timing settings. 204 */ 205 struct tegra_i2c_hw_feature { 206 bool has_continue_xfer_support; 207 bool has_per_pkt_xfer_complete_irq; 208 bool has_config_load_reg; 209 u32 clk_divisor_hs_mode; 210 u32 clk_divisor_std_mode; 211 u32 clk_divisor_fast_mode; 212 u32 clk_divisor_fast_plus_mode; 213 bool has_multi_master_mode; 214 bool has_slcg_override_reg; 215 bool has_mst_fifo; 216 const struct i2c_adapter_quirks *quirks; 217 bool supports_bus_clear; 218 bool has_apb_dma; 219 u32 tlow_std_mode; 220 u32 thigh_std_mode; 221 u32 tlow_fast_fastplus_mode; 222 u32 thigh_fast_fastplus_mode; 223 u32 setup_hold_time_std_mode; 224 u32 setup_hold_time_fast_fast_plus_mode; 225 u32 setup_hold_time_hs_mode; 226 bool has_interface_timing_reg; 227 }; 228 229 /** 230 * struct tegra_i2c_dev - per device I2C context 231 * @dev: device reference for power management 232 * @hw: Tegra I2C HW feature 233 * @adapter: core I2C layer adapter information 234 * @div_clk: clock reference for div clock of I2C controller 235 * @clocks: array of I2C controller clocks 236 * @nclocks: number of clocks in the array 237 * @rst: reset control for the I2C controller 238 * @base: ioremapped registers cookie 239 * @base_phys: physical base address of the I2C controller 240 * @cont_id: I2C controller ID, used for packet header 241 * @irq: IRQ number of transfer complete interrupt 242 * @is_dvc: identifies the DVC I2C controller, has a different register layout 243 * @is_vi: identifies the VI I2C controller, has a different register layout 244 * @msg_complete: transfer completion notifier 245 * @msg_buf_remaining: size of unsent data in the message buffer 246 * @msg_len: length of message in current transfer 247 * @msg_err: error code for completed message 248 * @msg_buf: pointer to current message data 249 * @msg_read: indicates that the transfer is a read access 250 * @timings: i2c timings information like bus frequency 251 * @multimaster_mode: indicates that I2C controller is in multi-master mode 252 * @dma_chan: DMA channel 253 * @dma_phys: handle to DMA resources 254 * @dma_buf: pointer to allocated DMA buffer 255 * @dma_buf_size: DMA buffer size 256 * @dma_dev: DMA device used for transfers 257 * @dma_mode: indicates active DMA transfer 258 * @dma_complete: DMA completion notifier 259 * @atomic_mode: indicates active atomic transfer 260 */ 261 struct tegra_i2c_dev { 262 struct device *dev; 263 struct i2c_adapter adapter; 264 265 const struct tegra_i2c_hw_feature *hw; 266 struct reset_control *rst; 267 unsigned int cont_id; 268 unsigned int irq; 269 270 phys_addr_t base_phys; 271 void __iomem *base; 272 273 struct clk_bulk_data clocks[2]; 274 unsigned int nclocks; 275 276 struct clk *div_clk; 277 struct i2c_timings timings; 278 279 struct completion msg_complete; 280 size_t msg_buf_remaining; 281 unsigned int msg_len; 282 int msg_err; 283 u8 *msg_buf; 284 285 struct completion dma_complete; 286 struct dma_chan *dma_chan; 287 unsigned int dma_buf_size; 288 struct device *dma_dev; 289 dma_addr_t dma_phys; 290 void *dma_buf; 291 292 bool multimaster_mode; 293 bool atomic_mode; 294 bool dma_mode; 295 bool msg_read; 296 bool is_dvc; 297 bool is_vi; 298 }; 299 300 #define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && (dev)->is_dvc) 301 #define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && (dev)->is_vi) 302 303 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 304 unsigned int reg) 305 { 306 writel_relaxed(val, i2c_dev->base + reg); 307 } 308 309 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 310 { 311 return readl_relaxed(i2c_dev->base + reg); 312 } 313 314 /* 315 * If necessary, i2c_writel() and i2c_readl() will offset the register 316 * in order to talk to the I2C block inside the DVC block. 317 */ 318 static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 319 { 320 if (IS_DVC(i2c_dev)) 321 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 322 else if (IS_VI(i2c_dev)) 323 reg = 0xc00 + (reg << 2); 324 325 return reg; 326 } 327 328 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg) 329 { 330 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 331 332 /* read back register to make sure that register writes completed */ 333 if (reg != I2C_TX_FIFO) 334 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 335 else if (IS_VI(i2c_dev)) 336 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS)); 337 } 338 339 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 340 { 341 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 342 } 343 344 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 345 unsigned int reg, unsigned int len) 346 { 347 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 348 } 349 350 static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data, 351 unsigned int reg, unsigned int len) 352 { 353 u32 *data32 = data; 354 355 /* 356 * VI I2C controller has known hardware bug where writes get stuck 357 * when immediate multiple writes happen to TX_FIFO register. 358 * Recommended software work around is to read I2C register after 359 * each write to TX_FIFO register to flush out the data. 360 */ 361 while (len--) 362 i2c_writel(i2c_dev, *data32++, reg); 363 } 364 365 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 366 unsigned int reg, unsigned int len) 367 { 368 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 369 } 370 371 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 372 { 373 u32 int_mask; 374 375 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; 376 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 377 } 378 379 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 380 { 381 u32 int_mask; 382 383 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; 384 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 385 } 386 387 static void tegra_i2c_dma_complete(void *args) 388 { 389 struct tegra_i2c_dev *i2c_dev = args; 390 391 complete(&i2c_dev->dma_complete); 392 } 393 394 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len) 395 { 396 struct dma_async_tx_descriptor *dma_desc; 397 enum dma_transfer_direction dir; 398 399 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len); 400 401 reinit_completion(&i2c_dev->dma_complete); 402 403 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 404 405 dma_desc = dmaengine_prep_slave_single(i2c_dev->dma_chan, i2c_dev->dma_phys, 406 len, dir, DMA_PREP_INTERRUPT | 407 DMA_CTRL_ACK); 408 if (!dma_desc) { 409 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n", 410 i2c_dev->msg_read ? "RX" : "TX"); 411 return -EINVAL; 412 } 413 414 dma_desc->callback = tegra_i2c_dma_complete; 415 dma_desc->callback_param = i2c_dev; 416 417 dmaengine_submit(dma_desc); 418 dma_async_issue_pending(i2c_dev->dma_chan); 419 420 return 0; 421 } 422 423 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev) 424 { 425 if (i2c_dev->dma_buf) { 426 dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, 427 i2c_dev->dma_buf, i2c_dev->dma_phys); 428 i2c_dev->dma_buf = NULL; 429 } 430 431 if (i2c_dev->dma_chan) { 432 dma_release_channel(i2c_dev->dma_chan); 433 i2c_dev->dma_chan = NULL; 434 } 435 } 436 437 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) 438 { 439 dma_addr_t dma_phys; 440 u32 *dma_buf; 441 int err; 442 443 if (IS_VI(i2c_dev)) 444 return 0; 445 446 if (i2c_dev->hw->has_apb_dma) { 447 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { 448 dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n"); 449 return 0; 450 } 451 } else if (!IS_ENABLED(CONFIG_TEGRA186_GPC_DMA)) { 452 dev_dbg(i2c_dev->dev, "GPC DMA support not enabled\n"); 453 return 0; 454 } 455 456 /* 457 * The same channel will be used for both RX and TX. 458 * Keeping the name as "tx" for backward compatibility 459 * with existing devicetrees. 460 */ 461 i2c_dev->dma_chan = dma_request_chan(i2c_dev->dev, "tx"); 462 if (IS_ERR(i2c_dev->dma_chan)) { 463 err = PTR_ERR(i2c_dev->dma_chan); 464 i2c_dev->dma_chan = NULL; 465 goto err_out; 466 } 467 468 i2c_dev->dma_dev = i2c_dev->dma_chan->device->dev; 469 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len + 470 I2C_PACKET_HEADER_SIZE; 471 472 dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, 473 &dma_phys, GFP_KERNEL | __GFP_NOWARN); 474 if (!dma_buf) { 475 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n"); 476 err = -ENOMEM; 477 goto err_out; 478 } 479 480 i2c_dev->dma_buf = dma_buf; 481 i2c_dev->dma_phys = dma_phys; 482 483 return 0; 484 485 err_out: 486 tegra_i2c_release_dma(i2c_dev); 487 if (err != -EPROBE_DEFER) { 488 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); 489 dev_err(i2c_dev->dev, "falling back to PIO\n"); 490 return 0; 491 } 492 493 return err; 494 } 495 496 /* 497 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 498 * block. This block is identical to the rest of the I2C blocks, except that 499 * it only supports master mode, it has registers moved around, and it needs 500 * some extra init to get it into I2C mode. The register moves are handled 501 * by i2c_readl() and i2c_writel(). 502 */ 503 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 504 { 505 u32 val; 506 507 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 508 val |= DVC_CTRL_REG3_SW_PROG; 509 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 510 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 511 512 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 513 val |= DVC_CTRL_REG1_INTR_EN; 514 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 515 } 516 517 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev) 518 { 519 u32 value; 520 521 value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) | 522 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4); 523 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0); 524 525 value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) | 526 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) | 527 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) | 528 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4); 529 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1); 530 531 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) | 532 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8); 533 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0); 534 535 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) | 536 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) | 537 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11); 538 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1); 539 540 value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND; 541 i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG); 542 543 i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT); 544 } 545 546 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, 547 u32 reg, u32 mask, u32 delay_us, 548 u32 timeout_us) 549 { 550 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); 551 u32 val; 552 553 if (!i2c_dev->atomic_mode) 554 return readl_relaxed_poll_timeout(addr, val, !(val & mask), 555 delay_us, timeout_us); 556 557 return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask), 558 delay_us, timeout_us); 559 } 560 561 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 562 { 563 u32 mask, val, offset; 564 int err; 565 566 if (i2c_dev->hw->has_mst_fifo) { 567 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH | 568 I2C_MST_FIFO_CONTROL_RX_FLUSH; 569 offset = I2C_MST_FIFO_CONTROL; 570 } else { 571 mask = I2C_FIFO_CONTROL_TX_FLUSH | 572 I2C_FIFO_CONTROL_RX_FLUSH; 573 offset = I2C_FIFO_CONTROL; 574 } 575 576 val = i2c_readl(i2c_dev, offset); 577 val |= mask; 578 i2c_writel(i2c_dev, val, offset); 579 580 err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000); 581 if (err) { 582 dev_err(i2c_dev->dev, "failed to flush FIFO\n"); 583 return err; 584 } 585 586 return 0; 587 } 588 589 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) 590 { 591 int err; 592 593 if (!i2c_dev->hw->has_config_load_reg) 594 return 0; 595 596 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); 597 598 err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff, 599 1000, I2C_CONFIG_LOAD_TIMEOUT); 600 if (err) { 601 dev_err(i2c_dev->dev, "failed to load config\n"); 602 return err; 603 } 604 605 return 0; 606 } 607 608 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 609 { 610 u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; 611 struct i2c_timings *t = &i2c_dev->timings; 612 int err; 613 614 /* 615 * The reset shouldn't ever fail in practice. The failure will be a 616 * sign of a severe problem that needs to be resolved. Still we don't 617 * want to fail the initialization completely because this may break 618 * kernel boot up since voltage regulators use I2C. Hence, we will 619 * emit a noisy warning on error, which won't stay unnoticed and 620 * won't hose machine entirely. 621 */ 622 err = device_reset(i2c_dev->dev); 623 WARN_ON_ONCE(err); 624 625 if (IS_DVC(i2c_dev)) 626 tegra_dvc_init(i2c_dev); 627 628 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 629 FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2); 630 631 if (i2c_dev->hw->has_multi_master_mode) 632 val |= I2C_CNFG_MULTI_MASTER_MODE; 633 634 i2c_writel(i2c_dev, val, I2C_CNFG); 635 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 636 637 if (IS_VI(i2c_dev)) 638 tegra_i2c_vi_init(i2c_dev); 639 640 switch (t->bus_freq_hz) { 641 case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: 642 default: 643 tlow = i2c_dev->hw->tlow_fast_fastplus_mode; 644 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; 645 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; 646 647 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) 648 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; 649 else 650 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; 651 break; 652 653 case 0 ... I2C_MAX_STANDARD_MODE_FREQ: 654 tlow = i2c_dev->hw->tlow_std_mode; 655 thigh = i2c_dev->hw->thigh_std_mode; 656 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; 657 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; 658 break; 659 } 660 661 /* make sure clock divisor programmed correctly */ 662 clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, 663 i2c_dev->hw->clk_divisor_hs_mode) | 664 FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode); 665 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 666 667 if (i2c_dev->hw->has_interface_timing_reg) { 668 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) | 669 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow); 670 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); 671 } 672 673 /* 674 * Configure setup and hold times only when tsu_thd is non-zero. 675 * Otherwise, preserve the chip default values. 676 */ 677 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) 678 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); 679 680 clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); 681 682 err = clk_set_rate(i2c_dev->div_clk, 683 t->bus_freq_hz * clk_multiplier); 684 if (err) { 685 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); 686 return err; 687 } 688 689 if (!IS_DVC(i2c_dev) && !IS_VI(i2c_dev)) { 690 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 691 692 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 693 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 694 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 695 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 696 } 697 698 err = tegra_i2c_flush_fifos(i2c_dev); 699 if (err) 700 return err; 701 702 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg) 703 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); 704 705 err = tegra_i2c_wait_for_config_load(i2c_dev); 706 if (err) 707 return err; 708 709 return 0; 710 } 711 712 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) 713 { 714 u32 cnfg; 715 716 /* 717 * NACK interrupt is generated before the I2C controller generates 718 * the STOP condition on the bus. So, wait for 2 clock periods 719 * before disabling the controller so that the STOP condition has 720 * been delivered properly. 721 */ 722 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz)); 723 724 cnfg = i2c_readl(i2c_dev, I2C_CNFG); 725 if (cnfg & I2C_CNFG_PACKET_MODE_EN) 726 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); 727 728 return tegra_i2c_wait_for_config_load(i2c_dev); 729 } 730 731 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 732 { 733 size_t buf_remaining = i2c_dev->msg_buf_remaining; 734 unsigned int words_to_transfer, rx_fifo_avail; 735 u8 *buf = i2c_dev->msg_buf; 736 u32 val; 737 738 /* 739 * Catch overflow due to message fully sent before the check for 740 * RX FIFO availability. 741 */ 742 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining))) 743 return -EINVAL; 744 745 if (i2c_dev->hw->has_mst_fifo) { 746 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 747 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val); 748 } else { 749 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 750 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val); 751 } 752 753 /* round down to exclude partial word at the end of buffer */ 754 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 755 if (words_to_transfer > rx_fifo_avail) 756 words_to_transfer = rx_fifo_avail; 757 758 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 759 760 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 761 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 762 rx_fifo_avail -= words_to_transfer; 763 764 /* 765 * If there is a partial word at the end of buffer, handle it 766 * manually to prevent overwriting past the end of buffer. 767 */ 768 if (rx_fifo_avail > 0 && buf_remaining > 0) { 769 /* 770 * buf_remaining > 3 check not needed as rx_fifo_avail == 0 771 * when (words_to_transfer was > rx_fifo_avail) earlier 772 * in this function. 773 */ 774 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 775 val = cpu_to_le32(val); 776 memcpy(buf, &val, buf_remaining); 777 buf_remaining = 0; 778 rx_fifo_avail--; 779 } 780 781 /* RX FIFO must be drained, otherwise it's an Overflow case. */ 782 if (WARN_ON_ONCE(rx_fifo_avail)) 783 return -EINVAL; 784 785 i2c_dev->msg_buf_remaining = buf_remaining; 786 i2c_dev->msg_buf = buf; 787 788 return 0; 789 } 790 791 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 792 { 793 size_t buf_remaining = i2c_dev->msg_buf_remaining; 794 unsigned int words_to_transfer, tx_fifo_avail; 795 u8 *buf = i2c_dev->msg_buf; 796 u32 val; 797 798 if (i2c_dev->hw->has_mst_fifo) { 799 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 800 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val); 801 } else { 802 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 803 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val); 804 } 805 806 /* round down to exclude partial word at the end of buffer */ 807 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 808 809 /* 810 * This hunk pushes 4 bytes at a time into the TX FIFO. 811 * 812 * It's very common to have < 4 bytes, hence there is no word 813 * to push if we have less than 4 bytes to transfer. 814 */ 815 if (words_to_transfer) { 816 if (words_to_transfer > tx_fifo_avail) 817 words_to_transfer = tx_fifo_avail; 818 819 /* 820 * Update state before writing to FIFO. Note that this may 821 * cause us to finish writing all bytes (AKA buf_remaining 822 * goes to 0), hence we have a potential for an interrupt 823 * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt 824 * is disabled at this point. 825 */ 826 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 827 tx_fifo_avail -= words_to_transfer; 828 829 i2c_dev->msg_buf_remaining = buf_remaining; 830 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD; 831 832 if (IS_VI(i2c_dev)) 833 i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 834 else 835 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 836 837 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 838 } 839 840 /* 841 * If there is a partial word at the end of buffer, handle it manually 842 * to prevent reading past the end of buffer, which could cross a page 843 * boundary and fault. 844 */ 845 if (tx_fifo_avail > 0 && buf_remaining > 0) { 846 /* 847 * buf_remaining > 3 check not needed as tx_fifo_avail == 0 848 * when (words_to_transfer was > tx_fifo_avail) earlier 849 * in this function for non-zero words_to_transfer. 850 */ 851 memcpy(&val, buf, buf_remaining); 852 val = le32_to_cpu(val); 853 854 i2c_dev->msg_buf_remaining = 0; 855 i2c_dev->msg_buf = NULL; 856 857 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 858 } 859 860 return 0; 861 } 862 863 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 864 { 865 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 866 struct tegra_i2c_dev *i2c_dev = dev_id; 867 u32 status; 868 869 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 870 871 if (status == 0) { 872 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n", 873 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 874 i2c_readl(i2c_dev, I2C_STATUS), 875 i2c_readl(i2c_dev, I2C_CNFG)); 876 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 877 goto err; 878 } 879 880 if (status & status_err) { 881 tegra_i2c_disable_packet_mode(i2c_dev); 882 if (status & I2C_INT_NO_ACK) 883 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 884 if (status & I2C_INT_ARBITRATION_LOST) 885 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 886 goto err; 887 } 888 889 /* 890 * I2C transfer is terminated during the bus clear, so skip 891 * processing the other interrupts. 892 */ 893 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE)) 894 goto err; 895 896 if (!i2c_dev->dma_mode) { 897 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 898 if (tegra_i2c_empty_rx_fifo(i2c_dev)) { 899 /* 900 * Overflow error condition: message fully sent, 901 * with no XFER_COMPLETE interrupt but hardware 902 * asks to transfer more. 903 */ 904 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW; 905 goto err; 906 } 907 } 908 909 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 910 if (i2c_dev->msg_buf_remaining) 911 tegra_i2c_fill_tx_fifo(i2c_dev); 912 else 913 tegra_i2c_mask_irq(i2c_dev, 914 I2C_INT_TX_FIFO_DATA_REQ); 915 } 916 } 917 918 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 919 if (IS_DVC(i2c_dev)) 920 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 921 922 /* 923 * During message read XFER_COMPLETE interrupt is triggered prior to 924 * DMA completion and during message write XFER_COMPLETE interrupt is 925 * triggered after DMA completion. 926 * 927 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer, 928 * so forcing msg_buf_remaining to 0 in DMA mode. 929 */ 930 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 931 if (i2c_dev->dma_mode) 932 i2c_dev->msg_buf_remaining = 0; 933 /* 934 * Underflow error condition: XFER_COMPLETE before message 935 * fully sent. 936 */ 937 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { 938 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 939 goto err; 940 } 941 complete(&i2c_dev->msg_complete); 942 } 943 goto done; 944 err: 945 /* mask all interrupts on error */ 946 tegra_i2c_mask_irq(i2c_dev, 947 I2C_INT_NO_ACK | 948 I2C_INT_ARBITRATION_LOST | 949 I2C_INT_PACKET_XFER_COMPLETE | 950 I2C_INT_TX_FIFO_DATA_REQ | 951 I2C_INT_RX_FIFO_DATA_REQ); 952 953 if (i2c_dev->hw->supports_bus_clear) 954 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 955 956 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 957 958 if (IS_DVC(i2c_dev)) 959 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 960 961 if (i2c_dev->dma_mode) { 962 dmaengine_terminate_async(i2c_dev->dma_chan); 963 complete(&i2c_dev->dma_complete); 964 } 965 966 complete(&i2c_dev->msg_complete); 967 done: 968 return IRQ_HANDLED; 969 } 970 971 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev, 972 size_t len) 973 { 974 struct dma_slave_config slv_config = {0}; 975 u32 val, reg, dma_burst, reg_offset; 976 int err; 977 978 if (i2c_dev->hw->has_mst_fifo) 979 reg = I2C_MST_FIFO_CONTROL; 980 else 981 reg = I2C_FIFO_CONTROL; 982 983 if (i2c_dev->dma_mode) { 984 if (len & 0xF) 985 dma_burst = 1; 986 else if (len & 0x10) 987 dma_burst = 4; 988 else 989 dma_burst = 8; 990 991 if (i2c_dev->msg_read) { 992 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO); 993 994 slv_config.src_addr = i2c_dev->base_phys + reg_offset; 995 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 996 slv_config.src_maxburst = dma_burst; 997 998 if (i2c_dev->hw->has_mst_fifo) 999 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst); 1000 else 1001 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst); 1002 } else { 1003 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO); 1004 1005 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; 1006 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1007 slv_config.dst_maxburst = dma_burst; 1008 1009 if (i2c_dev->hw->has_mst_fifo) 1010 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst); 1011 else 1012 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst); 1013 } 1014 1015 slv_config.device_fc = true; 1016 err = dmaengine_slave_config(i2c_dev->dma_chan, &slv_config); 1017 if (err) { 1018 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err); 1019 dev_err(i2c_dev->dev, "falling back to PIO\n"); 1020 1021 tegra_i2c_release_dma(i2c_dev); 1022 i2c_dev->dma_mode = false; 1023 } else { 1024 goto out; 1025 } 1026 } 1027 1028 if (i2c_dev->hw->has_mst_fifo) 1029 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) | 1030 I2C_MST_FIFO_CONTROL_RX_TRIG(1); 1031 else 1032 val = I2C_FIFO_CONTROL_TX_TRIG(8) | 1033 I2C_FIFO_CONTROL_RX_TRIG(1); 1034 out: 1035 i2c_writel(i2c_dev, val, reg); 1036 } 1037 1038 static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev, 1039 struct completion *complete, 1040 unsigned int timeout_ms) 1041 { 1042 ktime_t ktime = ktime_get(); 1043 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms); 1044 1045 do { 1046 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 1047 1048 if (status) 1049 tegra_i2c_isr(i2c_dev->irq, i2c_dev); 1050 1051 if (completion_done(complete)) { 1052 s64 delta = ktime_ms_delta(ktimeout, ktime); 1053 1054 return msecs_to_jiffies(delta) ?: 1; 1055 } 1056 1057 ktime = ktime_get(); 1058 1059 } while (ktime_before(ktime, ktimeout)); 1060 1061 return 0; 1062 } 1063 1064 static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev, 1065 struct completion *complete, 1066 unsigned int timeout_ms) 1067 { 1068 unsigned long ret; 1069 1070 if (i2c_dev->atomic_mode) { 1071 ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms); 1072 } else { 1073 enable_irq(i2c_dev->irq); 1074 ret = wait_for_completion_timeout(complete, 1075 msecs_to_jiffies(timeout_ms)); 1076 disable_irq(i2c_dev->irq); 1077 1078 /* 1079 * Under some rare circumstances (like running KASAN + 1080 * NFS root) CPU, which handles interrupt, may stuck in 1081 * uninterruptible state for a significant time. In this 1082 * case we will get timeout if I2C transfer is running on 1083 * a sibling CPU, despite of IRQ being raised. 1084 * 1085 * In order to handle this rare condition, the IRQ status 1086 * needs to be checked after timeout. 1087 */ 1088 if (ret == 0) 1089 ret = tegra_i2c_poll_completion(i2c_dev, complete, 0); 1090 } 1091 1092 return ret; 1093 } 1094 1095 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap) 1096 { 1097 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1098 u32 val, time_left; 1099 int err; 1100 1101 reinit_completion(&i2c_dev->msg_complete); 1102 1103 val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND | 1104 I2C_BC_TERMINATE; 1105 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1106 1107 err = tegra_i2c_wait_for_config_load(i2c_dev); 1108 if (err) 1109 return err; 1110 1111 val |= I2C_BC_ENABLE; 1112 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1113 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1114 1115 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50); 1116 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1117 1118 if (time_left == 0) { 1119 dev_err(i2c_dev->dev, "failed to clear bus\n"); 1120 return -ETIMEDOUT; 1121 } 1122 1123 val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS); 1124 if (!(val & I2C_BC_STATUS)) { 1125 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n"); 1126 return -EIO; 1127 } 1128 1129 return -EAGAIN; 1130 } 1131 1132 static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev, 1133 struct i2c_msg *msg, 1134 enum msg_end_type end_state) 1135 { 1136 u32 *dma_buf = i2c_dev->dma_buf; 1137 u32 packet_header; 1138 1139 packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) | 1140 FIELD_PREP(PACKET_HEADER0_PROTOCOL, 1141 PACKET_HEADER0_PROTOCOL_I2C) | 1142 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) | 1143 FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1); 1144 1145 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1146 *dma_buf++ = packet_header; 1147 else 1148 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1149 1150 packet_header = i2c_dev->msg_len - 1; 1151 1152 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1153 *dma_buf++ = packet_header; 1154 else 1155 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1156 1157 packet_header = I2C_HEADER_IE_ENABLE; 1158 1159 if (end_state == MSG_END_CONTINUE) 1160 packet_header |= I2C_HEADER_CONTINUE_XFER; 1161 else if (end_state == MSG_END_REPEAT_START) 1162 packet_header |= I2C_HEADER_REPEAT_START; 1163 1164 if (msg->flags & I2C_M_TEN) { 1165 packet_header |= msg->addr; 1166 packet_header |= I2C_HEADER_10BIT_ADDR; 1167 } else { 1168 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 1169 } 1170 1171 if (msg->flags & I2C_M_IGNORE_NAK) 1172 packet_header |= I2C_HEADER_CONT_ON_NAK; 1173 1174 if (msg->flags & I2C_M_RD) 1175 packet_header |= I2C_HEADER_READ; 1176 1177 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1178 *dma_buf++ = packet_header; 1179 else 1180 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1181 } 1182 1183 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev, 1184 struct i2c_msg *msg) 1185 { 1186 if (i2c_dev->msg_err == I2C_ERR_NONE) 1187 return 0; 1188 1189 tegra_i2c_init(i2c_dev); 1190 1191 /* start recovery upon arbitration loss in single master mode */ 1192 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) { 1193 if (!i2c_dev->multimaster_mode) 1194 return i2c_recover_bus(&i2c_dev->adapter); 1195 1196 return -EAGAIN; 1197 } 1198 1199 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 1200 if (msg->flags & I2C_M_IGNORE_NAK) 1201 return 0; 1202 1203 return -EREMOTEIO; 1204 } 1205 1206 return -EIO; 1207 } 1208 1209 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 1210 struct i2c_msg *msg, 1211 enum msg_end_type end_state) 1212 { 1213 unsigned long time_left, xfer_time = 100; 1214 size_t xfer_size; 1215 u32 int_mask; 1216 int err; 1217 1218 err = tegra_i2c_flush_fifos(i2c_dev); 1219 if (err) 1220 return err; 1221 1222 i2c_dev->msg_buf = msg->buf; 1223 i2c_dev->msg_len = msg->len; 1224 1225 i2c_dev->msg_err = I2C_ERR_NONE; 1226 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD); 1227 reinit_completion(&i2c_dev->msg_complete); 1228 1229 /* 1230 * For SMBUS block read command, read only 1 byte in the first transfer. 1231 * Adjust that 1 byte for the next transfer in the msg buffer and msg 1232 * length. 1233 */ 1234 if (msg->flags & I2C_M_RECV_LEN) { 1235 if (end_state == MSG_END_CONTINUE) { 1236 i2c_dev->msg_len = 1; 1237 } else { 1238 i2c_dev->msg_buf += 1; 1239 i2c_dev->msg_len -= 1; 1240 } 1241 } 1242 1243 i2c_dev->msg_buf_remaining = i2c_dev->msg_len; 1244 1245 if (i2c_dev->msg_read) 1246 xfer_size = i2c_dev->msg_len; 1247 else 1248 xfer_size = i2c_dev->msg_len + I2C_PACKET_HEADER_SIZE; 1249 1250 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD); 1251 1252 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN && 1253 i2c_dev->dma_buf && !i2c_dev->atomic_mode; 1254 1255 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size); 1256 1257 /* 1258 * Transfer time in mSec = Total bits / transfer rate 1259 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits 1260 */ 1261 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC, 1262 i2c_dev->timings.bus_freq_hz); 1263 1264 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 1265 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1266 1267 if (i2c_dev->dma_mode) { 1268 if (i2c_dev->msg_read) { 1269 dma_sync_single_for_device(i2c_dev->dma_dev, 1270 i2c_dev->dma_phys, 1271 xfer_size, DMA_FROM_DEVICE); 1272 1273 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1274 if (err) 1275 return err; 1276 } else { 1277 dma_sync_single_for_cpu(i2c_dev->dma_dev, 1278 i2c_dev->dma_phys, 1279 xfer_size, DMA_TO_DEVICE); 1280 } 1281 } 1282 1283 tegra_i2c_push_packet_header(i2c_dev, msg, end_state); 1284 1285 if (!i2c_dev->msg_read) { 1286 if (i2c_dev->dma_mode) { 1287 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE, 1288 msg->buf, i2c_dev->msg_len); 1289 1290 dma_sync_single_for_device(i2c_dev->dma_dev, 1291 i2c_dev->dma_phys, 1292 xfer_size, DMA_TO_DEVICE); 1293 1294 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1295 if (err) 1296 return err; 1297 } else { 1298 tegra_i2c_fill_tx_fifo(i2c_dev); 1299 } 1300 } 1301 1302 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) 1303 int_mask |= I2C_INT_PACKET_XFER_COMPLETE; 1304 1305 if (!i2c_dev->dma_mode) { 1306 if (msg->flags & I2C_M_RD) 1307 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 1308 else if (i2c_dev->msg_buf_remaining) 1309 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 1310 } 1311 1312 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1313 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n", 1314 i2c_readl(i2c_dev, I2C_INT_MASK)); 1315 1316 if (i2c_dev->dma_mode) { 1317 time_left = tegra_i2c_wait_completion(i2c_dev, 1318 &i2c_dev->dma_complete, 1319 xfer_time); 1320 1321 /* 1322 * Synchronize DMA first, since dmaengine_terminate_sync() 1323 * performs synchronization after the transfer's termination 1324 * and we want to get a completion if transfer succeeded. 1325 */ 1326 dmaengine_synchronize(i2c_dev->dma_chan); 1327 dmaengine_terminate_sync(i2c_dev->dma_chan); 1328 1329 if (!time_left && !completion_done(&i2c_dev->dma_complete)) { 1330 tegra_i2c_init(i2c_dev); 1331 return -ETIMEDOUT; 1332 } 1333 1334 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { 1335 dma_sync_single_for_cpu(i2c_dev->dma_dev, 1336 i2c_dev->dma_phys, 1337 xfer_size, DMA_FROM_DEVICE); 1338 1339 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, i2c_dev->msg_len); 1340 } 1341 } 1342 1343 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 1344 xfer_time); 1345 1346 tegra_i2c_mask_irq(i2c_dev, int_mask); 1347 1348 if (time_left == 0) { 1349 tegra_i2c_init(i2c_dev); 1350 return -ETIMEDOUT; 1351 } 1352 1353 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", 1354 time_left, completion_done(&i2c_dev->msg_complete), 1355 i2c_dev->msg_err); 1356 1357 i2c_dev->dma_mode = false; 1358 1359 err = tegra_i2c_error_recover(i2c_dev, msg); 1360 if (err) 1361 return err; 1362 1363 return 0; 1364 } 1365 1366 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 1367 int num) 1368 { 1369 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1370 int i, ret; 1371 1372 ret = pm_runtime_get_sync(i2c_dev->dev); 1373 if (ret < 0) { 1374 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); 1375 pm_runtime_put_noidle(i2c_dev->dev); 1376 return ret; 1377 } 1378 1379 for (i = 0; i < num; i++) { 1380 enum msg_end_type end_type = MSG_END_STOP; 1381 1382 if (i < (num - 1)) { 1383 /* check whether follow up message is coming */ 1384 if (msgs[i + 1].flags & I2C_M_NOSTART) 1385 end_type = MSG_END_CONTINUE; 1386 else 1387 end_type = MSG_END_REPEAT_START; 1388 } 1389 /* If M_RECV_LEN use ContinueXfer to read the first byte */ 1390 if (msgs[i].flags & I2C_M_RECV_LEN) { 1391 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], MSG_END_CONTINUE); 1392 if (ret) 1393 break; 1394 1395 /* Validate message length before proceeding */ 1396 if (msgs[i].buf[0] == 0 || msgs[i].buf[0] > I2C_SMBUS_BLOCK_MAX) 1397 break; 1398 1399 /* Set the msg length from first byte */ 1400 msgs[i].len += msgs[i].buf[0]; 1401 dev_dbg(i2c_dev->dev, "reading %d bytes\n", msgs[i].len); 1402 } 1403 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 1404 if (ret) 1405 break; 1406 } 1407 1408 pm_runtime_put(i2c_dev->dev); 1409 1410 return ret ?: i; 1411 } 1412 1413 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap, 1414 struct i2c_msg msgs[], int num) 1415 { 1416 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1417 int ret; 1418 1419 i2c_dev->atomic_mode = true; 1420 ret = tegra_i2c_xfer(adap, msgs, num); 1421 i2c_dev->atomic_mode = false; 1422 1423 return ret; 1424 } 1425 1426 static u32 tegra_i2c_func(struct i2c_adapter *adap) 1427 { 1428 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1429 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 1430 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; 1431 1432 if (i2c_dev->hw->has_continue_xfer_support) 1433 ret |= I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1434 1435 return ret; 1436 } 1437 1438 static const struct i2c_algorithm tegra_i2c_algo = { 1439 .xfer = tegra_i2c_xfer, 1440 .xfer_atomic = tegra_i2c_xfer_atomic, 1441 .functionality = tegra_i2c_func, 1442 }; 1443 1444 /* payload size is only 12 bit */ 1445 static const struct i2c_adapter_quirks tegra_i2c_quirks = { 1446 .flags = I2C_AQ_NO_ZERO_LEN, 1447 .max_read_len = SZ_4K, 1448 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE, 1449 }; 1450 1451 static const struct i2c_adapter_quirks tegra194_i2c_quirks = { 1452 .flags = I2C_AQ_NO_ZERO_LEN, 1453 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE, 1454 }; 1455 1456 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = { 1457 .recover_bus = tegra_i2c_issue_bus_clear, 1458 }; 1459 1460 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 1461 .has_continue_xfer_support = false, 1462 .has_per_pkt_xfer_complete_irq = false, 1463 .clk_divisor_hs_mode = 3, 1464 .clk_divisor_std_mode = 0, 1465 .clk_divisor_fast_mode = 0, 1466 .clk_divisor_fast_plus_mode = 0, 1467 .has_config_load_reg = false, 1468 .has_multi_master_mode = false, 1469 .has_slcg_override_reg = false, 1470 .has_mst_fifo = false, 1471 .quirks = &tegra_i2c_quirks, 1472 .supports_bus_clear = false, 1473 .has_apb_dma = true, 1474 .tlow_std_mode = 0x4, 1475 .thigh_std_mode = 0x2, 1476 .tlow_fast_fastplus_mode = 0x4, 1477 .thigh_fast_fastplus_mode = 0x2, 1478 .setup_hold_time_std_mode = 0x0, 1479 .setup_hold_time_fast_fast_plus_mode = 0x0, 1480 .setup_hold_time_hs_mode = 0x0, 1481 .has_interface_timing_reg = false, 1482 }; 1483 1484 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 1485 .has_continue_xfer_support = true, 1486 .has_per_pkt_xfer_complete_irq = false, 1487 .clk_divisor_hs_mode = 3, 1488 .clk_divisor_std_mode = 0, 1489 .clk_divisor_fast_mode = 0, 1490 .clk_divisor_fast_plus_mode = 0, 1491 .has_config_load_reg = false, 1492 .has_multi_master_mode = false, 1493 .has_slcg_override_reg = false, 1494 .has_mst_fifo = false, 1495 .quirks = &tegra_i2c_quirks, 1496 .supports_bus_clear = false, 1497 .has_apb_dma = true, 1498 .tlow_std_mode = 0x4, 1499 .thigh_std_mode = 0x2, 1500 .tlow_fast_fastplus_mode = 0x4, 1501 .thigh_fast_fastplus_mode = 0x2, 1502 .setup_hold_time_std_mode = 0x0, 1503 .setup_hold_time_fast_fast_plus_mode = 0x0, 1504 .setup_hold_time_hs_mode = 0x0, 1505 .has_interface_timing_reg = false, 1506 }; 1507 1508 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { 1509 .has_continue_xfer_support = true, 1510 .has_per_pkt_xfer_complete_irq = true, 1511 .clk_divisor_hs_mode = 1, 1512 .clk_divisor_std_mode = 0x19, 1513 .clk_divisor_fast_mode = 0x19, 1514 .clk_divisor_fast_plus_mode = 0x10, 1515 .has_config_load_reg = false, 1516 .has_multi_master_mode = false, 1517 .has_slcg_override_reg = false, 1518 .has_mst_fifo = false, 1519 .quirks = &tegra_i2c_quirks, 1520 .supports_bus_clear = true, 1521 .has_apb_dma = true, 1522 .tlow_std_mode = 0x4, 1523 .thigh_std_mode = 0x2, 1524 .tlow_fast_fastplus_mode = 0x4, 1525 .thigh_fast_fastplus_mode = 0x2, 1526 .setup_hold_time_std_mode = 0x0, 1527 .setup_hold_time_fast_fast_plus_mode = 0x0, 1528 .setup_hold_time_hs_mode = 0x0, 1529 .has_interface_timing_reg = false, 1530 }; 1531 1532 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { 1533 .has_continue_xfer_support = true, 1534 .has_per_pkt_xfer_complete_irq = true, 1535 .clk_divisor_hs_mode = 1, 1536 .clk_divisor_std_mode = 0x19, 1537 .clk_divisor_fast_mode = 0x19, 1538 .clk_divisor_fast_plus_mode = 0x10, 1539 .has_config_load_reg = true, 1540 .has_multi_master_mode = false, 1541 .has_slcg_override_reg = true, 1542 .has_mst_fifo = false, 1543 .quirks = &tegra_i2c_quirks, 1544 .supports_bus_clear = true, 1545 .has_apb_dma = true, 1546 .tlow_std_mode = 0x4, 1547 .thigh_std_mode = 0x2, 1548 .tlow_fast_fastplus_mode = 0x4, 1549 .thigh_fast_fastplus_mode = 0x2, 1550 .setup_hold_time_std_mode = 0x0, 1551 .setup_hold_time_fast_fast_plus_mode = 0x0, 1552 .setup_hold_time_hs_mode = 0x0, 1553 .has_interface_timing_reg = true, 1554 }; 1555 1556 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { 1557 .has_continue_xfer_support = true, 1558 .has_per_pkt_xfer_complete_irq = true, 1559 .clk_divisor_hs_mode = 1, 1560 .clk_divisor_std_mode = 0x19, 1561 .clk_divisor_fast_mode = 0x19, 1562 .clk_divisor_fast_plus_mode = 0x10, 1563 .has_config_load_reg = true, 1564 .has_multi_master_mode = false, 1565 .has_slcg_override_reg = true, 1566 .has_mst_fifo = false, 1567 .quirks = &tegra_i2c_quirks, 1568 .supports_bus_clear = true, 1569 .has_apb_dma = true, 1570 .tlow_std_mode = 0x4, 1571 .thigh_std_mode = 0x2, 1572 .tlow_fast_fastplus_mode = 0x4, 1573 .thigh_fast_fastplus_mode = 0x2, 1574 .setup_hold_time_std_mode = 0, 1575 .setup_hold_time_fast_fast_plus_mode = 0, 1576 .setup_hold_time_hs_mode = 0, 1577 .has_interface_timing_reg = true, 1578 }; 1579 1580 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { 1581 .has_continue_xfer_support = true, 1582 .has_per_pkt_xfer_complete_irq = true, 1583 .clk_divisor_hs_mode = 1, 1584 .clk_divisor_std_mode = 0x16, 1585 .clk_divisor_fast_mode = 0x19, 1586 .clk_divisor_fast_plus_mode = 0x10, 1587 .has_config_load_reg = true, 1588 .has_multi_master_mode = false, 1589 .has_slcg_override_reg = true, 1590 .has_mst_fifo = false, 1591 .quirks = &tegra_i2c_quirks, 1592 .supports_bus_clear = true, 1593 .has_apb_dma = false, 1594 .tlow_std_mode = 0x4, 1595 .thigh_std_mode = 0x3, 1596 .tlow_fast_fastplus_mode = 0x4, 1597 .thigh_fast_fastplus_mode = 0x2, 1598 .setup_hold_time_std_mode = 0, 1599 .setup_hold_time_fast_fast_plus_mode = 0, 1600 .setup_hold_time_hs_mode = 0, 1601 .has_interface_timing_reg = true, 1602 }; 1603 1604 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { 1605 .has_continue_xfer_support = true, 1606 .has_per_pkt_xfer_complete_irq = true, 1607 .clk_divisor_hs_mode = 1, 1608 .clk_divisor_std_mode = 0x4f, 1609 .clk_divisor_fast_mode = 0x3c, 1610 .clk_divisor_fast_plus_mode = 0x16, 1611 .has_config_load_reg = true, 1612 .has_multi_master_mode = true, 1613 .has_slcg_override_reg = true, 1614 .has_mst_fifo = true, 1615 .quirks = &tegra194_i2c_quirks, 1616 .supports_bus_clear = true, 1617 .has_apb_dma = false, 1618 .tlow_std_mode = 0x8, 1619 .thigh_std_mode = 0x7, 1620 .tlow_fast_fastplus_mode = 0x2, 1621 .thigh_fast_fastplus_mode = 0x2, 1622 .setup_hold_time_std_mode = 0x08080808, 1623 .setup_hold_time_fast_fast_plus_mode = 0x02020202, 1624 .setup_hold_time_hs_mode = 0x090909, 1625 .has_interface_timing_reg = true, 1626 }; 1627 1628 static const struct of_device_id tegra_i2c_of_match[] = { 1629 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, 1630 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, }, 1631 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) 1632 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, }, 1633 #endif 1634 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 1635 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, 1636 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, 1637 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, 1638 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, 1639 #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) 1640 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, 1641 #endif 1642 {}, 1643 }; 1644 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 1645 1646 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) 1647 { 1648 struct device_node *np = i2c_dev->dev->of_node; 1649 bool multi_mode; 1650 1651 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true); 1652 1653 multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master"); 1654 i2c_dev->multimaster_mode = multi_mode; 1655 1656 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && 1657 of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) 1658 i2c_dev->is_dvc = true; 1659 1660 if (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && 1661 of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) 1662 i2c_dev->is_vi = true; 1663 } 1664 1665 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) 1666 { 1667 int err; 1668 1669 if (ACPI_HANDLE(i2c_dev->dev)) 1670 return 0; 1671 1672 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk"; 1673 1674 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw) 1675 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk"; 1676 1677 if (IS_VI(i2c_dev)) 1678 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow"; 1679 1680 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks, 1681 i2c_dev->clocks); 1682 if (err) 1683 return err; 1684 1685 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks); 1686 if (err) 1687 return err; 1688 1689 i2c_dev->div_clk = i2c_dev->clocks[0].clk; 1690 1691 if (!i2c_dev->multimaster_mode) 1692 return 0; 1693 1694 err = clk_enable(i2c_dev->div_clk); 1695 if (err) { 1696 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err); 1697 goto unprepare_clocks; 1698 } 1699 1700 return 0; 1701 1702 unprepare_clocks: 1703 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1704 1705 return err; 1706 } 1707 1708 static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev) 1709 { 1710 if (i2c_dev->multimaster_mode) 1711 clk_disable(i2c_dev->div_clk); 1712 1713 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1714 } 1715 1716 static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev) 1717 { 1718 int ret; 1719 1720 ret = pm_runtime_get_sync(i2c_dev->dev); 1721 if (ret < 0) 1722 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret); 1723 else 1724 ret = tegra_i2c_init(i2c_dev); 1725 1726 pm_runtime_put_sync(i2c_dev->dev); 1727 1728 return ret; 1729 } 1730 1731 static int tegra_i2c_probe(struct platform_device *pdev) 1732 { 1733 struct tegra_i2c_dev *i2c_dev; 1734 struct resource *res; 1735 int err; 1736 1737 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 1738 if (!i2c_dev) 1739 return -ENOMEM; 1740 1741 platform_set_drvdata(pdev, i2c_dev); 1742 1743 init_completion(&i2c_dev->msg_complete); 1744 init_completion(&i2c_dev->dma_complete); 1745 1746 i2c_dev->hw = device_get_match_data(&pdev->dev); 1747 i2c_dev->cont_id = pdev->id; 1748 i2c_dev->dev = &pdev->dev; 1749 1750 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1751 if (IS_ERR(i2c_dev->base)) 1752 return PTR_ERR(i2c_dev->base); 1753 1754 i2c_dev->base_phys = res->start; 1755 1756 err = platform_get_irq(pdev, 0); 1757 if (err < 0) 1758 return err; 1759 1760 i2c_dev->irq = err; 1761 1762 /* interrupt will be enabled during of transfer time */ 1763 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN); 1764 1765 err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq, 1766 NULL, tegra_i2c_isr, 1767 IRQF_NO_SUSPEND | IRQF_ONESHOT, 1768 dev_name(i2c_dev->dev), i2c_dev); 1769 if (err) 1770 return err; 1771 1772 tegra_i2c_parse_dt(i2c_dev); 1773 1774 err = tegra_i2c_init_clocks(i2c_dev); 1775 if (err) 1776 return err; 1777 1778 err = tegra_i2c_init_dma(i2c_dev); 1779 if (err) 1780 goto release_clocks; 1781 1782 /* 1783 * VI I2C is in VE power domain which is not always ON and not 1784 * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a 1785 * non IRQ-safe domain because this prevents powering off the power 1786 * domain. 1787 * 1788 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't 1789 * be used for atomic transfers. ACPI device is not IRQ safe also. 1790 */ 1791 if (!IS_VI(i2c_dev) && !has_acpi_companion(i2c_dev->dev)) 1792 pm_runtime_irq_safe(i2c_dev->dev); 1793 1794 pm_runtime_enable(i2c_dev->dev); 1795 1796 err = tegra_i2c_init_hardware(i2c_dev); 1797 if (err) 1798 goto release_rpm; 1799 1800 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 1801 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node; 1802 i2c_dev->adapter.dev.parent = i2c_dev->dev; 1803 i2c_dev->adapter.retries = 1; 1804 i2c_dev->adapter.timeout = 6 * HZ; 1805 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; 1806 i2c_dev->adapter.owner = THIS_MODULE; 1807 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; 1808 i2c_dev->adapter.algo = &tegra_i2c_algo; 1809 i2c_dev->adapter.nr = pdev->id; 1810 ACPI_COMPANION_SET(&i2c_dev->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1811 1812 if (i2c_dev->hw->supports_bus_clear) 1813 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; 1814 1815 strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), 1816 sizeof(i2c_dev->adapter.name)); 1817 1818 err = i2c_add_numbered_adapter(&i2c_dev->adapter); 1819 if (err) 1820 goto release_rpm; 1821 1822 return 0; 1823 1824 release_rpm: 1825 pm_runtime_disable(i2c_dev->dev); 1826 1827 tegra_i2c_release_dma(i2c_dev); 1828 release_clocks: 1829 tegra_i2c_release_clocks(i2c_dev); 1830 1831 return err; 1832 } 1833 1834 static void tegra_i2c_remove(struct platform_device *pdev) 1835 { 1836 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1837 1838 i2c_del_adapter(&i2c_dev->adapter); 1839 pm_runtime_force_suspend(i2c_dev->dev); 1840 1841 tegra_i2c_release_dma(i2c_dev); 1842 tegra_i2c_release_clocks(i2c_dev); 1843 } 1844 1845 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) 1846 { 1847 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1848 int err; 1849 1850 err = pinctrl_pm_select_default_state(dev); 1851 if (err) 1852 return err; 1853 1854 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks); 1855 if (err) 1856 return err; 1857 1858 /* 1859 * VI I2C device is attached to VE power domain which goes through 1860 * power ON/OFF during runtime PM resume/suspend, meaning that 1861 * controller needs to be re-initialized after power ON. 1862 */ 1863 if (IS_VI(i2c_dev)) { 1864 err = tegra_i2c_init(i2c_dev); 1865 if (err) 1866 goto disable_clocks; 1867 } 1868 1869 return 0; 1870 1871 disable_clocks: 1872 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1873 1874 return err; 1875 } 1876 1877 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) 1878 { 1879 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1880 1881 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1882 1883 return pinctrl_pm_select_idle_state(dev); 1884 } 1885 1886 static int __maybe_unused tegra_i2c_suspend(struct device *dev) 1887 { 1888 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1889 int err; 1890 1891 i2c_mark_adapter_suspended(&i2c_dev->adapter); 1892 1893 if (!pm_runtime_status_suspended(dev)) { 1894 err = tegra_i2c_runtime_suspend(dev); 1895 if (err) 1896 return err; 1897 } 1898 1899 return 0; 1900 } 1901 1902 static int __maybe_unused tegra_i2c_resume(struct device *dev) 1903 { 1904 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1905 int err; 1906 1907 /* 1908 * We need to ensure that clocks are enabled so that registers can be 1909 * restored in tegra_i2c_init(). 1910 */ 1911 err = tegra_i2c_runtime_resume(dev); 1912 if (err) 1913 return err; 1914 1915 err = tegra_i2c_init(i2c_dev); 1916 if (err) 1917 return err; 1918 1919 /* 1920 * In case we are runtime suspended, disable clocks again so that we 1921 * don't unbalance the clock reference counts during the next runtime 1922 * resume transition. 1923 */ 1924 if (pm_runtime_status_suspended(dev)) { 1925 err = tegra_i2c_runtime_suspend(dev); 1926 if (err) 1927 return err; 1928 } 1929 1930 i2c_mark_adapter_resumed(&i2c_dev->adapter); 1931 1932 return 0; 1933 } 1934 1935 static const struct dev_pm_ops tegra_i2c_pm = { 1936 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume) 1937 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, 1938 NULL) 1939 }; 1940 1941 static const struct acpi_device_id tegra_i2c_acpi_match[] = { 1942 {.id = "NVDA0101", .driver_data = (kernel_ulong_t)&tegra210_i2c_hw}, 1943 {.id = "NVDA0201", .driver_data = (kernel_ulong_t)&tegra186_i2c_hw}, 1944 {.id = "NVDA0301", .driver_data = (kernel_ulong_t)&tegra194_i2c_hw}, 1945 { } 1946 }; 1947 MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match); 1948 1949 static struct platform_driver tegra_i2c_driver = { 1950 .probe = tegra_i2c_probe, 1951 .remove = tegra_i2c_remove, 1952 .driver = { 1953 .name = "tegra-i2c", 1954 .of_match_table = tegra_i2c_of_match, 1955 .acpi_match_table = tegra_i2c_acpi_match, 1956 .pm = &tegra_i2c_pm, 1957 }, 1958 }; 1959 module_platform_driver(tegra_i2c_driver); 1960 1961 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver"); 1962 MODULE_AUTHOR("Colin Cross"); 1963 MODULE_LICENSE("GPL v2"); 1964