1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/i2c/busses/i2c-tegra.c 4 * 5 * Copyright (C) 2010 Google, Inc. 6 * Author: Colin Cross <ccross@android.com> 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/init.h> 11 #include <linux/platform_device.h> 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/i2c.h> 15 #include <linux/io.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/slab.h> 19 #include <linux/of_device.h> 20 #include <linux/module.h> 21 #include <linux/reset.h> 22 #include <linux/pinctrl/consumer.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/iopoll.h> 25 26 #include <asm/unaligned.h> 27 28 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000)) 29 #define BYTES_PER_FIFO_WORD 4 30 31 #define I2C_CNFG 0x000 32 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 33 #define I2C_CNFG_PACKET_MODE_EN BIT(10) 34 #define I2C_CNFG_NEW_MASTER_FSM BIT(11) 35 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) 36 #define I2C_STATUS 0x01C 37 #define I2C_SL_CNFG 0x020 38 #define I2C_SL_CNFG_NACK BIT(1) 39 #define I2C_SL_CNFG_NEWSL BIT(2) 40 #define I2C_SL_ADDR1 0x02c 41 #define I2C_SL_ADDR2 0x030 42 #define I2C_TX_FIFO 0x050 43 #define I2C_RX_FIFO 0x054 44 #define I2C_PACKET_TRANSFER_STATUS 0x058 45 #define I2C_FIFO_CONTROL 0x05c 46 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 47 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 48 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5 49 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2 50 #define I2C_FIFO_STATUS 0x060 51 #define I2C_FIFO_STATUS_TX_MASK 0xF0 52 #define I2C_FIFO_STATUS_TX_SHIFT 4 53 #define I2C_FIFO_STATUS_RX_MASK 0x0F 54 #define I2C_FIFO_STATUS_RX_SHIFT 0 55 #define I2C_INT_MASK 0x064 56 #define I2C_INT_STATUS 0x068 57 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 58 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE BIT(6) 59 #define I2C_INT_TX_FIFO_OVERFLOW BIT(5) 60 #define I2C_INT_RX_FIFO_UNDERFLOW BIT(4) 61 #define I2C_INT_NO_ACK BIT(3) 62 #define I2C_INT_ARBITRATION_LOST BIT(2) 63 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) 64 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) 65 #define I2C_CLK_DIVISOR 0x06c 66 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16 67 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8 68 69 #define DVC_CTRL_REG1 0x000 70 #define DVC_CTRL_REG1_INTR_EN BIT(10) 71 #define DVC_CTRL_REG2 0x004 72 #define DVC_CTRL_REG3 0x008 73 #define DVC_CTRL_REG3_SW_PROG BIT(26) 74 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30) 75 #define DVC_STATUS 0x00c 76 #define DVC_STATUS_I2C_DONE_INTR BIT(30) 77 78 #define I2C_ERR_NONE 0x00 79 #define I2C_ERR_NO_ACK 0x01 80 #define I2C_ERR_ARBITRATION_LOST 0x02 81 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04 82 83 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 84 #define PACKET_HEADER0_PACKET_ID_SHIFT 16 85 #define PACKET_HEADER0_CONT_ID_SHIFT 12 86 #define PACKET_HEADER0_PROTOCOL_I2C BIT(4) 87 88 #define I2C_HEADER_HIGHSPEED_MODE BIT(22) 89 #define I2C_HEADER_CONT_ON_NAK BIT(21) 90 #define I2C_HEADER_SEND_START_BYTE BIT(20) 91 #define I2C_HEADER_READ BIT(19) 92 #define I2C_HEADER_10BIT_ADDR BIT(18) 93 #define I2C_HEADER_IE_ENABLE BIT(17) 94 #define I2C_HEADER_REPEAT_START BIT(16) 95 #define I2C_HEADER_CONTINUE_XFER BIT(15) 96 #define I2C_HEADER_MASTER_ADDR_SHIFT 12 97 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 98 99 #define I2C_CONFIG_LOAD 0x08C 100 #define I2C_MSTR_CONFIG_LOAD BIT(0) 101 #define I2C_SLV_CONFIG_LOAD BIT(1) 102 #define I2C_TIMEOUT_CONFIG_LOAD BIT(2) 103 104 #define I2C_CLKEN_OVERRIDE 0x090 105 #define I2C_MST_CORE_CLKEN_OVR BIT(0) 106 107 #define I2C_CONFIG_LOAD_TIMEOUT 1000000 108 109 #define I2C_MST_FIFO_CONTROL 0x0b4 110 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) 111 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) 112 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4) 113 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16) 114 115 #define I2C_MST_FIFO_STATUS 0x0b8 116 #define I2C_MST_FIFO_STATUS_RX_MASK 0xff 117 #define I2C_MST_FIFO_STATUS_RX_SHIFT 0 118 #define I2C_MST_FIFO_STATUS_TX_MASK 0xff0000 119 #define I2C_MST_FIFO_STATUS_TX_SHIFT 16 120 121 /* 122 * msg_end_type: The bus control which need to be send at end of transfer. 123 * @MSG_END_STOP: Send stop pulse at end of transfer. 124 * @MSG_END_REPEAT_START: Send repeat start at end of transfer. 125 * @MSG_END_CONTINUE: The following on message is coming and so do not send 126 * stop or repeat start. 127 */ 128 enum msg_end_type { 129 MSG_END_STOP, 130 MSG_END_REPEAT_START, 131 MSG_END_CONTINUE, 132 }; 133 134 /** 135 * struct tegra_i2c_hw_feature : Different HW support on Tegra 136 * @has_continue_xfer_support: Continue transfer supports. 137 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer 138 * complete interrupt per packet basis. 139 * @has_single_clk_source: The I2C controller has single clock source. Tegra30 140 * and earlier SoCs have two clock sources i.e. div-clk and 141 * fast-clk. 142 * @has_config_load_reg: Has the config load register to load the new 143 * configuration. 144 * @clk_divisor_hs_mode: Clock divisor in HS mode. 145 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is 146 * applicable if there is no fast clock source i.e. single clock 147 * source. 148 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is 149 * applicable if there is no fast clock source (i.e. single 150 * clock source). 151 * @has_multi_master_mode: The I2C controller supports running in single-master 152 * or multi-master mode. 153 * @has_slcg_override_reg: The I2C controller supports a register that 154 * overrides the second level clock gating. 155 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that 156 * provides additional features and allows for longer messages to 157 * be transferred in one go. 158 * @quirks: i2c adapter quirks for limiting write/read transfer size and not 159 * allowing 0 length transfers. 160 */ 161 struct tegra_i2c_hw_feature { 162 bool has_continue_xfer_support; 163 bool has_per_pkt_xfer_complete_irq; 164 bool has_single_clk_source; 165 bool has_config_load_reg; 166 int clk_divisor_hs_mode; 167 int clk_divisor_std_fast_mode; 168 u16 clk_divisor_fast_plus_mode; 169 bool has_multi_master_mode; 170 bool has_slcg_override_reg; 171 bool has_mst_fifo; 172 const struct i2c_adapter_quirks *quirks; 173 }; 174 175 /** 176 * struct tegra_i2c_dev - per device I2C context 177 * @dev: device reference for power management 178 * @hw: Tegra I2C HW feature 179 * @adapter: core I2C layer adapter information 180 * @div_clk: clock reference for div clock of I2C controller 181 * @fast_clk: clock reference for fast clock of I2C controller 182 * @rst: reset control for the I2C controller 183 * @base: ioremapped registers cookie 184 * @cont_id: I2C controller ID, used for packet header 185 * @irq: IRQ number of transfer complete interrupt 186 * @irq_disabled: used to track whether or not the interrupt is enabled 187 * @is_dvc: identifies the DVC I2C controller, has a different register layout 188 * @msg_complete: transfer completion notifier 189 * @msg_err: error code for completed message 190 * @msg_buf: pointer to current message data 191 * @msg_buf_remaining: size of unsent data in the message buffer 192 * @msg_read: identifies read transfers 193 * @bus_clk_rate: current I2C bus clock rate 194 * @clk_divisor_non_hs_mode: clock divider for non-high-speed modes 195 * @is_multimaster_mode: track if I2C controller is in multi-master mode 196 * @xfer_lock: lock to serialize transfer submission and processing 197 */ 198 struct tegra_i2c_dev { 199 struct device *dev; 200 const struct tegra_i2c_hw_feature *hw; 201 struct i2c_adapter adapter; 202 struct clk *div_clk; 203 struct clk *fast_clk; 204 struct reset_control *rst; 205 void __iomem *base; 206 int cont_id; 207 int irq; 208 bool irq_disabled; 209 int is_dvc; 210 struct completion msg_complete; 211 int msg_err; 212 u8 *msg_buf; 213 size_t msg_buf_remaining; 214 int msg_read; 215 u32 bus_clk_rate; 216 u16 clk_divisor_non_hs_mode; 217 bool is_multimaster_mode; 218 spinlock_t xfer_lock; 219 }; 220 221 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 222 unsigned long reg) 223 { 224 writel(val, i2c_dev->base + reg); 225 } 226 227 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 228 { 229 return readl(i2c_dev->base + reg); 230 } 231 232 /* 233 * i2c_writel and i2c_readl will offset the register if necessary to talk 234 * to the I2C block inside the DVC block 235 */ 236 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, 237 unsigned long reg) 238 { 239 if (i2c_dev->is_dvc) 240 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 241 return reg; 242 } 243 244 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 245 unsigned long reg) 246 { 247 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 248 249 /* Read back register to make sure that register writes completed */ 250 if (reg != I2C_TX_FIFO) 251 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 252 } 253 254 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 255 { 256 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 257 } 258 259 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 260 unsigned long reg, int len) 261 { 262 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 263 } 264 265 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 266 unsigned long reg, int len) 267 { 268 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 269 } 270 271 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 272 { 273 u32 int_mask; 274 275 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; 276 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 277 } 278 279 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 280 { 281 u32 int_mask; 282 283 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; 284 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 285 } 286 287 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 288 { 289 unsigned long timeout = jiffies + HZ; 290 unsigned int offset; 291 u32 mask, val; 292 293 if (i2c_dev->hw->has_mst_fifo) { 294 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH | 295 I2C_MST_FIFO_CONTROL_RX_FLUSH; 296 offset = I2C_MST_FIFO_CONTROL; 297 } else { 298 mask = I2C_FIFO_CONTROL_TX_FLUSH | 299 I2C_FIFO_CONTROL_RX_FLUSH; 300 offset = I2C_FIFO_CONTROL; 301 } 302 303 val = i2c_readl(i2c_dev, offset); 304 val |= mask; 305 i2c_writel(i2c_dev, val, offset); 306 307 while (i2c_readl(i2c_dev, offset) & mask) { 308 if (time_after(jiffies, timeout)) { 309 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); 310 return -ETIMEDOUT; 311 } 312 msleep(1); 313 } 314 return 0; 315 } 316 317 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 318 { 319 u32 val; 320 int rx_fifo_avail; 321 u8 *buf = i2c_dev->msg_buf; 322 size_t buf_remaining = i2c_dev->msg_buf_remaining; 323 int words_to_transfer; 324 325 if (i2c_dev->hw->has_mst_fifo) { 326 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 327 rx_fifo_avail = (val & I2C_MST_FIFO_STATUS_RX_MASK) >> 328 I2C_MST_FIFO_STATUS_RX_SHIFT; 329 } else { 330 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 331 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >> 332 I2C_FIFO_STATUS_RX_SHIFT; 333 } 334 335 /* Rounds down to not include partial word at the end of buf */ 336 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 337 if (words_to_transfer > rx_fifo_avail) 338 words_to_transfer = rx_fifo_avail; 339 340 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 341 342 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 343 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 344 rx_fifo_avail -= words_to_transfer; 345 346 /* 347 * If there is a partial word at the end of buf, handle it manually to 348 * prevent overwriting past the end of buf 349 */ 350 if (rx_fifo_avail > 0 && buf_remaining > 0) { 351 BUG_ON(buf_remaining > 3); 352 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 353 val = cpu_to_le32(val); 354 memcpy(buf, &val, buf_remaining); 355 buf_remaining = 0; 356 rx_fifo_avail--; 357 } 358 359 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0); 360 i2c_dev->msg_buf_remaining = buf_remaining; 361 i2c_dev->msg_buf = buf; 362 363 return 0; 364 } 365 366 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 367 { 368 u32 val; 369 int tx_fifo_avail; 370 u8 *buf = i2c_dev->msg_buf; 371 size_t buf_remaining = i2c_dev->msg_buf_remaining; 372 int words_to_transfer; 373 374 if (i2c_dev->hw->has_mst_fifo) { 375 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 376 tx_fifo_avail = (val & I2C_MST_FIFO_STATUS_TX_MASK) >> 377 I2C_MST_FIFO_STATUS_TX_SHIFT; 378 } else { 379 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 380 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >> 381 I2C_FIFO_STATUS_TX_SHIFT; 382 } 383 384 /* Rounds down to not include partial word at the end of buf */ 385 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 386 387 /* It's very common to have < 4 bytes, so optimize that case. */ 388 if (words_to_transfer) { 389 if (words_to_transfer > tx_fifo_avail) 390 words_to_transfer = tx_fifo_avail; 391 392 /* 393 * Update state before writing to FIFO. If this casues us 394 * to finish writing all bytes (AKA buf_remaining goes to 0) we 395 * have a potential for an interrupt (PACKET_XFER_COMPLETE is 396 * not maskable). We need to make sure that the isr sees 397 * buf_remaining as 0 and doesn't call us back re-entrantly. 398 */ 399 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 400 tx_fifo_avail -= words_to_transfer; 401 i2c_dev->msg_buf_remaining = buf_remaining; 402 i2c_dev->msg_buf = buf + 403 words_to_transfer * BYTES_PER_FIFO_WORD; 404 barrier(); 405 406 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 407 408 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 409 } 410 411 /* 412 * If there is a partial word at the end of buf, handle it manually to 413 * prevent reading past the end of buf, which could cross a page 414 * boundary and fault. 415 */ 416 if (tx_fifo_avail > 0 && buf_remaining > 0) { 417 BUG_ON(buf_remaining > 3); 418 memcpy(&val, buf, buf_remaining); 419 val = le32_to_cpu(val); 420 421 /* Again update before writing to FIFO to make sure isr sees. */ 422 i2c_dev->msg_buf_remaining = 0; 423 i2c_dev->msg_buf = NULL; 424 barrier(); 425 426 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 427 } 428 429 return 0; 430 } 431 432 /* 433 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 434 * block. This block is identical to the rest of the I2C blocks, except that 435 * it only supports master mode, it has registers moved around, and it needs 436 * some extra init to get it into I2C mode. The register moves are handled 437 * by i2c_readl and i2c_writel 438 */ 439 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 440 { 441 u32 val; 442 443 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 444 val |= DVC_CTRL_REG3_SW_PROG; 445 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 446 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 447 448 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 449 val |= DVC_CTRL_REG1_INTR_EN; 450 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 451 } 452 453 static int tegra_i2c_runtime_resume(struct device *dev) 454 { 455 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 456 int ret; 457 458 ret = pinctrl_pm_select_default_state(i2c_dev->dev); 459 if (ret) 460 return ret; 461 462 if (!i2c_dev->hw->has_single_clk_source) { 463 ret = clk_enable(i2c_dev->fast_clk); 464 if (ret < 0) { 465 dev_err(i2c_dev->dev, 466 "Enabling fast clk failed, err %d\n", ret); 467 return ret; 468 } 469 } 470 471 ret = clk_enable(i2c_dev->div_clk); 472 if (ret < 0) { 473 dev_err(i2c_dev->dev, 474 "Enabling div clk failed, err %d\n", ret); 475 clk_disable(i2c_dev->fast_clk); 476 return ret; 477 } 478 479 return 0; 480 } 481 482 static int tegra_i2c_runtime_suspend(struct device *dev) 483 { 484 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 485 486 clk_disable(i2c_dev->div_clk); 487 if (!i2c_dev->hw->has_single_clk_source) 488 clk_disable(i2c_dev->fast_clk); 489 490 return pinctrl_pm_select_idle_state(i2c_dev->dev); 491 } 492 493 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) 494 { 495 unsigned long reg_offset; 496 void __iomem *addr; 497 u32 val; 498 int err; 499 500 if (i2c_dev->hw->has_config_load_reg) { 501 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD); 502 addr = i2c_dev->base + reg_offset; 503 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); 504 if (in_interrupt()) 505 err = readl_poll_timeout_atomic(addr, val, val == 0, 506 1000, I2C_CONFIG_LOAD_TIMEOUT); 507 else 508 err = readl_poll_timeout(addr, val, val == 0, 509 1000, I2C_CONFIG_LOAD_TIMEOUT); 510 511 if (err) { 512 dev_warn(i2c_dev->dev, 513 "timeout waiting for config load\n"); 514 return err; 515 } 516 } 517 518 return 0; 519 } 520 521 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 522 { 523 u32 val; 524 int err; 525 u32 clk_divisor; 526 527 err = pm_runtime_get_sync(i2c_dev->dev); 528 if (err < 0) { 529 dev_err(i2c_dev->dev, "runtime resume failed %d\n", err); 530 return err; 531 } 532 533 reset_control_assert(i2c_dev->rst); 534 udelay(2); 535 reset_control_deassert(i2c_dev->rst); 536 537 if (i2c_dev->is_dvc) 538 tegra_dvc_init(i2c_dev); 539 540 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 541 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); 542 543 if (i2c_dev->hw->has_multi_master_mode) 544 val |= I2C_CNFG_MULTI_MASTER_MODE; 545 546 i2c_writel(i2c_dev, val, I2C_CNFG); 547 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 548 549 /* Make sure clock divisor programmed correctly */ 550 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode; 551 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode << 552 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT; 553 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 554 555 if (!i2c_dev->is_dvc) { 556 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 557 558 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 559 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 560 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 561 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 562 } 563 564 if (i2c_dev->hw->has_mst_fifo) { 565 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) | 566 I2C_MST_FIFO_CONTROL_RX_TRIG(1); 567 i2c_writel(i2c_dev, val, I2C_MST_FIFO_CONTROL); 568 } else { 569 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT | 570 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT; 571 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); 572 } 573 574 err = tegra_i2c_flush_fifos(i2c_dev); 575 if (err) 576 goto err; 577 578 if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg) 579 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); 580 581 err = tegra_i2c_wait_for_config_load(i2c_dev); 582 if (err) 583 goto err; 584 585 if (i2c_dev->irq_disabled) { 586 i2c_dev->irq_disabled = false; 587 enable_irq(i2c_dev->irq); 588 } 589 590 err: 591 pm_runtime_put(i2c_dev->dev); 592 return err; 593 } 594 595 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) 596 { 597 u32 cnfg; 598 599 /* 600 * NACK interrupt is generated before the I2C controller generates 601 * the STOP condition on the bus. So wait for 2 clock periods 602 * before disabling the controller so that the STOP condition has 603 * been delivered properly. 604 */ 605 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); 606 607 cnfg = i2c_readl(i2c_dev, I2C_CNFG); 608 if (cnfg & I2C_CNFG_PACKET_MODE_EN) 609 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); 610 611 return tegra_i2c_wait_for_config_load(i2c_dev); 612 } 613 614 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 615 { 616 u32 status; 617 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 618 struct tegra_i2c_dev *i2c_dev = dev_id; 619 620 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 621 622 spin_lock(&i2c_dev->xfer_lock); 623 if (status == 0) { 624 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n", 625 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 626 i2c_readl(i2c_dev, I2C_STATUS), 627 i2c_readl(i2c_dev, I2C_CNFG)); 628 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 629 630 if (!i2c_dev->irq_disabled) { 631 disable_irq_nosync(i2c_dev->irq); 632 i2c_dev->irq_disabled = true; 633 } 634 goto err; 635 } 636 637 if (unlikely(status & status_err)) { 638 tegra_i2c_disable_packet_mode(i2c_dev); 639 if (status & I2C_INT_NO_ACK) 640 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 641 if (status & I2C_INT_ARBITRATION_LOST) 642 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 643 goto err; 644 } 645 646 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 647 if (i2c_dev->msg_buf_remaining) 648 tegra_i2c_empty_rx_fifo(i2c_dev); 649 else 650 BUG(); 651 } 652 653 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 654 if (i2c_dev->msg_buf_remaining) 655 tegra_i2c_fill_tx_fifo(i2c_dev); 656 else 657 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ); 658 } 659 660 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 661 if (i2c_dev->is_dvc) 662 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 663 664 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 665 BUG_ON(i2c_dev->msg_buf_remaining); 666 complete(&i2c_dev->msg_complete); 667 } 668 goto done; 669 err: 670 /* An error occurred, mask all interrupts */ 671 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | 672 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ | 673 I2C_INT_RX_FIFO_DATA_REQ); 674 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 675 if (i2c_dev->is_dvc) 676 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 677 678 complete(&i2c_dev->msg_complete); 679 done: 680 spin_unlock(&i2c_dev->xfer_lock); 681 return IRQ_HANDLED; 682 } 683 684 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 685 struct i2c_msg *msg, enum msg_end_type end_state) 686 { 687 u32 packet_header; 688 u32 int_mask; 689 unsigned long time_left; 690 unsigned long flags; 691 692 tegra_i2c_flush_fifos(i2c_dev); 693 694 i2c_dev->msg_buf = msg->buf; 695 i2c_dev->msg_buf_remaining = msg->len; 696 i2c_dev->msg_err = I2C_ERR_NONE; 697 i2c_dev->msg_read = (msg->flags & I2C_M_RD); 698 reinit_completion(&i2c_dev->msg_complete); 699 700 spin_lock_irqsave(&i2c_dev->xfer_lock, flags); 701 702 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 703 tegra_i2c_unmask_irq(i2c_dev, int_mask); 704 705 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | 706 PACKET_HEADER0_PROTOCOL_I2C | 707 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | 708 (1 << PACKET_HEADER0_PACKET_ID_SHIFT); 709 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 710 711 packet_header = msg->len - 1; 712 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 713 714 packet_header = I2C_HEADER_IE_ENABLE; 715 if (end_state == MSG_END_CONTINUE) 716 packet_header |= I2C_HEADER_CONTINUE_XFER; 717 else if (end_state == MSG_END_REPEAT_START) 718 packet_header |= I2C_HEADER_REPEAT_START; 719 if (msg->flags & I2C_M_TEN) { 720 packet_header |= msg->addr; 721 packet_header |= I2C_HEADER_10BIT_ADDR; 722 } else { 723 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 724 } 725 if (msg->flags & I2C_M_IGNORE_NAK) 726 packet_header |= I2C_HEADER_CONT_ON_NAK; 727 if (msg->flags & I2C_M_RD) 728 packet_header |= I2C_HEADER_READ; 729 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 730 731 if (!(msg->flags & I2C_M_RD)) 732 tegra_i2c_fill_tx_fifo(i2c_dev); 733 734 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) 735 int_mask |= I2C_INT_PACKET_XFER_COMPLETE; 736 if (msg->flags & I2C_M_RD) 737 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 738 else if (i2c_dev->msg_buf_remaining) 739 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 740 741 tegra_i2c_unmask_irq(i2c_dev, int_mask); 742 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags); 743 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", 744 i2c_readl(i2c_dev, I2C_INT_MASK)); 745 746 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, 747 TEGRA_I2C_TIMEOUT); 748 tegra_i2c_mask_irq(i2c_dev, int_mask); 749 750 if (time_left == 0) { 751 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); 752 753 tegra_i2c_init(i2c_dev); 754 return -ETIMEDOUT; 755 } 756 757 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", 758 time_left, completion_done(&i2c_dev->msg_complete), 759 i2c_dev->msg_err); 760 761 if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) 762 return 0; 763 764 tegra_i2c_init(i2c_dev); 765 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 766 if (msg->flags & I2C_M_IGNORE_NAK) 767 return 0; 768 return -EREMOTEIO; 769 } 770 771 return -EIO; 772 } 773 774 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 775 int num) 776 { 777 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 778 int i; 779 int ret = 0; 780 781 ret = pm_runtime_get_sync(i2c_dev->dev); 782 if (ret < 0) { 783 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); 784 return ret; 785 } 786 787 for (i = 0; i < num; i++) { 788 enum msg_end_type end_type = MSG_END_STOP; 789 790 if (i < (num - 1)) { 791 if (msgs[i + 1].flags & I2C_M_NOSTART) 792 end_type = MSG_END_CONTINUE; 793 else 794 end_type = MSG_END_REPEAT_START; 795 } 796 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 797 if (ret) 798 break; 799 } 800 801 pm_runtime_put(i2c_dev->dev); 802 803 return ret ?: i; 804 } 805 806 static u32 tegra_i2c_func(struct i2c_adapter *adap) 807 { 808 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 809 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 810 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; 811 812 if (i2c_dev->hw->has_continue_xfer_support) 813 ret |= I2C_FUNC_NOSTART; 814 return ret; 815 } 816 817 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) 818 { 819 struct device_node *np = i2c_dev->dev->of_node; 820 int ret; 821 822 ret = of_property_read_u32(np, "clock-frequency", 823 &i2c_dev->bus_clk_rate); 824 if (ret) 825 i2c_dev->bus_clk_rate = 100000; /* default clock rate */ 826 827 i2c_dev->is_multimaster_mode = of_property_read_bool(np, 828 "multi-master"); 829 } 830 831 static const struct i2c_algorithm tegra_i2c_algo = { 832 .master_xfer = tegra_i2c_xfer, 833 .functionality = tegra_i2c_func, 834 }; 835 836 /* payload size is only 12 bit */ 837 static const struct i2c_adapter_quirks tegra_i2c_quirks = { 838 .flags = I2C_AQ_NO_ZERO_LEN, 839 .max_read_len = 4096, 840 .max_write_len = 4096, 841 }; 842 843 static const struct i2c_adapter_quirks tegra194_i2c_quirks = { 844 .flags = I2C_AQ_NO_ZERO_LEN, 845 }; 846 847 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 848 .has_continue_xfer_support = false, 849 .has_per_pkt_xfer_complete_irq = false, 850 .has_single_clk_source = false, 851 .clk_divisor_hs_mode = 3, 852 .clk_divisor_std_fast_mode = 0, 853 .clk_divisor_fast_plus_mode = 0, 854 .has_config_load_reg = false, 855 .has_multi_master_mode = false, 856 .has_slcg_override_reg = false, 857 .has_mst_fifo = false, 858 .quirks = &tegra_i2c_quirks, 859 }; 860 861 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 862 .has_continue_xfer_support = true, 863 .has_per_pkt_xfer_complete_irq = false, 864 .has_single_clk_source = false, 865 .clk_divisor_hs_mode = 3, 866 .clk_divisor_std_fast_mode = 0, 867 .clk_divisor_fast_plus_mode = 0, 868 .has_config_load_reg = false, 869 .has_multi_master_mode = false, 870 .has_slcg_override_reg = false, 871 .has_mst_fifo = false, 872 .quirks = &tegra_i2c_quirks, 873 }; 874 875 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { 876 .has_continue_xfer_support = true, 877 .has_per_pkt_xfer_complete_irq = true, 878 .has_single_clk_source = true, 879 .clk_divisor_hs_mode = 1, 880 .clk_divisor_std_fast_mode = 0x19, 881 .clk_divisor_fast_plus_mode = 0x10, 882 .has_config_load_reg = false, 883 .has_multi_master_mode = false, 884 .has_slcg_override_reg = false, 885 .has_mst_fifo = false, 886 .quirks = &tegra_i2c_quirks, 887 }; 888 889 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { 890 .has_continue_xfer_support = true, 891 .has_per_pkt_xfer_complete_irq = true, 892 .has_single_clk_source = true, 893 .clk_divisor_hs_mode = 1, 894 .clk_divisor_std_fast_mode = 0x19, 895 .clk_divisor_fast_plus_mode = 0x10, 896 .has_config_load_reg = true, 897 .has_multi_master_mode = false, 898 .has_slcg_override_reg = true, 899 .has_mst_fifo = false, 900 .quirks = &tegra_i2c_quirks, 901 }; 902 903 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { 904 .has_continue_xfer_support = true, 905 .has_per_pkt_xfer_complete_irq = true, 906 .has_single_clk_source = true, 907 .clk_divisor_hs_mode = 1, 908 .clk_divisor_std_fast_mode = 0x19, 909 .clk_divisor_fast_plus_mode = 0x10, 910 .has_config_load_reg = true, 911 .has_multi_master_mode = true, 912 .has_slcg_override_reg = true, 913 .has_mst_fifo = false, 914 .quirks = &tegra_i2c_quirks, 915 }; 916 917 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { 918 .has_continue_xfer_support = true, 919 .has_per_pkt_xfer_complete_irq = true, 920 .has_single_clk_source = true, 921 .clk_divisor_hs_mode = 1, 922 .clk_divisor_std_fast_mode = 0x19, 923 .clk_divisor_fast_plus_mode = 0x10, 924 .has_config_load_reg = true, 925 .has_multi_master_mode = true, 926 .has_slcg_override_reg = true, 927 .has_mst_fifo = true, 928 .quirks = &tegra194_i2c_quirks, 929 }; 930 931 /* Match table for of_platform binding */ 932 static const struct of_device_id tegra_i2c_of_match[] = { 933 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, 934 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 935 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, 936 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, 937 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, 938 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, 939 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, 940 {}, 941 }; 942 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 943 944 static int tegra_i2c_probe(struct platform_device *pdev) 945 { 946 struct tegra_i2c_dev *i2c_dev; 947 struct resource *res; 948 struct clk *div_clk; 949 struct clk *fast_clk; 950 void __iomem *base; 951 int irq; 952 int ret = 0; 953 int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE; 954 955 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 956 base = devm_ioremap_resource(&pdev->dev, res); 957 if (IS_ERR(base)) 958 return PTR_ERR(base); 959 960 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 961 if (!res) { 962 dev_err(&pdev->dev, "no irq resource\n"); 963 return -EINVAL; 964 } 965 irq = res->start; 966 967 div_clk = devm_clk_get(&pdev->dev, "div-clk"); 968 if (IS_ERR(div_clk)) { 969 dev_err(&pdev->dev, "missing controller clock\n"); 970 return PTR_ERR(div_clk); 971 } 972 973 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 974 if (!i2c_dev) 975 return -ENOMEM; 976 977 i2c_dev->base = base; 978 i2c_dev->div_clk = div_clk; 979 i2c_dev->adapter.algo = &tegra_i2c_algo; 980 i2c_dev->irq = irq; 981 i2c_dev->cont_id = pdev->id; 982 i2c_dev->dev = &pdev->dev; 983 984 i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c"); 985 if (IS_ERR(i2c_dev->rst)) { 986 dev_err(&pdev->dev, "missing controller reset\n"); 987 return PTR_ERR(i2c_dev->rst); 988 } 989 990 tegra_i2c_parse_dt(i2c_dev); 991 992 i2c_dev->hw = of_device_get_match_data(&pdev->dev); 993 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, 994 "nvidia,tegra20-i2c-dvc"); 995 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; 996 init_completion(&i2c_dev->msg_complete); 997 spin_lock_init(&i2c_dev->xfer_lock); 998 999 if (!i2c_dev->hw->has_single_clk_source) { 1000 fast_clk = devm_clk_get(&pdev->dev, "fast-clk"); 1001 if (IS_ERR(fast_clk)) { 1002 dev_err(&pdev->dev, "missing fast clock\n"); 1003 return PTR_ERR(fast_clk); 1004 } 1005 i2c_dev->fast_clk = fast_clk; 1006 } 1007 1008 platform_set_drvdata(pdev, i2c_dev); 1009 1010 if (!i2c_dev->hw->has_single_clk_source) { 1011 ret = clk_prepare(i2c_dev->fast_clk); 1012 if (ret < 0) { 1013 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); 1014 return ret; 1015 } 1016 } 1017 1018 i2c_dev->clk_divisor_non_hs_mode = 1019 i2c_dev->hw->clk_divisor_std_fast_mode; 1020 if (i2c_dev->hw->clk_divisor_fast_plus_mode && 1021 (i2c_dev->bus_clk_rate == 1000000)) 1022 i2c_dev->clk_divisor_non_hs_mode = 1023 i2c_dev->hw->clk_divisor_fast_plus_mode; 1024 1025 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1); 1026 ret = clk_set_rate(i2c_dev->div_clk, 1027 i2c_dev->bus_clk_rate * clk_multiplier); 1028 if (ret) { 1029 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret); 1030 goto unprepare_fast_clk; 1031 } 1032 1033 ret = clk_prepare(i2c_dev->div_clk); 1034 if (ret < 0) { 1035 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); 1036 goto unprepare_fast_clk; 1037 } 1038 1039 pm_runtime_enable(&pdev->dev); 1040 if (!pm_runtime_enabled(&pdev->dev)) { 1041 ret = tegra_i2c_runtime_resume(&pdev->dev); 1042 if (ret < 0) { 1043 dev_err(&pdev->dev, "runtime resume failed\n"); 1044 goto unprepare_div_clk; 1045 } 1046 } 1047 1048 if (i2c_dev->is_multimaster_mode) { 1049 ret = clk_enable(i2c_dev->div_clk); 1050 if (ret < 0) { 1051 dev_err(i2c_dev->dev, "div_clk enable failed %d\n", 1052 ret); 1053 goto disable_rpm; 1054 } 1055 } 1056 1057 ret = tegra_i2c_init(i2c_dev); 1058 if (ret) { 1059 dev_err(&pdev->dev, "Failed to initialize i2c controller\n"); 1060 goto disable_div_clk; 1061 } 1062 1063 ret = devm_request_irq(&pdev->dev, i2c_dev->irq, 1064 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev); 1065 if (ret) { 1066 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); 1067 goto disable_div_clk; 1068 } 1069 1070 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 1071 i2c_dev->adapter.owner = THIS_MODULE; 1072 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; 1073 strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev), 1074 sizeof(i2c_dev->adapter.name)); 1075 i2c_dev->adapter.dev.parent = &pdev->dev; 1076 i2c_dev->adapter.nr = pdev->id; 1077 i2c_dev->adapter.dev.of_node = pdev->dev.of_node; 1078 1079 ret = i2c_add_numbered_adapter(&i2c_dev->adapter); 1080 if (ret) 1081 goto disable_div_clk; 1082 1083 return 0; 1084 1085 disable_div_clk: 1086 if (i2c_dev->is_multimaster_mode) 1087 clk_disable(i2c_dev->div_clk); 1088 1089 disable_rpm: 1090 pm_runtime_disable(&pdev->dev); 1091 if (!pm_runtime_status_suspended(&pdev->dev)) 1092 tegra_i2c_runtime_suspend(&pdev->dev); 1093 1094 unprepare_div_clk: 1095 clk_unprepare(i2c_dev->div_clk); 1096 1097 unprepare_fast_clk: 1098 if (!i2c_dev->hw->has_single_clk_source) 1099 clk_unprepare(i2c_dev->fast_clk); 1100 1101 return ret; 1102 } 1103 1104 static int tegra_i2c_remove(struct platform_device *pdev) 1105 { 1106 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1107 1108 i2c_del_adapter(&i2c_dev->adapter); 1109 1110 if (i2c_dev->is_multimaster_mode) 1111 clk_disable(i2c_dev->div_clk); 1112 1113 pm_runtime_disable(&pdev->dev); 1114 if (!pm_runtime_status_suspended(&pdev->dev)) 1115 tegra_i2c_runtime_suspend(&pdev->dev); 1116 1117 clk_unprepare(i2c_dev->div_clk); 1118 if (!i2c_dev->hw->has_single_clk_source) 1119 clk_unprepare(i2c_dev->fast_clk); 1120 1121 return 0; 1122 } 1123 1124 #ifdef CONFIG_PM_SLEEP 1125 static const struct dev_pm_ops tegra_i2c_pm = { 1126 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, 1127 NULL) 1128 }; 1129 #define TEGRA_I2C_PM (&tegra_i2c_pm) 1130 #else 1131 #define TEGRA_I2C_PM NULL 1132 #endif 1133 1134 static struct platform_driver tegra_i2c_driver = { 1135 .probe = tegra_i2c_probe, 1136 .remove = tegra_i2c_remove, 1137 .driver = { 1138 .name = "tegra-i2c", 1139 .of_match_table = tegra_i2c_of_match, 1140 .pm = TEGRA_I2C_PM, 1141 }, 1142 }; 1143 1144 static int __init tegra_i2c_init_driver(void) 1145 { 1146 return platform_driver_register(&tegra_i2c_driver); 1147 } 1148 1149 static void __exit tegra_i2c_exit_driver(void) 1150 { 1151 platform_driver_unregister(&tegra_i2c_driver); 1152 } 1153 1154 subsys_initcall(tegra_i2c_init_driver); 1155 module_exit(tegra_i2c_exit_driver); 1156 1157 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver"); 1158 MODULE_AUTHOR("Colin Cross"); 1159 MODULE_LICENSE("GPL v2"); 1160