1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics STM32F7 I2C controller 4 * 5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc 6 * reference manual. 7 * Please see below a link to the documentation: 8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf 9 * 10 * Copyright (C) M'boumba Cedric Madianga 2017 11 * Copyright (C) STMicroelectronics 2017 12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 13 * 14 * This driver is based on i2c-stm32f4.c 15 * 16 */ 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/i2c.h> 21 #include <linux/i2c-smbus.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/of_address.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/pm_wakeirq.h> 34 #include <linux/regmap.h> 35 #include <linux/reset.h> 36 #include <linux/slab.h> 37 38 #include "i2c-stm32.h" 39 40 /* STM32F7 I2C registers */ 41 #define STM32F7_I2C_CR1 0x00 42 #define STM32F7_I2C_CR2 0x04 43 #define STM32F7_I2C_OAR1 0x08 44 #define STM32F7_I2C_OAR2 0x0C 45 #define STM32F7_I2C_PECR 0x20 46 #define STM32F7_I2C_TIMINGR 0x10 47 #define STM32F7_I2C_ISR 0x18 48 #define STM32F7_I2C_ICR 0x1C 49 #define STM32F7_I2C_RXDR 0x24 50 #define STM32F7_I2C_TXDR 0x28 51 52 /* STM32F7 I2C control 1 */ 53 #define STM32_I2C_CR1_FMP BIT(24) 54 #define STM32F7_I2C_CR1_PECEN BIT(23) 55 #define STM32F7_I2C_CR1_ALERTEN BIT(22) 56 #define STM32F7_I2C_CR1_SMBHEN BIT(20) 57 #define STM32F7_I2C_CR1_WUPEN BIT(18) 58 #define STM32F7_I2C_CR1_SBC BIT(16) 59 #define STM32F7_I2C_CR1_RXDMAEN BIT(15) 60 #define STM32F7_I2C_CR1_TXDMAEN BIT(14) 61 #define STM32F7_I2C_CR1_ANFOFF BIT(12) 62 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8) 63 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8) 64 #define STM32F7_I2C_CR1_ERRIE BIT(7) 65 #define STM32F7_I2C_CR1_TCIE BIT(6) 66 #define STM32F7_I2C_CR1_STOPIE BIT(5) 67 #define STM32F7_I2C_CR1_NACKIE BIT(4) 68 #define STM32F7_I2C_CR1_ADDRIE BIT(3) 69 #define STM32F7_I2C_CR1_RXIE BIT(2) 70 #define STM32F7_I2C_CR1_TXIE BIT(1) 71 #define STM32F7_I2C_CR1_PE BIT(0) 72 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \ 73 | STM32F7_I2C_CR1_TCIE \ 74 | STM32F7_I2C_CR1_STOPIE \ 75 | STM32F7_I2C_CR1_NACKIE \ 76 | STM32F7_I2C_CR1_RXIE \ 77 | STM32F7_I2C_CR1_TXIE) 78 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \ 79 | STM32F7_I2C_CR1_STOPIE \ 80 | STM32F7_I2C_CR1_NACKIE \ 81 | STM32F7_I2C_CR1_RXIE \ 82 | STM32F7_I2C_CR1_TXIE) 83 84 /* STM32F7 I2C control 2 */ 85 #define STM32F7_I2C_CR2_PECBYTE BIT(26) 86 #define STM32F7_I2C_CR2_RELOAD BIT(24) 87 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16) 88 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16) 89 #define STM32F7_I2C_CR2_NACK BIT(15) 90 #define STM32F7_I2C_CR2_STOP BIT(14) 91 #define STM32F7_I2C_CR2_START BIT(13) 92 #define STM32F7_I2C_CR2_HEAD10R BIT(12) 93 #define STM32F7_I2C_CR2_ADD10 BIT(11) 94 #define STM32F7_I2C_CR2_RD_WRN BIT(10) 95 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0) 96 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \ 97 STM32F7_I2C_CR2_SADD10_MASK)) 98 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1) 99 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1) 100 101 /* STM32F7 I2C Own Address 1 */ 102 #define STM32F7_I2C_OAR1_OA1EN BIT(15) 103 #define STM32F7_I2C_OAR1_OA1MODE BIT(10) 104 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0) 105 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \ 106 STM32F7_I2C_OAR1_OA1_10_MASK)) 107 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1) 108 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1) 109 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \ 110 | STM32F7_I2C_OAR1_OA1_10_MASK \ 111 | STM32F7_I2C_OAR1_OA1EN \ 112 | STM32F7_I2C_OAR1_OA1MODE) 113 114 /* STM32F7 I2C Own Address 2 */ 115 #define STM32F7_I2C_OAR2_OA2EN BIT(15) 116 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8) 117 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8) 118 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1) 119 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1) 120 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \ 121 | STM32F7_I2C_OAR2_OA2_7_MASK \ 122 | STM32F7_I2C_OAR2_OA2EN) 123 124 /* STM32F7 I2C Interrupt Status */ 125 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17) 126 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \ 127 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17) 128 #define STM32F7_I2C_ISR_DIR BIT(16) 129 #define STM32F7_I2C_ISR_BUSY BIT(15) 130 #define STM32F7_I2C_ISR_ALERT BIT(13) 131 #define STM32F7_I2C_ISR_PECERR BIT(11) 132 #define STM32F7_I2C_ISR_ARLO BIT(9) 133 #define STM32F7_I2C_ISR_BERR BIT(8) 134 #define STM32F7_I2C_ISR_TCR BIT(7) 135 #define STM32F7_I2C_ISR_TC BIT(6) 136 #define STM32F7_I2C_ISR_STOPF BIT(5) 137 #define STM32F7_I2C_ISR_NACKF BIT(4) 138 #define STM32F7_I2C_ISR_ADDR BIT(3) 139 #define STM32F7_I2C_ISR_RXNE BIT(2) 140 #define STM32F7_I2C_ISR_TXIS BIT(1) 141 #define STM32F7_I2C_ISR_TXE BIT(0) 142 143 /* STM32F7 I2C Interrupt Clear */ 144 #define STM32F7_I2C_ICR_ALERTCF BIT(13) 145 #define STM32F7_I2C_ICR_PECCF BIT(11) 146 #define STM32F7_I2C_ICR_ARLOCF BIT(9) 147 #define STM32F7_I2C_ICR_BERRCF BIT(8) 148 #define STM32F7_I2C_ICR_STOPCF BIT(5) 149 #define STM32F7_I2C_ICR_NACKCF BIT(4) 150 #define STM32F7_I2C_ICR_ADDRCF BIT(3) 151 152 /* STM32F7 I2C Timing */ 153 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28) 154 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20) 155 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16) 156 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8) 157 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff) 158 159 #define STM32F7_I2C_MAX_LEN 0xff 160 #define STM32F7_I2C_DMA_LEN_MIN 0x16 161 enum { 162 STM32F7_SLAVE_HOSTNOTIFY, 163 STM32F7_SLAVE_7_10_BITS_ADDR, 164 STM32F7_SLAVE_7_BITS_ADDR, 165 STM32F7_I2C_MAX_SLAVE 166 }; 167 168 #define STM32F7_I2C_DNF_DEFAULT 0 169 #define STM32F7_I2C_DNF_MAX 15 170 171 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 172 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 173 174 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */ 175 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */ 176 177 #define STM32F7_PRESC_MAX BIT(4) 178 #define STM32F7_SCLDEL_MAX BIT(4) 179 #define STM32F7_SDADEL_MAX BIT(4) 180 #define STM32F7_SCLH_MAX BIT(8) 181 #define STM32F7_SCLL_MAX BIT(8) 182 183 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100) 184 185 /** 186 * struct stm32f7_i2c_regs - i2c f7 registers backup 187 * @cr1: Control register 1 188 * @cr2: Control register 2 189 * @oar1: Own address 1 register 190 * @oar2: Own address 2 register 191 * @tmgr: Timing register 192 */ 193 struct stm32f7_i2c_regs { 194 u32 cr1; 195 u32 cr2; 196 u32 oar1; 197 u32 oar2; 198 u32 tmgr; 199 }; 200 201 /** 202 * struct stm32f7_i2c_spec - private i2c specification timing 203 * @rate: I2C bus speed (Hz) 204 * @fall_max: Max fall time of both SDA and SCL signals (ns) 205 * @rise_max: Max rise time of both SDA and SCL signals (ns) 206 * @hddat_min: Min data hold time (ns) 207 * @vddat_max: Max data valid time (ns) 208 * @sudat_min: Min data setup time (ns) 209 * @l_min: Min low period of the SCL clock (ns) 210 * @h_min: Min high period of the SCL clock (ns) 211 */ 212 struct stm32f7_i2c_spec { 213 u32 rate; 214 u32 fall_max; 215 u32 rise_max; 216 u32 hddat_min; 217 u32 vddat_max; 218 u32 sudat_min; 219 u32 l_min; 220 u32 h_min; 221 }; 222 223 /** 224 * struct stm32f7_i2c_setup - private I2C timing setup parameters 225 * @speed_freq: I2C speed frequency (Hz) 226 * @clock_src: I2C clock source frequency (Hz) 227 * @rise_time: Rise time (ns) 228 * @fall_time: Fall time (ns) 229 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register 230 * @single_it_line: Only a single IT line is used for both events/errors 231 * @fmp_cr1_bit: Fast Mode Plus control is done via a bit in CR1 232 */ 233 struct stm32f7_i2c_setup { 234 u32 speed_freq; 235 u32 clock_src; 236 u32 rise_time; 237 u32 fall_time; 238 u32 fmp_clr_offset; 239 bool single_it_line; 240 bool fmp_cr1_bit; 241 }; 242 243 /** 244 * struct stm32f7_i2c_timings - private I2C output parameters 245 * @node: List entry 246 * @presc: Prescaler value 247 * @scldel: Data setup time 248 * @sdadel: Data hold time 249 * @sclh: SCL high period (master mode) 250 * @scll: SCL low period (master mode) 251 */ 252 struct stm32f7_i2c_timings { 253 struct list_head node; 254 u8 presc; 255 u8 scldel; 256 u8 sdadel; 257 u8 sclh; 258 u8 scll; 259 }; 260 261 /** 262 * struct stm32f7_i2c_msg - client specific data 263 * @addr: 8-bit or 10-bit slave addr, including r/w bit 264 * @count: number of bytes to be transferred 265 * @buf: data buffer 266 * @result: result of the transfer 267 * @stop: last I2C msg to be sent, i.e. STOP to be generated 268 * @smbus: boolean to know if the I2C IP is used in SMBus mode 269 * @size: type of SMBus protocol 270 * @read_write: direction of SMBus protocol 271 * SMBus block read and SMBus block write - block read process call protocols 272 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will 273 * contain a maximum of 32 bytes of data + byte command + byte count + PEC 274 * This buffer has to be 32-bit aligned to be compliant with memory address 275 * register in DMA mode. 276 */ 277 struct stm32f7_i2c_msg { 278 u16 addr; 279 u32 count; 280 u8 *buf; 281 int result; 282 bool stop; 283 bool smbus; 284 int size; 285 char read_write; 286 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4); 287 }; 288 289 /** 290 * struct stm32f7_i2c_alert - SMBus alert specific data 291 * @setup: platform data for the smbus_alert i2c client 292 * @ara: I2C slave device used to respond to the SMBus Alert with Alert 293 * Response Address 294 */ 295 struct stm32f7_i2c_alert { 296 struct i2c_smbus_alert_setup setup; 297 struct i2c_client *ara; 298 }; 299 300 /** 301 * struct stm32f7_i2c_dev - private data of the controller 302 * @adap: I2C adapter for this controller 303 * @dev: device for this controller 304 * @base: virtual memory area 305 * @complete: completion of I2C message 306 * @clk: hw i2c clock 307 * @bus_rate: I2C clock frequency of the controller 308 * @msg: Pointer to data to be written 309 * @msg_num: number of I2C messages to be executed 310 * @msg_id: message identifiant 311 * @f7_msg: customized i2c msg for driver usage 312 * @setup: I2C timing input setup 313 * @timing: I2C computed timings 314 * @slave: list of slave devices registered on the I2C bus 315 * @slave_running: slave device currently used 316 * @backup_regs: backup of i2c controller registers (for suspend/resume) 317 * @slave_dir: transfer direction for the current slave device 318 * @master_mode: boolean to know in which mode the I2C is running (master or 319 * slave) 320 * @dma: dma data 321 * @use_dma: boolean to know if dma is used in the current transfer 322 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits 323 * @fmp_sreg: register address for setting Fast Mode Plus bits 324 * @fmp_creg: register address for clearing Fast Mode Plus bits 325 * @fmp_mask: mask for Fast Mode Plus bits in set register 326 * @wakeup_src: boolean to know if the device is a wakeup source 327 * @smbus_mode: states that the controller is configured in SMBus mode 328 * @host_notify_client: SMBus host-notify client 329 * @analog_filter: boolean to indicate enabling of the analog filter 330 * @dnf_dt: value of digital filter requested via dt 331 * @dnf: value of digital filter to apply 332 * @alert: SMBus alert specific data 333 * @atomic: boolean indicating that current transfer is atomic 334 */ 335 struct stm32f7_i2c_dev { 336 struct i2c_adapter adap; 337 struct device *dev; 338 void __iomem *base; 339 struct completion complete; 340 struct clk *clk; 341 unsigned int bus_rate; 342 struct i2c_msg *msg; 343 unsigned int msg_num; 344 unsigned int msg_id; 345 struct stm32f7_i2c_msg f7_msg; 346 struct stm32f7_i2c_setup setup; 347 struct stm32f7_i2c_timings timing; 348 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE]; 349 struct i2c_client *slave_running; 350 struct stm32f7_i2c_regs backup_regs; 351 u32 slave_dir; 352 bool master_mode; 353 struct stm32_i2c_dma *dma; 354 bool use_dma; 355 struct regmap *regmap; 356 u32 fmp_sreg; 357 u32 fmp_creg; 358 u32 fmp_mask; 359 bool wakeup_src; 360 bool smbus_mode; 361 struct i2c_client *host_notify_client; 362 bool analog_filter; 363 u32 dnf_dt; 364 u32 dnf; 365 struct stm32f7_i2c_alert *alert; 366 bool atomic; 367 }; 368 369 /* 370 * All these values are coming from I2C Specification, Version 6.0, 4th of 371 * April 2014. 372 * 373 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast, 374 * and Fast-mode Plus I2C-bus devices 375 */ 376 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = { 377 { 378 .rate = I2C_MAX_STANDARD_MODE_FREQ, 379 .fall_max = 300, 380 .rise_max = 1000, 381 .hddat_min = 0, 382 .vddat_max = 3450, 383 .sudat_min = 250, 384 .l_min = 4700, 385 .h_min = 4000, 386 }, 387 { 388 .rate = I2C_MAX_FAST_MODE_FREQ, 389 .fall_max = 300, 390 .rise_max = 300, 391 .hddat_min = 0, 392 .vddat_max = 900, 393 .sudat_min = 100, 394 .l_min = 1300, 395 .h_min = 600, 396 }, 397 { 398 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ, 399 .fall_max = 100, 400 .rise_max = 120, 401 .hddat_min = 0, 402 .vddat_max = 450, 403 .sudat_min = 50, 404 .l_min = 500, 405 .h_min = 260, 406 }, 407 }; 408 409 static const struct stm32f7_i2c_setup stm32f7_setup = { 410 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 411 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 412 }; 413 414 static const struct stm32f7_i2c_setup stm32mp15_setup = { 415 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 416 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 417 .fmp_clr_offset = 0x40, 418 }; 419 420 static const struct stm32f7_i2c_setup stm32mp13_setup = { 421 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 422 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 423 .fmp_clr_offset = 0x4, 424 }; 425 426 static const struct stm32f7_i2c_setup stm32mp25_setup = { 427 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 428 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 429 .single_it_line = true, 430 .fmp_cr1_bit = true, 431 }; 432 433 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask) 434 { 435 writel_relaxed(readl_relaxed(reg) | mask, reg); 436 } 437 438 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask) 439 { 440 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 441 } 442 443 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask) 444 { 445 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); 446 } 447 448 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate) 449 { 450 int i; 451 452 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++) 453 if (rate <= stm32f7_i2c_specs[i].rate) 454 return &stm32f7_i2c_specs[i]; 455 456 return ERR_PTR(-EINVAL); 457 } 458 459 #define RATE_MIN(rate) ((rate) * 8 / 10) 460 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev, 461 struct stm32f7_i2c_setup *setup, 462 struct stm32f7_i2c_timings *output) 463 { 464 struct stm32f7_i2c_spec *specs; 465 u32 p_prev = STM32F7_PRESC_MAX; 466 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 467 setup->clock_src); 468 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 469 setup->speed_freq); 470 u32 clk_error_prev = i2cbus; 471 u32 tsync; 472 u32 af_delay_min, af_delay_max; 473 u32 dnf_delay; 474 u32 clk_min, clk_max; 475 int sdadel_min, sdadel_max; 476 int scldel_min; 477 struct stm32f7_i2c_timings *v, *_v, *s; 478 struct list_head solutions; 479 u16 p, l, a, h; 480 int ret = 0; 481 482 specs = stm32f7_get_specs(setup->speed_freq); 483 if (specs == ERR_PTR(-EINVAL)) { 484 dev_err(i2c_dev->dev, "speed out of bound {%d}\n", 485 setup->speed_freq); 486 return -EINVAL; 487 } 488 489 if ((setup->rise_time > specs->rise_max) || 490 (setup->fall_time > specs->fall_max)) { 491 dev_err(i2c_dev->dev, 492 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", 493 setup->rise_time, specs->rise_max, 494 setup->fall_time, specs->fall_max); 495 return -EINVAL; 496 } 497 498 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk); 499 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) { 500 dev_err(i2c_dev->dev, 501 "DNF out of bound %d/%d\n", 502 i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk); 503 return -EINVAL; 504 } 505 506 /* Analog and Digital Filters */ 507 af_delay_min = 508 (i2c_dev->analog_filter ? 509 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0); 510 af_delay_max = 511 (i2c_dev->analog_filter ? 512 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0); 513 dnf_delay = i2c_dev->dnf * i2cclk; 514 515 sdadel_min = specs->hddat_min + setup->fall_time - 516 af_delay_min - (i2c_dev->dnf + 3) * i2cclk; 517 518 sdadel_max = specs->vddat_max - setup->rise_time - 519 af_delay_max - (i2c_dev->dnf + 4) * i2cclk; 520 521 scldel_min = setup->rise_time + specs->sudat_min; 522 523 if (sdadel_min < 0) 524 sdadel_min = 0; 525 if (sdadel_max < 0) 526 sdadel_max = 0; 527 528 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", 529 sdadel_min, sdadel_max, scldel_min); 530 531 INIT_LIST_HEAD(&solutions); 532 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 533 for (p = 0; p < STM32F7_PRESC_MAX; p++) { 534 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) { 535 u32 scldel = (l + 1) * (p + 1) * i2cclk; 536 537 if (scldel < scldel_min) 538 continue; 539 540 for (a = 0; a < STM32F7_SDADEL_MAX; a++) { 541 u32 sdadel = (a * (p + 1) + 1) * i2cclk; 542 543 if (((sdadel >= sdadel_min) && 544 (sdadel <= sdadel_max)) && 545 (p != p_prev)) { 546 v = kmalloc(sizeof(*v), GFP_KERNEL); 547 if (!v) { 548 ret = -ENOMEM; 549 goto exit; 550 } 551 552 v->presc = p; 553 v->scldel = l; 554 v->sdadel = a; 555 p_prev = p; 556 557 list_add_tail(&v->node, 558 &solutions); 559 break; 560 } 561 } 562 563 if (p_prev == p) 564 break; 565 } 566 } 567 568 if (list_empty(&solutions)) { 569 dev_err(i2c_dev->dev, "no Prescaler solution\n"); 570 ret = -EPERM; 571 goto exit; 572 } 573 574 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 575 s = NULL; 576 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq); 577 clk_min = NSEC_PER_SEC / setup->speed_freq; 578 579 /* 580 * Among Prescaler possibilities discovered above figures out SCL Low 581 * and High Period. Provided: 582 * - SCL Low Period has to be higher than SCL Clock Low Period 583 * defined by I2C Specification. I2C Clock has to be lower than 584 * (SCL Low Period - Analog/Digital filters) / 4. 585 * - SCL High Period has to be lower than SCL Clock High Period 586 * defined by I2C Specification 587 * - I2C Clock has to be lower than SCL High Period 588 */ 589 list_for_each_entry(v, &solutions, node) { 590 u32 prescaler = (v->presc + 1) * i2cclk; 591 592 for (l = 0; l < STM32F7_SCLL_MAX; l++) { 593 u32 tscl_l = (l + 1) * prescaler + tsync; 594 595 if ((tscl_l < specs->l_min) || 596 (i2cclk >= 597 ((tscl_l - af_delay_min - dnf_delay) / 4))) { 598 continue; 599 } 600 601 for (h = 0; h < STM32F7_SCLH_MAX; h++) { 602 u32 tscl_h = (h + 1) * prescaler + tsync; 603 u32 tscl = tscl_l + tscl_h + 604 setup->rise_time + setup->fall_time; 605 606 if ((tscl >= clk_min) && (tscl <= clk_max) && 607 (tscl_h >= specs->h_min) && 608 (i2cclk < tscl_h)) { 609 int clk_error = tscl - i2cbus; 610 611 if (clk_error < 0) 612 clk_error = -clk_error; 613 614 if (clk_error < clk_error_prev) { 615 clk_error_prev = clk_error; 616 v->scll = l; 617 v->sclh = h; 618 s = v; 619 } 620 } 621 } 622 } 623 } 624 625 if (!s) { 626 dev_err(i2c_dev->dev, "no solution at all\n"); 627 ret = -EPERM; 628 goto exit; 629 } 630 631 output->presc = s->presc; 632 output->scldel = s->scldel; 633 output->sdadel = s->sdadel; 634 output->scll = s->scll; 635 output->sclh = s->sclh; 636 637 dev_dbg(i2c_dev->dev, 638 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", 639 output->presc, 640 output->scldel, output->sdadel, 641 output->scll, output->sclh); 642 643 exit: 644 /* Release list and memory */ 645 list_for_each_entry_safe(v, _v, &solutions, node) { 646 list_del(&v->node); 647 kfree(v); 648 } 649 650 return ret; 651 } 652 653 static u32 stm32f7_get_lower_rate(u32 rate) 654 { 655 int i = ARRAY_SIZE(stm32f7_i2c_specs); 656 657 while (--i) 658 if (stm32f7_i2c_specs[i].rate < rate) 659 break; 660 661 return stm32f7_i2c_specs[i].rate; 662 } 663 664 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev, 665 struct stm32f7_i2c_setup *setup) 666 { 667 struct i2c_timings timings, *t = &timings; 668 int ret = 0; 669 670 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 671 t->scl_rise_ns = i2c_dev->setup.rise_time; 672 t->scl_fall_ns = i2c_dev->setup.fall_time; 673 674 i2c_parse_fw_timings(i2c_dev->dev, t, false); 675 676 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) { 677 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n", 678 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ); 679 return -EINVAL; 680 } 681 682 setup->speed_freq = t->bus_freq_hz; 683 i2c_dev->setup.rise_time = t->scl_rise_ns; 684 i2c_dev->setup.fall_time = t->scl_fall_ns; 685 i2c_dev->dnf_dt = t->digital_filter_width_ns; 686 setup->clock_src = clk_get_rate(i2c_dev->clk); 687 688 if (!setup->clock_src) { 689 dev_err(i2c_dev->dev, "clock rate is 0\n"); 690 return -EINVAL; 691 } 692 693 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter")) 694 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT; 695 696 do { 697 ret = stm32f7_i2c_compute_timing(i2c_dev, setup, 698 &i2c_dev->timing); 699 if (ret) { 700 dev_err(i2c_dev->dev, 701 "failed to compute I2C timings.\n"); 702 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ) 703 break; 704 setup->speed_freq = 705 stm32f7_get_lower_rate(setup->speed_freq); 706 dev_warn(i2c_dev->dev, 707 "downgrade I2C Speed Freq to (%i)\n", 708 setup->speed_freq); 709 } 710 } while (ret); 711 712 if (ret) { 713 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n"); 714 return ret; 715 } 716 717 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node, 718 "i2c-analog-filter"); 719 720 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n", 721 setup->speed_freq, setup->clock_src); 722 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", 723 setup->rise_time, setup->fall_time); 724 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", 725 (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf); 726 727 i2c_dev->bus_rate = setup->speed_freq; 728 729 return 0; 730 } 731 732 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev) 733 { 734 void __iomem *base = i2c_dev->base; 735 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN; 736 737 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 738 } 739 740 static void stm32f7_i2c_dma_callback(void *arg) 741 { 742 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg; 743 struct stm32_i2c_dma *dma = i2c_dev->dma; 744 struct device *dev = dma->chan_using->device->dev; 745 746 stm32f7_i2c_disable_dma_req(i2c_dev); 747 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir); 748 complete(&dma->dma_complete); 749 } 750 751 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev) 752 { 753 struct stm32f7_i2c_timings *t = &i2c_dev->timing; 754 u32 timing = 0; 755 756 /* Timing settings */ 757 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); 758 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); 759 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); 760 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); 761 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); 762 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); 763 764 /* Configure the Analog Filter */ 765 if (i2c_dev->analog_filter) 766 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 767 STM32F7_I2C_CR1_ANFOFF); 768 else 769 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 770 STM32F7_I2C_CR1_ANFOFF); 771 772 /* Program the Digital Filter */ 773 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 774 STM32F7_I2C_CR1_DNF_MASK); 775 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 776 STM32F7_I2C_CR1_DNF(i2c_dev->dnf)); 777 778 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 779 STM32F7_I2C_CR1_PE); 780 } 781 782 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev) 783 { 784 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 785 void __iomem *base = i2c_dev->base; 786 787 if (f7_msg->count) { 788 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); 789 f7_msg->count--; 790 } 791 } 792 793 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev) 794 { 795 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 796 void __iomem *base = i2c_dev->base; 797 798 if (f7_msg->count) { 799 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); 800 f7_msg->count--; 801 } else { 802 /* Flush RX buffer has no data is expected */ 803 readb_relaxed(base + STM32F7_I2C_RXDR); 804 } 805 } 806 807 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev) 808 { 809 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 810 u32 cr2; 811 812 if (i2c_dev->use_dma) 813 f7_msg->count -= STM32F7_I2C_MAX_LEN; 814 815 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 816 817 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK; 818 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 819 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 820 } else { 821 cr2 &= ~STM32F7_I2C_CR2_RELOAD; 822 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 823 } 824 825 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 826 } 827 828 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev) 829 { 830 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 831 u32 cr2; 832 u8 *val; 833 834 /* 835 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first 836 * data received inform us how many data will follow. 837 */ 838 stm32f7_i2c_read_rx_data(i2c_dev); 839 840 /* 841 * Update NBYTES with the value read to continue the transfer 842 */ 843 val = f7_msg->buf - sizeof(u8); 844 f7_msg->count = *val; 845 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 846 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 847 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 848 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 849 } 850 851 static void stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap) 852 { 853 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 854 855 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 856 STM32F7_I2C_CR1_PE); 857 858 stm32f7_i2c_hw_config(i2c_dev); 859 } 860 861 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev) 862 { 863 u32 status; 864 int ret; 865 866 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, 867 status, 868 !(status & STM32F7_I2C_ISR_BUSY), 869 10, 1000); 870 if (!ret) 871 return 0; 872 873 stm32f7_i2c_release_bus(&i2c_dev->adap); 874 875 return -EBUSY; 876 } 877 878 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 879 struct i2c_msg *msg) 880 { 881 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 882 void __iomem *base = i2c_dev->base; 883 u32 cr1, cr2; 884 int ret; 885 886 f7_msg->addr = msg->addr; 887 f7_msg->buf = msg->buf; 888 f7_msg->count = msg->len; 889 f7_msg->result = 0; 890 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1); 891 892 reinit_completion(&i2c_dev->complete); 893 894 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 895 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 896 897 /* Set transfer direction */ 898 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 899 if (msg->flags & I2C_M_RD) 900 cr2 |= STM32F7_I2C_CR2_RD_WRN; 901 902 /* Set slave address */ 903 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10); 904 if (msg->flags & I2C_M_TEN) { 905 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK; 906 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr); 907 cr2 |= STM32F7_I2C_CR2_ADD10; 908 } else { 909 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK; 910 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 911 } 912 913 /* Set nb bytes to transfer and reload if needed */ 914 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 915 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 916 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 917 cr2 |= STM32F7_I2C_CR2_RELOAD; 918 } else { 919 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 920 } 921 922 /* Enable NACK, STOP, error and transfer complete interrupts */ 923 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 924 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 925 926 /* Clear DMA req and TX/RX interrupt */ 927 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 928 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 929 930 /* Configure DMA or enable RX/TX interrupt */ 931 i2c_dev->use_dma = false; 932 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN 933 && !i2c_dev->atomic) { 934 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 935 msg->flags & I2C_M_RD, 936 f7_msg->count, f7_msg->buf, 937 stm32f7_i2c_dma_callback, 938 i2c_dev); 939 if (!ret) 940 i2c_dev->use_dma = true; 941 else 942 dev_warn(i2c_dev->dev, "can't use DMA\n"); 943 } 944 945 if (!i2c_dev->use_dma) { 946 if (msg->flags & I2C_M_RD) 947 cr1 |= STM32F7_I2C_CR1_RXIE; 948 else 949 cr1 |= STM32F7_I2C_CR1_TXIE; 950 } else { 951 if (msg->flags & I2C_M_RD) 952 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 953 else 954 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 955 } 956 957 if (i2c_dev->atomic) 958 cr1 &= ~STM32F7_I2C_ALL_IRQ_MASK; /* Disable all interrupts */ 959 960 /* Configure Start/Repeated Start */ 961 cr2 |= STM32F7_I2C_CR2_START; 962 963 i2c_dev->master_mode = true; 964 965 /* Write configurations registers */ 966 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 967 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 968 } 969 970 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 971 unsigned short flags, u8 command, 972 union i2c_smbus_data *data) 973 { 974 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 975 struct device *dev = i2c_dev->dev; 976 void __iomem *base = i2c_dev->base; 977 u32 cr1, cr2; 978 int i, ret; 979 980 f7_msg->result = 0; 981 reinit_completion(&i2c_dev->complete); 982 983 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 984 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 985 986 /* Set transfer direction */ 987 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 988 if (f7_msg->read_write) 989 cr2 |= STM32F7_I2C_CR2_RD_WRN; 990 991 /* Set slave address */ 992 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK); 993 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 994 995 f7_msg->smbus_buf[0] = command; 996 switch (f7_msg->size) { 997 case I2C_SMBUS_QUICK: 998 f7_msg->stop = true; 999 f7_msg->count = 0; 1000 break; 1001 case I2C_SMBUS_BYTE: 1002 f7_msg->stop = true; 1003 f7_msg->count = 1; 1004 break; 1005 case I2C_SMBUS_BYTE_DATA: 1006 if (f7_msg->read_write) { 1007 f7_msg->stop = false; 1008 f7_msg->count = 1; 1009 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1010 } else { 1011 f7_msg->stop = true; 1012 f7_msg->count = 2; 1013 f7_msg->smbus_buf[1] = data->byte; 1014 } 1015 break; 1016 case I2C_SMBUS_WORD_DATA: 1017 if (f7_msg->read_write) { 1018 f7_msg->stop = false; 1019 f7_msg->count = 1; 1020 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1021 } else { 1022 f7_msg->stop = true; 1023 f7_msg->count = 3; 1024 f7_msg->smbus_buf[1] = data->word & 0xff; 1025 f7_msg->smbus_buf[2] = data->word >> 8; 1026 } 1027 break; 1028 case I2C_SMBUS_BLOCK_DATA: 1029 if (f7_msg->read_write) { 1030 f7_msg->stop = false; 1031 f7_msg->count = 1; 1032 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1033 } else { 1034 f7_msg->stop = true; 1035 if (data->block[0] > I2C_SMBUS_BLOCK_MAX || 1036 !data->block[0]) { 1037 dev_err(dev, "Invalid block write size %d\n", 1038 data->block[0]); 1039 return -EINVAL; 1040 } 1041 f7_msg->count = data->block[0] + 2; 1042 for (i = 1; i < f7_msg->count; i++) 1043 f7_msg->smbus_buf[i] = data->block[i - 1]; 1044 } 1045 break; 1046 case I2C_SMBUS_PROC_CALL: 1047 f7_msg->stop = false; 1048 f7_msg->count = 3; 1049 f7_msg->smbus_buf[1] = data->word & 0xff; 1050 f7_msg->smbus_buf[2] = data->word >> 8; 1051 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1052 f7_msg->read_write = I2C_SMBUS_READ; 1053 break; 1054 case I2C_SMBUS_BLOCK_PROC_CALL: 1055 f7_msg->stop = false; 1056 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) { 1057 dev_err(dev, "Invalid block write size %d\n", 1058 data->block[0]); 1059 return -EINVAL; 1060 } 1061 f7_msg->count = data->block[0] + 2; 1062 for (i = 1; i < f7_msg->count; i++) 1063 f7_msg->smbus_buf[i] = data->block[i - 1]; 1064 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1065 f7_msg->read_write = I2C_SMBUS_READ; 1066 break; 1067 case I2C_SMBUS_I2C_BLOCK_DATA: 1068 /* Rely on emulated i2c transfer (through master_xfer) */ 1069 return -EOPNOTSUPP; 1070 default: 1071 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size); 1072 return -EOPNOTSUPP; 1073 } 1074 1075 f7_msg->buf = f7_msg->smbus_buf; 1076 1077 /* Configure PEC */ 1078 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { 1079 cr1 |= STM32F7_I2C_CR1_PECEN; 1080 if (!f7_msg->read_write) { 1081 cr2 |= STM32F7_I2C_CR2_PECBYTE; 1082 f7_msg->count++; 1083 } 1084 } else { 1085 cr1 &= ~STM32F7_I2C_CR1_PECEN; 1086 cr2 &= ~STM32F7_I2C_CR2_PECBYTE; 1087 } 1088 1089 /* Set number of bytes to be transferred */ 1090 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 1091 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1092 1093 /* Enable NACK, STOP, error and transfer complete interrupts */ 1094 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 1095 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 1096 1097 /* Clear DMA req and TX/RX interrupt */ 1098 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1099 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1100 1101 /* Configure DMA or enable RX/TX interrupt */ 1102 i2c_dev->use_dma = false; 1103 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 1104 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1105 cr2 & STM32F7_I2C_CR2_RD_WRN, 1106 f7_msg->count, f7_msg->buf, 1107 stm32f7_i2c_dma_callback, 1108 i2c_dev); 1109 if (!ret) 1110 i2c_dev->use_dma = true; 1111 else 1112 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1113 } 1114 1115 if (!i2c_dev->use_dma) { 1116 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1117 cr1 |= STM32F7_I2C_CR1_RXIE; 1118 else 1119 cr1 |= STM32F7_I2C_CR1_TXIE; 1120 } else { 1121 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1122 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1123 else 1124 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 1125 } 1126 1127 /* Set Start bit */ 1128 cr2 |= STM32F7_I2C_CR2_START; 1129 1130 i2c_dev->master_mode = true; 1131 1132 /* Write configurations registers */ 1133 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1134 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1135 1136 return 0; 1137 } 1138 1139 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev) 1140 { 1141 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1142 void __iomem *base = i2c_dev->base; 1143 u32 cr1, cr2; 1144 int ret; 1145 1146 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 1147 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 1148 1149 /* Set transfer direction */ 1150 cr2 |= STM32F7_I2C_CR2_RD_WRN; 1151 1152 switch (f7_msg->size) { 1153 case I2C_SMBUS_BYTE_DATA: 1154 f7_msg->count = 1; 1155 break; 1156 case I2C_SMBUS_WORD_DATA: 1157 case I2C_SMBUS_PROC_CALL: 1158 f7_msg->count = 2; 1159 break; 1160 case I2C_SMBUS_BLOCK_DATA: 1161 case I2C_SMBUS_BLOCK_PROC_CALL: 1162 f7_msg->count = 1; 1163 cr2 |= STM32F7_I2C_CR2_RELOAD; 1164 break; 1165 } 1166 1167 f7_msg->buf = f7_msg->smbus_buf; 1168 f7_msg->stop = true; 1169 1170 /* Add one byte for PEC if needed */ 1171 if (cr1 & STM32F7_I2C_CR1_PECEN) { 1172 cr2 |= STM32F7_I2C_CR2_PECBYTE; 1173 f7_msg->count++; 1174 } 1175 1176 /* Set number of bytes to be transferred */ 1177 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK); 1178 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1179 1180 /* 1181 * Configure RX/TX interrupt: 1182 */ 1183 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE); 1184 cr1 |= STM32F7_I2C_CR1_RXIE; 1185 1186 /* 1187 * Configure DMA or enable RX/TX interrupt: 1188 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use 1189 * dma as we don't know in advance how many data will be received 1190 */ 1191 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1192 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1193 1194 i2c_dev->use_dma = false; 1195 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN && 1196 f7_msg->size != I2C_SMBUS_BLOCK_DATA && 1197 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) { 1198 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1199 cr2 & STM32F7_I2C_CR2_RD_WRN, 1200 f7_msg->count, f7_msg->buf, 1201 stm32f7_i2c_dma_callback, 1202 i2c_dev); 1203 1204 if (!ret) 1205 i2c_dev->use_dma = true; 1206 else 1207 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1208 } 1209 1210 if (!i2c_dev->use_dma) 1211 cr1 |= STM32F7_I2C_CR1_RXIE; 1212 else 1213 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1214 1215 /* Configure Repeated Start */ 1216 cr2 |= STM32F7_I2C_CR2_START; 1217 1218 /* Write configurations registers */ 1219 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1220 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1221 } 1222 1223 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev) 1224 { 1225 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1226 u8 count, internal_pec, received_pec; 1227 1228 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR); 1229 1230 switch (f7_msg->size) { 1231 case I2C_SMBUS_BYTE: 1232 case I2C_SMBUS_BYTE_DATA: 1233 received_pec = f7_msg->smbus_buf[1]; 1234 break; 1235 case I2C_SMBUS_WORD_DATA: 1236 case I2C_SMBUS_PROC_CALL: 1237 received_pec = f7_msg->smbus_buf[2]; 1238 break; 1239 case I2C_SMBUS_BLOCK_DATA: 1240 case I2C_SMBUS_BLOCK_PROC_CALL: 1241 count = f7_msg->smbus_buf[0]; 1242 received_pec = f7_msg->smbus_buf[count]; 1243 break; 1244 default: 1245 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n"); 1246 return -EINVAL; 1247 } 1248 1249 if (internal_pec != received_pec) { 1250 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n", 1251 internal_pec, received_pec); 1252 return -EBADMSG; 1253 } 1254 1255 return 0; 1256 } 1257 1258 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode) 1259 { 1260 u32 addr; 1261 1262 if (!slave) 1263 return false; 1264 1265 if (slave->flags & I2C_CLIENT_TEN) { 1266 /* 1267 * For 10-bit addr, addcode = 11110XY with 1268 * X = Bit 9 of slave address 1269 * Y = Bit 8 of slave address 1270 */ 1271 addr = slave->addr >> 8; 1272 addr |= 0x78; 1273 if (addr == addcode) 1274 return true; 1275 } else { 1276 addr = slave->addr & 0x7f; 1277 if (addr == addcode) 1278 return true; 1279 } 1280 1281 return false; 1282 } 1283 1284 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev) 1285 { 1286 struct i2c_client *slave = i2c_dev->slave_running; 1287 void __iomem *base = i2c_dev->base; 1288 u32 mask; 1289 u8 value = 0; 1290 1291 if (i2c_dev->slave_dir) { 1292 /* Notify i2c slave that new read transfer is starting */ 1293 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1294 1295 /* 1296 * Disable slave TX config in case of I2C combined message 1297 * (I2C Write followed by I2C Read) 1298 */ 1299 mask = STM32F7_I2C_CR2_RELOAD; 1300 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask); 1301 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1302 STM32F7_I2C_CR1_TCIE; 1303 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1304 1305 /* Enable TX empty, STOP, NACK interrupts */ 1306 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1307 STM32F7_I2C_CR1_TXIE; 1308 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1309 1310 /* Write 1st data byte */ 1311 writel_relaxed(value, base + STM32F7_I2C_TXDR); 1312 } else { 1313 /* Notify i2c slave that new write transfer is starting */ 1314 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1315 1316 /* Set reload mode to be able to ACK/NACK each received byte */ 1317 mask = STM32F7_I2C_CR2_RELOAD; 1318 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1319 1320 /* 1321 * Set STOP, NACK, RX empty and transfer complete interrupts.* 1322 * Set Slave Byte Control to be able to ACK/NACK each data 1323 * byte received 1324 */ 1325 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1326 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1327 STM32F7_I2C_CR1_TCIE; 1328 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1329 } 1330 } 1331 1332 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev) 1333 { 1334 void __iomem *base = i2c_dev->base; 1335 u32 isr, addcode, dir, mask; 1336 int i; 1337 1338 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1339 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr); 1340 dir = isr & STM32F7_I2C_ISR_DIR; 1341 1342 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1343 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) { 1344 i2c_dev->slave_running = i2c_dev->slave[i]; 1345 i2c_dev->slave_dir = dir; 1346 1347 /* Start I2C slave processing */ 1348 stm32f7_i2c_slave_start(i2c_dev); 1349 1350 /* Clear ADDR flag */ 1351 mask = STM32F7_I2C_ICR_ADDRCF; 1352 writel_relaxed(mask, base + STM32F7_I2C_ICR); 1353 break; 1354 } 1355 } 1356 } 1357 1358 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1359 struct i2c_client *slave, int *id) 1360 { 1361 int i; 1362 1363 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1364 if (i2c_dev->slave[i] == slave) { 1365 *id = i; 1366 return 0; 1367 } 1368 } 1369 1370 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr); 1371 1372 return -ENODEV; 1373 } 1374 1375 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1376 struct i2c_client *slave, int *id) 1377 { 1378 struct device *dev = i2c_dev->dev; 1379 int i; 1380 1381 /* 1382 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8) 1383 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address 1384 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only 1385 */ 1386 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) { 1387 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY]) 1388 goto fail; 1389 *id = STM32F7_SLAVE_HOSTNOTIFY; 1390 return 0; 1391 } 1392 1393 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) { 1394 if ((i == STM32F7_SLAVE_7_BITS_ADDR) && 1395 (slave->flags & I2C_CLIENT_TEN)) 1396 continue; 1397 if (!i2c_dev->slave[i]) { 1398 *id = i; 1399 return 0; 1400 } 1401 } 1402 1403 fail: 1404 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr); 1405 1406 return -EINVAL; 1407 } 1408 1409 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev) 1410 { 1411 int i; 1412 1413 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1414 if (i2c_dev->slave[i]) 1415 return true; 1416 } 1417 1418 return false; 1419 } 1420 1421 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev) 1422 { 1423 int i, busy; 1424 1425 busy = 0; 1426 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1427 if (i2c_dev->slave[i]) 1428 busy++; 1429 } 1430 1431 return i == busy; 1432 } 1433 1434 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev, u32 status) 1435 { 1436 void __iomem *base = i2c_dev->base; 1437 u32 cr2, mask; 1438 u8 val; 1439 int ret; 1440 1441 /* Slave transmitter mode */ 1442 if (status & STM32F7_I2C_ISR_TXIS) { 1443 i2c_slave_event(i2c_dev->slave_running, 1444 I2C_SLAVE_READ_PROCESSED, 1445 &val); 1446 1447 /* Write data byte */ 1448 writel_relaxed(val, base + STM32F7_I2C_TXDR); 1449 } 1450 1451 /* Transfer Complete Reload for Slave receiver mode */ 1452 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) { 1453 /* 1454 * Read data byte then set NBYTES to receive next byte or NACK 1455 * the current received byte 1456 */ 1457 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); 1458 ret = i2c_slave_event(i2c_dev->slave_running, 1459 I2C_SLAVE_WRITE_RECEIVED, 1460 &val); 1461 if (!ret) { 1462 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 1463 cr2 |= STM32F7_I2C_CR2_NBYTES(1); 1464 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 1465 } else { 1466 mask = STM32F7_I2C_CR2_NACK; 1467 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1468 } 1469 } 1470 1471 /* NACK received */ 1472 if (status & STM32F7_I2C_ISR_NACKF) { 1473 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); 1474 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1475 } 1476 1477 /* STOP received */ 1478 if (status & STM32F7_I2C_ISR_STOPF) { 1479 /* Disable interrupts */ 1480 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK); 1481 1482 if (i2c_dev->slave_dir) { 1483 /* 1484 * Flush TX buffer in order to not used the byte in 1485 * TXDR for the next transfer 1486 */ 1487 mask = STM32F7_I2C_ISR_TXE; 1488 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask); 1489 } 1490 1491 /* Clear STOP flag */ 1492 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1493 1494 /* Notify i2c slave that a STOP flag has been detected */ 1495 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val); 1496 1497 i2c_dev->slave_running = NULL; 1498 } 1499 1500 /* Address match received */ 1501 if (status & STM32F7_I2C_ISR_ADDR) 1502 stm32f7_i2c_slave_addr(i2c_dev); 1503 1504 return IRQ_HANDLED; 1505 } 1506 1507 static irqreturn_t stm32f7_i2c_handle_isr_errs(struct stm32f7_i2c_dev *i2c_dev, u32 status) 1508 { 1509 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1510 u16 addr = f7_msg->addr; 1511 void __iomem *base = i2c_dev->base; 1512 struct device *dev = i2c_dev->dev; 1513 struct stm32_i2c_dma *dma = i2c_dev->dma; 1514 1515 /* Bus error */ 1516 if (status & STM32F7_I2C_ISR_BERR) { 1517 dev_err(dev, "Bus error accessing addr 0x%x\n", addr); 1518 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR); 1519 stm32f7_i2c_release_bus(&i2c_dev->adap); 1520 f7_msg->result = -EIO; 1521 } 1522 1523 /* Arbitration loss */ 1524 if (status & STM32F7_I2C_ISR_ARLO) { 1525 dev_dbg(dev, "Arbitration loss accessing addr 0x%x\n", addr); 1526 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR); 1527 f7_msg->result = -EAGAIN; 1528 } 1529 1530 if (status & STM32F7_I2C_ISR_PECERR) { 1531 dev_err(dev, "PEC error in reception accessing addr 0x%x\n", addr); 1532 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR); 1533 f7_msg->result = -EINVAL; 1534 } 1535 1536 if (status & STM32F7_I2C_ISR_ALERT) { 1537 dev_dbg(dev, "SMBus alert received\n"); 1538 writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR); 1539 i2c_handle_smbus_alert(i2c_dev->alert->ara); 1540 return IRQ_HANDLED; 1541 } 1542 1543 if (!i2c_dev->slave_running) { 1544 u32 mask; 1545 /* Disable interrupts */ 1546 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1547 mask = STM32F7_I2C_XFER_IRQ_MASK; 1548 else 1549 mask = STM32F7_I2C_ALL_IRQ_MASK; 1550 stm32f7_i2c_disable_irq(i2c_dev, mask); 1551 } 1552 1553 /* Disable dma */ 1554 if (i2c_dev->use_dma) { 1555 stm32f7_i2c_disable_dma_req(i2c_dev); 1556 dmaengine_terminate_async(dma->chan_using); 1557 } 1558 1559 i2c_dev->master_mode = false; 1560 complete(&i2c_dev->complete); 1561 1562 return IRQ_HANDLED; 1563 } 1564 1565 #define STM32F7_ERR_EVENTS (STM32F7_I2C_ISR_BERR | STM32F7_I2C_ISR_ARLO |\ 1566 STM32F7_I2C_ISR_PECERR | STM32F7_I2C_ISR_ALERT) 1567 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data) 1568 { 1569 struct stm32f7_i2c_dev *i2c_dev = data; 1570 u32 status; 1571 1572 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1573 1574 /* 1575 * Check if the interrupt is for a slave device or related 1576 * to errors flags (in case of single it line mode) 1577 */ 1578 if (!i2c_dev->master_mode || 1579 (i2c_dev->setup.single_it_line && (status & STM32F7_ERR_EVENTS))) 1580 return IRQ_WAKE_THREAD; 1581 1582 /* Tx empty */ 1583 if (status & STM32F7_I2C_ISR_TXIS) 1584 stm32f7_i2c_write_tx_data(i2c_dev); 1585 1586 /* RX not empty */ 1587 if (status & STM32F7_I2C_ISR_RXNE) 1588 stm32f7_i2c_read_rx_data(i2c_dev); 1589 1590 /* Wake up the thread if other flags are raised */ 1591 if (status & 1592 (STM32F7_I2C_ISR_NACKF | STM32F7_I2C_ISR_STOPF | 1593 STM32F7_I2C_ISR_TC | STM32F7_I2C_ISR_TCR)) 1594 return IRQ_WAKE_THREAD; 1595 1596 return IRQ_HANDLED; 1597 } 1598 1599 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data) 1600 { 1601 struct stm32f7_i2c_dev *i2c_dev = data; 1602 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1603 struct stm32_i2c_dma *dma = i2c_dev->dma; 1604 void __iomem *base = i2c_dev->base; 1605 u32 status, mask; 1606 int ret; 1607 1608 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1609 1610 if (!i2c_dev->master_mode) 1611 return stm32f7_i2c_slave_isr_event(i2c_dev, status); 1612 1613 /* Handle errors in case of this handler is used for events/errors */ 1614 if (i2c_dev->setup.single_it_line && (status & STM32F7_ERR_EVENTS)) 1615 return stm32f7_i2c_handle_isr_errs(i2c_dev, status); 1616 1617 /* NACK received */ 1618 if (status & STM32F7_I2C_ISR_NACKF) { 1619 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n", 1620 __func__, f7_msg->addr); 1621 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1622 if (i2c_dev->use_dma) { 1623 stm32f7_i2c_disable_dma_req(i2c_dev); 1624 dmaengine_terminate_async(dma->chan_using); 1625 } 1626 f7_msg->result = -ENXIO; 1627 } 1628 1629 if (status & STM32F7_I2C_ISR_TCR) { 1630 if (f7_msg->smbus) 1631 stm32f7_i2c_smbus_reload(i2c_dev); 1632 else 1633 stm32f7_i2c_reload(i2c_dev); 1634 } 1635 1636 /* Transfer complete */ 1637 if (status & STM32F7_I2C_ISR_TC) { 1638 /* Wait for dma transfer completion before sending next message */ 1639 if (i2c_dev->use_dma && !f7_msg->result) { 1640 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ); 1641 if (!ret) { 1642 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__); 1643 stm32f7_i2c_disable_dma_req(i2c_dev); 1644 dmaengine_terminate_async(dma->chan_using); 1645 f7_msg->result = -ETIMEDOUT; 1646 } 1647 } 1648 if (f7_msg->stop) { 1649 mask = STM32F7_I2C_CR2_STOP; 1650 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1651 } else if (f7_msg->smbus) { 1652 stm32f7_i2c_smbus_rep_start(i2c_dev); 1653 } else { 1654 i2c_dev->msg_id++; 1655 i2c_dev->msg++; 1656 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1657 } 1658 } 1659 1660 /* STOP detection flag */ 1661 if (status & STM32F7_I2C_ISR_STOPF) { 1662 /* Disable interrupts */ 1663 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1664 mask = STM32F7_I2C_XFER_IRQ_MASK; 1665 else 1666 mask = STM32F7_I2C_ALL_IRQ_MASK; 1667 stm32f7_i2c_disable_irq(i2c_dev, mask); 1668 1669 /* Clear STOP flag */ 1670 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1671 1672 i2c_dev->master_mode = false; 1673 complete(&i2c_dev->complete); 1674 } 1675 1676 return IRQ_HANDLED; 1677 } 1678 1679 static irqreturn_t stm32f7_i2c_isr_error_thread(int irq, void *data) 1680 { 1681 struct stm32f7_i2c_dev *i2c_dev = data; 1682 u32 status; 1683 1684 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1685 1686 return stm32f7_i2c_handle_isr_errs(i2c_dev, status); 1687 } 1688 1689 static int stm32f7_i2c_wait_polling(struct stm32f7_i2c_dev *i2c_dev) 1690 { 1691 ktime_t timeout = ktime_add_ms(ktime_get(), i2c_dev->adap.timeout); 1692 1693 while (ktime_compare(ktime_get(), timeout) < 0) { 1694 udelay(5); 1695 stm32f7_i2c_isr_event(0, i2c_dev); 1696 1697 if (completion_done(&i2c_dev->complete)) 1698 return 1; 1699 } 1700 1701 return 0; 1702 } 1703 1704 static int stm32f7_i2c_xfer_core(struct i2c_adapter *i2c_adap, 1705 struct i2c_msg msgs[], int num) 1706 { 1707 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1708 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1709 struct stm32_i2c_dma *dma = i2c_dev->dma; 1710 unsigned long time_left; 1711 int ret; 1712 1713 i2c_dev->msg = msgs; 1714 i2c_dev->msg_num = num; 1715 i2c_dev->msg_id = 0; 1716 f7_msg->smbus = false; 1717 1718 ret = pm_runtime_resume_and_get(i2c_dev->dev); 1719 if (ret < 0) 1720 return ret; 1721 1722 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1723 if (ret) 1724 goto pm_free; 1725 1726 stm32f7_i2c_xfer_msg(i2c_dev, msgs); 1727 1728 if (!i2c_dev->atomic) 1729 time_left = wait_for_completion_timeout(&i2c_dev->complete, 1730 i2c_dev->adap.timeout); 1731 else 1732 time_left = stm32f7_i2c_wait_polling(i2c_dev); 1733 1734 ret = f7_msg->result; 1735 if (ret) { 1736 if (i2c_dev->use_dma) 1737 dmaengine_synchronize(dma->chan_using); 1738 1739 /* 1740 * It is possible that some unsent data have already been 1741 * written into TXDR. To avoid sending old data in a 1742 * further transfer, flush TXDR in case of any error 1743 */ 1744 writel_relaxed(STM32F7_I2C_ISR_TXE, 1745 i2c_dev->base + STM32F7_I2C_ISR); 1746 goto pm_free; 1747 } 1748 1749 if (!time_left) { 1750 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", 1751 i2c_dev->msg->addr); 1752 if (i2c_dev->use_dma) 1753 dmaengine_terminate_sync(dma->chan_using); 1754 stm32f7_i2c_wait_free_bus(i2c_dev); 1755 ret = -ETIMEDOUT; 1756 } 1757 1758 pm_free: 1759 pm_runtime_mark_last_busy(i2c_dev->dev); 1760 pm_runtime_put_autosuspend(i2c_dev->dev); 1761 1762 return (ret < 0) ? ret : num; 1763 } 1764 1765 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap, 1766 struct i2c_msg msgs[], int num) 1767 { 1768 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1769 1770 i2c_dev->atomic = false; 1771 return stm32f7_i2c_xfer_core(i2c_adap, msgs, num); 1772 } 1773 1774 static int stm32f7_i2c_xfer_atomic(struct i2c_adapter *i2c_adap, 1775 struct i2c_msg msgs[], int num) 1776 { 1777 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1778 1779 i2c_dev->atomic = true; 1780 return stm32f7_i2c_xfer_core(i2c_adap, msgs, num); 1781 } 1782 1783 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr, 1784 unsigned short flags, char read_write, 1785 u8 command, int size, 1786 union i2c_smbus_data *data) 1787 { 1788 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); 1789 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1790 struct stm32_i2c_dma *dma = i2c_dev->dma; 1791 struct device *dev = i2c_dev->dev; 1792 unsigned long timeout; 1793 int i, ret; 1794 1795 f7_msg->addr = addr; 1796 f7_msg->size = size; 1797 f7_msg->read_write = read_write; 1798 f7_msg->smbus = true; 1799 1800 ret = pm_runtime_resume_and_get(dev); 1801 if (ret < 0) 1802 return ret; 1803 1804 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1805 if (ret) 1806 goto pm_free; 1807 1808 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data); 1809 if (ret) 1810 goto pm_free; 1811 1812 timeout = wait_for_completion_timeout(&i2c_dev->complete, 1813 i2c_dev->adap.timeout); 1814 ret = f7_msg->result; 1815 if (ret) { 1816 if (i2c_dev->use_dma) 1817 dmaengine_synchronize(dma->chan_using); 1818 1819 /* 1820 * It is possible that some unsent data have already been 1821 * written into TXDR. To avoid sending old data in a 1822 * further transfer, flush TXDR in case of any error 1823 */ 1824 writel_relaxed(STM32F7_I2C_ISR_TXE, 1825 i2c_dev->base + STM32F7_I2C_ISR); 1826 goto pm_free; 1827 } 1828 1829 if (!timeout) { 1830 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr); 1831 if (i2c_dev->use_dma) 1832 dmaengine_terminate_sync(dma->chan_using); 1833 stm32f7_i2c_wait_free_bus(i2c_dev); 1834 ret = -ETIMEDOUT; 1835 goto pm_free; 1836 } 1837 1838 /* Check PEC */ 1839 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) { 1840 ret = stm32f7_i2c_smbus_check_pec(i2c_dev); 1841 if (ret) 1842 goto pm_free; 1843 } 1844 1845 if (read_write && size != I2C_SMBUS_QUICK) { 1846 switch (size) { 1847 case I2C_SMBUS_BYTE: 1848 case I2C_SMBUS_BYTE_DATA: 1849 data->byte = f7_msg->smbus_buf[0]; 1850 break; 1851 case I2C_SMBUS_WORD_DATA: 1852 case I2C_SMBUS_PROC_CALL: 1853 data->word = f7_msg->smbus_buf[0] | 1854 (f7_msg->smbus_buf[1] << 8); 1855 break; 1856 case I2C_SMBUS_BLOCK_DATA: 1857 case I2C_SMBUS_BLOCK_PROC_CALL: 1858 for (i = 0; i <= f7_msg->smbus_buf[0]; i++) 1859 data->block[i] = f7_msg->smbus_buf[i]; 1860 break; 1861 default: 1862 dev_err(dev, "Unsupported smbus transaction\n"); 1863 ret = -EINVAL; 1864 } 1865 } 1866 1867 pm_free: 1868 pm_runtime_mark_last_busy(dev); 1869 pm_runtime_put_autosuspend(dev); 1870 return ret; 1871 } 1872 1873 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev, 1874 bool enable) 1875 { 1876 void __iomem *base = i2c_dev->base; 1877 u32 mask = STM32F7_I2C_CR1_WUPEN; 1878 1879 if (!i2c_dev->wakeup_src) 1880 return; 1881 1882 if (enable) { 1883 device_set_wakeup_enable(i2c_dev->dev, true); 1884 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1885 } else { 1886 device_set_wakeup_enable(i2c_dev->dev, false); 1887 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1888 } 1889 } 1890 1891 static int stm32f7_i2c_reg_slave(struct i2c_client *slave) 1892 { 1893 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1894 void __iomem *base = i2c_dev->base; 1895 struct device *dev = i2c_dev->dev; 1896 u32 oar1, oar2, mask; 1897 int id, ret; 1898 1899 if (slave->flags & I2C_CLIENT_PEC) { 1900 dev_err(dev, "SMBus PEC not supported in slave mode\n"); 1901 return -EINVAL; 1902 } 1903 1904 if (stm32f7_i2c_is_slave_busy(i2c_dev)) { 1905 dev_err(dev, "Too much slave registered\n"); 1906 return -EBUSY; 1907 } 1908 1909 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id); 1910 if (ret) 1911 return ret; 1912 1913 ret = pm_runtime_resume_and_get(dev); 1914 if (ret < 0) 1915 return ret; 1916 1917 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1918 stm32f7_i2c_enable_wakeup(i2c_dev, true); 1919 1920 switch (id) { 1921 case 0: 1922 /* Slave SMBus Host */ 1923 i2c_dev->slave[id] = slave; 1924 break; 1925 1926 case 1: 1927 /* Configure Own Address 1 */ 1928 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 1929 oar1 &= ~STM32F7_I2C_OAR1_MASK; 1930 if (slave->flags & I2C_CLIENT_TEN) { 1931 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr); 1932 oar1 |= STM32F7_I2C_OAR1_OA1MODE; 1933 } else { 1934 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr); 1935 } 1936 oar1 |= STM32F7_I2C_OAR1_OA1EN; 1937 i2c_dev->slave[id] = slave; 1938 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1); 1939 break; 1940 1941 case 2: 1942 /* Configure Own Address 2 */ 1943 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 1944 oar2 &= ~STM32F7_I2C_OAR2_MASK; 1945 if (slave->flags & I2C_CLIENT_TEN) { 1946 ret = -EOPNOTSUPP; 1947 goto pm_free; 1948 } 1949 1950 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr); 1951 oar2 |= STM32F7_I2C_OAR2_OA2EN; 1952 i2c_dev->slave[id] = slave; 1953 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2); 1954 break; 1955 1956 default: 1957 dev_err(dev, "I2C slave id not supported\n"); 1958 ret = -ENODEV; 1959 goto pm_free; 1960 } 1961 1962 /* Enable ACK */ 1963 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK); 1964 1965 /* Enable Address match interrupt, error interrupt and enable I2C */ 1966 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE | 1967 STM32F7_I2C_CR1_PE; 1968 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1969 1970 ret = 0; 1971 pm_free: 1972 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1973 stm32f7_i2c_enable_wakeup(i2c_dev, false); 1974 1975 pm_runtime_mark_last_busy(dev); 1976 pm_runtime_put_autosuspend(dev); 1977 1978 return ret; 1979 } 1980 1981 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave) 1982 { 1983 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1984 void __iomem *base = i2c_dev->base; 1985 u32 mask; 1986 int id, ret; 1987 1988 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id); 1989 if (ret) 1990 return ret; 1991 1992 WARN_ON(!i2c_dev->slave[id]); 1993 1994 ret = pm_runtime_resume_and_get(i2c_dev->dev); 1995 if (ret < 0) 1996 return ret; 1997 1998 if (id == 1) { 1999 mask = STM32F7_I2C_OAR1_OA1EN; 2000 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask); 2001 } else if (id == 2) { 2002 mask = STM32F7_I2C_OAR2_OA2EN; 2003 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask); 2004 } 2005 2006 i2c_dev->slave[id] = NULL; 2007 2008 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 2009 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK); 2010 stm32f7_i2c_enable_wakeup(i2c_dev, false); 2011 } 2012 2013 pm_runtime_mark_last_busy(i2c_dev->dev); 2014 pm_runtime_put_autosuspend(i2c_dev->dev); 2015 2016 return 0; 2017 } 2018 2019 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev, 2020 bool enable) 2021 { 2022 int ret = 0; 2023 2024 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ || 2025 (!i2c_dev->setup.fmp_cr1_bit && IS_ERR_OR_NULL(i2c_dev->regmap))) 2026 /* Optional */ 2027 return 0; 2028 2029 if (i2c_dev->setup.fmp_cr1_bit) { 2030 if (enable) 2031 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP); 2032 else 2033 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP); 2034 } else { 2035 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg) 2036 ret = regmap_update_bits(i2c_dev->regmap, i2c_dev->fmp_sreg, 2037 i2c_dev->fmp_mask, enable ? i2c_dev->fmp_mask : 0); 2038 else 2039 ret = regmap_write(i2c_dev->regmap, 2040 enable ? i2c_dev->fmp_sreg : i2c_dev->fmp_creg, 2041 i2c_dev->fmp_mask); 2042 } 2043 2044 return ret; 2045 } 2046 2047 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev, 2048 struct stm32f7_i2c_dev *i2c_dev) 2049 { 2050 struct device_node *np = pdev->dev.of_node; 2051 int ret; 2052 2053 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp"); 2054 if (IS_ERR(i2c_dev->regmap)) 2055 /* Optional */ 2056 return 0; 2057 2058 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, 2059 &i2c_dev->fmp_sreg); 2060 if (ret) 2061 return ret; 2062 2063 i2c_dev->fmp_creg = i2c_dev->fmp_sreg + 2064 i2c_dev->setup.fmp_clr_offset; 2065 2066 return of_property_read_u32_index(np, "st,syscfg-fmp", 2, 2067 &i2c_dev->fmp_mask); 2068 } 2069 2070 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev) 2071 { 2072 struct i2c_adapter *adap = &i2c_dev->adap; 2073 void __iomem *base = i2c_dev->base; 2074 struct i2c_client *client; 2075 2076 client = i2c_new_slave_host_notify_device(adap); 2077 if (IS_ERR(client)) 2078 return PTR_ERR(client); 2079 2080 i2c_dev->host_notify_client = client; 2081 2082 /* Enable SMBus Host address */ 2083 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN); 2084 2085 return 0; 2086 } 2087 2088 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev) 2089 { 2090 void __iomem *base = i2c_dev->base; 2091 2092 if (i2c_dev->host_notify_client) { 2093 /* Disable SMBus Host address */ 2094 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, 2095 STM32F7_I2C_CR1_SMBHEN); 2096 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client); 2097 } 2098 } 2099 2100 static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 2101 { 2102 struct stm32f7_i2c_alert *alert; 2103 struct i2c_adapter *adap = &i2c_dev->adap; 2104 struct device *dev = i2c_dev->dev; 2105 void __iomem *base = i2c_dev->base; 2106 2107 alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL); 2108 if (!alert) 2109 return -ENOMEM; 2110 2111 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup); 2112 if (IS_ERR(alert->ara)) 2113 return PTR_ERR(alert->ara); 2114 2115 i2c_dev->alert = alert; 2116 2117 /* Enable SMBus Alert */ 2118 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN); 2119 2120 return 0; 2121 } 2122 2123 static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 2124 { 2125 struct stm32f7_i2c_alert *alert = i2c_dev->alert; 2126 void __iomem *base = i2c_dev->base; 2127 2128 if (alert) { 2129 /* Disable SMBus Alert */ 2130 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, 2131 STM32F7_I2C_CR1_ALERTEN); 2132 i2c_unregister_device(alert->ara); 2133 } 2134 } 2135 2136 static u32 stm32f7_i2c_func(struct i2c_adapter *adap) 2137 { 2138 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 2139 2140 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE | 2141 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 2142 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 2143 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 2144 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC | 2145 I2C_FUNC_SMBUS_I2C_BLOCK; 2146 2147 if (i2c_dev->smbus_mode) 2148 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 2149 2150 return func; 2151 } 2152 2153 static const struct i2c_algorithm stm32f7_i2c_algo = { 2154 .master_xfer = stm32f7_i2c_xfer, 2155 .master_xfer_atomic = stm32f7_i2c_xfer_atomic, 2156 .smbus_xfer = stm32f7_i2c_smbus_xfer, 2157 .functionality = stm32f7_i2c_func, 2158 .reg_slave = stm32f7_i2c_reg_slave, 2159 .unreg_slave = stm32f7_i2c_unreg_slave, 2160 }; 2161 2162 static int stm32f7_i2c_probe(struct platform_device *pdev) 2163 { 2164 struct stm32f7_i2c_dev *i2c_dev; 2165 const struct stm32f7_i2c_setup *setup; 2166 struct resource *res; 2167 struct i2c_adapter *adap; 2168 struct reset_control *rst; 2169 dma_addr_t phy_addr; 2170 int irq_error, irq_event, ret; 2171 2172 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 2173 if (!i2c_dev) 2174 return -ENOMEM; 2175 2176 setup = of_device_get_match_data(&pdev->dev); 2177 if (!setup) { 2178 dev_err(&pdev->dev, "Can't get device data\n"); 2179 return -ENODEV; 2180 } 2181 i2c_dev->setup = *setup; 2182 2183 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2184 if (IS_ERR(i2c_dev->base)) 2185 return PTR_ERR(i2c_dev->base); 2186 phy_addr = (dma_addr_t)res->start; 2187 2188 irq_event = platform_get_irq(pdev, 0); 2189 if (irq_event < 0) 2190 return irq_event; 2191 2192 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node, 2193 "wakeup-source"); 2194 2195 i2c_dev->clk = devm_clk_get_enabled(&pdev->dev, NULL); 2196 if (IS_ERR(i2c_dev->clk)) 2197 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk), 2198 "Failed to enable controller clock\n"); 2199 2200 rst = devm_reset_control_get(&pdev->dev, NULL); 2201 if (IS_ERR(rst)) 2202 return dev_err_probe(&pdev->dev, PTR_ERR(rst), 2203 "Error: Missing reset ctrl\n"); 2204 2205 reset_control_assert(rst); 2206 udelay(2); 2207 reset_control_deassert(rst); 2208 2209 i2c_dev->dev = &pdev->dev; 2210 2211 ret = devm_request_threaded_irq(&pdev->dev, irq_event, 2212 stm32f7_i2c_isr_event, 2213 stm32f7_i2c_isr_event_thread, 2214 IRQF_ONESHOT, 2215 pdev->name, i2c_dev); 2216 if (ret) 2217 return dev_err_probe(&pdev->dev, ret, "Failed to request irq event\n"); 2218 2219 if (!i2c_dev->setup.single_it_line) { 2220 irq_error = platform_get_irq(pdev, 1); 2221 if (irq_error < 0) 2222 return irq_error; 2223 2224 ret = devm_request_threaded_irq(&pdev->dev, irq_error, 2225 NULL, 2226 stm32f7_i2c_isr_error_thread, 2227 IRQF_ONESHOT, 2228 pdev->name, i2c_dev); 2229 if (ret) 2230 return dev_err_probe(&pdev->dev, ret, "Failed to request irq error\n"); 2231 } 2232 2233 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup); 2234 if (ret) 2235 return ret; 2236 2237 /* Setup Fast mode plus if necessary */ 2238 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) { 2239 if (!i2c_dev->setup.fmp_cr1_bit) { 2240 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev); 2241 if (ret) 2242 return ret; 2243 } 2244 2245 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2246 if (ret) 2247 return ret; 2248 } 2249 2250 adap = &i2c_dev->adap; 2251 i2c_set_adapdata(adap, i2c_dev); 2252 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)", 2253 &res->start); 2254 adap->owner = THIS_MODULE; 2255 adap->timeout = 2 * HZ; 2256 adap->retries = 3; 2257 adap->algo = &stm32f7_i2c_algo; 2258 adap->dev.parent = &pdev->dev; 2259 adap->dev.of_node = pdev->dev.of_node; 2260 2261 init_completion(&i2c_dev->complete); 2262 2263 /* Init DMA config if supported */ 2264 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr, 2265 STM32F7_I2C_TXDR, 2266 STM32F7_I2C_RXDR); 2267 if (IS_ERR(i2c_dev->dma)) { 2268 ret = PTR_ERR(i2c_dev->dma); 2269 /* DMA support is optional, only report other errors */ 2270 if (ret != -ENODEV) 2271 goto fmp_clear; 2272 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n"); 2273 i2c_dev->dma = NULL; 2274 } 2275 2276 if (i2c_dev->wakeup_src) { 2277 device_set_wakeup_capable(i2c_dev->dev, true); 2278 2279 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event); 2280 if (ret) { 2281 dev_err(i2c_dev->dev, "Failed to set wake up irq\n"); 2282 goto clr_wakeup_capable; 2283 } 2284 } 2285 2286 platform_set_drvdata(pdev, i2c_dev); 2287 2288 pm_runtime_set_autosuspend_delay(i2c_dev->dev, 2289 STM32F7_AUTOSUSPEND_DELAY); 2290 pm_runtime_use_autosuspend(i2c_dev->dev); 2291 pm_runtime_set_active(i2c_dev->dev); 2292 pm_runtime_enable(i2c_dev->dev); 2293 2294 pm_runtime_get_noresume(&pdev->dev); 2295 2296 stm32f7_i2c_hw_config(i2c_dev); 2297 2298 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus"); 2299 2300 ret = i2c_add_adapter(adap); 2301 if (ret) 2302 goto pm_disable; 2303 2304 if (i2c_dev->smbus_mode) { 2305 ret = stm32f7_i2c_enable_smbus_host(i2c_dev); 2306 if (ret) { 2307 dev_err(i2c_dev->dev, 2308 "failed to enable SMBus Host-Notify protocol (%d)\n", 2309 ret); 2310 goto i2c_adapter_remove; 2311 } 2312 } 2313 2314 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) { 2315 ret = stm32f7_i2c_enable_smbus_alert(i2c_dev); 2316 if (ret) { 2317 dev_err(i2c_dev->dev, 2318 "failed to enable SMBus alert protocol (%d)\n", 2319 ret); 2320 goto i2c_disable_smbus_host; 2321 } 2322 } 2323 2324 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); 2325 2326 pm_runtime_mark_last_busy(i2c_dev->dev); 2327 pm_runtime_put_autosuspend(i2c_dev->dev); 2328 2329 return 0; 2330 2331 i2c_disable_smbus_host: 2332 stm32f7_i2c_disable_smbus_host(i2c_dev); 2333 2334 i2c_adapter_remove: 2335 i2c_del_adapter(adap); 2336 2337 pm_disable: 2338 pm_runtime_put_noidle(i2c_dev->dev); 2339 pm_runtime_disable(i2c_dev->dev); 2340 pm_runtime_set_suspended(i2c_dev->dev); 2341 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2342 2343 if (i2c_dev->wakeup_src) 2344 dev_pm_clear_wake_irq(i2c_dev->dev); 2345 2346 clr_wakeup_capable: 2347 if (i2c_dev->wakeup_src) 2348 device_set_wakeup_capable(i2c_dev->dev, false); 2349 2350 if (i2c_dev->dma) { 2351 stm32_i2c_dma_free(i2c_dev->dma); 2352 i2c_dev->dma = NULL; 2353 } 2354 2355 fmp_clear: 2356 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2357 2358 return ret; 2359 } 2360 2361 static void stm32f7_i2c_remove(struct platform_device *pdev) 2362 { 2363 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 2364 2365 stm32f7_i2c_disable_smbus_alert(i2c_dev); 2366 stm32f7_i2c_disable_smbus_host(i2c_dev); 2367 2368 i2c_del_adapter(&i2c_dev->adap); 2369 pm_runtime_get_sync(i2c_dev->dev); 2370 2371 if (i2c_dev->wakeup_src) { 2372 dev_pm_clear_wake_irq(i2c_dev->dev); 2373 /* 2374 * enforce that wakeup is disabled and that the device 2375 * is marked as non wakeup capable 2376 */ 2377 device_init_wakeup(i2c_dev->dev, false); 2378 } 2379 2380 pm_runtime_put_noidle(i2c_dev->dev); 2381 pm_runtime_disable(i2c_dev->dev); 2382 pm_runtime_set_suspended(i2c_dev->dev); 2383 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2384 2385 if (i2c_dev->dma) { 2386 stm32_i2c_dma_free(i2c_dev->dma); 2387 i2c_dev->dma = NULL; 2388 } 2389 2390 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2391 } 2392 2393 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev) 2394 { 2395 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2396 2397 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 2398 clk_disable_unprepare(i2c_dev->clk); 2399 2400 return 0; 2401 } 2402 2403 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev) 2404 { 2405 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2406 int ret; 2407 2408 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 2409 ret = clk_prepare_enable(i2c_dev->clk); 2410 if (ret) { 2411 dev_err(dev, "failed to prepare_enable clock\n"); 2412 return ret; 2413 } 2414 } 2415 2416 return 0; 2417 } 2418 2419 static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev) 2420 { 2421 int ret; 2422 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2423 2424 ret = pm_runtime_resume_and_get(i2c_dev->dev); 2425 if (ret < 0) 2426 return ret; 2427 2428 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2429 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 2430 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 2431 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 2432 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR); 2433 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2434 2435 pm_runtime_put_sync(i2c_dev->dev); 2436 2437 return ret; 2438 } 2439 2440 static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev) 2441 { 2442 u32 cr1; 2443 int ret; 2444 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2445 2446 ret = pm_runtime_resume_and_get(i2c_dev->dev); 2447 if (ret < 0) 2448 return ret; 2449 2450 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2451 if (cr1 & STM32F7_I2C_CR1_PE) 2452 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 2453 STM32F7_I2C_CR1_PE); 2454 2455 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR); 2456 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE, 2457 i2c_dev->base + STM32F7_I2C_CR1); 2458 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE) 2459 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 2460 STM32F7_I2C_CR1_PE); 2461 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2); 2462 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1); 2463 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2); 2464 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2465 2466 pm_runtime_put_sync(i2c_dev->dev); 2467 2468 return ret; 2469 } 2470 2471 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev) 2472 { 2473 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2474 int ret; 2475 2476 i2c_mark_adapter_suspended(&i2c_dev->adap); 2477 2478 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) { 2479 ret = stm32f7_i2c_regs_backup(i2c_dev); 2480 if (ret < 0) { 2481 i2c_mark_adapter_resumed(&i2c_dev->adap); 2482 return ret; 2483 } 2484 2485 pinctrl_pm_select_sleep_state(dev); 2486 pm_runtime_force_suspend(dev); 2487 } 2488 2489 return 0; 2490 } 2491 2492 static int __maybe_unused stm32f7_i2c_resume(struct device *dev) 2493 { 2494 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2495 int ret; 2496 2497 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) { 2498 ret = pm_runtime_force_resume(dev); 2499 if (ret < 0) 2500 return ret; 2501 pinctrl_pm_select_default_state(dev); 2502 2503 ret = stm32f7_i2c_regs_restore(i2c_dev); 2504 if (ret < 0) 2505 return ret; 2506 } 2507 2508 i2c_mark_adapter_resumed(&i2c_dev->adap); 2509 2510 return 0; 2511 } 2512 2513 static const struct dev_pm_ops stm32f7_i2c_pm_ops = { 2514 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend, 2515 stm32f7_i2c_runtime_resume, NULL) 2516 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume) 2517 }; 2518 2519 static const struct of_device_id stm32f7_i2c_match[] = { 2520 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup}, 2521 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup}, 2522 { .compatible = "st,stm32mp13-i2c", .data = &stm32mp13_setup}, 2523 { .compatible = "st,stm32mp25-i2c", .data = &stm32mp25_setup}, 2524 {}, 2525 }; 2526 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match); 2527 2528 static struct platform_driver stm32f7_i2c_driver = { 2529 .driver = { 2530 .name = "stm32f7-i2c", 2531 .of_match_table = stm32f7_i2c_match, 2532 .pm = &stm32f7_i2c_pm_ops, 2533 }, 2534 .probe = stm32f7_i2c_probe, 2535 .remove_new = stm32f7_i2c_remove, 2536 }; 2537 2538 module_platform_driver(stm32f7_i2c_driver); 2539 2540 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); 2541 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver"); 2542 MODULE_LICENSE("GPL v2"); 2543