1 /* 2 * Driver for STMicroelectronics STM32 I2C controller 3 * 4 * This I2C controller is described in the STM32F429/439 Soc reference manual. 5 * Please see below a link to the documentation: 6 * http://www.st.com/resource/en/reference_manual/DM00031020.pdf 7 * 8 * Copyright (C) M'boumba Cedric Madianga 2016 9 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 10 * 11 * This driver is based on i2c-st.c 12 * 13 * License terms: GNU General Public License (GPL), version 2 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/i2c.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/module.h> 24 #include <linux/of_address.h> 25 #include <linux/of_irq.h> 26 #include <linux/of.h> 27 #include <linux/platform_device.h> 28 #include <linux/reset.h> 29 30 /* STM32F4 I2C offset registers */ 31 #define STM32F4_I2C_CR1 0x00 32 #define STM32F4_I2C_CR2 0x04 33 #define STM32F4_I2C_DR 0x10 34 #define STM32F4_I2C_SR1 0x14 35 #define STM32F4_I2C_SR2 0x18 36 #define STM32F4_I2C_CCR 0x1C 37 #define STM32F4_I2C_TRISE 0x20 38 #define STM32F4_I2C_FLTR 0x24 39 40 /* STM32F4 I2C control 1*/ 41 #define STM32F4_I2C_CR1_POS BIT(11) 42 #define STM32F4_I2C_CR1_ACK BIT(10) 43 #define STM32F4_I2C_CR1_STOP BIT(9) 44 #define STM32F4_I2C_CR1_START BIT(8) 45 #define STM32F4_I2C_CR1_PE BIT(0) 46 47 /* STM32F4 I2C control 2 */ 48 #define STM32F4_I2C_CR2_FREQ_MASK GENMASK(5, 0) 49 #define STM32F4_I2C_CR2_FREQ(n) ((n) & STM32F4_I2C_CR2_FREQ_MASK) 50 #define STM32F4_I2C_CR2_ITBUFEN BIT(10) 51 #define STM32F4_I2C_CR2_ITEVTEN BIT(9) 52 #define STM32F4_I2C_CR2_ITERREN BIT(8) 53 #define STM32F4_I2C_CR2_IRQ_MASK (STM32F4_I2C_CR2_ITBUFEN | \ 54 STM32F4_I2C_CR2_ITEVTEN | \ 55 STM32F4_I2C_CR2_ITERREN) 56 57 /* STM32F4 I2C Status 1 */ 58 #define STM32F4_I2C_SR1_AF BIT(10) 59 #define STM32F4_I2C_SR1_ARLO BIT(9) 60 #define STM32F4_I2C_SR1_BERR BIT(8) 61 #define STM32F4_I2C_SR1_TXE BIT(7) 62 #define STM32F4_I2C_SR1_RXNE BIT(6) 63 #define STM32F4_I2C_SR1_BTF BIT(2) 64 #define STM32F4_I2C_SR1_ADDR BIT(1) 65 #define STM32F4_I2C_SR1_SB BIT(0) 66 #define STM32F4_I2C_SR1_ITEVTEN_MASK (STM32F4_I2C_SR1_BTF | \ 67 STM32F4_I2C_SR1_ADDR | \ 68 STM32F4_I2C_SR1_SB) 69 #define STM32F4_I2C_SR1_ITBUFEN_MASK (STM32F4_I2C_SR1_TXE | \ 70 STM32F4_I2C_SR1_RXNE) 71 #define STM32F4_I2C_SR1_ITERREN_MASK (STM32F4_I2C_SR1_AF | \ 72 STM32F4_I2C_SR1_ARLO | \ 73 STM32F4_I2C_SR1_BERR) 74 75 /* STM32F4 I2C Status 2 */ 76 #define STM32F4_I2C_SR2_BUSY BIT(1) 77 78 /* STM32F4 I2C Control Clock */ 79 #define STM32F4_I2C_CCR_CCR_MASK GENMASK(11, 0) 80 #define STM32F4_I2C_CCR_CCR(n) ((n) & STM32F4_I2C_CCR_CCR_MASK) 81 #define STM32F4_I2C_CCR_FS BIT(15) 82 #define STM32F4_I2C_CCR_DUTY BIT(14) 83 84 /* STM32F4 I2C Trise */ 85 #define STM32F4_I2C_TRISE_VALUE_MASK GENMASK(5, 0) 86 #define STM32F4_I2C_TRISE_VALUE(n) ((n) & STM32F4_I2C_TRISE_VALUE_MASK) 87 88 #define STM32F4_I2C_MIN_STANDARD_FREQ 2U 89 #define STM32F4_I2C_MIN_FAST_FREQ 6U 90 #define STM32F4_I2C_MAX_FREQ 46U 91 #define HZ_TO_MHZ 1000000 92 93 enum stm32f4_i2c_speed { 94 STM32F4_I2C_SPEED_STANDARD, /* 100 kHz */ 95 STM32F4_I2C_SPEED_FAST, /* 400 kHz */ 96 STM32F4_I2C_SPEED_END, 97 }; 98 99 /** 100 * struct stm32f4_i2c_msg - client specific data 101 * @addr: 8-bit slave addr, including r/w bit 102 * @count: number of bytes to be transferred 103 * @buf: data buffer 104 * @result: result of the transfer 105 * @stop: last I2C msg to be sent, i.e. STOP to be generated 106 */ 107 struct stm32f4_i2c_msg { 108 u8 addr; 109 u32 count; 110 u8 *buf; 111 int result; 112 bool stop; 113 }; 114 115 /** 116 * struct stm32f4_i2c_dev - private data of the controller 117 * @adap: I2C adapter for this controller 118 * @dev: device for this controller 119 * @base: virtual memory area 120 * @complete: completion of I2C message 121 * @clk: hw i2c clock 122 * @speed: I2C clock frequency of the controller. Standard or Fast are supported 123 * @parent_rate: I2C clock parent rate in MHz 124 * @msg: I2C transfer information 125 */ 126 struct stm32f4_i2c_dev { 127 struct i2c_adapter adap; 128 struct device *dev; 129 void __iomem *base; 130 struct completion complete; 131 struct clk *clk; 132 int speed; 133 int parent_rate; 134 struct stm32f4_i2c_msg msg; 135 }; 136 137 static inline void stm32f4_i2c_set_bits(void __iomem *reg, u32 mask) 138 { 139 writel_relaxed(readl_relaxed(reg) | mask, reg); 140 } 141 142 static inline void stm32f4_i2c_clr_bits(void __iomem *reg, u32 mask) 143 { 144 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 145 } 146 147 static void stm32f4_i2c_disable_irq(struct stm32f4_i2c_dev *i2c_dev) 148 { 149 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; 150 151 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_IRQ_MASK); 152 } 153 154 static int stm32f4_i2c_set_periph_clk_freq(struct stm32f4_i2c_dev *i2c_dev) 155 { 156 u32 freq; 157 u32 cr2 = 0; 158 159 i2c_dev->parent_rate = clk_get_rate(i2c_dev->clk); 160 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ); 161 162 if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD) { 163 /* 164 * To reach 100 kHz, the parent clk frequency should be between 165 * a minimum value of 2 MHz and a maximum value of 46 MHz due 166 * to hardware limitation 167 */ 168 if (freq < STM32F4_I2C_MIN_STANDARD_FREQ || 169 freq > STM32F4_I2C_MAX_FREQ) { 170 dev_err(i2c_dev->dev, 171 "bad parent clk freq for standard mode\n"); 172 return -EINVAL; 173 } 174 } else { 175 /* 176 * To be as close as possible to 400 kHz, the parent clk 177 * frequency should be between a minimum value of 6 MHz and a 178 * maximum value of 46 MHz due to hardware limitation 179 */ 180 if (freq < STM32F4_I2C_MIN_FAST_FREQ || 181 freq > STM32F4_I2C_MAX_FREQ) { 182 dev_err(i2c_dev->dev, 183 "bad parent clk freq for fast mode\n"); 184 return -EINVAL; 185 } 186 } 187 188 cr2 |= STM32F4_I2C_CR2_FREQ(freq); 189 writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2); 190 191 return 0; 192 } 193 194 static void stm32f4_i2c_set_rise_time(struct stm32f4_i2c_dev *i2c_dev) 195 { 196 u32 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ); 197 u32 trise; 198 199 /* 200 * These bits must be programmed with the maximum SCL rise time given in 201 * the I2C bus specification, incremented by 1. 202 * 203 * In standard mode, the maximum allowed SCL rise time is 1000 ns. 204 * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 205 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be 206 * programmed with 0x9. (1000 ns / 125 ns + 1) 207 * So, for I2C standard mode TRISE = FREQ[5:0] + 1 208 * 209 * In fast mode, the maximum allowed SCL rise time is 300 ns. 210 * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 211 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be 212 * programmed with 0x3. (300 ns / 125 ns + 1) 213 * So, for I2C fast mode TRISE = FREQ[5:0] * 300 / 1000 + 1 214 * 215 * Function stm32f4_i2c_set_periph_clk_freq made sure that parent rate 216 * is not higher than 46 MHz . As a result trise is at most 4 bits wide 217 * and so fits into the TRISE bits [5:0]. 218 */ 219 if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD) 220 trise = freq + 1; 221 else 222 trise = freq * 3 / 10 + 1; 223 224 writel_relaxed(STM32F4_I2C_TRISE_VALUE(trise), 225 i2c_dev->base + STM32F4_I2C_TRISE); 226 } 227 228 static void stm32f4_i2c_set_speed_mode(struct stm32f4_i2c_dev *i2c_dev) 229 { 230 u32 val; 231 u32 ccr = 0; 232 233 if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD) { 234 /* 235 * In standard mode: 236 * t_scl_high = t_scl_low = CCR * I2C parent clk period 237 * So to reach 100 kHz, we have: 238 * CCR = I2C parent rate / 100 kHz >> 1 239 * 240 * For example with parent rate = 2 MHz: 241 * CCR = 2000000 / (100000 << 1) = 10 242 * t_scl_high = t_scl_low = 10 * (1 / 2000000) = 5000 ns 243 * t_scl_high + t_scl_low = 10000 ns so 100 kHz is reached 244 * 245 * Function stm32f4_i2c_set_periph_clk_freq made sure that 246 * parent rate is not higher than 46 MHz . As a result val 247 * is at most 8 bits wide and so fits into the CCR bits [11:0]. 248 */ 249 val = i2c_dev->parent_rate / (100000 << 1); 250 } else { 251 /* 252 * In fast mode, we compute CCR with duty = 0 as with low 253 * frequencies we are not able to reach 400 kHz. 254 * In that case: 255 * t_scl_high = CCR * I2C parent clk period 256 * t_scl_low = 2 * CCR * I2C parent clk period 257 * So, CCR = I2C parent rate / (400 kHz * 3) 258 * 259 * For example with parent rate = 6 MHz: 260 * CCR = 6000000 / (400000 * 3) = 5 261 * t_scl_high = 5 * (1 / 6000000) = 833 ns > 600 ns 262 * t_scl_low = 2 * 5 * (1 / 6000000) = 1667 ns > 1300 ns 263 * t_scl_high + t_scl_low = 2500 ns so 400 kHz is reached 264 * 265 * Function stm32f4_i2c_set_periph_clk_freq made sure that 266 * parent rate is not higher than 46 MHz . As a result val 267 * is at most 6 bits wide and so fits into the CCR bits [11:0]. 268 */ 269 val = DIV_ROUND_UP(i2c_dev->parent_rate, 400000 * 3); 270 271 /* Select Fast mode */ 272 ccr |= STM32F4_I2C_CCR_FS; 273 } 274 275 ccr |= STM32F4_I2C_CCR_CCR(val); 276 writel_relaxed(ccr, i2c_dev->base + STM32F4_I2C_CCR); 277 } 278 279 /** 280 * stm32f4_i2c_hw_config() - Prepare I2C block 281 * @i2c_dev: Controller's private data 282 */ 283 static int stm32f4_i2c_hw_config(struct stm32f4_i2c_dev *i2c_dev) 284 { 285 int ret; 286 287 ret = stm32f4_i2c_set_periph_clk_freq(i2c_dev); 288 if (ret) 289 return ret; 290 291 stm32f4_i2c_set_rise_time(i2c_dev); 292 293 stm32f4_i2c_set_speed_mode(i2c_dev); 294 295 /* Enable I2C */ 296 writel_relaxed(STM32F4_I2C_CR1_PE, i2c_dev->base + STM32F4_I2C_CR1); 297 298 return 0; 299 } 300 301 static int stm32f4_i2c_wait_free_bus(struct stm32f4_i2c_dev *i2c_dev) 302 { 303 u32 status; 304 int ret; 305 306 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F4_I2C_SR2, 307 status, 308 !(status & STM32F4_I2C_SR2_BUSY), 309 10, 1000); 310 if (ret) { 311 dev_dbg(i2c_dev->dev, "bus not free\n"); 312 ret = -EBUSY; 313 } 314 315 return ret; 316 } 317 318 /** 319 * stm32f4_i2c_write_ byte() - Write a byte in the data register 320 * @i2c_dev: Controller's private data 321 * @byte: Data to write in the register 322 */ 323 static void stm32f4_i2c_write_byte(struct stm32f4_i2c_dev *i2c_dev, u8 byte) 324 { 325 writel_relaxed(byte, i2c_dev->base + STM32F4_I2C_DR); 326 } 327 328 /** 329 * stm32f4_i2c_write_msg() - Fill the data register in write mode 330 * @i2c_dev: Controller's private data 331 * 332 * This function fills the data register with I2C transfer buffer 333 */ 334 static void stm32f4_i2c_write_msg(struct stm32f4_i2c_dev *i2c_dev) 335 { 336 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 337 338 stm32f4_i2c_write_byte(i2c_dev, *msg->buf++); 339 msg->count--; 340 } 341 342 static void stm32f4_i2c_read_msg(struct stm32f4_i2c_dev *i2c_dev) 343 { 344 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 345 u32 rbuf; 346 347 rbuf = readl_relaxed(i2c_dev->base + STM32F4_I2C_DR); 348 *msg->buf++ = rbuf; 349 msg->count--; 350 } 351 352 static void stm32f4_i2c_terminate_xfer(struct stm32f4_i2c_dev *i2c_dev) 353 { 354 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 355 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; 356 357 stm32f4_i2c_disable_irq(i2c_dev); 358 359 reg = i2c_dev->base + STM32F4_I2C_CR1; 360 if (msg->stop) 361 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); 362 else 363 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); 364 365 complete(&i2c_dev->complete); 366 } 367 368 /** 369 * stm32f4_i2c_handle_write() - Handle FIFO empty interrupt in case of write 370 * @i2c_dev: Controller's private data 371 */ 372 static void stm32f4_i2c_handle_write(struct stm32f4_i2c_dev *i2c_dev) 373 { 374 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 375 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; 376 377 if (msg->count) { 378 stm32f4_i2c_write_msg(i2c_dev); 379 if (!msg->count) { 380 /* 381 * Disable buffer interrupts for RX not empty and TX 382 * empty events 383 */ 384 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN); 385 } 386 } else { 387 stm32f4_i2c_terminate_xfer(i2c_dev); 388 } 389 } 390 391 /** 392 * stm32f4_i2c_handle_read() - Handle FIFO empty interrupt in case of read 393 * @i2c_dev: Controller's private data 394 * 395 * This function is called when a new data is received in data register 396 */ 397 static void stm32f4_i2c_handle_read(struct stm32f4_i2c_dev *i2c_dev) 398 { 399 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 400 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; 401 402 switch (msg->count) { 403 case 1: 404 stm32f4_i2c_disable_irq(i2c_dev); 405 stm32f4_i2c_read_msg(i2c_dev); 406 complete(&i2c_dev->complete); 407 break; 408 /* 409 * For 2-byte reception, 3-byte reception and for Data N-2, N-1 and N 410 * for N-byte reception with N > 3, we do not have to read the data 411 * register when RX not empty event occurs as we have to wait for byte 412 * transferred finished event before reading data. 413 * So, here we just disable buffer interrupt in order to avoid another 414 * system preemption due to RX not empty event. 415 */ 416 case 2: 417 case 3: 418 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN); 419 break; 420 /* 421 * For N byte reception with N > 3 we directly read data register 422 * until N-2 data. 423 */ 424 default: 425 stm32f4_i2c_read_msg(i2c_dev); 426 } 427 } 428 429 /** 430 * stm32f4_i2c_handle_rx_done() - Handle byte transfer finished interrupt 431 * in case of read 432 * @i2c_dev: Controller's private data 433 * 434 * This function is called when a new data is received in the shift register 435 * but data register has not been read yet. 436 */ 437 static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev) 438 { 439 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 440 void __iomem *reg; 441 u32 mask; 442 int i; 443 444 switch (msg->count) { 445 case 2: 446 /* 447 * In order to correctly send the Stop or Repeated Start 448 * condition on the I2C bus, the STOP/START bit has to be set 449 * before reading the last two bytes (data N-1 and N). 450 * After that, we could read the last two bytes, disable 451 * remaining interrupts and notify the end of xfer to the 452 * client 453 */ 454 reg = i2c_dev->base + STM32F4_I2C_CR1; 455 if (msg->stop) 456 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); 457 else 458 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); 459 460 for (i = 2; i > 0; i--) 461 stm32f4_i2c_read_msg(i2c_dev); 462 463 reg = i2c_dev->base + STM32F4_I2C_CR2; 464 mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN; 465 stm32f4_i2c_clr_bits(reg, mask); 466 467 complete(&i2c_dev->complete); 468 break; 469 case 3: 470 /* 471 * In order to correctly generate the NACK pulse after the last 472 * received data byte, we have to enable NACK before reading N-2 473 * data 474 */ 475 reg = i2c_dev->base + STM32F4_I2C_CR1; 476 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR1_ACK); 477 stm32f4_i2c_read_msg(i2c_dev); 478 break; 479 default: 480 stm32f4_i2c_read_msg(i2c_dev); 481 } 482 } 483 484 /** 485 * stm32f4_i2c_handle_rx_addr() - Handle address matched interrupt in case of 486 * master receiver 487 * @i2c_dev: Controller's private data 488 */ 489 static void stm32f4_i2c_handle_rx_addr(struct stm32f4_i2c_dev *i2c_dev) 490 { 491 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 492 u32 cr1; 493 494 switch (msg->count) { 495 case 0: 496 stm32f4_i2c_terminate_xfer(i2c_dev); 497 498 /* Clear ADDR flag */ 499 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); 500 break; 501 case 1: 502 /* 503 * Single byte reception: 504 * Enable NACK and reset POS (Acknowledge position). 505 * Then, clear ADDR flag and set STOP or RepSTART. 506 * In that way, the NACK and STOP or RepStart pulses will be 507 * sent as soon as the byte will be received in shift register 508 */ 509 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); 510 cr1 &= ~(STM32F4_I2C_CR1_ACK | STM32F4_I2C_CR1_POS); 511 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); 512 513 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); 514 515 if (msg->stop) 516 cr1 |= STM32F4_I2C_CR1_STOP; 517 else 518 cr1 |= STM32F4_I2C_CR1_START; 519 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); 520 break; 521 case 2: 522 /* 523 * 2-byte reception: 524 * Enable NACK, set POS (NACK position) and clear ADDR flag. 525 * In that way, NACK will be sent for the next byte which will 526 * be received in the shift register instead of the current 527 * one. 528 */ 529 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); 530 cr1 &= ~STM32F4_I2C_CR1_ACK; 531 cr1 |= STM32F4_I2C_CR1_POS; 532 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); 533 534 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); 535 break; 536 537 default: 538 /* 539 * N-byte reception: 540 * Enable ACK, reset POS (ACK postion) and clear ADDR flag. 541 * In that way, ACK will be sent as soon as the current byte 542 * will be received in the shift register 543 */ 544 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); 545 cr1 |= STM32F4_I2C_CR1_ACK; 546 cr1 &= ~STM32F4_I2C_CR1_POS; 547 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); 548 549 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); 550 break; 551 } 552 } 553 554 /** 555 * stm32f4_i2c_isr_event() - Interrupt routine for I2C bus event 556 * @irq: interrupt number 557 * @data: Controller's private data 558 */ 559 static irqreturn_t stm32f4_i2c_isr_event(int irq, void *data) 560 { 561 struct stm32f4_i2c_dev *i2c_dev = data; 562 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 563 u32 possible_status = STM32F4_I2C_SR1_ITEVTEN_MASK; 564 u32 status, ien, event, cr2; 565 566 cr2 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR2); 567 ien = cr2 & STM32F4_I2C_CR2_IRQ_MASK; 568 569 /* Update possible_status if buffer interrupt is enabled */ 570 if (ien & STM32F4_I2C_CR2_ITBUFEN) 571 possible_status |= STM32F4_I2C_SR1_ITBUFEN_MASK; 572 573 status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1); 574 event = status & possible_status; 575 if (!event) { 576 dev_dbg(i2c_dev->dev, 577 "spurious evt irq (status=0x%08x, ien=0x%08x)\n", 578 status, ien); 579 return IRQ_NONE; 580 } 581 582 /* Start condition generated */ 583 if (event & STM32F4_I2C_SR1_SB) 584 stm32f4_i2c_write_byte(i2c_dev, msg->addr); 585 586 /* I2C Address sent */ 587 if (event & STM32F4_I2C_SR1_ADDR) { 588 if (msg->addr & I2C_M_RD) 589 stm32f4_i2c_handle_rx_addr(i2c_dev); 590 else 591 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); 592 593 /* 594 * Enable buffer interrupts for RX not empty and TX empty 595 * events 596 */ 597 cr2 |= STM32F4_I2C_CR2_ITBUFEN; 598 writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2); 599 } 600 601 /* TX empty */ 602 if ((event & STM32F4_I2C_SR1_TXE) && !(msg->addr & I2C_M_RD)) 603 stm32f4_i2c_handle_write(i2c_dev); 604 605 /* RX not empty */ 606 if ((event & STM32F4_I2C_SR1_RXNE) && (msg->addr & I2C_M_RD)) 607 stm32f4_i2c_handle_read(i2c_dev); 608 609 /* 610 * The BTF (Byte Transfer finished) event occurs when: 611 * - in reception : a new byte is received in the shift register 612 * but the previous byte has not been read yet from data register 613 * - in transmission: a new byte should be sent but the data register 614 * has not been written yet 615 */ 616 if (event & STM32F4_I2C_SR1_BTF) { 617 if (msg->addr & I2C_M_RD) 618 stm32f4_i2c_handle_rx_done(i2c_dev); 619 else 620 stm32f4_i2c_handle_write(i2c_dev); 621 } 622 623 return IRQ_HANDLED; 624 } 625 626 /** 627 * stm32f4_i2c_isr_error() - Interrupt routine for I2C bus error 628 * @irq: interrupt number 629 * @data: Controller's private data 630 */ 631 static irqreturn_t stm32f4_i2c_isr_error(int irq, void *data) 632 { 633 struct stm32f4_i2c_dev *i2c_dev = data; 634 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 635 void __iomem *reg; 636 u32 status; 637 638 status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1); 639 640 /* Arbitration lost */ 641 if (status & STM32F4_I2C_SR1_ARLO) { 642 status &= ~STM32F4_I2C_SR1_ARLO; 643 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); 644 msg->result = -EAGAIN; 645 } 646 647 /* 648 * Acknowledge failure: 649 * In master transmitter mode a Stop must be generated by software 650 */ 651 if (status & STM32F4_I2C_SR1_AF) { 652 if (!(msg->addr & I2C_M_RD)) { 653 reg = i2c_dev->base + STM32F4_I2C_CR1; 654 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); 655 } 656 status &= ~STM32F4_I2C_SR1_AF; 657 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); 658 msg->result = -EIO; 659 } 660 661 /* Bus error */ 662 if (status & STM32F4_I2C_SR1_BERR) { 663 status &= ~STM32F4_I2C_SR1_BERR; 664 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); 665 msg->result = -EIO; 666 } 667 668 stm32f4_i2c_disable_irq(i2c_dev); 669 complete(&i2c_dev->complete); 670 671 return IRQ_HANDLED; 672 } 673 674 /** 675 * stm32f4_i2c_xfer_msg() - Transfer a single I2C message 676 * @i2c_dev: Controller's private data 677 * @msg: I2C message to transfer 678 * @is_first: first message of the sequence 679 * @is_last: last message of the sequence 680 */ 681 static int stm32f4_i2c_xfer_msg(struct stm32f4_i2c_dev *i2c_dev, 682 struct i2c_msg *msg, bool is_first, 683 bool is_last) 684 { 685 struct stm32f4_i2c_msg *f4_msg = &i2c_dev->msg; 686 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR1; 687 unsigned long timeout; 688 u32 mask; 689 int ret; 690 691 f4_msg->addr = i2c_8bit_addr_from_msg(msg); 692 f4_msg->buf = msg->buf; 693 f4_msg->count = msg->len; 694 f4_msg->result = 0; 695 f4_msg->stop = is_last; 696 697 reinit_completion(&i2c_dev->complete); 698 699 /* Enable events and errors interrupts */ 700 mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN; 701 stm32f4_i2c_set_bits(i2c_dev->base + STM32F4_I2C_CR2, mask); 702 703 if (is_first) { 704 ret = stm32f4_i2c_wait_free_bus(i2c_dev); 705 if (ret) 706 return ret; 707 708 /* START generation */ 709 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); 710 } 711 712 timeout = wait_for_completion_timeout(&i2c_dev->complete, 713 i2c_dev->adap.timeout); 714 ret = f4_msg->result; 715 716 if (!timeout) 717 ret = -ETIMEDOUT; 718 719 return ret; 720 } 721 722 /** 723 * stm32f4_i2c_xfer() - Transfer combined I2C message 724 * @i2c_adap: Adapter pointer to the controller 725 * @msgs: Pointer to data to be written. 726 * @num: Number of messages to be executed 727 */ 728 static int stm32f4_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], 729 int num) 730 { 731 struct stm32f4_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 732 int ret, i; 733 734 ret = clk_enable(i2c_dev->clk); 735 if (ret) { 736 dev_err(i2c_dev->dev, "Failed to enable clock\n"); 737 return ret; 738 } 739 740 for (i = 0; i < num && !ret; i++) 741 ret = stm32f4_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, 742 i == num - 1); 743 744 clk_disable(i2c_dev->clk); 745 746 return (ret < 0) ? ret : num; 747 } 748 749 static u32 stm32f4_i2c_func(struct i2c_adapter *adap) 750 { 751 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 752 } 753 754 static struct i2c_algorithm stm32f4_i2c_algo = { 755 .master_xfer = stm32f4_i2c_xfer, 756 .functionality = stm32f4_i2c_func, 757 }; 758 759 static int stm32f4_i2c_probe(struct platform_device *pdev) 760 { 761 struct device_node *np = pdev->dev.of_node; 762 struct stm32f4_i2c_dev *i2c_dev; 763 struct resource *res; 764 u32 irq_event, irq_error, clk_rate; 765 struct i2c_adapter *adap; 766 struct reset_control *rst; 767 int ret; 768 769 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 770 if (!i2c_dev) 771 return -ENOMEM; 772 773 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 774 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); 775 if (IS_ERR(i2c_dev->base)) 776 return PTR_ERR(i2c_dev->base); 777 778 irq_event = irq_of_parse_and_map(np, 0); 779 if (!irq_event) { 780 dev_err(&pdev->dev, "IRQ event missing or invalid\n"); 781 return -EINVAL; 782 } 783 784 irq_error = irq_of_parse_and_map(np, 1); 785 if (!irq_error) { 786 dev_err(&pdev->dev, "IRQ error missing or invalid\n"); 787 return -EINVAL; 788 } 789 790 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); 791 if (IS_ERR(i2c_dev->clk)) { 792 dev_err(&pdev->dev, "Error: Missing controller clock\n"); 793 return PTR_ERR(i2c_dev->clk); 794 } 795 ret = clk_prepare_enable(i2c_dev->clk); 796 if (ret) { 797 dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n"); 798 return ret; 799 } 800 801 rst = devm_reset_control_get(&pdev->dev, NULL); 802 if (IS_ERR(rst)) { 803 dev_err(&pdev->dev, "Error: Missing controller reset\n"); 804 ret = PTR_ERR(rst); 805 goto clk_free; 806 } 807 reset_control_assert(rst); 808 udelay(2); 809 reset_control_deassert(rst); 810 811 i2c_dev->speed = STM32F4_I2C_SPEED_STANDARD; 812 ret = of_property_read_u32(np, "clock-frequency", &clk_rate); 813 if (!ret && clk_rate >= 400000) 814 i2c_dev->speed = STM32F4_I2C_SPEED_FAST; 815 816 i2c_dev->dev = &pdev->dev; 817 818 ret = devm_request_irq(&pdev->dev, irq_event, stm32f4_i2c_isr_event, 0, 819 pdev->name, i2c_dev); 820 if (ret) { 821 dev_err(&pdev->dev, "Failed to request irq event %i\n", 822 irq_event); 823 goto clk_free; 824 } 825 826 ret = devm_request_irq(&pdev->dev, irq_error, stm32f4_i2c_isr_error, 0, 827 pdev->name, i2c_dev); 828 if (ret) { 829 dev_err(&pdev->dev, "Failed to request irq error %i\n", 830 irq_error); 831 goto clk_free; 832 } 833 834 ret = stm32f4_i2c_hw_config(i2c_dev); 835 if (ret) 836 goto clk_free; 837 838 adap = &i2c_dev->adap; 839 i2c_set_adapdata(adap, i2c_dev); 840 snprintf(adap->name, sizeof(adap->name), "STM32 I2C(%pa)", &res->start); 841 adap->owner = THIS_MODULE; 842 adap->timeout = 2 * HZ; 843 adap->retries = 0; 844 adap->algo = &stm32f4_i2c_algo; 845 adap->dev.parent = &pdev->dev; 846 adap->dev.of_node = pdev->dev.of_node; 847 848 init_completion(&i2c_dev->complete); 849 850 ret = i2c_add_adapter(adap); 851 if (ret) 852 goto clk_free; 853 854 platform_set_drvdata(pdev, i2c_dev); 855 856 clk_disable(i2c_dev->clk); 857 858 dev_info(i2c_dev->dev, "STM32F4 I2C driver registered\n"); 859 860 return 0; 861 862 clk_free: 863 clk_disable_unprepare(i2c_dev->clk); 864 return ret; 865 } 866 867 static int stm32f4_i2c_remove(struct platform_device *pdev) 868 { 869 struct stm32f4_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 870 871 i2c_del_adapter(&i2c_dev->adap); 872 873 clk_unprepare(i2c_dev->clk); 874 875 return 0; 876 } 877 878 static const struct of_device_id stm32f4_i2c_match[] = { 879 { .compatible = "st,stm32f4-i2c", }, 880 {}, 881 }; 882 MODULE_DEVICE_TABLE(of, stm32f4_i2c_match); 883 884 static struct platform_driver stm32f4_i2c_driver = { 885 .driver = { 886 .name = "stm32f4-i2c", 887 .of_match_table = stm32f4_i2c_match, 888 }, 889 .probe = stm32f4_i2c_probe, 890 .remove = stm32f4_i2c_remove, 891 }; 892 893 module_platform_driver(stm32f4_i2c_driver); 894 895 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); 896 MODULE_DESCRIPTION("STMicroelectronics STM32F4 I2C driver"); 897 MODULE_LICENSE("GPL v2"); 898