1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics STM32 I2C controller 4 * 5 * This I2C controller is described in the STM32F429/439 Soc reference manual. 6 * Please see below a link to the documentation: 7 * http://www.st.com/resource/en/reference_manual/DM00031020.pdf 8 * 9 * Copyright (C) M'boumba Cedric Madianga 2016 10 * Copyright (C) STMicroelectronics 2017 11 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 12 * 13 * This driver is based on i2c-st.c 14 * 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/i2c.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/iopoll.h> 24 #include <linux/module.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/of.h> 28 #include <linux/platform_device.h> 29 #include <linux/reset.h> 30 31 #include "i2c-stm32.h" 32 33 /* STM32F4 I2C offset registers */ 34 #define STM32F4_I2C_CR1 0x00 35 #define STM32F4_I2C_CR2 0x04 36 #define STM32F4_I2C_DR 0x10 37 #define STM32F4_I2C_SR1 0x14 38 #define STM32F4_I2C_SR2 0x18 39 #define STM32F4_I2C_CCR 0x1C 40 #define STM32F4_I2C_TRISE 0x20 41 #define STM32F4_I2C_FLTR 0x24 42 43 /* STM32F4 I2C control 1*/ 44 #define STM32F4_I2C_CR1_POS BIT(11) 45 #define STM32F4_I2C_CR1_ACK BIT(10) 46 #define STM32F4_I2C_CR1_STOP BIT(9) 47 #define STM32F4_I2C_CR1_START BIT(8) 48 #define STM32F4_I2C_CR1_PE BIT(0) 49 50 /* STM32F4 I2C control 2 */ 51 #define STM32F4_I2C_CR2_FREQ_MASK GENMASK(5, 0) 52 #define STM32F4_I2C_CR2_FREQ(n) ((n) & STM32F4_I2C_CR2_FREQ_MASK) 53 #define STM32F4_I2C_CR2_ITBUFEN BIT(10) 54 #define STM32F4_I2C_CR2_ITEVTEN BIT(9) 55 #define STM32F4_I2C_CR2_ITERREN BIT(8) 56 #define STM32F4_I2C_CR2_IRQ_MASK (STM32F4_I2C_CR2_ITBUFEN | \ 57 STM32F4_I2C_CR2_ITEVTEN | \ 58 STM32F4_I2C_CR2_ITERREN) 59 60 /* STM32F4 I2C Status 1 */ 61 #define STM32F4_I2C_SR1_AF BIT(10) 62 #define STM32F4_I2C_SR1_ARLO BIT(9) 63 #define STM32F4_I2C_SR1_BERR BIT(8) 64 #define STM32F4_I2C_SR1_TXE BIT(7) 65 #define STM32F4_I2C_SR1_RXNE BIT(6) 66 #define STM32F4_I2C_SR1_BTF BIT(2) 67 #define STM32F4_I2C_SR1_ADDR BIT(1) 68 #define STM32F4_I2C_SR1_SB BIT(0) 69 #define STM32F4_I2C_SR1_ITEVTEN_MASK (STM32F4_I2C_SR1_BTF | \ 70 STM32F4_I2C_SR1_ADDR | \ 71 STM32F4_I2C_SR1_SB) 72 #define STM32F4_I2C_SR1_ITBUFEN_MASK (STM32F4_I2C_SR1_TXE | \ 73 STM32F4_I2C_SR1_RXNE) 74 #define STM32F4_I2C_SR1_ITERREN_MASK (STM32F4_I2C_SR1_AF | \ 75 STM32F4_I2C_SR1_ARLO | \ 76 STM32F4_I2C_SR1_BERR) 77 78 /* STM32F4 I2C Status 2 */ 79 #define STM32F4_I2C_SR2_BUSY BIT(1) 80 81 /* STM32F4 I2C Control Clock */ 82 #define STM32F4_I2C_CCR_CCR_MASK GENMASK(11, 0) 83 #define STM32F4_I2C_CCR_CCR(n) ((n) & STM32F4_I2C_CCR_CCR_MASK) 84 #define STM32F4_I2C_CCR_FS BIT(15) 85 #define STM32F4_I2C_CCR_DUTY BIT(14) 86 87 /* STM32F4 I2C Trise */ 88 #define STM32F4_I2C_TRISE_VALUE_MASK GENMASK(5, 0) 89 #define STM32F4_I2C_TRISE_VALUE(n) ((n) & STM32F4_I2C_TRISE_VALUE_MASK) 90 91 #define STM32F4_I2C_MIN_STANDARD_FREQ 2U 92 #define STM32F4_I2C_MIN_FAST_FREQ 6U 93 #define STM32F4_I2C_MAX_FREQ 46U 94 #define HZ_TO_MHZ 1000000 95 96 /** 97 * struct stm32f4_i2c_msg - client specific data 98 * @addr: 8-bit target addr, including r/w bit 99 * @count: number of bytes to be transferred 100 * @buf: data buffer 101 * @result: result of the transfer 102 * @stop: last I2C msg to be sent, i.e. STOP to be generated 103 */ 104 struct stm32f4_i2c_msg { 105 u8 addr; 106 u32 count; 107 u8 *buf; 108 int result; 109 bool stop; 110 }; 111 112 /** 113 * struct stm32f4_i2c_dev - private data of the controller 114 * @adap: I2C adapter for this controller 115 * @dev: device for this controller 116 * @base: virtual memory area 117 * @complete: completion of I2C message 118 * @clk: hw i2c clock 119 * @speed: I2C clock frequency of the controller. Standard or Fast are supported 120 * @parent_rate: I2C clock parent rate in MHz 121 * @msg: I2C transfer information 122 */ 123 struct stm32f4_i2c_dev { 124 struct i2c_adapter adap; 125 struct device *dev; 126 void __iomem *base; 127 struct completion complete; 128 struct clk *clk; 129 int speed; 130 int parent_rate; 131 struct stm32f4_i2c_msg msg; 132 }; 133 134 static inline void stm32f4_i2c_set_bits(void __iomem *reg, u32 mask) 135 { 136 writel_relaxed(readl_relaxed(reg) | mask, reg); 137 } 138 139 static inline void stm32f4_i2c_clr_bits(void __iomem *reg, u32 mask) 140 { 141 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 142 } 143 144 static void stm32f4_i2c_disable_irq(struct stm32f4_i2c_dev *i2c_dev) 145 { 146 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; 147 148 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_IRQ_MASK); 149 } 150 151 static int stm32f4_i2c_set_periph_clk_freq(struct stm32f4_i2c_dev *i2c_dev) 152 { 153 u32 freq; 154 u32 cr2 = 0; 155 156 i2c_dev->parent_rate = clk_get_rate(i2c_dev->clk); 157 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ); 158 159 if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) { 160 /* 161 * To reach 100 kHz, the parent clk frequency should be between 162 * a minimum value of 2 MHz and a maximum value of 46 MHz due 163 * to hardware limitation 164 */ 165 if (freq < STM32F4_I2C_MIN_STANDARD_FREQ || 166 freq > STM32F4_I2C_MAX_FREQ) 167 return dev_err_probe(i2c_dev->dev, -EINVAL, 168 "bad parent clk freq for standard mode\n"); 169 } else { 170 /* 171 * To be as close as possible to 400 kHz, the parent clk 172 * frequency should be between a minimum value of 6 MHz and a 173 * maximum value of 46 MHz due to hardware limitation 174 */ 175 if (freq < STM32F4_I2C_MIN_FAST_FREQ || 176 freq > STM32F4_I2C_MAX_FREQ) 177 return dev_err_probe(i2c_dev->dev, -EINVAL, 178 "bad parent clk freq for fast mode\n"); 179 } 180 181 cr2 |= STM32F4_I2C_CR2_FREQ(freq); 182 writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2); 183 184 return 0; 185 } 186 187 static void stm32f4_i2c_set_rise_time(struct stm32f4_i2c_dev *i2c_dev) 188 { 189 u32 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ); 190 u32 trise; 191 192 /* 193 * These bits must be programmed with the maximum SCL rise time given in 194 * the I2C bus specification, incremented by 1. 195 * 196 * In standard mode, the maximum allowed SCL rise time is 1000 ns. 197 * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 198 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be 199 * programmed with 0x9. (1000 ns / 125 ns + 1) 200 * So, for I2C standard mode TRISE = FREQ[5:0] + 1 201 * 202 * In fast mode, the maximum allowed SCL rise time is 300 ns. 203 * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 204 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be 205 * programmed with 0x3. (300 ns / 125 ns + 1) 206 * So, for I2C fast mode TRISE = FREQ[5:0] * 300 / 1000 + 1 207 * 208 * Function stm32f4_i2c_set_periph_clk_freq made sure that parent rate 209 * is not higher than 46 MHz . As a result trise is at most 4 bits wide 210 * and so fits into the TRISE bits [5:0]. 211 */ 212 if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) 213 trise = freq + 1; 214 else 215 trise = freq * 3 / 10 + 1; 216 217 writel_relaxed(STM32F4_I2C_TRISE_VALUE(trise), 218 i2c_dev->base + STM32F4_I2C_TRISE); 219 } 220 221 static void stm32f4_i2c_set_speed_mode(struct stm32f4_i2c_dev *i2c_dev) 222 { 223 u32 val; 224 u32 ccr = 0; 225 226 if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) { 227 /* 228 * In standard mode: 229 * t_scl_high = t_scl_low = CCR * I2C parent clk period 230 * So to reach 100 kHz, we have: 231 * CCR = I2C parent rate / (100 kHz * 2) 232 * 233 * For example with parent rate = 2 MHz: 234 * CCR = 2000000 / (100000 * 2) = 10 235 * t_scl_high = t_scl_low = 10 * (1 / 2000000) = 5000 ns 236 * t_scl_high + t_scl_low = 10000 ns so 100 kHz is reached 237 * 238 * Function stm32f4_i2c_set_periph_clk_freq made sure that 239 * parent rate is not higher than 46 MHz . As a result val 240 * is at most 8 bits wide and so fits into the CCR bits [11:0]. 241 */ 242 val = i2c_dev->parent_rate / (I2C_MAX_STANDARD_MODE_FREQ * 2); 243 } else { 244 /* 245 * In fast mode, we compute CCR with duty = 0 as with low 246 * frequencies we are not able to reach 400 kHz. 247 * In that case: 248 * t_scl_high = CCR * I2C parent clk period 249 * t_scl_low = 2 * CCR * I2C parent clk period 250 * So, CCR = I2C parent rate / (400 kHz * 3) 251 * 252 * For example with parent rate = 6 MHz: 253 * CCR = 6000000 / (400000 * 3) = 5 254 * t_scl_high = 5 * (1 / 6000000) = 833 ns > 600 ns 255 * t_scl_low = 2 * 5 * (1 / 6000000) = 1667 ns > 1300 ns 256 * t_scl_high + t_scl_low = 2500 ns so 400 kHz is reached 257 * 258 * Function stm32f4_i2c_set_periph_clk_freq made sure that 259 * parent rate is not higher than 46 MHz . As a result val 260 * is at most 6 bits wide and so fits into the CCR bits [11:0]. 261 */ 262 val = DIV_ROUND_UP(i2c_dev->parent_rate, I2C_MAX_FAST_MODE_FREQ * 3); 263 264 /* Select Fast mode */ 265 ccr |= STM32F4_I2C_CCR_FS; 266 } 267 268 ccr |= STM32F4_I2C_CCR_CCR(val); 269 writel_relaxed(ccr, i2c_dev->base + STM32F4_I2C_CCR); 270 } 271 272 /** 273 * stm32f4_i2c_hw_config() - Prepare I2C block 274 * @i2c_dev: Controller's private data 275 */ 276 static int stm32f4_i2c_hw_config(struct stm32f4_i2c_dev *i2c_dev) 277 { 278 int ret; 279 280 ret = stm32f4_i2c_set_periph_clk_freq(i2c_dev); 281 if (ret) 282 return ret; 283 284 stm32f4_i2c_set_rise_time(i2c_dev); 285 286 stm32f4_i2c_set_speed_mode(i2c_dev); 287 288 /* Enable I2C */ 289 writel_relaxed(STM32F4_I2C_CR1_PE, i2c_dev->base + STM32F4_I2C_CR1); 290 291 return 0; 292 } 293 294 static int stm32f4_i2c_wait_free_bus(struct stm32f4_i2c_dev *i2c_dev) 295 { 296 u32 status; 297 int ret; 298 299 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F4_I2C_SR2, 300 status, 301 !(status & STM32F4_I2C_SR2_BUSY), 302 10, 1000); 303 if (ret) { 304 dev_dbg(i2c_dev->dev, "bus not free\n"); 305 ret = -EBUSY; 306 } 307 308 return ret; 309 } 310 311 /** 312 * stm32f4_i2c_write_byte() - Write a byte in the data register 313 * @i2c_dev: Controller's private data 314 * @byte: Data to write in the register 315 */ 316 static void stm32f4_i2c_write_byte(struct stm32f4_i2c_dev *i2c_dev, u8 byte) 317 { 318 writel_relaxed(byte, i2c_dev->base + STM32F4_I2C_DR); 319 } 320 321 /** 322 * stm32f4_i2c_write_msg() - Fill the data register in write mode 323 * @i2c_dev: Controller's private data 324 * 325 * This function fills the data register with I2C transfer buffer 326 */ 327 static void stm32f4_i2c_write_msg(struct stm32f4_i2c_dev *i2c_dev) 328 { 329 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 330 331 stm32f4_i2c_write_byte(i2c_dev, *msg->buf++); 332 msg->count--; 333 } 334 335 static void stm32f4_i2c_read_msg(struct stm32f4_i2c_dev *i2c_dev) 336 { 337 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 338 u32 rbuf; 339 340 rbuf = readl_relaxed(i2c_dev->base + STM32F4_I2C_DR); 341 *msg->buf++ = rbuf; 342 msg->count--; 343 } 344 345 static void stm32f4_i2c_terminate_xfer(struct stm32f4_i2c_dev *i2c_dev) 346 { 347 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 348 void __iomem *reg; 349 350 stm32f4_i2c_disable_irq(i2c_dev); 351 352 reg = i2c_dev->base + STM32F4_I2C_CR1; 353 if (msg->stop) 354 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); 355 else 356 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); 357 358 complete(&i2c_dev->complete); 359 } 360 361 /** 362 * stm32f4_i2c_handle_write() - Handle FIFO empty interrupt in case of write 363 * @i2c_dev: Controller's private data 364 */ 365 static void stm32f4_i2c_handle_write(struct stm32f4_i2c_dev *i2c_dev) 366 { 367 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 368 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; 369 370 if (msg->count) { 371 stm32f4_i2c_write_msg(i2c_dev); 372 if (!msg->count) { 373 /* 374 * Disable buffer interrupts for RX not empty and TX 375 * empty events 376 */ 377 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN); 378 } 379 } else { 380 stm32f4_i2c_terminate_xfer(i2c_dev); 381 } 382 } 383 384 /** 385 * stm32f4_i2c_handle_read() - Handle FIFO empty interrupt in case of read 386 * @i2c_dev: Controller's private data 387 * 388 * This function is called when a new data is received in data register 389 */ 390 static void stm32f4_i2c_handle_read(struct stm32f4_i2c_dev *i2c_dev) 391 { 392 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 393 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; 394 395 switch (msg->count) { 396 case 1: 397 stm32f4_i2c_disable_irq(i2c_dev); 398 stm32f4_i2c_read_msg(i2c_dev); 399 complete(&i2c_dev->complete); 400 break; 401 /* 402 * For 2-byte reception, 3-byte reception and for Data N-2, N-1 and N 403 * for N-byte reception with N > 3, we do not have to read the data 404 * register when RX not empty event occurs as we have to wait for byte 405 * transferred finished event before reading data. 406 * So, here we just disable buffer interrupt in order to avoid another 407 * system preemption due to RX not empty event. 408 */ 409 case 2: 410 case 3: 411 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN); 412 break; 413 /* 414 * For N byte reception with N > 3 we directly read data register 415 * until N-2 data. 416 */ 417 default: 418 stm32f4_i2c_read_msg(i2c_dev); 419 } 420 } 421 422 /** 423 * stm32f4_i2c_handle_rx_done() - Handle byte transfer finished interrupt 424 * in case of read 425 * @i2c_dev: Controller's private data 426 * 427 * This function is called when a new data is received in the shift register 428 * but data register has not been read yet. 429 */ 430 static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev) 431 { 432 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 433 void __iomem *reg; 434 u32 mask; 435 int i; 436 437 switch (msg->count) { 438 case 2: 439 /* 440 * In order to correctly send the Stop or Repeated Start 441 * condition on the I2C bus, the STOP/START bit has to be set 442 * before reading the last two bytes (data N-1 and N). 443 * After that, we could read the last two bytes, disable 444 * remaining interrupts and notify the end of xfer to the 445 * client 446 */ 447 reg = i2c_dev->base + STM32F4_I2C_CR1; 448 if (msg->stop) 449 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); 450 else 451 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); 452 453 for (i = 2; i > 0; i--) 454 stm32f4_i2c_read_msg(i2c_dev); 455 456 reg = i2c_dev->base + STM32F4_I2C_CR2; 457 mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN; 458 stm32f4_i2c_clr_bits(reg, mask); 459 460 complete(&i2c_dev->complete); 461 break; 462 case 3: 463 /* 464 * In order to correctly generate the NACK pulse after the last 465 * received data byte, we have to enable NACK before reading N-2 466 * data 467 */ 468 reg = i2c_dev->base + STM32F4_I2C_CR1; 469 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR1_ACK); 470 stm32f4_i2c_read_msg(i2c_dev); 471 break; 472 default: 473 stm32f4_i2c_read_msg(i2c_dev); 474 } 475 } 476 477 /** 478 * stm32f4_i2c_handle_rx_addr() - Handle address matched interrupt in case of 479 * controller receiver 480 * @i2c_dev: Controller's private data 481 */ 482 static void stm32f4_i2c_handle_rx_addr(struct stm32f4_i2c_dev *i2c_dev) 483 { 484 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 485 u32 cr1; 486 487 switch (msg->count) { 488 case 0: 489 stm32f4_i2c_terminate_xfer(i2c_dev); 490 491 /* Clear ADDR flag */ 492 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); 493 break; 494 case 1: 495 /* 496 * Single byte reception: 497 * Enable NACK and reset POS (Acknowledge position). 498 * Then, clear ADDR flag and set STOP or RepSTART. 499 * In that way, the NACK and STOP or RepStart pulses will be 500 * sent as soon as the byte will be received in shift register 501 */ 502 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); 503 cr1 &= ~(STM32F4_I2C_CR1_ACK | STM32F4_I2C_CR1_POS); 504 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); 505 506 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); 507 508 if (msg->stop) 509 cr1 |= STM32F4_I2C_CR1_STOP; 510 else 511 cr1 |= STM32F4_I2C_CR1_START; 512 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); 513 break; 514 case 2: 515 /* 516 * 2-byte reception: 517 * Enable NACK, set POS (NACK position) and clear ADDR flag. 518 * In that way, NACK will be sent for the next byte which will 519 * be received in the shift register instead of the current 520 * one. 521 */ 522 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); 523 cr1 &= ~STM32F4_I2C_CR1_ACK; 524 cr1 |= STM32F4_I2C_CR1_POS; 525 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); 526 527 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); 528 break; 529 530 default: 531 /* 532 * N-byte reception: 533 * Enable ACK, reset POS (ACK position) and clear ADDR flag. 534 * In that way, ACK will be sent as soon as the current byte 535 * will be received in the shift register 536 */ 537 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); 538 cr1 |= STM32F4_I2C_CR1_ACK; 539 cr1 &= ~STM32F4_I2C_CR1_POS; 540 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); 541 542 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); 543 break; 544 } 545 } 546 547 /** 548 * stm32f4_i2c_isr_event() - Interrupt routine for I2C bus event 549 * @irq: interrupt number 550 * @data: Controller's private data 551 */ 552 static irqreturn_t stm32f4_i2c_isr_event(int irq, void *data) 553 { 554 struct stm32f4_i2c_dev *i2c_dev = data; 555 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 556 u32 possible_status = STM32F4_I2C_SR1_ITEVTEN_MASK; 557 u32 status, ien, event, cr2; 558 559 cr2 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR2); 560 ien = cr2 & STM32F4_I2C_CR2_IRQ_MASK; 561 562 /* Update possible_status if buffer interrupt is enabled */ 563 if (ien & STM32F4_I2C_CR2_ITBUFEN) 564 possible_status |= STM32F4_I2C_SR1_ITBUFEN_MASK; 565 566 status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1); 567 event = status & possible_status; 568 if (!event) { 569 dev_dbg(i2c_dev->dev, 570 "spurious evt irq (status=0x%08x, ien=0x%08x)\n", 571 status, ien); 572 return IRQ_NONE; 573 } 574 575 /* Start condition generated */ 576 if (event & STM32F4_I2C_SR1_SB) 577 stm32f4_i2c_write_byte(i2c_dev, msg->addr); 578 579 /* I2C Address sent */ 580 if (event & STM32F4_I2C_SR1_ADDR) { 581 if (msg->addr & I2C_M_RD) 582 stm32f4_i2c_handle_rx_addr(i2c_dev); 583 else 584 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); 585 586 /* 587 * Enable buffer interrupts for RX not empty and TX empty 588 * events 589 */ 590 cr2 |= STM32F4_I2C_CR2_ITBUFEN; 591 writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2); 592 } 593 594 /* TX empty */ 595 if ((event & STM32F4_I2C_SR1_TXE) && !(msg->addr & I2C_M_RD)) 596 stm32f4_i2c_handle_write(i2c_dev); 597 598 /* RX not empty */ 599 if ((event & STM32F4_I2C_SR1_RXNE) && (msg->addr & I2C_M_RD)) 600 stm32f4_i2c_handle_read(i2c_dev); 601 602 /* 603 * The BTF (Byte Transfer finished) event occurs when: 604 * - in reception : a new byte is received in the shift register 605 * but the previous byte has not been read yet from data register 606 * - in transmission: a new byte should be sent but the data register 607 * has not been written yet 608 */ 609 if (event & STM32F4_I2C_SR1_BTF) { 610 if (msg->addr & I2C_M_RD) 611 stm32f4_i2c_handle_rx_done(i2c_dev); 612 else 613 stm32f4_i2c_handle_write(i2c_dev); 614 } 615 616 return IRQ_HANDLED; 617 } 618 619 /** 620 * stm32f4_i2c_isr_error() - Interrupt routine for I2C bus error 621 * @irq: interrupt number 622 * @data: Controller's private data 623 */ 624 static irqreturn_t stm32f4_i2c_isr_error(int irq, void *data) 625 { 626 struct stm32f4_i2c_dev *i2c_dev = data; 627 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; 628 void __iomem *reg; 629 u32 status; 630 631 status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1); 632 633 /* Arbitration lost */ 634 if (status & STM32F4_I2C_SR1_ARLO) { 635 status &= ~STM32F4_I2C_SR1_ARLO; 636 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); 637 msg->result = -EAGAIN; 638 } 639 640 /* 641 * Acknowledge failure: 642 * In controller transmitter mode a Stop must be generated by software 643 */ 644 if (status & STM32F4_I2C_SR1_AF) { 645 if (!(msg->addr & I2C_M_RD)) { 646 reg = i2c_dev->base + STM32F4_I2C_CR1; 647 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); 648 } 649 status &= ~STM32F4_I2C_SR1_AF; 650 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); 651 msg->result = -EIO; 652 } 653 654 /* Bus error */ 655 if (status & STM32F4_I2C_SR1_BERR) { 656 status &= ~STM32F4_I2C_SR1_BERR; 657 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); 658 msg->result = -EIO; 659 } 660 661 stm32f4_i2c_disable_irq(i2c_dev); 662 complete(&i2c_dev->complete); 663 664 return IRQ_HANDLED; 665 } 666 667 /** 668 * stm32f4_i2c_xfer_msg() - Transfer a single I2C message 669 * @i2c_dev: Controller's private data 670 * @msg: I2C message to transfer 671 * @is_first: first message of the sequence 672 * @is_last: last message of the sequence 673 */ 674 static int stm32f4_i2c_xfer_msg(struct stm32f4_i2c_dev *i2c_dev, 675 struct i2c_msg *msg, bool is_first, 676 bool is_last) 677 { 678 struct stm32f4_i2c_msg *f4_msg = &i2c_dev->msg; 679 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR1; 680 unsigned long time_left; 681 u32 mask; 682 int ret; 683 684 f4_msg->addr = i2c_8bit_addr_from_msg(msg); 685 f4_msg->buf = msg->buf; 686 f4_msg->count = msg->len; 687 f4_msg->result = 0; 688 f4_msg->stop = is_last; 689 690 reinit_completion(&i2c_dev->complete); 691 692 /* Enable events and errors interrupts */ 693 mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN; 694 stm32f4_i2c_set_bits(i2c_dev->base + STM32F4_I2C_CR2, mask); 695 696 if (is_first) { 697 ret = stm32f4_i2c_wait_free_bus(i2c_dev); 698 if (ret) 699 return ret; 700 701 /* START generation */ 702 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); 703 } 704 705 time_left = wait_for_completion_timeout(&i2c_dev->complete, 706 i2c_dev->adap.timeout); 707 ret = f4_msg->result; 708 709 if (!time_left) 710 ret = -ETIMEDOUT; 711 712 return ret; 713 } 714 715 /** 716 * stm32f4_i2c_xfer() - Transfer combined I2C message 717 * @i2c_adap: Adapter pointer to the controller 718 * @msgs: Pointer to data to be written. 719 * @num: Number of messages to be executed 720 */ 721 static int stm32f4_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], 722 int num) 723 { 724 struct stm32f4_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 725 int ret, i; 726 727 ret = clk_enable(i2c_dev->clk); 728 if (ret) { 729 dev_err(i2c_dev->dev, "Failed to enable clock\n"); 730 return ret; 731 } 732 733 for (i = 0; i < num && !ret; i++) 734 ret = stm32f4_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, 735 i == num - 1); 736 737 clk_disable(i2c_dev->clk); 738 739 return (ret < 0) ? ret : num; 740 } 741 742 static u32 stm32f4_i2c_func(struct i2c_adapter *adap) 743 { 744 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 745 } 746 747 static const struct i2c_algorithm stm32f4_i2c_algo = { 748 .xfer = stm32f4_i2c_xfer, 749 .functionality = stm32f4_i2c_func, 750 }; 751 752 static int stm32f4_i2c_probe(struct platform_device *pdev) 753 { 754 struct device_node *np = pdev->dev.of_node; 755 struct stm32f4_i2c_dev *i2c_dev; 756 struct resource *res; 757 u32 irq_event, irq_error, clk_rate; 758 struct i2c_adapter *adap; 759 struct reset_control *rst; 760 int ret; 761 762 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 763 if (!i2c_dev) 764 return -ENOMEM; 765 766 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 767 if (IS_ERR(i2c_dev->base)) 768 return PTR_ERR(i2c_dev->base); 769 770 irq_event = irq_of_parse_and_map(np, 0); 771 if (!irq_event) 772 return dev_err_probe(&pdev->dev, -EINVAL, 773 "IRQ event missing or invalid\n"); 774 775 irq_error = irq_of_parse_and_map(np, 1); 776 if (!irq_error) 777 return dev_err_probe(&pdev->dev, -EINVAL, 778 "IRQ error missing or invalid\n"); 779 780 i2c_dev->clk = devm_clk_get_enabled(&pdev->dev, NULL); 781 if (IS_ERR(i2c_dev->clk)) 782 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk), 783 "Failed to enable clock\n"); 784 785 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 786 if (IS_ERR(rst)) 787 return dev_err_probe(&pdev->dev, PTR_ERR(rst), 788 "Error: Missing reset ctrl\n"); 789 790 reset_control_assert(rst); 791 udelay(2); 792 reset_control_deassert(rst); 793 794 i2c_dev->speed = STM32_I2C_SPEED_STANDARD; 795 ret = of_property_read_u32(np, "clock-frequency", &clk_rate); 796 if (!ret && clk_rate >= I2C_MAX_FAST_MODE_FREQ) 797 i2c_dev->speed = STM32_I2C_SPEED_FAST; 798 799 i2c_dev->dev = &pdev->dev; 800 801 ret = devm_request_irq(&pdev->dev, irq_event, stm32f4_i2c_isr_event, 0, 802 pdev->name, i2c_dev); 803 if (ret) 804 return ret; 805 806 ret = devm_request_irq(&pdev->dev, irq_error, stm32f4_i2c_isr_error, 0, 807 pdev->name, i2c_dev); 808 if (ret) 809 return ret; 810 811 ret = stm32f4_i2c_hw_config(i2c_dev); 812 if (ret) 813 return ret; 814 815 adap = &i2c_dev->adap; 816 i2c_set_adapdata(adap, i2c_dev); 817 snprintf(adap->name, sizeof(adap->name), "STM32 I2C(%pa)", &res->start); 818 adap->owner = THIS_MODULE; 819 adap->timeout = 2 * HZ; 820 adap->retries = 0; 821 adap->algo = &stm32f4_i2c_algo; 822 adap->dev.parent = &pdev->dev; 823 adap->dev.of_node = pdev->dev.of_node; 824 825 init_completion(&i2c_dev->complete); 826 827 ret = i2c_add_adapter(adap); 828 if (ret) 829 return ret; 830 831 platform_set_drvdata(pdev, i2c_dev); 832 833 clk_disable(i2c_dev->clk); 834 835 dev_info(i2c_dev->dev, "STM32F4 I2C driver registered\n"); 836 837 return 0; 838 } 839 840 static void stm32f4_i2c_remove(struct platform_device *pdev) 841 { 842 struct stm32f4_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 843 844 i2c_del_adapter(&i2c_dev->adap); 845 } 846 847 static const struct of_device_id stm32f4_i2c_match[] = { 848 { .compatible = "st,stm32f4-i2c", }, 849 {}, 850 }; 851 MODULE_DEVICE_TABLE(of, stm32f4_i2c_match); 852 853 static struct platform_driver stm32f4_i2c_driver = { 854 .driver = { 855 .name = "stm32f4-i2c", 856 .of_match_table = stm32f4_i2c_match, 857 }, 858 .probe = stm32f4_i2c_probe, 859 .remove = stm32f4_i2c_remove, 860 }; 861 862 module_platform_driver(stm32f4_i2c_driver); 863 864 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); 865 MODULE_DESCRIPTION("STMicroelectronics STM32F4 I2C driver"); 866 MODULE_LICENSE("GPL v2"); 867