1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 STMicroelectronics 4 * 5 * I2C controller driver, used in STMicroelectronics devices. 6 * 7 * Author: Maxime Coquelin <maxime.coquelin@st.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/i2c.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/minmax.h> 17 #include <linux/module.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of.h> 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/platform_device.h> 23 24 /* SSC registers */ 25 #define SSC_BRG 0x000 26 #define SSC_TBUF 0x004 27 #define SSC_RBUF 0x008 28 #define SSC_CTL 0x00C 29 #define SSC_IEN 0x010 30 #define SSC_STA 0x014 31 #define SSC_I2C 0x018 32 #define SSC_SLAD 0x01C 33 #define SSC_REP_START_HOLD 0x020 34 #define SSC_START_HOLD 0x024 35 #define SSC_REP_START_SETUP 0x028 36 #define SSC_DATA_SETUP 0x02C 37 #define SSC_STOP_SETUP 0x030 38 #define SSC_BUS_FREE 0x034 39 #define SSC_TX_FSTAT 0x038 40 #define SSC_RX_FSTAT 0x03C 41 #define SSC_PRE_SCALER_BRG 0x040 42 #define SSC_CLR 0x080 43 #define SSC_NOISE_SUPP_WIDTH 0x100 44 #define SSC_PRSCALER 0x104 45 #define SSC_NOISE_SUPP_WIDTH_DATAOUT 0x108 46 #define SSC_PRSCALER_DATAOUT 0x10c 47 48 /* SSC Control */ 49 #define SSC_CTL_DATA_WIDTH_9 0x8 50 #define SSC_CTL_DATA_WIDTH_MSK 0xf 51 #define SSC_CTL_BM 0xf 52 #define SSC_CTL_HB BIT(4) 53 #define SSC_CTL_PH BIT(5) 54 #define SSC_CTL_PO BIT(6) 55 #define SSC_CTL_SR BIT(7) 56 #define SSC_CTL_MS BIT(8) 57 #define SSC_CTL_EN BIT(9) 58 #define SSC_CTL_LPB BIT(10) 59 #define SSC_CTL_EN_TX_FIFO BIT(11) 60 #define SSC_CTL_EN_RX_FIFO BIT(12) 61 #define SSC_CTL_EN_CLST_RX BIT(13) 62 63 /* SSC Interrupt Enable */ 64 #define SSC_IEN_RIEN BIT(0) 65 #define SSC_IEN_TIEN BIT(1) 66 #define SSC_IEN_TEEN BIT(2) 67 #define SSC_IEN_REEN BIT(3) 68 #define SSC_IEN_PEEN BIT(4) 69 #define SSC_IEN_AASEN BIT(6) 70 #define SSC_IEN_STOPEN BIT(7) 71 #define SSC_IEN_ARBLEN BIT(8) 72 #define SSC_IEN_NACKEN BIT(10) 73 #define SSC_IEN_REPSTRTEN BIT(11) 74 #define SSC_IEN_TX_FIFO_HALF BIT(12) 75 #define SSC_IEN_RX_FIFO_HALF_FULL BIT(14) 76 77 /* SSC Status */ 78 #define SSC_STA_RIR BIT(0) 79 #define SSC_STA_TIR BIT(1) 80 #define SSC_STA_TE BIT(2) 81 #define SSC_STA_RE BIT(3) 82 #define SSC_STA_PE BIT(4) 83 #define SSC_STA_CLST BIT(5) 84 #define SSC_STA_AAS BIT(6) 85 #define SSC_STA_STOP BIT(7) 86 #define SSC_STA_ARBL BIT(8) 87 #define SSC_STA_BUSY BIT(9) 88 #define SSC_STA_NACK BIT(10) 89 #define SSC_STA_REPSTRT BIT(11) 90 #define SSC_STA_TX_FIFO_HALF BIT(12) 91 #define SSC_STA_TX_FIFO_FULL BIT(13) 92 #define SSC_STA_RX_FIFO_HALF BIT(14) 93 94 /* SSC I2C Control */ 95 #define SSC_I2C_I2CM BIT(0) 96 #define SSC_I2C_STRTG BIT(1) 97 #define SSC_I2C_STOPG BIT(2) 98 #define SSC_I2C_ACKG BIT(3) 99 #define SSC_I2C_AD10 BIT(4) 100 #define SSC_I2C_TXENB BIT(5) 101 #define SSC_I2C_REPSTRTG BIT(11) 102 #define SSC_I2C_SLAVE_DISABLE BIT(12) 103 104 /* SSC Tx FIFO Status */ 105 #define SSC_TX_FSTAT_STATUS 0x07 106 107 /* SSC Rx FIFO Status */ 108 #define SSC_RX_FSTAT_STATUS 0x07 109 110 /* SSC Clear bit operation */ 111 #define SSC_CLR_SSCAAS BIT(6) 112 #define SSC_CLR_SSCSTOP BIT(7) 113 #define SSC_CLR_SSCARBL BIT(8) 114 #define SSC_CLR_NACK BIT(10) 115 #define SSC_CLR_REPSTRT BIT(11) 116 117 /* SSC Clock Prescaler */ 118 #define SSC_PRSC_VALUE 0x0f 119 120 121 #define SSC_TXFIFO_SIZE 0x8 122 #define SSC_RXFIFO_SIZE 0x8 123 124 enum st_i2c_mode { 125 I2C_MODE_STANDARD, 126 I2C_MODE_FAST, 127 I2C_MODE_END, 128 }; 129 130 /** 131 * struct st_i2c_timings - per-Mode tuning parameters 132 * @rate: I2C bus rate 133 * @rep_start_hold: I2C repeated start hold time requirement 134 * @rep_start_setup: I2C repeated start set up time requirement 135 * @start_hold: I2C start hold time requirement 136 * @data_setup_time: I2C data set up time requirement 137 * @stop_setup_time: I2C stop set up time requirement 138 * @bus_free_time: I2C bus free time requirement 139 * @sda_pulse_min_limit: I2C SDA pulse mini width limit 140 */ 141 struct st_i2c_timings { 142 u32 rate; 143 u32 rep_start_hold; 144 u32 rep_start_setup; 145 u32 start_hold; 146 u32 data_setup_time; 147 u32 stop_setup_time; 148 u32 bus_free_time; 149 u32 sda_pulse_min_limit; 150 }; 151 152 /** 153 * struct st_i2c_client - client specific data 154 * @addr: 8-bit target addr, including r/w bit 155 * @count: number of bytes to be transfered 156 * @xfered: number of bytes already transferred 157 * @buf: data buffer 158 * @result: result of the transfer 159 * @stop: last I2C msg to be sent, i.e. STOP to be generated 160 */ 161 struct st_i2c_client { 162 u8 addr; 163 u32 count; 164 u32 xfered; 165 u8 *buf; 166 int result; 167 bool stop; 168 }; 169 170 /** 171 * struct st_i2c_dev - private data of the controller 172 * @adap: I2C adapter for this controller 173 * @dev: device for this controller 174 * @base: virtual memory area 175 * @complete: completion of I2C message 176 * @irq: interrupt line for th controller 177 * @clk: hw ssc block clock 178 * @mode: I2C mode of the controller. Standard or Fast only supported 179 * @scl_min_width_us: SCL line minimum pulse width in us 180 * @sda_min_width_us: SDA line minimum pulse width in us 181 * @client: I2C transfert information 182 * @busy: I2C transfer on-going 183 */ 184 struct st_i2c_dev { 185 struct i2c_adapter adap; 186 struct device *dev; 187 void __iomem *base; 188 struct completion complete; 189 int irq; 190 struct clk *clk; 191 int mode; 192 u32 scl_min_width_us; 193 u32 sda_min_width_us; 194 struct st_i2c_client client; 195 bool busy; 196 }; 197 198 static inline void st_i2c_set_bits(void __iomem *reg, u32 mask) 199 { 200 writel_relaxed(readl_relaxed(reg) | mask, reg); 201 } 202 203 static inline void st_i2c_clr_bits(void __iomem *reg, u32 mask) 204 { 205 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 206 } 207 208 /* 209 * From I2C Specifications v0.5. 210 * 211 * All the values below have +10% margin added to be 212 * compatible with some out-of-spec devices, 213 * like HDMI link of the Toshiba 19AV600 TV. 214 */ 215 static struct st_i2c_timings i2c_timings[] = { 216 [I2C_MODE_STANDARD] = { 217 .rate = I2C_MAX_STANDARD_MODE_FREQ, 218 .rep_start_hold = 4400, 219 .rep_start_setup = 5170, 220 .start_hold = 4400, 221 .data_setup_time = 275, 222 .stop_setup_time = 4400, 223 .bus_free_time = 5170, 224 }, 225 [I2C_MODE_FAST] = { 226 .rate = I2C_MAX_FAST_MODE_FREQ, 227 .rep_start_hold = 660, 228 .rep_start_setup = 660, 229 .start_hold = 660, 230 .data_setup_time = 110, 231 .stop_setup_time = 660, 232 .bus_free_time = 1430, 233 }, 234 }; 235 236 static void st_i2c_flush_rx_fifo(struct st_i2c_dev *i2c_dev) 237 { 238 int count, i; 239 240 /* 241 * Counter only counts up to 7 but fifo size is 8... 242 * When fifo is full, counter is 0 and RIR bit of status register is 243 * set 244 */ 245 if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR) 246 count = SSC_RXFIFO_SIZE; 247 else 248 count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) & 249 SSC_RX_FSTAT_STATUS; 250 251 for (i = 0; i < count; i++) 252 readl_relaxed(i2c_dev->base + SSC_RBUF); 253 } 254 255 static void st_i2c_soft_reset(struct st_i2c_dev *i2c_dev) 256 { 257 /* 258 * FIFO needs to be emptied before reseting the IP, 259 * else the controller raises a BUSY error. 260 */ 261 st_i2c_flush_rx_fifo(i2c_dev); 262 263 st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); 264 st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); 265 } 266 267 /** 268 * st_i2c_hw_config() - Prepare SSC block, calculate and apply tuning timings 269 * @i2c_dev: Controller's private data 270 */ 271 static void st_i2c_hw_config(struct st_i2c_dev *i2c_dev) 272 { 273 unsigned long rate; 274 u32 val, ns_per_clk; 275 struct st_i2c_timings *t = &i2c_timings[i2c_dev->mode]; 276 277 st_i2c_soft_reset(i2c_dev); 278 279 val = SSC_CLR_REPSTRT | SSC_CLR_NACK | SSC_CLR_SSCARBL | 280 SSC_CLR_SSCAAS | SSC_CLR_SSCSTOP; 281 writel_relaxed(val, i2c_dev->base + SSC_CLR); 282 283 /* SSC Control register setup */ 284 val = SSC_CTL_PO | SSC_CTL_PH | SSC_CTL_HB | SSC_CTL_DATA_WIDTH_9; 285 writel_relaxed(val, i2c_dev->base + SSC_CTL); 286 287 rate = clk_get_rate(i2c_dev->clk); 288 ns_per_clk = 1000000000 / rate; 289 290 /* Baudrate */ 291 val = rate / (2 * t->rate); 292 writel_relaxed(val, i2c_dev->base + SSC_BRG); 293 294 /* Pre-scaler baudrate */ 295 writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG); 296 297 /* Enable I2C mode */ 298 writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C); 299 300 /* Repeated start hold time */ 301 val = t->rep_start_hold / ns_per_clk; 302 writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD); 303 304 /* Repeated start set up time */ 305 val = t->rep_start_setup / ns_per_clk; 306 writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP); 307 308 /* Start hold time */ 309 val = t->start_hold / ns_per_clk; 310 writel_relaxed(val, i2c_dev->base + SSC_START_HOLD); 311 312 /* Data set up time */ 313 val = t->data_setup_time / ns_per_clk; 314 writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP); 315 316 /* Stop set up time */ 317 val = t->stop_setup_time / ns_per_clk; 318 writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP); 319 320 /* Bus free time */ 321 val = t->bus_free_time / ns_per_clk; 322 writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE); 323 324 /* Prescalers set up */ 325 val = rate / 10000000; 326 writel_relaxed(val, i2c_dev->base + SSC_PRSCALER); 327 writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT); 328 329 /* Noise suppression witdh */ 330 val = i2c_dev->scl_min_width_us * rate / 100000000; 331 writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH); 332 333 /* Noise suppression max output data delay width */ 334 val = i2c_dev->sda_min_width_us * rate / 100000000; 335 writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT); 336 } 337 338 static int st_i2c_recover_bus(struct i2c_adapter *i2c_adap) 339 { 340 struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 341 u32 ctl; 342 343 dev_dbg(i2c_dev->dev, "Trying to recover bus\n"); 344 345 /* 346 * SSP IP is dual role SPI/I2C to generate 9 clock pulses 347 * we switch to SPI node, 9 bit words and write a 0. This 348 * has been validate with a oscilloscope and is easier 349 * than switching to GPIO mode. 350 */ 351 352 /* Disable interrupts */ 353 writel_relaxed(0, i2c_dev->base + SSC_IEN); 354 355 st_i2c_hw_config(i2c_dev); 356 357 ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO; 358 st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl); 359 360 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM); 361 usleep_range(8000, 10000); 362 363 writel_relaxed(0, i2c_dev->base + SSC_TBUF); 364 usleep_range(2000, 4000); 365 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM); 366 367 return 0; 368 } 369 370 static int st_i2c_wait_free_bus(struct st_i2c_dev *i2c_dev) 371 { 372 u32 sta; 373 int i, ret; 374 375 for (i = 0; i < 10; i++) { 376 sta = readl_relaxed(i2c_dev->base + SSC_STA); 377 if (!(sta & SSC_STA_BUSY)) 378 return 0; 379 380 usleep_range(2000, 4000); 381 } 382 383 dev_err(i2c_dev->dev, "bus not free (status = 0x%08x)\n", sta); 384 385 ret = i2c_recover_bus(&i2c_dev->adap); 386 if (ret) { 387 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret); 388 return ret; 389 } 390 391 return -EBUSY; 392 } 393 394 /** 395 * st_i2c_write_tx_fifo() - Write a byte in the Tx FIFO 396 * @i2c_dev: Controller's private data 397 * @byte: Data to write in the Tx FIFO 398 */ 399 static inline void st_i2c_write_tx_fifo(struct st_i2c_dev *i2c_dev, u8 byte) 400 { 401 u16 tbuf = byte << 1; 402 403 writel_relaxed(tbuf | 1, i2c_dev->base + SSC_TBUF); 404 } 405 406 /** 407 * st_i2c_wr_fill_tx_fifo() - Fill the Tx FIFO in write mode 408 * @i2c_dev: Controller's private data 409 * 410 * This functions fills the Tx FIFO with I2C transfert buffer when 411 * in write mode. 412 */ 413 static void st_i2c_wr_fill_tx_fifo(struct st_i2c_dev *i2c_dev) 414 { 415 struct st_i2c_client *c = &i2c_dev->client; 416 u32 tx_fstat, sta; 417 int i; 418 419 sta = readl_relaxed(i2c_dev->base + SSC_STA); 420 if (sta & SSC_STA_TX_FIFO_FULL) 421 return; 422 423 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); 424 tx_fstat &= SSC_TX_FSTAT_STATUS; 425 426 for (i = min(c->count, SSC_TXFIFO_SIZE - tx_fstat); 427 i > 0; i--, c->count--, c->buf++) 428 st_i2c_write_tx_fifo(i2c_dev, *c->buf); 429 } 430 431 /** 432 * st_i2c_rd_fill_tx_fifo() - Fill the Tx FIFO in read mode 433 * @i2c_dev: Controller's private data 434 * @max: Maximum amount of data to fill into the Tx FIFO 435 * 436 * This functions fills the Tx FIFO with fixed pattern when 437 * in read mode to trigger clock. 438 */ 439 static void st_i2c_rd_fill_tx_fifo(struct st_i2c_dev *i2c_dev, u32 max) 440 { 441 struct st_i2c_client *c = &i2c_dev->client; 442 u32 tx_fstat, sta; 443 int i; 444 445 sta = readl_relaxed(i2c_dev->base + SSC_STA); 446 if (sta & SSC_STA_TX_FIFO_FULL) 447 return; 448 449 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); 450 tx_fstat &= SSC_TX_FSTAT_STATUS; 451 452 for (i = min(max, SSC_TXFIFO_SIZE - tx_fstat); 453 i > 0; i--, c->xfered++) 454 st_i2c_write_tx_fifo(i2c_dev, 0xff); 455 } 456 457 static void st_i2c_read_rx_fifo(struct st_i2c_dev *i2c_dev) 458 { 459 struct st_i2c_client *c = &i2c_dev->client; 460 u32 i, sta; 461 u16 rbuf; 462 463 sta = readl_relaxed(i2c_dev->base + SSC_STA); 464 if (sta & SSC_STA_RIR) { 465 i = SSC_RXFIFO_SIZE; 466 } else { 467 i = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT); 468 i &= SSC_RX_FSTAT_STATUS; 469 } 470 471 for (; (i > 0) && (c->count > 0); i--, c->count--) { 472 rbuf = readl_relaxed(i2c_dev->base + SSC_RBUF) >> 1; 473 *c->buf++ = (u8)rbuf & 0xff; 474 } 475 476 if (i) { 477 dev_err(i2c_dev->dev, "Unexpected %d bytes in rx fifo\n", i); 478 st_i2c_flush_rx_fifo(i2c_dev); 479 } 480 } 481 482 /** 483 * st_i2c_terminate_xfer() - Send either STOP or REPSTART condition 484 * @i2c_dev: Controller's private data 485 */ 486 static void st_i2c_terminate_xfer(struct st_i2c_dev *i2c_dev) 487 { 488 struct st_i2c_client *c = &i2c_dev->client; 489 490 st_i2c_clr_bits(i2c_dev->base + SSC_IEN, SSC_IEN_TEEN); 491 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG); 492 493 if (c->stop) { 494 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_STOPEN); 495 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); 496 } else { 497 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_REPSTRTEN); 498 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_REPSTRTG); 499 } 500 } 501 502 /** 503 * st_i2c_handle_write() - Handle FIFO empty interrupt in case of write 504 * @i2c_dev: Controller's private data 505 */ 506 static void st_i2c_handle_write(struct st_i2c_dev *i2c_dev) 507 { 508 struct st_i2c_client *c = &i2c_dev->client; 509 510 st_i2c_flush_rx_fifo(i2c_dev); 511 512 if (!c->count) 513 /* End of xfer, send stop or repstart */ 514 st_i2c_terminate_xfer(i2c_dev); 515 else 516 st_i2c_wr_fill_tx_fifo(i2c_dev); 517 } 518 519 /** 520 * st_i2c_handle_read() - Handle FIFO empty interrupt in case of read 521 * @i2c_dev: Controller's private data 522 */ 523 static void st_i2c_handle_read(struct st_i2c_dev *i2c_dev) 524 { 525 struct st_i2c_client *c = &i2c_dev->client; 526 u32 ien; 527 528 /* Trash the address read back */ 529 if (!c->xfered) { 530 readl_relaxed(i2c_dev->base + SSC_RBUF); 531 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_TXENB); 532 } else { 533 st_i2c_read_rx_fifo(i2c_dev); 534 } 535 536 if (!c->count) { 537 /* End of xfer, send stop or repstart */ 538 st_i2c_terminate_xfer(i2c_dev); 539 } else if (c->count == 1) { 540 /* Penultimate byte to xfer, disable ACK gen. */ 541 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_ACKG); 542 543 /* Last received byte is to be handled by NACK interrupt */ 544 ien = SSC_IEN_NACKEN | SSC_IEN_ARBLEN; 545 writel_relaxed(ien, i2c_dev->base + SSC_IEN); 546 547 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count); 548 } else { 549 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count - 1); 550 } 551 } 552 553 /** 554 * st_i2c_isr_thread() - Interrupt routine 555 * @irq: interrupt number 556 * @data: Controller's private data 557 */ 558 static irqreturn_t st_i2c_isr_thread(int irq, void *data) 559 { 560 struct st_i2c_dev *i2c_dev = data; 561 struct st_i2c_client *c = &i2c_dev->client; 562 u32 sta, ien; 563 int it; 564 565 ien = readl_relaxed(i2c_dev->base + SSC_IEN); 566 sta = readl_relaxed(i2c_dev->base + SSC_STA); 567 568 /* Use __fls() to check error bits first */ 569 it = __fls(sta & ien); 570 if (it < 0) { 571 dev_dbg(i2c_dev->dev, "spurious it (sta=0x%04x, ien=0x%04x)\n", 572 sta, ien); 573 return IRQ_NONE; 574 } 575 576 switch (1 << it) { 577 case SSC_STA_TE: 578 if (c->addr & I2C_M_RD) 579 st_i2c_handle_read(i2c_dev); 580 else 581 st_i2c_handle_write(i2c_dev); 582 break; 583 584 case SSC_STA_STOP: 585 case SSC_STA_REPSTRT: 586 writel_relaxed(0, i2c_dev->base + SSC_IEN); 587 complete(&i2c_dev->complete); 588 break; 589 590 case SSC_STA_NACK: 591 writel_relaxed(SSC_CLR_NACK, i2c_dev->base + SSC_CLR); 592 593 /* Last received byte handled by NACK interrupt */ 594 if ((c->addr & I2C_M_RD) && (c->count == 1) && (c->xfered)) { 595 st_i2c_handle_read(i2c_dev); 596 break; 597 } 598 599 it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN; 600 writel_relaxed(it, i2c_dev->base + SSC_IEN); 601 602 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); 603 c->result = -EIO; 604 break; 605 606 case SSC_STA_ARBL: 607 writel_relaxed(SSC_CLR_SSCARBL, i2c_dev->base + SSC_CLR); 608 609 it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN; 610 writel_relaxed(it, i2c_dev->base + SSC_IEN); 611 612 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); 613 c->result = -EAGAIN; 614 break; 615 616 default: 617 dev_err(i2c_dev->dev, 618 "it %d unhandled (sta=0x%04x)\n", it, sta); 619 } 620 621 /* 622 * Read IEN register to ensure interrupt mask write is effective 623 * before re-enabling interrupt at GIC level, and thus avoid spurious 624 * interrupts. 625 */ 626 readl(i2c_dev->base + SSC_IEN); 627 628 return IRQ_HANDLED; 629 } 630 631 /** 632 * st_i2c_xfer_msg() - Transfer a single I2C message 633 * @i2c_dev: Controller's private data 634 * @msg: I2C message to transfer 635 * @is_first: first message of the sequence 636 * @is_last: last message of the sequence 637 */ 638 static int st_i2c_xfer_msg(struct st_i2c_dev *i2c_dev, struct i2c_msg *msg, 639 bool is_first, bool is_last) 640 { 641 struct st_i2c_client *c = &i2c_dev->client; 642 u32 ctl, i2c, it; 643 unsigned long time_left; 644 int ret; 645 646 c->addr = i2c_8bit_addr_from_msg(msg); 647 c->buf = msg->buf; 648 c->count = msg->len; 649 c->xfered = 0; 650 c->result = 0; 651 c->stop = is_last; 652 653 reinit_completion(&i2c_dev->complete); 654 655 ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO; 656 st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl); 657 658 i2c = SSC_I2C_TXENB; 659 if (c->addr & I2C_M_RD) 660 i2c |= SSC_I2C_ACKG; 661 st_i2c_set_bits(i2c_dev->base + SSC_I2C, i2c); 662 663 /* Write target address */ 664 st_i2c_write_tx_fifo(i2c_dev, c->addr); 665 666 /* Pre-fill Tx fifo with data in case of write */ 667 if (!(c->addr & I2C_M_RD)) 668 st_i2c_wr_fill_tx_fifo(i2c_dev); 669 670 it = SSC_IEN_NACKEN | SSC_IEN_TEEN | SSC_IEN_ARBLEN; 671 writel_relaxed(it, i2c_dev->base + SSC_IEN); 672 673 if (is_first) { 674 ret = st_i2c_wait_free_bus(i2c_dev); 675 if (ret) 676 return ret; 677 678 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG); 679 } 680 681 time_left = wait_for_completion_timeout(&i2c_dev->complete, 682 i2c_dev->adap.timeout); 683 ret = c->result; 684 685 if (!time_left) 686 ret = -ETIMEDOUT; 687 688 i2c = SSC_I2C_STOPG | SSC_I2C_REPSTRTG; 689 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, i2c); 690 691 writel_relaxed(SSC_CLR_SSCSTOP | SSC_CLR_REPSTRT, 692 i2c_dev->base + SSC_CLR); 693 694 return ret; 695 } 696 697 /** 698 * st_i2c_xfer() - Transfer a single I2C message 699 * @i2c_adap: Adapter pointer to the controller 700 * @msgs: Pointer to data to be written. 701 * @num: Number of messages to be executed 702 */ 703 static int st_i2c_xfer(struct i2c_adapter *i2c_adap, 704 struct i2c_msg msgs[], int num) 705 { 706 struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 707 int ret, i; 708 709 i2c_dev->busy = true; 710 711 ret = clk_prepare_enable(i2c_dev->clk); 712 if (ret) { 713 dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n"); 714 return ret; 715 } 716 717 pinctrl_pm_select_default_state(i2c_dev->dev); 718 719 st_i2c_hw_config(i2c_dev); 720 721 for (i = 0; (i < num) && !ret; i++) 722 ret = st_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, i == num - 1); 723 724 pinctrl_pm_select_idle_state(i2c_dev->dev); 725 726 clk_disable_unprepare(i2c_dev->clk); 727 728 i2c_dev->busy = false; 729 730 return (ret < 0) ? ret : i; 731 } 732 733 static int st_i2c_suspend(struct device *dev) 734 { 735 struct st_i2c_dev *i2c_dev = dev_get_drvdata(dev); 736 737 if (i2c_dev->busy) 738 return -EBUSY; 739 740 pinctrl_pm_select_sleep_state(dev); 741 742 return 0; 743 } 744 745 static int st_i2c_resume(struct device *dev) 746 { 747 pinctrl_pm_select_default_state(dev); 748 /* Go in idle state if available */ 749 pinctrl_pm_select_idle_state(dev); 750 751 return 0; 752 } 753 754 static DEFINE_SIMPLE_DEV_PM_OPS(st_i2c_pm, st_i2c_suspend, st_i2c_resume); 755 756 static u32 st_i2c_func(struct i2c_adapter *adap) 757 { 758 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 759 } 760 761 static const struct i2c_algorithm st_i2c_algo = { 762 .xfer = st_i2c_xfer, 763 .functionality = st_i2c_func, 764 }; 765 766 static struct i2c_bus_recovery_info st_i2c_recovery_info = { 767 .recover_bus = st_i2c_recover_bus, 768 }; 769 770 static int st_i2c_of_get_deglitch(struct device_node *np, 771 struct st_i2c_dev *i2c_dev) 772 { 773 int ret; 774 775 ret = of_property_read_u32(np, "st,i2c-min-scl-pulse-width-us", 776 &i2c_dev->scl_min_width_us); 777 if ((ret == -ENODATA) || (ret == -EOVERFLOW)) { 778 dev_err(i2c_dev->dev, "st,i2c-min-scl-pulse-width-us invalid\n"); 779 return ret; 780 } 781 782 ret = of_property_read_u32(np, "st,i2c-min-sda-pulse-width-us", 783 &i2c_dev->sda_min_width_us); 784 if ((ret == -ENODATA) || (ret == -EOVERFLOW)) { 785 dev_err(i2c_dev->dev, "st,i2c-min-sda-pulse-width-us invalid\n"); 786 return ret; 787 } 788 789 return 0; 790 } 791 792 static int st_i2c_probe(struct platform_device *pdev) 793 { 794 struct device_node *np = pdev->dev.of_node; 795 struct st_i2c_dev *i2c_dev; 796 struct resource *res; 797 u32 clk_rate; 798 struct i2c_adapter *adap; 799 int ret; 800 801 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 802 if (!i2c_dev) 803 return -ENOMEM; 804 805 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 806 if (IS_ERR(i2c_dev->base)) 807 return PTR_ERR(i2c_dev->base); 808 809 i2c_dev->irq = irq_of_parse_and_map(np, 0); 810 if (!i2c_dev->irq) { 811 dev_err(&pdev->dev, "IRQ missing or invalid\n"); 812 return -EINVAL; 813 } 814 815 i2c_dev->clk = of_clk_get_by_name(np, "ssc"); 816 if (IS_ERR(i2c_dev->clk)) { 817 dev_err(&pdev->dev, "Unable to request clock\n"); 818 return PTR_ERR(i2c_dev->clk); 819 } 820 821 i2c_dev->mode = I2C_MODE_STANDARD; 822 ret = of_property_read_u32(np, "clock-frequency", &clk_rate); 823 if (!ret && (clk_rate == I2C_MAX_FAST_MODE_FREQ)) 824 i2c_dev->mode = I2C_MODE_FAST; 825 826 i2c_dev->dev = &pdev->dev; 827 828 ret = devm_request_threaded_irq(&pdev->dev, i2c_dev->irq, 829 NULL, st_i2c_isr_thread, 830 IRQF_ONESHOT, pdev->name, i2c_dev); 831 if (ret) { 832 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); 833 return ret; 834 } 835 836 pinctrl_pm_select_default_state(i2c_dev->dev); 837 /* In case idle state available, select it */ 838 pinctrl_pm_select_idle_state(i2c_dev->dev); 839 840 ret = st_i2c_of_get_deglitch(np, i2c_dev); 841 if (ret) 842 return ret; 843 844 adap = &i2c_dev->adap; 845 i2c_set_adapdata(adap, i2c_dev); 846 snprintf(adap->name, sizeof(adap->name), "ST I2C(%pa)", &res->start); 847 adap->owner = THIS_MODULE; 848 adap->timeout = 2 * HZ; 849 adap->retries = 0; 850 adap->algo = &st_i2c_algo; 851 adap->bus_recovery_info = &st_i2c_recovery_info; 852 adap->dev.parent = &pdev->dev; 853 adap->dev.of_node = pdev->dev.of_node; 854 855 init_completion(&i2c_dev->complete); 856 857 ret = i2c_add_adapter(adap); 858 if (ret) 859 return ret; 860 861 platform_set_drvdata(pdev, i2c_dev); 862 863 dev_info(i2c_dev->dev, "%s initialized\n", adap->name); 864 865 return 0; 866 } 867 868 static void st_i2c_remove(struct platform_device *pdev) 869 { 870 struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 871 872 i2c_del_adapter(&i2c_dev->adap); 873 } 874 875 static const struct of_device_id st_i2c_match[] = { 876 { .compatible = "st,comms-ssc-i2c", }, 877 { .compatible = "st,comms-ssc4-i2c", }, 878 {}, 879 }; 880 MODULE_DEVICE_TABLE(of, st_i2c_match); 881 882 static struct platform_driver st_i2c_driver = { 883 .driver = { 884 .name = "st-i2c", 885 .of_match_table = st_i2c_match, 886 .pm = pm_sleep_ptr(&st_i2c_pm), 887 }, 888 .probe = st_i2c_probe, 889 .remove = st_i2c_remove, 890 }; 891 892 module_platform_driver(st_i2c_driver); 893 894 MODULE_AUTHOR("Maxime Coquelin <maxime.coquelin@st.com>"); 895 MODULE_DESCRIPTION("STMicroelectronics I2C driver"); 896 MODULE_LICENSE("GPL v2"); 897