1 /* 2 * Copyright (C) 2013 STMicroelectronics 3 * 4 * I2C master mode controller driver, used in STMicroelectronics devices. 5 * 6 * Author: Maxime Coquelin <maxime.coquelin@st.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2, as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/err.h> 16 #include <linux/i2c.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/platform_device.h> 25 26 /* SSC registers */ 27 #define SSC_BRG 0x000 28 #define SSC_TBUF 0x004 29 #define SSC_RBUF 0x008 30 #define SSC_CTL 0x00C 31 #define SSC_IEN 0x010 32 #define SSC_STA 0x014 33 #define SSC_I2C 0x018 34 #define SSC_SLAD 0x01C 35 #define SSC_REP_START_HOLD 0x020 36 #define SSC_START_HOLD 0x024 37 #define SSC_REP_START_SETUP 0x028 38 #define SSC_DATA_SETUP 0x02C 39 #define SSC_STOP_SETUP 0x030 40 #define SSC_BUS_FREE 0x034 41 #define SSC_TX_FSTAT 0x038 42 #define SSC_RX_FSTAT 0x03C 43 #define SSC_PRE_SCALER_BRG 0x040 44 #define SSC_CLR 0x080 45 #define SSC_NOISE_SUPP_WIDTH 0x100 46 #define SSC_PRSCALER 0x104 47 #define SSC_NOISE_SUPP_WIDTH_DATAOUT 0x108 48 #define SSC_PRSCALER_DATAOUT 0x10c 49 50 /* SSC Control */ 51 #define SSC_CTL_DATA_WIDTH_9 0x8 52 #define SSC_CTL_DATA_WIDTH_MSK 0xf 53 #define SSC_CTL_BM 0xf 54 #define SSC_CTL_HB BIT(4) 55 #define SSC_CTL_PH BIT(5) 56 #define SSC_CTL_PO BIT(6) 57 #define SSC_CTL_SR BIT(7) 58 #define SSC_CTL_MS BIT(8) 59 #define SSC_CTL_EN BIT(9) 60 #define SSC_CTL_LPB BIT(10) 61 #define SSC_CTL_EN_TX_FIFO BIT(11) 62 #define SSC_CTL_EN_RX_FIFO BIT(12) 63 #define SSC_CTL_EN_CLST_RX BIT(13) 64 65 /* SSC Interrupt Enable */ 66 #define SSC_IEN_RIEN BIT(0) 67 #define SSC_IEN_TIEN BIT(1) 68 #define SSC_IEN_TEEN BIT(2) 69 #define SSC_IEN_REEN BIT(3) 70 #define SSC_IEN_PEEN BIT(4) 71 #define SSC_IEN_AASEN BIT(6) 72 #define SSC_IEN_STOPEN BIT(7) 73 #define SSC_IEN_ARBLEN BIT(8) 74 #define SSC_IEN_NACKEN BIT(10) 75 #define SSC_IEN_REPSTRTEN BIT(11) 76 #define SSC_IEN_TX_FIFO_HALF BIT(12) 77 #define SSC_IEN_RX_FIFO_HALF_FULL BIT(14) 78 79 /* SSC Status */ 80 #define SSC_STA_RIR BIT(0) 81 #define SSC_STA_TIR BIT(1) 82 #define SSC_STA_TE BIT(2) 83 #define SSC_STA_RE BIT(3) 84 #define SSC_STA_PE BIT(4) 85 #define SSC_STA_CLST BIT(5) 86 #define SSC_STA_AAS BIT(6) 87 #define SSC_STA_STOP BIT(7) 88 #define SSC_STA_ARBL BIT(8) 89 #define SSC_STA_BUSY BIT(9) 90 #define SSC_STA_NACK BIT(10) 91 #define SSC_STA_REPSTRT BIT(11) 92 #define SSC_STA_TX_FIFO_HALF BIT(12) 93 #define SSC_STA_TX_FIFO_FULL BIT(13) 94 #define SSC_STA_RX_FIFO_HALF BIT(14) 95 96 /* SSC I2C Control */ 97 #define SSC_I2C_I2CM BIT(0) 98 #define SSC_I2C_STRTG BIT(1) 99 #define SSC_I2C_STOPG BIT(2) 100 #define SSC_I2C_ACKG BIT(3) 101 #define SSC_I2C_AD10 BIT(4) 102 #define SSC_I2C_TXENB BIT(5) 103 #define SSC_I2C_REPSTRTG BIT(11) 104 #define SSC_I2C_SLAVE_DISABLE BIT(12) 105 106 /* SSC Tx FIFO Status */ 107 #define SSC_TX_FSTAT_STATUS 0x07 108 109 /* SSC Rx FIFO Status */ 110 #define SSC_RX_FSTAT_STATUS 0x07 111 112 /* SSC Clear bit operation */ 113 #define SSC_CLR_SSCAAS BIT(6) 114 #define SSC_CLR_SSCSTOP BIT(7) 115 #define SSC_CLR_SSCARBL BIT(8) 116 #define SSC_CLR_NACK BIT(10) 117 #define SSC_CLR_REPSTRT BIT(11) 118 119 /* SSC Clock Prescaler */ 120 #define SSC_PRSC_VALUE 0x0f 121 122 123 #define SSC_TXFIFO_SIZE 0x8 124 #define SSC_RXFIFO_SIZE 0x8 125 126 enum st_i2c_mode { 127 I2C_MODE_STANDARD, 128 I2C_MODE_FAST, 129 I2C_MODE_END, 130 }; 131 132 /** 133 * struct st_i2c_timings - per-Mode tuning parameters 134 * @rate: I2C bus rate 135 * @rep_start_hold: I2C repeated start hold time requirement 136 * @rep_start_setup: I2C repeated start set up time requirement 137 * @start_hold: I2C start hold time requirement 138 * @data_setup_time: I2C data set up time requirement 139 * @stop_setup_time: I2C stop set up time requirement 140 * @bus_free_time: I2C bus free time requirement 141 * @sda_pulse_min_limit: I2C SDA pulse mini width limit 142 */ 143 struct st_i2c_timings { 144 u32 rate; 145 u32 rep_start_hold; 146 u32 rep_start_setup; 147 u32 start_hold; 148 u32 data_setup_time; 149 u32 stop_setup_time; 150 u32 bus_free_time; 151 u32 sda_pulse_min_limit; 152 }; 153 154 /** 155 * struct st_i2c_client - client specific data 156 * @addr: 8-bit slave addr, including r/w bit 157 * @count: number of bytes to be transfered 158 * @xfered: number of bytes already transferred 159 * @buf: data buffer 160 * @result: result of the transfer 161 * @stop: last I2C msg to be sent, i.e. STOP to be generated 162 */ 163 struct st_i2c_client { 164 u8 addr; 165 u32 count; 166 u32 xfered; 167 u8 *buf; 168 int result; 169 bool stop; 170 }; 171 172 /** 173 * struct st_i2c_dev - private data of the controller 174 * @adap: I2C adapter for this controller 175 * @dev: device for this controller 176 * @base: virtual memory area 177 * @complete: completion of I2C message 178 * @irq: interrupt line for th controller 179 * @clk: hw ssc block clock 180 * @mode: I2C mode of the controller. Standard or Fast only supported 181 * @scl_min_width_us: SCL line minimum pulse width in us 182 * @sda_min_width_us: SDA line minimum pulse width in us 183 * @client: I2C transfert information 184 * @busy: I2C transfer on-going 185 */ 186 struct st_i2c_dev { 187 struct i2c_adapter adap; 188 struct device *dev; 189 void __iomem *base; 190 struct completion complete; 191 int irq; 192 struct clk *clk; 193 int mode; 194 u32 scl_min_width_us; 195 u32 sda_min_width_us; 196 struct st_i2c_client client; 197 bool busy; 198 }; 199 200 static inline void st_i2c_set_bits(void __iomem *reg, u32 mask) 201 { 202 writel_relaxed(readl_relaxed(reg) | mask, reg); 203 } 204 205 static inline void st_i2c_clr_bits(void __iomem *reg, u32 mask) 206 { 207 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 208 } 209 210 /* 211 * From I2C Specifications v0.5. 212 * 213 * All the values below have +10% margin added to be 214 * compatible with some out-of-spec devices, 215 * like HDMI link of the Toshiba 19AV600 TV. 216 */ 217 static struct st_i2c_timings i2c_timings[] = { 218 [I2C_MODE_STANDARD] = { 219 .rate = 100000, 220 .rep_start_hold = 4400, 221 .rep_start_setup = 5170, 222 .start_hold = 4400, 223 .data_setup_time = 275, 224 .stop_setup_time = 4400, 225 .bus_free_time = 5170, 226 }, 227 [I2C_MODE_FAST] = { 228 .rate = 400000, 229 .rep_start_hold = 660, 230 .rep_start_setup = 660, 231 .start_hold = 660, 232 .data_setup_time = 110, 233 .stop_setup_time = 660, 234 .bus_free_time = 1430, 235 }, 236 }; 237 238 static void st_i2c_flush_rx_fifo(struct st_i2c_dev *i2c_dev) 239 { 240 int count, i; 241 242 /* 243 * Counter only counts up to 7 but fifo size is 8... 244 * When fifo is full, counter is 0 and RIR bit of status register is 245 * set 246 */ 247 if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR) 248 count = SSC_RXFIFO_SIZE; 249 else 250 count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) & 251 SSC_RX_FSTAT_STATUS; 252 253 for (i = 0; i < count; i++) 254 readl_relaxed(i2c_dev->base + SSC_RBUF); 255 } 256 257 static void st_i2c_soft_reset(struct st_i2c_dev *i2c_dev) 258 { 259 /* 260 * FIFO needs to be emptied before reseting the IP, 261 * else the controller raises a BUSY error. 262 */ 263 st_i2c_flush_rx_fifo(i2c_dev); 264 265 st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); 266 st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); 267 } 268 269 /** 270 * st_i2c_hw_config() - Prepare SSC block, calculate and apply tuning timings 271 * @i2c_dev: Controller's private data 272 */ 273 static void st_i2c_hw_config(struct st_i2c_dev *i2c_dev) 274 { 275 unsigned long rate; 276 u32 val, ns_per_clk; 277 struct st_i2c_timings *t = &i2c_timings[i2c_dev->mode]; 278 279 st_i2c_soft_reset(i2c_dev); 280 281 val = SSC_CLR_REPSTRT | SSC_CLR_NACK | SSC_CLR_SSCARBL | 282 SSC_CLR_SSCAAS | SSC_CLR_SSCSTOP; 283 writel_relaxed(val, i2c_dev->base + SSC_CLR); 284 285 /* SSC Control register setup */ 286 val = SSC_CTL_PO | SSC_CTL_PH | SSC_CTL_HB | SSC_CTL_DATA_WIDTH_9; 287 writel_relaxed(val, i2c_dev->base + SSC_CTL); 288 289 rate = clk_get_rate(i2c_dev->clk); 290 ns_per_clk = 1000000000 / rate; 291 292 /* Baudrate */ 293 val = rate / (2 * t->rate); 294 writel_relaxed(val, i2c_dev->base + SSC_BRG); 295 296 /* Pre-scaler baudrate */ 297 writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG); 298 299 /* Enable I2C mode */ 300 writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C); 301 302 /* Repeated start hold time */ 303 val = t->rep_start_hold / ns_per_clk; 304 writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD); 305 306 /* Repeated start set up time */ 307 val = t->rep_start_setup / ns_per_clk; 308 writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP); 309 310 /* Start hold time */ 311 val = t->start_hold / ns_per_clk; 312 writel_relaxed(val, i2c_dev->base + SSC_START_HOLD); 313 314 /* Data set up time */ 315 val = t->data_setup_time / ns_per_clk; 316 writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP); 317 318 /* Stop set up time */ 319 val = t->stop_setup_time / ns_per_clk; 320 writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP); 321 322 /* Bus free time */ 323 val = t->bus_free_time / ns_per_clk; 324 writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE); 325 326 /* Prescalers set up */ 327 val = rate / 10000000; 328 writel_relaxed(val, i2c_dev->base + SSC_PRSCALER); 329 writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT); 330 331 /* Noise suppression witdh */ 332 val = i2c_dev->scl_min_width_us * rate / 100000000; 333 writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH); 334 335 /* Noise suppression max output data delay width */ 336 val = i2c_dev->sda_min_width_us * rate / 100000000; 337 writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT); 338 } 339 340 static int st_i2c_wait_free_bus(struct st_i2c_dev *i2c_dev) 341 { 342 u32 sta; 343 int i; 344 345 for (i = 0; i < 10; i++) { 346 sta = readl_relaxed(i2c_dev->base + SSC_STA); 347 if (!(sta & SSC_STA_BUSY)) 348 return 0; 349 350 usleep_range(2000, 4000); 351 } 352 353 dev_err(i2c_dev->dev, "bus not free (status = 0x%08x)\n", sta); 354 355 return -EBUSY; 356 } 357 358 /** 359 * st_i2c_write_tx_fifo() - Write a byte in the Tx FIFO 360 * @i2c_dev: Controller's private data 361 * @byte: Data to write in the Tx FIFO 362 */ 363 static inline void st_i2c_write_tx_fifo(struct st_i2c_dev *i2c_dev, u8 byte) 364 { 365 u16 tbuf = byte << 1; 366 367 writel_relaxed(tbuf | 1, i2c_dev->base + SSC_TBUF); 368 } 369 370 /** 371 * st_i2c_wr_fill_tx_fifo() - Fill the Tx FIFO in write mode 372 * @i2c_dev: Controller's private data 373 * 374 * This functions fills the Tx FIFO with I2C transfert buffer when 375 * in write mode. 376 */ 377 static void st_i2c_wr_fill_tx_fifo(struct st_i2c_dev *i2c_dev) 378 { 379 struct st_i2c_client *c = &i2c_dev->client; 380 u32 tx_fstat, sta; 381 int i; 382 383 sta = readl_relaxed(i2c_dev->base + SSC_STA); 384 if (sta & SSC_STA_TX_FIFO_FULL) 385 return; 386 387 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); 388 tx_fstat &= SSC_TX_FSTAT_STATUS; 389 390 if (c->count < (SSC_TXFIFO_SIZE - tx_fstat)) 391 i = c->count; 392 else 393 i = SSC_TXFIFO_SIZE - tx_fstat; 394 395 for (; i > 0; i--, c->count--, c->buf++) 396 st_i2c_write_tx_fifo(i2c_dev, *c->buf); 397 } 398 399 /** 400 * st_i2c_rd_fill_tx_fifo() - Fill the Tx FIFO in read mode 401 * @i2c_dev: Controller's private data 402 * 403 * This functions fills the Tx FIFO with fixed pattern when 404 * in read mode to trigger clock. 405 */ 406 static void st_i2c_rd_fill_tx_fifo(struct st_i2c_dev *i2c_dev, int max) 407 { 408 struct st_i2c_client *c = &i2c_dev->client; 409 u32 tx_fstat, sta; 410 int i; 411 412 sta = readl_relaxed(i2c_dev->base + SSC_STA); 413 if (sta & SSC_STA_TX_FIFO_FULL) 414 return; 415 416 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); 417 tx_fstat &= SSC_TX_FSTAT_STATUS; 418 419 if (max < (SSC_TXFIFO_SIZE - tx_fstat)) 420 i = max; 421 else 422 i = SSC_TXFIFO_SIZE - tx_fstat; 423 424 for (; i > 0; i--, c->xfered++) 425 st_i2c_write_tx_fifo(i2c_dev, 0xff); 426 } 427 428 static void st_i2c_read_rx_fifo(struct st_i2c_dev *i2c_dev) 429 { 430 struct st_i2c_client *c = &i2c_dev->client; 431 u32 i, sta; 432 u16 rbuf; 433 434 sta = readl_relaxed(i2c_dev->base + SSC_STA); 435 if (sta & SSC_STA_RIR) { 436 i = SSC_RXFIFO_SIZE; 437 } else { 438 i = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT); 439 i &= SSC_RX_FSTAT_STATUS; 440 } 441 442 for (; (i > 0) && (c->count > 0); i--, c->count--) { 443 rbuf = readl_relaxed(i2c_dev->base + SSC_RBUF) >> 1; 444 *c->buf++ = (u8)rbuf & 0xff; 445 } 446 447 if (i) { 448 dev_err(i2c_dev->dev, "Unexpected %d bytes in rx fifo\n", i); 449 st_i2c_flush_rx_fifo(i2c_dev); 450 } 451 } 452 453 /** 454 * st_i2c_terminate_xfer() - Send either STOP or REPSTART condition 455 * @i2c_dev: Controller's private data 456 */ 457 static void st_i2c_terminate_xfer(struct st_i2c_dev *i2c_dev) 458 { 459 struct st_i2c_client *c = &i2c_dev->client; 460 461 st_i2c_clr_bits(i2c_dev->base + SSC_IEN, SSC_IEN_TEEN); 462 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG); 463 464 if (c->stop) { 465 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_STOPEN); 466 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); 467 } else { 468 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_REPSTRTEN); 469 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_REPSTRTG); 470 } 471 } 472 473 /** 474 * st_i2c_handle_write() - Handle FIFO empty interrupt in case of write 475 * @i2c_dev: Controller's private data 476 */ 477 static void st_i2c_handle_write(struct st_i2c_dev *i2c_dev) 478 { 479 struct st_i2c_client *c = &i2c_dev->client; 480 481 st_i2c_flush_rx_fifo(i2c_dev); 482 483 if (!c->count) 484 /* End of xfer, send stop or repstart */ 485 st_i2c_terminate_xfer(i2c_dev); 486 else 487 st_i2c_wr_fill_tx_fifo(i2c_dev); 488 } 489 490 /** 491 * st_i2c_handle_write() - Handle FIFO enmpty interrupt in case of read 492 * @i2c_dev: Controller's private data 493 */ 494 static void st_i2c_handle_read(struct st_i2c_dev *i2c_dev) 495 { 496 struct st_i2c_client *c = &i2c_dev->client; 497 u32 ien; 498 499 /* Trash the address read back */ 500 if (!c->xfered) { 501 readl_relaxed(i2c_dev->base + SSC_RBUF); 502 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_TXENB); 503 } else { 504 st_i2c_read_rx_fifo(i2c_dev); 505 } 506 507 if (!c->count) { 508 /* End of xfer, send stop or repstart */ 509 st_i2c_terminate_xfer(i2c_dev); 510 } else if (c->count == 1) { 511 /* Penultimate byte to xfer, disable ACK gen. */ 512 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_ACKG); 513 514 /* Last received byte is to be handled by NACK interrupt */ 515 ien = SSC_IEN_NACKEN | SSC_IEN_ARBLEN; 516 writel_relaxed(ien, i2c_dev->base + SSC_IEN); 517 518 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count); 519 } else { 520 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count - 1); 521 } 522 } 523 524 /** 525 * st_i2c_isr() - Interrupt routine 526 * @irq: interrupt number 527 * @data: Controller's private data 528 */ 529 static irqreturn_t st_i2c_isr_thread(int irq, void *data) 530 { 531 struct st_i2c_dev *i2c_dev = data; 532 struct st_i2c_client *c = &i2c_dev->client; 533 u32 sta, ien; 534 int it; 535 536 ien = readl_relaxed(i2c_dev->base + SSC_IEN); 537 sta = readl_relaxed(i2c_dev->base + SSC_STA); 538 539 /* Use __fls() to check error bits first */ 540 it = __fls(sta & ien); 541 if (it < 0) { 542 dev_dbg(i2c_dev->dev, "spurious it (sta=0x%04x, ien=0x%04x)\n", 543 sta, ien); 544 return IRQ_NONE; 545 } 546 547 switch (1 << it) { 548 case SSC_STA_TE: 549 if (c->addr & I2C_M_RD) 550 st_i2c_handle_read(i2c_dev); 551 else 552 st_i2c_handle_write(i2c_dev); 553 break; 554 555 case SSC_STA_STOP: 556 case SSC_STA_REPSTRT: 557 writel_relaxed(0, i2c_dev->base + SSC_IEN); 558 complete(&i2c_dev->complete); 559 break; 560 561 case SSC_STA_NACK: 562 writel_relaxed(SSC_CLR_NACK, i2c_dev->base + SSC_CLR); 563 564 /* Last received byte handled by NACK interrupt */ 565 if ((c->addr & I2C_M_RD) && (c->count == 1) && (c->xfered)) { 566 st_i2c_handle_read(i2c_dev); 567 break; 568 } 569 570 it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN; 571 writel_relaxed(it, i2c_dev->base + SSC_IEN); 572 573 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); 574 c->result = -EIO; 575 break; 576 577 case SSC_STA_ARBL: 578 writel_relaxed(SSC_CLR_SSCARBL, i2c_dev->base + SSC_CLR); 579 580 it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN; 581 writel_relaxed(it, i2c_dev->base + SSC_IEN); 582 583 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); 584 c->result = -EAGAIN; 585 break; 586 587 default: 588 dev_err(i2c_dev->dev, 589 "it %d unhandled (sta=0x%04x)\n", it, sta); 590 } 591 592 /* 593 * Read IEN register to ensure interrupt mask write is effective 594 * before re-enabling interrupt at GIC level, and thus avoid spurious 595 * interrupts. 596 */ 597 readl(i2c_dev->base + SSC_IEN); 598 599 return IRQ_HANDLED; 600 } 601 602 /** 603 * st_i2c_xfer_msg() - Transfer a single I2C message 604 * @i2c_dev: Controller's private data 605 * @msg: I2C message to transfer 606 * @is_first: first message of the sequence 607 * @is_last: last message of the sequence 608 */ 609 static int st_i2c_xfer_msg(struct st_i2c_dev *i2c_dev, struct i2c_msg *msg, 610 bool is_first, bool is_last) 611 { 612 struct st_i2c_client *c = &i2c_dev->client; 613 u32 ctl, i2c, it; 614 unsigned long timeout; 615 int ret; 616 617 c->addr = (u8)(msg->addr << 1); 618 c->addr |= (msg->flags & I2C_M_RD); 619 c->buf = msg->buf; 620 c->count = msg->len; 621 c->xfered = 0; 622 c->result = 0; 623 c->stop = is_last; 624 625 reinit_completion(&i2c_dev->complete); 626 627 ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO; 628 st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl); 629 630 i2c = SSC_I2C_TXENB; 631 if (c->addr & I2C_M_RD) 632 i2c |= SSC_I2C_ACKG; 633 st_i2c_set_bits(i2c_dev->base + SSC_I2C, i2c); 634 635 /* Write slave address */ 636 st_i2c_write_tx_fifo(i2c_dev, c->addr); 637 638 /* Pre-fill Tx fifo with data in case of write */ 639 if (!(c->addr & I2C_M_RD)) 640 st_i2c_wr_fill_tx_fifo(i2c_dev); 641 642 it = SSC_IEN_NACKEN | SSC_IEN_TEEN | SSC_IEN_ARBLEN; 643 writel_relaxed(it, i2c_dev->base + SSC_IEN); 644 645 if (is_first) { 646 ret = st_i2c_wait_free_bus(i2c_dev); 647 if (ret) 648 return ret; 649 650 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG); 651 } 652 653 timeout = wait_for_completion_timeout(&i2c_dev->complete, 654 i2c_dev->adap.timeout); 655 ret = c->result; 656 657 if (!timeout) { 658 dev_err(i2c_dev->dev, "Write to slave 0x%x timed out\n", 659 c->addr); 660 ret = -ETIMEDOUT; 661 } 662 663 i2c = SSC_I2C_STOPG | SSC_I2C_REPSTRTG; 664 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, i2c); 665 666 writel_relaxed(SSC_CLR_SSCSTOP | SSC_CLR_REPSTRT, 667 i2c_dev->base + SSC_CLR); 668 669 return ret; 670 } 671 672 /** 673 * st_i2c_xfer() - Transfer a single I2C message 674 * @i2c_adap: Adapter pointer to the controller 675 * @msgs: Pointer to data to be written. 676 * @num: Number of messages to be executed 677 */ 678 static int st_i2c_xfer(struct i2c_adapter *i2c_adap, 679 struct i2c_msg msgs[], int num) 680 { 681 struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 682 int ret, i; 683 684 i2c_dev->busy = true; 685 686 ret = clk_prepare_enable(i2c_dev->clk); 687 if (ret) { 688 dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n"); 689 return ret; 690 } 691 692 pinctrl_pm_select_default_state(i2c_dev->dev); 693 694 st_i2c_hw_config(i2c_dev); 695 696 for (i = 0; (i < num) && !ret; i++) 697 ret = st_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, i == num - 1); 698 699 pinctrl_pm_select_idle_state(i2c_dev->dev); 700 701 clk_disable_unprepare(i2c_dev->clk); 702 703 i2c_dev->busy = false; 704 705 return (ret < 0) ? ret : i; 706 } 707 708 #ifdef CONFIG_PM_SLEEP 709 static int st_i2c_suspend(struct device *dev) 710 { 711 struct platform_device *pdev = 712 container_of(dev, struct platform_device, dev); 713 struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 714 715 if (i2c_dev->busy) 716 return -EBUSY; 717 718 pinctrl_pm_select_sleep_state(dev); 719 720 return 0; 721 } 722 723 static int st_i2c_resume(struct device *dev) 724 { 725 pinctrl_pm_select_default_state(dev); 726 /* Go in idle state if available */ 727 pinctrl_pm_select_idle_state(dev); 728 729 return 0; 730 } 731 732 static SIMPLE_DEV_PM_OPS(st_i2c_pm, st_i2c_suspend, st_i2c_resume); 733 #define ST_I2C_PM (&st_i2c_pm) 734 #else 735 #define ST_I2C_PM NULL 736 #endif 737 738 static u32 st_i2c_func(struct i2c_adapter *adap) 739 { 740 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 741 } 742 743 static struct i2c_algorithm st_i2c_algo = { 744 .master_xfer = st_i2c_xfer, 745 .functionality = st_i2c_func, 746 }; 747 748 static int st_i2c_of_get_deglitch(struct device_node *np, 749 struct st_i2c_dev *i2c_dev) 750 { 751 int ret; 752 753 ret = of_property_read_u32(np, "st,i2c-min-scl-pulse-width-us", 754 &i2c_dev->scl_min_width_us); 755 if ((ret == -ENODATA) || (ret == -EOVERFLOW)) { 756 dev_err(i2c_dev->dev, "st,i2c-min-scl-pulse-width-us invalid\n"); 757 return ret; 758 } 759 760 ret = of_property_read_u32(np, "st,i2c-min-sda-pulse-width-us", 761 &i2c_dev->sda_min_width_us); 762 if ((ret == -ENODATA) || (ret == -EOVERFLOW)) { 763 dev_err(i2c_dev->dev, "st,i2c-min-sda-pulse-width-us invalid\n"); 764 return ret; 765 } 766 767 return 0; 768 } 769 770 static int st_i2c_probe(struct platform_device *pdev) 771 { 772 struct device_node *np = pdev->dev.of_node; 773 struct st_i2c_dev *i2c_dev; 774 struct resource *res; 775 u32 clk_rate; 776 struct i2c_adapter *adap; 777 int ret; 778 779 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 780 if (!i2c_dev) 781 return -ENOMEM; 782 783 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 784 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); 785 if (IS_ERR(i2c_dev->base)) 786 return PTR_ERR(i2c_dev->base); 787 788 i2c_dev->irq = irq_of_parse_and_map(np, 0); 789 if (!i2c_dev->irq) { 790 dev_err(&pdev->dev, "IRQ missing or invalid\n"); 791 return -EINVAL; 792 } 793 794 i2c_dev->clk = of_clk_get_by_name(np, "ssc"); 795 if (IS_ERR(i2c_dev->clk)) { 796 dev_err(&pdev->dev, "Unable to request clock\n"); 797 return PTR_ERR(i2c_dev->clk); 798 } 799 800 i2c_dev->mode = I2C_MODE_STANDARD; 801 ret = of_property_read_u32(np, "clock-frequency", &clk_rate); 802 if ((!ret) && (clk_rate == 400000)) 803 i2c_dev->mode = I2C_MODE_FAST; 804 805 i2c_dev->dev = &pdev->dev; 806 807 ret = devm_request_threaded_irq(&pdev->dev, i2c_dev->irq, 808 NULL, st_i2c_isr_thread, 809 IRQF_ONESHOT, pdev->name, i2c_dev); 810 if (ret) { 811 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); 812 return ret; 813 } 814 815 pinctrl_pm_select_default_state(i2c_dev->dev); 816 /* In case idle state available, select it */ 817 pinctrl_pm_select_idle_state(i2c_dev->dev); 818 819 ret = st_i2c_of_get_deglitch(np, i2c_dev); 820 if (ret) 821 return ret; 822 823 adap = &i2c_dev->adap; 824 i2c_set_adapdata(adap, i2c_dev); 825 snprintf(adap->name, sizeof(adap->name), "ST I2C(0x%pa)", &res->start); 826 adap->owner = THIS_MODULE; 827 adap->timeout = 2 * HZ; 828 adap->retries = 0; 829 adap->algo = &st_i2c_algo; 830 adap->dev.parent = &pdev->dev; 831 adap->dev.of_node = pdev->dev.of_node; 832 833 init_completion(&i2c_dev->complete); 834 835 ret = i2c_add_adapter(adap); 836 if (ret) { 837 dev_err(&pdev->dev, "Failed to add adapter\n"); 838 return ret; 839 } 840 841 platform_set_drvdata(pdev, i2c_dev); 842 843 dev_info(i2c_dev->dev, "%s initialized\n", adap->name); 844 845 return 0; 846 } 847 848 static int st_i2c_remove(struct platform_device *pdev) 849 { 850 struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 851 852 i2c_del_adapter(&i2c_dev->adap); 853 854 return 0; 855 } 856 857 static const struct of_device_id st_i2c_match[] = { 858 { .compatible = "st,comms-ssc-i2c", }, 859 { .compatible = "st,comms-ssc4-i2c", }, 860 {}, 861 }; 862 MODULE_DEVICE_TABLE(of, st_i2c_match); 863 864 static struct platform_driver st_i2c_driver = { 865 .driver = { 866 .name = "st-i2c", 867 .of_match_table = st_i2c_match, 868 .pm = ST_I2C_PM, 869 }, 870 .probe = st_i2c_probe, 871 .remove = st_i2c_remove, 872 }; 873 874 module_platform_driver(st_i2c_driver); 875 876 MODULE_AUTHOR("Maxime Coquelin <maxime.coquelin@st.com>"); 877 MODULE_DESCRIPTION("STMicroelectronics I2C driver"); 878 MODULE_LICENSE("GPL v2"); 879