xref: /linux/drivers/i2c/busses/i2c-sprd.c (revision e04e2b760ddbe3d7b283a05898c3a029085cd8cd)
1 /*
2  * Copyright (C) 2017 Spreadtrum Communications Inc.
3  *
4  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/i2c.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 
20 #define I2C_CTL			0x00
21 #define I2C_ADDR_CFG		0x04
22 #define I2C_COUNT		0x08
23 #define I2C_RX			0x0c
24 #define I2C_TX			0x10
25 #define I2C_STATUS		0x14
26 #define I2C_HSMODE_CFG		0x18
27 #define I2C_VERSION		0x1c
28 #define ADDR_DVD0		0x20
29 #define ADDR_DVD1		0x24
30 #define ADDR_STA0_DVD		0x28
31 #define ADDR_RST		0x2c
32 
33 /* I2C_CTL */
34 #define STP_EN			BIT(20)
35 #define FIFO_AF_LVL_MASK	GENMASK(19, 16)
36 #define FIFO_AF_LVL		16
37 #define FIFO_AE_LVL_MASK	GENMASK(15, 12)
38 #define FIFO_AE_LVL		12
39 #define I2C_DMA_EN		BIT(11)
40 #define FULL_INTEN		BIT(10)
41 #define EMPTY_INTEN		BIT(9)
42 #define I2C_DVD_OPT		BIT(8)
43 #define I2C_OUT_OPT		BIT(7)
44 #define I2C_TRIM_OPT		BIT(6)
45 #define I2C_HS_MODE		BIT(4)
46 #define I2C_MODE		BIT(3)
47 #define I2C_EN			BIT(2)
48 #define I2C_INT_EN		BIT(1)
49 #define I2C_START		BIT(0)
50 
51 /* I2C_STATUS */
52 #define SDA_IN			BIT(21)
53 #define SCL_IN			BIT(20)
54 #define FIFO_FULL		BIT(4)
55 #define FIFO_EMPTY		BIT(3)
56 #define I2C_INT			BIT(2)
57 #define I2C_RX_ACK		BIT(1)
58 #define I2C_BUSY		BIT(0)
59 
60 /* ADDR_RST */
61 #define I2C_RST			BIT(0)
62 
63 #define I2C_FIFO_DEEP		12
64 #define I2C_FIFO_FULL_THLD	15
65 #define I2C_FIFO_EMPTY_THLD	4
66 #define I2C_DATA_STEP		8
67 #define I2C_ADDR_DVD0_CALC(high, low)	\
68 	((((high) & GENMASK(15, 0)) << 16) | ((low) & GENMASK(15, 0)))
69 #define I2C_ADDR_DVD1_CALC(high, low)	\
70 	(((high) & GENMASK(31, 16)) | (((low) & GENMASK(31, 16)) >> 16))
71 
72 /* timeout (ms) for pm runtime autosuspend */
73 #define SPRD_I2C_PM_TIMEOUT	1000
74 /* timeout (ms) for transfer message */
75 #define I2C_XFER_TIMEOUT	1000
76 
77 /* SPRD i2c data structure */
78 struct sprd_i2c {
79 	struct i2c_adapter adap;
80 	struct device *dev;
81 	void __iomem *base;
82 	struct i2c_msg *msg;
83 	struct clk *clk;
84 	u32 src_clk;
85 	u32 bus_freq;
86 	struct completion complete;
87 	u8 *buf;
88 	u32 count;
89 	int irq;
90 	int err;
91 };
92 
93 static void sprd_i2c_set_count(struct sprd_i2c *i2c_dev, u32 count)
94 {
95 	writel(count, i2c_dev->base + I2C_COUNT);
96 }
97 
98 static void sprd_i2c_send_stop(struct sprd_i2c *i2c_dev, int stop)
99 {
100 	u32 tmp = readl(i2c_dev->base + I2C_CTL);
101 
102 	if (stop)
103 		writel(tmp & ~STP_EN, i2c_dev->base + I2C_CTL);
104 	else
105 		writel(tmp | STP_EN, i2c_dev->base + I2C_CTL);
106 }
107 
108 static void sprd_i2c_clear_start(struct sprd_i2c *i2c_dev)
109 {
110 	u32 tmp = readl(i2c_dev->base + I2C_CTL);
111 
112 	writel(tmp & ~I2C_START, i2c_dev->base + I2C_CTL);
113 }
114 
115 static void sprd_i2c_clear_ack(struct sprd_i2c *i2c_dev)
116 {
117 	u32 tmp = readl(i2c_dev->base + I2C_STATUS);
118 
119 	writel(tmp & ~I2C_RX_ACK, i2c_dev->base + I2C_STATUS);
120 }
121 
122 static void sprd_i2c_clear_irq(struct sprd_i2c *i2c_dev)
123 {
124 	u32 tmp = readl(i2c_dev->base + I2C_STATUS);
125 
126 	writel(tmp & ~I2C_INT, i2c_dev->base + I2C_STATUS);
127 }
128 
129 static void sprd_i2c_reset_fifo(struct sprd_i2c *i2c_dev)
130 {
131 	writel(I2C_RST, i2c_dev->base + ADDR_RST);
132 }
133 
134 static void sprd_i2c_set_devaddr(struct sprd_i2c *i2c_dev, struct i2c_msg *m)
135 {
136 	writel(m->addr << 1, i2c_dev->base + I2C_ADDR_CFG);
137 }
138 
139 static void sprd_i2c_write_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
140 {
141 	u32 i;
142 
143 	for (i = 0; i < len; i++)
144 		writeb(buf[i], i2c_dev->base + I2C_TX);
145 }
146 
147 static void sprd_i2c_read_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
148 {
149 	u32 i;
150 
151 	for (i = 0; i < len; i++)
152 		buf[i] = readb(i2c_dev->base + I2C_RX);
153 }
154 
155 static void sprd_i2c_set_full_thld(struct sprd_i2c *i2c_dev, u32 full_thld)
156 {
157 	u32 tmp = readl(i2c_dev->base + I2C_CTL);
158 
159 	tmp &= ~FIFO_AF_LVL_MASK;
160 	tmp |= full_thld << FIFO_AF_LVL;
161 	writel(tmp, i2c_dev->base + I2C_CTL);
162 };
163 
164 static void sprd_i2c_set_empty_thld(struct sprd_i2c *i2c_dev, u32 empty_thld)
165 {
166 	u32 tmp = readl(i2c_dev->base + I2C_CTL);
167 
168 	tmp &= ~FIFO_AE_LVL_MASK;
169 	tmp |= empty_thld << FIFO_AE_LVL;
170 	writel(tmp, i2c_dev->base + I2C_CTL);
171 };
172 
173 static void sprd_i2c_set_fifo_full_int(struct sprd_i2c *i2c_dev, int enable)
174 {
175 	u32 tmp = readl(i2c_dev->base + I2C_CTL);
176 
177 	if (enable)
178 		tmp |= FULL_INTEN;
179 	else
180 		tmp &= ~FULL_INTEN;
181 
182 	writel(tmp, i2c_dev->base + I2C_CTL);
183 };
184 
185 static void sprd_i2c_set_fifo_empty_int(struct sprd_i2c *i2c_dev, int enable)
186 {
187 	u32 tmp = readl(i2c_dev->base + I2C_CTL);
188 
189 	if (enable)
190 		tmp |= EMPTY_INTEN;
191 	else
192 		tmp &= ~EMPTY_INTEN;
193 
194 	writel(tmp, i2c_dev->base + I2C_CTL);
195 };
196 
197 static void sprd_i2c_opt_start(struct sprd_i2c *i2c_dev)
198 {
199 	u32 tmp = readl(i2c_dev->base + I2C_CTL);
200 
201 	writel(tmp | I2C_START, i2c_dev->base + I2C_CTL);
202 }
203 
204 static void sprd_i2c_opt_mode(struct sprd_i2c *i2c_dev, int rw)
205 {
206 	u32 cmd = readl(i2c_dev->base + I2C_CTL) & ~I2C_MODE;
207 
208 	writel(cmd | rw << 3, i2c_dev->base + I2C_CTL);
209 }
210 
211 static void sprd_i2c_data_transfer(struct sprd_i2c *i2c_dev)
212 {
213 	u32 i2c_count = i2c_dev->count;
214 	u32 need_tran = i2c_count <= I2C_FIFO_DEEP ? i2c_count : I2C_FIFO_DEEP;
215 	struct i2c_msg *msg = i2c_dev->msg;
216 
217 	if (msg->flags & I2C_M_RD) {
218 		sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, I2C_FIFO_FULL_THLD);
219 		i2c_dev->count -= I2C_FIFO_FULL_THLD;
220 		i2c_dev->buf += I2C_FIFO_FULL_THLD;
221 
222 		/*
223 		 * If the read data count is larger than rx fifo full threshold,
224 		 * we should enable the rx fifo full interrupt to read data
225 		 * again.
226 		 */
227 		if (i2c_dev->count >= I2C_FIFO_FULL_THLD)
228 			sprd_i2c_set_fifo_full_int(i2c_dev, 1);
229 	} else {
230 		sprd_i2c_write_bytes(i2c_dev, i2c_dev->buf, need_tran);
231 		i2c_dev->buf += need_tran;
232 		i2c_dev->count -= need_tran;
233 
234 		/*
235 		 * If the write data count is arger than tx fifo depth which
236 		 * means we can not write all data in one time, then we should
237 		 * enable the tx fifo empty interrupt to write again.
238 		 */
239 		if (i2c_count > I2C_FIFO_DEEP)
240 			sprd_i2c_set_fifo_empty_int(i2c_dev, 1);
241 	}
242 }
243 
244 static int sprd_i2c_handle_msg(struct i2c_adapter *i2c_adap,
245 			       struct i2c_msg *msg, bool is_last_msg)
246 {
247 	struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
248 	unsigned long time_left;
249 
250 	i2c_dev->msg = msg;
251 	i2c_dev->buf = msg->buf;
252 	i2c_dev->count = msg->len;
253 
254 	reinit_completion(&i2c_dev->complete);
255 	sprd_i2c_reset_fifo(i2c_dev);
256 	sprd_i2c_set_devaddr(i2c_dev, msg);
257 	sprd_i2c_set_count(i2c_dev, msg->len);
258 
259 	if (msg->flags & I2C_M_RD) {
260 		sprd_i2c_opt_mode(i2c_dev, 1);
261 		sprd_i2c_send_stop(i2c_dev, 1);
262 	} else {
263 		sprd_i2c_opt_mode(i2c_dev, 0);
264 		sprd_i2c_send_stop(i2c_dev, !!is_last_msg);
265 	}
266 
267 	/*
268 	 * We should enable rx fifo full interrupt to get data when receiving
269 	 * full data.
270 	 */
271 	if (msg->flags & I2C_M_RD)
272 		sprd_i2c_set_fifo_full_int(i2c_dev, 1);
273 	else
274 		sprd_i2c_data_transfer(i2c_dev);
275 
276 	sprd_i2c_opt_start(i2c_dev);
277 
278 	time_left = wait_for_completion_timeout(&i2c_dev->complete,
279 				msecs_to_jiffies(I2C_XFER_TIMEOUT));
280 	if (!time_left)
281 		return -ETIMEDOUT;
282 
283 	return i2c_dev->err;
284 }
285 
286 static int sprd_i2c_xfer(struct i2c_adapter *i2c_adap,
287 			 struct i2c_msg *msgs, int num)
288 {
289 	struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
290 	int im, ret;
291 
292 	ret = pm_runtime_resume_and_get(i2c_dev->dev);
293 	if (ret < 0)
294 		return ret;
295 
296 	for (im = 0; im < num - 1; im++) {
297 		ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im], 0);
298 		if (ret)
299 			goto err_msg;
300 	}
301 
302 	ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im++], 1);
303 
304 err_msg:
305 	pm_runtime_mark_last_busy(i2c_dev->dev);
306 	pm_runtime_put_autosuspend(i2c_dev->dev);
307 
308 	return ret < 0 ? ret : im;
309 }
310 
311 static u32 sprd_i2c_func(struct i2c_adapter *adap)
312 {
313 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
314 }
315 
316 static const struct i2c_algorithm sprd_i2c_algo = {
317 	.xfer = sprd_i2c_xfer,
318 	.functionality = sprd_i2c_func,
319 };
320 
321 static void sprd_i2c_set_clk(struct sprd_i2c *i2c_dev, u32 freq)
322 {
323 	u32 apb_clk = i2c_dev->src_clk;
324 	/*
325 	 * From I2C databook, the prescale calculation formula:
326 	 * prescale = freq_i2c / (4 * freq_scl) - 1;
327 	 */
328 	u32 i2c_dvd = apb_clk / (4 * freq) - 1;
329 	/*
330 	 * From I2C databook, the high period of SCL clock is recommended as
331 	 * 40% (2/5), and the low period of SCL clock is recommended as 60%
332 	 * (3/5), then the formula should be:
333 	 * high = (prescale * 2 * 2) / 5
334 	 * low = (prescale * 2 * 3) / 5
335 	 */
336 	u32 high = ((i2c_dvd << 1) * 2) / 5;
337 	u32 low = ((i2c_dvd << 1) * 3) / 5;
338 	u32 div0 = I2C_ADDR_DVD0_CALC(high, low);
339 	u32 div1 = I2C_ADDR_DVD1_CALC(high, low);
340 
341 	writel(div0, i2c_dev->base + ADDR_DVD0);
342 	writel(div1, i2c_dev->base + ADDR_DVD1);
343 
344 	/* Start hold timing = hold time(us) * source clock */
345 	if (freq == I2C_MAX_FAST_MODE_FREQ)
346 		writel((6 * apb_clk) / 10000000, i2c_dev->base + ADDR_STA0_DVD);
347 	else if (freq == I2C_MAX_STANDARD_MODE_FREQ)
348 		writel((4 * apb_clk) / 1000000, i2c_dev->base + ADDR_STA0_DVD);
349 }
350 
351 static void sprd_i2c_enable(struct sprd_i2c *i2c_dev)
352 {
353 	u32 tmp = I2C_DVD_OPT;
354 
355 	writel(tmp, i2c_dev->base + I2C_CTL);
356 
357 	sprd_i2c_set_full_thld(i2c_dev, I2C_FIFO_FULL_THLD);
358 	sprd_i2c_set_empty_thld(i2c_dev, I2C_FIFO_EMPTY_THLD);
359 
360 	sprd_i2c_set_clk(i2c_dev, i2c_dev->bus_freq);
361 	sprd_i2c_reset_fifo(i2c_dev);
362 	sprd_i2c_clear_irq(i2c_dev);
363 
364 	tmp = readl(i2c_dev->base + I2C_CTL);
365 	writel(tmp | I2C_EN | I2C_INT_EN, i2c_dev->base + I2C_CTL);
366 }
367 
368 static irqreturn_t sprd_i2c_isr_thread(int irq, void *dev_id)
369 {
370 	struct sprd_i2c *i2c_dev = dev_id;
371 	struct i2c_msg *msg = i2c_dev->msg;
372 	bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
373 	u32 i2c_tran;
374 
375 	if (msg->flags & I2C_M_RD)
376 		i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
377 	else
378 		i2c_tran = i2c_dev->count;
379 
380 	/*
381 	 * If we got one ACK from target when writing data, and we did not
382 	 * finish this transmission (i2c_tran is not zero), then we should
383 	 * continue to write data.
384 	 *
385 	 * For reading data, ack is always true, if i2c_tran is not 0 which
386 	 * means we still need to contine to read data from target.
387 	 */
388 	if (i2c_tran && ack) {
389 		sprd_i2c_data_transfer(i2c_dev);
390 		return IRQ_HANDLED;
391 	}
392 
393 	i2c_dev->err = 0;
394 
395 	/*
396 	 * If we did not get one ACK from target when writing data, we should
397 	 * return -EIO to notify users.
398 	 */
399 	if (!ack)
400 		i2c_dev->err = -EIO;
401 	else if (msg->flags & I2C_M_RD && i2c_dev->count)
402 		sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, i2c_dev->count);
403 
404 	/* Transmission is done and clear ack and start operation */
405 	sprd_i2c_clear_ack(i2c_dev);
406 	sprd_i2c_clear_start(i2c_dev);
407 	complete(&i2c_dev->complete);
408 
409 	return IRQ_HANDLED;
410 }
411 
412 static irqreturn_t sprd_i2c_isr(int irq, void *dev_id)
413 {
414 	struct sprd_i2c *i2c_dev = dev_id;
415 	struct i2c_msg *msg = i2c_dev->msg;
416 	bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
417 	u32 i2c_tran;
418 
419 	if (msg->flags & I2C_M_RD)
420 		i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
421 	else
422 		i2c_tran = i2c_dev->count;
423 
424 	/*
425 	 * If we did not get one ACK from target when writing data, then we
426 	 * should finish this transmission since we got some errors.
427 	 *
428 	 * When writing data, if i2c_tran == 0 which means we have writen
429 	 * done all data, then we can finish this transmission.
430 	 *
431 	 * When reading data, if conut < rx fifo full threshold, which
432 	 * means we can read all data in one time, then we can finish this
433 	 * transmission too.
434 	 */
435 	if (!i2c_tran || !ack) {
436 		sprd_i2c_clear_start(i2c_dev);
437 		sprd_i2c_clear_irq(i2c_dev);
438 	}
439 
440 	sprd_i2c_set_fifo_empty_int(i2c_dev, 0);
441 	sprd_i2c_set_fifo_full_int(i2c_dev, 0);
442 
443 	return IRQ_WAKE_THREAD;
444 }
445 
446 static int sprd_i2c_clk_init(struct sprd_i2c *i2c_dev)
447 {
448 	struct clk *clk_i2c, *clk_parent;
449 
450 	clk_i2c = devm_clk_get(i2c_dev->dev, "i2c");
451 	if (IS_ERR(clk_i2c)) {
452 		dev_warn(i2c_dev->dev, "i2c%d can't get the i2c clock\n",
453 			 i2c_dev->adap.nr);
454 		clk_i2c = NULL;
455 	}
456 
457 	clk_parent = devm_clk_get(i2c_dev->dev, "source");
458 	if (IS_ERR(clk_parent)) {
459 		dev_warn(i2c_dev->dev, "i2c%d can't get the source clock\n",
460 			 i2c_dev->adap.nr);
461 		clk_parent = NULL;
462 	}
463 
464 	if (clk_set_parent(clk_i2c, clk_parent))
465 		i2c_dev->src_clk = clk_get_rate(clk_i2c);
466 	else
467 		i2c_dev->src_clk = 26000000;
468 
469 	dev_dbg(i2c_dev->dev, "i2c%d set source clock is %d\n",
470 		i2c_dev->adap.nr, i2c_dev->src_clk);
471 
472 	i2c_dev->clk = devm_clk_get(i2c_dev->dev, "enable");
473 	if (IS_ERR(i2c_dev->clk)) {
474 		dev_err(i2c_dev->dev, "i2c%d can't get the enable clock\n",
475 			i2c_dev->adap.nr);
476 		return PTR_ERR(i2c_dev->clk);
477 	}
478 
479 	return 0;
480 }
481 
482 static int sprd_i2c_probe(struct platform_device *pdev)
483 {
484 	struct device *dev = &pdev->dev;
485 	struct sprd_i2c *i2c_dev;
486 	u32 prop;
487 	int ret;
488 
489 	pdev->id = of_alias_get_id(dev->of_node, "i2c");
490 
491 	i2c_dev = devm_kzalloc(dev, sizeof(struct sprd_i2c), GFP_KERNEL);
492 	if (!i2c_dev)
493 		return -ENOMEM;
494 
495 	i2c_dev->base = devm_platform_ioremap_resource(pdev, 0);
496 	if (IS_ERR(i2c_dev->base))
497 		return PTR_ERR(i2c_dev->base);
498 
499 	i2c_dev->irq = platform_get_irq(pdev, 0);
500 	if (i2c_dev->irq < 0)
501 		return i2c_dev->irq;
502 
503 	i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
504 	init_completion(&i2c_dev->complete);
505 	snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
506 		 "%s", "sprd-i2c");
507 
508 	i2c_dev->bus_freq = I2C_MAX_STANDARD_MODE_FREQ;
509 	i2c_dev->adap.owner = THIS_MODULE;
510 	i2c_dev->dev = dev;
511 	i2c_dev->adap.retries = 3;
512 	i2c_dev->adap.algo = &sprd_i2c_algo;
513 	i2c_dev->adap.algo_data = i2c_dev;
514 	i2c_dev->adap.dev.parent = dev;
515 	i2c_dev->adap.nr = pdev->id;
516 	i2c_dev->adap.dev.of_node = dev->of_node;
517 
518 	if (!of_property_read_u32(dev->of_node, "clock-frequency", &prop))
519 		i2c_dev->bus_freq = prop;
520 
521 	/* We only support 100k and 400k now, otherwise will return error. */
522 	if (i2c_dev->bus_freq != I2C_MAX_STANDARD_MODE_FREQ &&
523 	    i2c_dev->bus_freq != I2C_MAX_FAST_MODE_FREQ)
524 		return -EINVAL;
525 
526 	ret = sprd_i2c_clk_init(i2c_dev);
527 	if (ret)
528 		return ret;
529 
530 	platform_set_drvdata(pdev, i2c_dev);
531 
532 	ret = clk_prepare_enable(i2c_dev->clk);
533 	if (ret)
534 		return ret;
535 
536 	sprd_i2c_enable(i2c_dev);
537 
538 	pm_runtime_set_autosuspend_delay(i2c_dev->dev, SPRD_I2C_PM_TIMEOUT);
539 	pm_runtime_use_autosuspend(i2c_dev->dev);
540 	pm_runtime_set_active(i2c_dev->dev);
541 	pm_runtime_enable(i2c_dev->dev);
542 
543 	ret = pm_runtime_get_sync(i2c_dev->dev);
544 	if (ret < 0)
545 		goto err_rpm_put;
546 
547 	ret = devm_request_threaded_irq(dev, i2c_dev->irq,
548 		sprd_i2c_isr, sprd_i2c_isr_thread,
549 		IRQF_NO_SUSPEND | IRQF_ONESHOT,
550 		pdev->name, i2c_dev);
551 	if (ret) {
552 		dev_err(&pdev->dev, "failed to request irq %d\n", i2c_dev->irq);
553 		goto err_rpm_put;
554 	}
555 
556 	ret = i2c_add_numbered_adapter(&i2c_dev->adap);
557 	if (ret) {
558 		dev_err(&pdev->dev, "add adapter failed\n");
559 		goto err_rpm_put;
560 	}
561 
562 	pm_runtime_mark_last_busy(i2c_dev->dev);
563 	pm_runtime_put_autosuspend(i2c_dev->dev);
564 	return 0;
565 
566 err_rpm_put:
567 	pm_runtime_put_noidle(i2c_dev->dev);
568 	pm_runtime_disable(i2c_dev->dev);
569 	clk_disable_unprepare(i2c_dev->clk);
570 	return ret;
571 }
572 
573 static void sprd_i2c_remove(struct platform_device *pdev)
574 {
575 	struct sprd_i2c *i2c_dev = platform_get_drvdata(pdev);
576 	int ret;
577 
578 	ret = pm_runtime_get_sync(i2c_dev->dev);
579 	if (ret < 0)
580 		dev_err(&pdev->dev, "Failed to resume device (%pe)\n", ERR_PTR(ret));
581 
582 	i2c_del_adapter(&i2c_dev->adap);
583 
584 	if (ret >= 0)
585 		clk_disable_unprepare(i2c_dev->clk);
586 
587 	pm_runtime_put_noidle(i2c_dev->dev);
588 	pm_runtime_disable(i2c_dev->dev);
589 }
590 
591 static int __maybe_unused sprd_i2c_suspend_noirq(struct device *dev)
592 {
593 	struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
594 
595 	i2c_mark_adapter_suspended(&i2c_dev->adap);
596 	return pm_runtime_force_suspend(dev);
597 }
598 
599 static int __maybe_unused sprd_i2c_resume_noirq(struct device *dev)
600 {
601 	struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
602 
603 	i2c_mark_adapter_resumed(&i2c_dev->adap);
604 	return pm_runtime_force_resume(dev);
605 }
606 
607 static int __maybe_unused sprd_i2c_runtime_suspend(struct device *dev)
608 {
609 	struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
610 
611 	clk_disable_unprepare(i2c_dev->clk);
612 
613 	return 0;
614 }
615 
616 static int __maybe_unused sprd_i2c_runtime_resume(struct device *dev)
617 {
618 	struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
619 	int ret;
620 
621 	ret = clk_prepare_enable(i2c_dev->clk);
622 	if (ret)
623 		return ret;
624 
625 	sprd_i2c_enable(i2c_dev);
626 
627 	return 0;
628 }
629 
630 static const struct dev_pm_ops sprd_i2c_pm_ops = {
631 	SET_RUNTIME_PM_OPS(sprd_i2c_runtime_suspend,
632 			   sprd_i2c_runtime_resume, NULL)
633 
634 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sprd_i2c_suspend_noirq,
635 				      sprd_i2c_resume_noirq)
636 };
637 
638 static const struct of_device_id sprd_i2c_of_match[] = {
639 	{ .compatible = "sprd,sc9860-i2c", },
640 	{},
641 };
642 MODULE_DEVICE_TABLE(of, sprd_i2c_of_match);
643 
644 static struct platform_driver sprd_i2c_driver = {
645 	.probe = sprd_i2c_probe,
646 	.remove_new = sprd_i2c_remove,
647 	.driver = {
648 		   .name = "sprd-i2c",
649 		   .of_match_table = sprd_i2c_of_match,
650 		   .pm = &sprd_i2c_pm_ops,
651 	},
652 };
653 
654 module_platform_driver(sprd_i2c_driver);
655 
656 MODULE_DESCRIPTION("Spreadtrum I2C controller driver");
657 MODULE_LICENSE("GPL v2");
658