1 /* 2 sis96x.c - Part of lm_sensors, Linux kernel modules for hardware 3 monitoring 4 5 Copyright (c) 2003 Mark M. Hoffman <mhoffman@lightlink.com> 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 /* 23 This module must be considered BETA unless and until 24 the chipset manufacturer releases a datasheet. 25 The register definitions are based on the SiS630. 26 27 This module relies on quirk_sis_96x_smbus (drivers/pci/quirks.c) 28 for just about every machine for which users have reported. 29 If this module isn't detecting your 96x south bridge, have a 30 look there. 31 32 We assume there can only be one SiS96x with one SMBus interface. 33 */ 34 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/kernel.h> 38 #include <linux/delay.h> 39 #include <linux/stddef.h> 40 #include <linux/sched.h> 41 #include <linux/ioport.h> 42 #include <linux/i2c.h> 43 #include <linux/init.h> 44 #include <asm/io.h> 45 46 /* 47 HISTORY: 48 2003-05-11 1.0.0 Updated from lm_sensors project for kernel 2.5 49 (was i2c-sis645.c from lm_sensors 2.7.0) 50 */ 51 #define SIS96x_VERSION "1.0.0" 52 53 /* base address register in PCI config space */ 54 #define SIS96x_BAR 0x04 55 56 /* SiS96x SMBus registers */ 57 #define SMB_STS 0x00 58 #define SMB_EN 0x01 59 #define SMB_CNT 0x02 60 #define SMB_HOST_CNT 0x03 61 #define SMB_ADDR 0x04 62 #define SMB_CMD 0x05 63 #define SMB_PCOUNT 0x06 64 #define SMB_COUNT 0x07 65 #define SMB_BYTE 0x08 66 #define SMB_DEV_ADDR 0x10 67 #define SMB_DB0 0x11 68 #define SMB_DB1 0x12 69 #define SMB_SAA 0x13 70 71 /* register count for request_region */ 72 #define SMB_IOSIZE 0x20 73 74 /* Other settings */ 75 #define MAX_TIMEOUT 500 76 77 /* SiS96x SMBus constants */ 78 #define SIS96x_QUICK 0x00 79 #define SIS96x_BYTE 0x01 80 #define SIS96x_BYTE_DATA 0x02 81 #define SIS96x_WORD_DATA 0x03 82 #define SIS96x_PROC_CALL 0x04 83 #define SIS96x_BLOCK_DATA 0x05 84 85 static struct pci_driver sis96x_driver; 86 static struct i2c_adapter sis96x_adapter; 87 static u16 sis96x_smbus_base; 88 89 static inline u8 sis96x_read(u8 reg) 90 { 91 return inb(sis96x_smbus_base + reg) ; 92 } 93 94 static inline void sis96x_write(u8 reg, u8 data) 95 { 96 outb(data, sis96x_smbus_base + reg) ; 97 } 98 99 /* Execute a SMBus transaction. 100 int size is from SIS96x_QUICK to SIS96x_BLOCK_DATA 101 */ 102 static int sis96x_transaction(int size) 103 { 104 int temp; 105 int result = 0; 106 int timeout = 0; 107 108 dev_dbg(&sis96x_adapter.dev, "SMBus transaction %d\n", size); 109 110 /* Make sure the SMBus host is ready to start transmitting */ 111 if (((temp = sis96x_read(SMB_CNT)) & 0x03) != 0x00) { 112 113 dev_dbg(&sis96x_adapter.dev, "SMBus busy (0x%02x). " 114 "Resetting...\n", temp); 115 116 /* kill the transaction */ 117 sis96x_write(SMB_HOST_CNT, 0x20); 118 119 /* check it again */ 120 if (((temp = sis96x_read(SMB_CNT)) & 0x03) != 0x00) { 121 dev_dbg(&sis96x_adapter.dev, "Failed (0x%02x)\n", temp); 122 return -1; 123 } else { 124 dev_dbg(&sis96x_adapter.dev, "Successful\n"); 125 } 126 } 127 128 /* Turn off timeout interrupts, set fast host clock */ 129 sis96x_write(SMB_CNT, 0x20); 130 131 /* clear all (sticky) status flags */ 132 temp = sis96x_read(SMB_STS); 133 sis96x_write(SMB_STS, temp & 0x1e); 134 135 /* start the transaction by setting bit 4 and size bits */ 136 sis96x_write(SMB_HOST_CNT, 0x10 | (size & 0x07)); 137 138 /* We will always wait for a fraction of a second! */ 139 do { 140 msleep(1); 141 temp = sis96x_read(SMB_STS); 142 } while (!(temp & 0x0e) && (timeout++ < MAX_TIMEOUT)); 143 144 /* If the SMBus is still busy, we give up */ 145 if (timeout >= MAX_TIMEOUT) { 146 dev_dbg(&sis96x_adapter.dev, "SMBus Timeout! (0x%02x)\n", temp); 147 result = -1; 148 } 149 150 /* device error - probably missing ACK */ 151 if (temp & 0x02) { 152 dev_dbg(&sis96x_adapter.dev, "Failed bus transaction!\n"); 153 result = -1; 154 } 155 156 /* bus collision */ 157 if (temp & 0x04) { 158 dev_dbg(&sis96x_adapter.dev, "Bus collision!\n"); 159 result = -1; 160 } 161 162 /* Finish up by resetting the bus */ 163 sis96x_write(SMB_STS, temp); 164 if ((temp = sis96x_read(SMB_STS))) { 165 dev_dbg(&sis96x_adapter.dev, "Failed reset at " 166 "end of transaction! (0x%02x)\n", temp); 167 } 168 169 return result; 170 } 171 172 /* Return -1 on error. */ 173 static s32 sis96x_access(struct i2c_adapter * adap, u16 addr, 174 unsigned short flags, char read_write, 175 u8 command, int size, union i2c_smbus_data * data) 176 { 177 178 switch (size) { 179 case I2C_SMBUS_QUICK: 180 sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01)); 181 size = SIS96x_QUICK; 182 break; 183 184 case I2C_SMBUS_BYTE: 185 sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01)); 186 if (read_write == I2C_SMBUS_WRITE) 187 sis96x_write(SMB_CMD, command); 188 size = SIS96x_BYTE; 189 break; 190 191 case I2C_SMBUS_BYTE_DATA: 192 sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01)); 193 sis96x_write(SMB_CMD, command); 194 if (read_write == I2C_SMBUS_WRITE) 195 sis96x_write(SMB_BYTE, data->byte); 196 size = SIS96x_BYTE_DATA; 197 break; 198 199 case I2C_SMBUS_PROC_CALL: 200 case I2C_SMBUS_WORD_DATA: 201 sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01)); 202 sis96x_write(SMB_CMD, command); 203 if (read_write == I2C_SMBUS_WRITE) { 204 sis96x_write(SMB_BYTE, data->word & 0xff); 205 sis96x_write(SMB_BYTE + 1, (data->word & 0xff00) >> 8); 206 } 207 size = (size == I2C_SMBUS_PROC_CALL ? 208 SIS96x_PROC_CALL : SIS96x_WORD_DATA); 209 break; 210 211 case I2C_SMBUS_BLOCK_DATA: 212 /* TO DO: */ 213 dev_info(&adap->dev, "SMBus block not implemented!\n"); 214 return -1; 215 break; 216 217 default: 218 dev_info(&adap->dev, "Unsupported I2C size\n"); 219 return -1; 220 break; 221 } 222 223 if (sis96x_transaction(size)) 224 return -1; 225 226 if ((size != SIS96x_PROC_CALL) && 227 ((read_write == I2C_SMBUS_WRITE) || (size == SIS96x_QUICK))) 228 return 0; 229 230 switch (size) { 231 case SIS96x_BYTE: 232 case SIS96x_BYTE_DATA: 233 data->byte = sis96x_read(SMB_BYTE); 234 break; 235 236 case SIS96x_WORD_DATA: 237 case SIS96x_PROC_CALL: 238 data->word = sis96x_read(SMB_BYTE) + 239 (sis96x_read(SMB_BYTE + 1) << 8); 240 break; 241 } 242 return 0; 243 } 244 245 static u32 sis96x_func(struct i2c_adapter *adapter) 246 { 247 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 248 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 249 I2C_FUNC_SMBUS_PROC_CALL; 250 } 251 252 static struct i2c_algorithm smbus_algorithm = { 253 .smbus_xfer = sis96x_access, 254 .functionality = sis96x_func, 255 }; 256 257 static struct i2c_adapter sis96x_adapter = { 258 .owner = THIS_MODULE, 259 .class = I2C_CLASS_HWMON, 260 .algo = &smbus_algorithm, 261 }; 262 263 static struct pci_device_id sis96x_ids[] = { 264 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_SMBUS) }, 265 { 0, } 266 }; 267 268 MODULE_DEVICE_TABLE (pci, sis96x_ids); 269 270 static int __devinit sis96x_probe(struct pci_dev *dev, 271 const struct pci_device_id *id) 272 { 273 u16 ww = 0; 274 int retval; 275 276 if (sis96x_smbus_base) { 277 dev_err(&dev->dev, "Only one device supported.\n"); 278 return -EBUSY; 279 } 280 281 pci_read_config_word(dev, PCI_CLASS_DEVICE, &ww); 282 if (PCI_CLASS_SERIAL_SMBUS != ww) { 283 dev_err(&dev->dev, "Unsupported device class 0x%04x!\n", ww); 284 return -ENODEV; 285 } 286 287 sis96x_smbus_base = pci_resource_start(dev, SIS96x_BAR); 288 if (!sis96x_smbus_base) { 289 dev_err(&dev->dev, "SiS96x SMBus base address " 290 "not initialized!\n"); 291 return -EINVAL; 292 } 293 dev_info(&dev->dev, "SiS96x SMBus base address: 0x%04x\n", 294 sis96x_smbus_base); 295 296 /* Everything is happy, let's grab the memory and set things up. */ 297 if (!request_region(sis96x_smbus_base, SMB_IOSIZE, 298 sis96x_driver.name)) { 299 dev_err(&dev->dev, "SMBus registers 0x%04x-0x%04x " 300 "already in use!\n", sis96x_smbus_base, 301 sis96x_smbus_base + SMB_IOSIZE - 1); 302 303 sis96x_smbus_base = 0; 304 return -EINVAL; 305 } 306 307 /* set up the driverfs linkage to our parent device */ 308 sis96x_adapter.dev.parent = &dev->dev; 309 310 snprintf(sis96x_adapter.name, I2C_NAME_SIZE, 311 "SiS96x SMBus adapter at 0x%04x", sis96x_smbus_base); 312 313 if ((retval = i2c_add_adapter(&sis96x_adapter))) { 314 dev_err(&dev->dev, "Couldn't register adapter!\n"); 315 release_region(sis96x_smbus_base, SMB_IOSIZE); 316 sis96x_smbus_base = 0; 317 } 318 319 return retval; 320 } 321 322 static void __devexit sis96x_remove(struct pci_dev *dev) 323 { 324 if (sis96x_smbus_base) { 325 i2c_del_adapter(&sis96x_adapter); 326 release_region(sis96x_smbus_base, SMB_IOSIZE); 327 sis96x_smbus_base = 0; 328 } 329 } 330 331 static struct pci_driver sis96x_driver = { 332 .owner = THIS_MODULE, 333 .name = "sis96x_smbus", 334 .id_table = sis96x_ids, 335 .probe = sis96x_probe, 336 .remove = __devexit_p(sis96x_remove), 337 }; 338 339 static int __init i2c_sis96x_init(void) 340 { 341 printk(KERN_INFO "i2c-sis96x version %s\n", SIS96x_VERSION); 342 return pci_register_driver(&sis96x_driver); 343 } 344 345 static void __exit i2c_sis96x_exit(void) 346 { 347 pci_unregister_driver(&sis96x_driver); 348 } 349 350 MODULE_AUTHOR("Mark M. Hoffman <mhoffman@lightlink.com>"); 351 MODULE_DESCRIPTION("SiS96x SMBus driver"); 352 MODULE_LICENSE("GPL"); 353 354 /* Register initialization functions using helper macros */ 355 module_init(i2c_sis96x_init); 356 module_exit(i2c_sis96x_exit); 357 358