1 /* 2 * SuperH Mobile I2C Controller 3 * 4 * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com> 5 * 6 * Copyright (C) 2008 Magnus Damm 7 * 8 * Portions of the code based on out-of-tree driver i2c-sh7343.c 9 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/dmaengine.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/err.h> 26 #include <linux/i2c.h> 27 #include <linux/i2c/i2c-sh_mobile.h> 28 #include <linux/init.h> 29 #include <linux/interrupt.h> 30 #include <linux/io.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/of_device.h> 34 #include <linux/platform_device.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/slab.h> 37 38 /* Transmit operation: */ 39 /* */ 40 /* 0 byte transmit */ 41 /* BUS: S A8 ACK P(*) */ 42 /* IRQ: DTE WAIT */ 43 /* ICIC: */ 44 /* ICCR: 0x94 0x90 */ 45 /* ICDR: A8 */ 46 /* */ 47 /* 1 byte transmit */ 48 /* BUS: S A8 ACK D8(1) ACK P(*) */ 49 /* IRQ: DTE WAIT WAIT */ 50 /* ICIC: -DTE */ 51 /* ICCR: 0x94 0x90 */ 52 /* ICDR: A8 D8(1) */ 53 /* */ 54 /* 2 byte transmit */ 55 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */ 56 /* IRQ: DTE WAIT WAIT WAIT */ 57 /* ICIC: -DTE */ 58 /* ICCR: 0x94 0x90 */ 59 /* ICDR: A8 D8(1) D8(2) */ 60 /* */ 61 /* 3 bytes or more, +---------+ gets repeated */ 62 /* */ 63 /* */ 64 /* Receive operation: */ 65 /* */ 66 /* 0 byte receive - not supported since slave may hold SDA low */ 67 /* */ 68 /* 1 byte receive [TX] | [RX] */ 69 /* BUS: S A8 ACK | D8(1) ACK P(*) */ 70 /* IRQ: DTE WAIT | WAIT DTE */ 71 /* ICIC: -DTE | +DTE */ 72 /* ICCR: 0x94 0x81 | 0xc0 */ 73 /* ICDR: A8 | D8(1) */ 74 /* */ 75 /* 2 byte receive [TX]| [RX] */ 76 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */ 77 /* IRQ: DTE WAIT | WAIT WAIT DTE */ 78 /* ICIC: -DTE | +DTE */ 79 /* ICCR: 0x94 0x81 | 0xc0 */ 80 /* ICDR: A8 | D8(1) D8(2) */ 81 /* */ 82 /* 3 byte receive [TX] | [RX] (*) */ 83 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */ 84 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */ 85 /* ICIC: -DTE | +DTE */ 86 /* ICCR: 0x94 0x81 | 0xc0 */ 87 /* ICDR: A8 | D8(1) D8(2) D8(3) */ 88 /* */ 89 /* 4 bytes or more, this part is repeated +---------+ */ 90 /* */ 91 /* */ 92 /* Interrupt order and BUSY flag */ 93 /* ___ _ */ 94 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */ 95 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */ 96 /* */ 97 /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */ 98 /* ___ */ 99 /* WAIT IRQ ________________________________/ \___________ */ 100 /* TACK IRQ ____________________________________/ \_______ */ 101 /* DTE IRQ __________________________________________/ \_ */ 102 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 103 /* _______________________________________________ */ 104 /* BUSY __/ \_ */ 105 /* */ 106 /* (*) The STOP condition is only sent by the master at the end of the last */ 107 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */ 108 /* only cleared after the STOP condition, so, between messages we have to */ 109 /* poll for the DTE bit. */ 110 /* */ 111 112 enum sh_mobile_i2c_op { 113 OP_START = 0, 114 OP_TX_FIRST, 115 OP_TX, 116 OP_TX_STOP, 117 OP_TX_STOP_DATA, 118 OP_TX_TO_RX, 119 OP_RX, 120 OP_RX_STOP, 121 OP_RX_STOP_DATA, 122 }; 123 124 struct sh_mobile_i2c_data { 125 struct device *dev; 126 void __iomem *reg; 127 struct i2c_adapter adap; 128 unsigned long bus_speed; 129 unsigned int clks_per_count; 130 struct clk *clk; 131 u_int8_t icic; 132 u_int8_t flags; 133 u_int16_t iccl; 134 u_int16_t icch; 135 136 spinlock_t lock; 137 wait_queue_head_t wait; 138 struct i2c_msg *msg; 139 int pos; 140 int sr; 141 bool send_stop; 142 bool stop_after_dma; 143 144 struct resource *res; 145 struct dma_chan *dma_tx; 146 struct dma_chan *dma_rx; 147 struct scatterlist sg; 148 enum dma_data_direction dma_direction; 149 }; 150 151 struct sh_mobile_dt_config { 152 int clks_per_count; 153 }; 154 155 #define IIC_FLAG_HAS_ICIC67 (1 << 0) 156 157 #define STANDARD_MODE 100000 158 #define FAST_MODE 400000 159 160 /* Register offsets */ 161 #define ICDR 0x00 162 #define ICCR 0x04 163 #define ICSR 0x08 164 #define ICIC 0x0c 165 #define ICCL 0x10 166 #define ICCH 0x14 167 168 /* Register bits */ 169 #define ICCR_ICE 0x80 170 #define ICCR_RACK 0x40 171 #define ICCR_TRS 0x10 172 #define ICCR_BBSY 0x04 173 #define ICCR_SCP 0x01 174 175 #define ICSR_SCLM 0x80 176 #define ICSR_SDAM 0x40 177 #define SW_DONE 0x20 178 #define ICSR_BUSY 0x10 179 #define ICSR_AL 0x08 180 #define ICSR_TACK 0x04 181 #define ICSR_WAIT 0x02 182 #define ICSR_DTE 0x01 183 184 #define ICIC_ICCLB8 0x80 185 #define ICIC_ICCHB8 0x40 186 #define ICIC_TDMAE 0x20 187 #define ICIC_RDMAE 0x10 188 #define ICIC_ALE 0x08 189 #define ICIC_TACKE 0x04 190 #define ICIC_WAITE 0x02 191 #define ICIC_DTEE 0x01 192 193 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data) 194 { 195 if (offs == ICIC) 196 data |= pd->icic; 197 198 iowrite8(data, pd->reg + offs); 199 } 200 201 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs) 202 { 203 return ioread8(pd->reg + offs); 204 } 205 206 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs, 207 unsigned char set, unsigned char clr) 208 { 209 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr); 210 } 211 212 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf) 213 { 214 /* 215 * Conditional expression: 216 * ICCL >= COUNT_CLK * (tLOW + tf) 217 * 218 * SH-Mobile IIC hardware starts counting the LOW period of 219 * the SCL signal (tLOW) as soon as it pulls the SCL line. 220 * In order to meet the tLOW timing spec, we need to take into 221 * account the fall time of SCL signal (tf). Default tf value 222 * should be 0.3 us, for safety. 223 */ 224 return (((count_khz * (tLOW + tf)) + 5000) / 10000); 225 } 226 227 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf) 228 { 229 /* 230 * Conditional expression: 231 * ICCH >= COUNT_CLK * (tHIGH + tf) 232 * 233 * SH-Mobile IIC hardware is aware of SCL transition period 'tr', 234 * and can ignore it. SH-Mobile IIC controller starts counting 235 * the HIGH period of the SCL signal (tHIGH) after the SCL input 236 * voltage increases at VIH. 237 * 238 * Afterward it turned out calculating ICCH using only tHIGH spec 239 * will result in violation of the tHD;STA timing spec. We need 240 * to take into account the fall time of SDA signal (tf) at START 241 * condition, in order to meet both tHIGH and tHD;STA specs. 242 */ 243 return (((count_khz * (tHIGH + tf)) + 5000) / 10000); 244 } 245 246 static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd) 247 { 248 unsigned long i2c_clk_khz; 249 u32 tHIGH, tLOW, tf; 250 uint16_t max_val; 251 252 /* Get clock rate after clock is enabled */ 253 clk_prepare_enable(pd->clk); 254 i2c_clk_khz = clk_get_rate(pd->clk) / 1000; 255 clk_disable_unprepare(pd->clk); 256 i2c_clk_khz /= pd->clks_per_count; 257 258 if (pd->bus_speed == STANDARD_MODE) { 259 tLOW = 47; /* tLOW = 4.7 us */ 260 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */ 261 tf = 3; /* tf = 0.3 us */ 262 } else if (pd->bus_speed == FAST_MODE) { 263 tLOW = 13; /* tLOW = 1.3 us */ 264 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */ 265 tf = 3; /* tf = 0.3 us */ 266 } else { 267 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n", 268 pd->bus_speed); 269 return -EINVAL; 270 } 271 272 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf); 273 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf); 274 275 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff; 276 if (pd->iccl > max_val || pd->icch > max_val) { 277 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n", 278 pd->iccl, pd->icch); 279 return -EINVAL; 280 } 281 282 /* one more bit of ICCL in ICIC */ 283 if (pd->iccl & 0x100) 284 pd->icic |= ICIC_ICCLB8; 285 else 286 pd->icic &= ~ICIC_ICCLB8; 287 288 /* one more bit of ICCH in ICIC */ 289 if (pd->icch & 0x100) 290 pd->icic |= ICIC_ICCHB8; 291 else 292 pd->icic &= ~ICIC_ICCHB8; 293 294 dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch); 295 return 0; 296 } 297 298 static void activate_ch(struct sh_mobile_i2c_data *pd) 299 { 300 /* Wake up device and enable clock */ 301 pm_runtime_get_sync(pd->dev); 302 clk_prepare_enable(pd->clk); 303 304 /* Enable channel and configure rx ack */ 305 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 306 307 /* Mask all interrupts */ 308 iic_wr(pd, ICIC, 0); 309 310 /* Set the clock */ 311 iic_wr(pd, ICCL, pd->iccl & 0xff); 312 iic_wr(pd, ICCH, pd->icch & 0xff); 313 } 314 315 static void deactivate_ch(struct sh_mobile_i2c_data *pd) 316 { 317 /* Clear/disable interrupts */ 318 iic_wr(pd, ICSR, 0); 319 iic_wr(pd, ICIC, 0); 320 321 /* Disable channel */ 322 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 323 324 /* Disable clock and mark device as idle */ 325 clk_disable_unprepare(pd->clk); 326 pm_runtime_put_sync(pd->dev); 327 } 328 329 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, 330 enum sh_mobile_i2c_op op, unsigned char data) 331 { 332 unsigned char ret = 0; 333 unsigned long flags; 334 335 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data); 336 337 spin_lock_irqsave(&pd->lock, flags); 338 339 switch (op) { 340 case OP_START: /* issue start and trigger DTE interrupt */ 341 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY); 342 break; 343 case OP_TX_FIRST: /* disable DTE interrupt and write data */ 344 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 345 iic_wr(pd, ICDR, data); 346 break; 347 case OP_TX: /* write data */ 348 iic_wr(pd, ICDR, data); 349 break; 350 case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */ 351 iic_wr(pd, ICDR, data); 352 /* fallthrough */ 353 case OP_TX_STOP: /* issue a stop */ 354 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS 355 : ICCR_ICE | ICCR_TRS | ICCR_BBSY); 356 break; 357 case OP_TX_TO_RX: /* select read mode */ 358 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP); 359 break; 360 case OP_RX: /* just read data */ 361 ret = iic_rd(pd, ICDR); 362 break; 363 case OP_RX_STOP: /* enable DTE interrupt, issue stop */ 364 iic_wr(pd, ICIC, 365 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 366 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); 367 break; 368 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ 369 iic_wr(pd, ICIC, 370 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 371 ret = iic_rd(pd, ICDR); 372 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); 373 break; 374 } 375 376 spin_unlock_irqrestore(&pd->lock, flags); 377 378 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret); 379 return ret; 380 } 381 382 static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd) 383 { 384 return pd->pos == -1; 385 } 386 387 static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd) 388 { 389 return pd->pos == pd->msg->len - 1; 390 } 391 392 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd, 393 unsigned char *buf) 394 { 395 switch (pd->pos) { 396 case -1: 397 *buf = (pd->msg->addr & 0x7f) << 1; 398 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0; 399 break; 400 default: 401 *buf = pd->msg->buf[pd->pos]; 402 } 403 } 404 405 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd) 406 { 407 unsigned char data; 408 409 if (pd->pos == pd->msg->len) { 410 /* Send stop if we haven't yet (DMA case) */ 411 if (pd->send_stop && pd->stop_after_dma) 412 i2c_op(pd, OP_TX_STOP, 0); 413 return 1; 414 } 415 416 sh_mobile_i2c_get_data(pd, &data); 417 418 if (sh_mobile_i2c_is_last_byte(pd)) 419 i2c_op(pd, OP_TX_STOP_DATA, data); 420 else if (sh_mobile_i2c_is_first_byte(pd)) 421 i2c_op(pd, OP_TX_FIRST, data); 422 else 423 i2c_op(pd, OP_TX, data); 424 425 pd->pos++; 426 return 0; 427 } 428 429 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd) 430 { 431 unsigned char data; 432 int real_pos; 433 434 do { 435 if (pd->pos <= -1) { 436 sh_mobile_i2c_get_data(pd, &data); 437 438 if (sh_mobile_i2c_is_first_byte(pd)) 439 i2c_op(pd, OP_TX_FIRST, data); 440 else 441 i2c_op(pd, OP_TX, data); 442 break; 443 } 444 445 if (pd->pos == 0) { 446 i2c_op(pd, OP_TX_TO_RX, 0); 447 break; 448 } 449 450 real_pos = pd->pos - 2; 451 452 if (pd->pos == pd->msg->len) { 453 if (pd->stop_after_dma) { 454 /* Simulate PIO end condition after DMA transfer */ 455 i2c_op(pd, OP_RX_STOP, 0); 456 pd->pos++; 457 break; 458 } 459 460 if (real_pos < 0) { 461 i2c_op(pd, OP_RX_STOP, 0); 462 break; 463 } 464 data = i2c_op(pd, OP_RX_STOP_DATA, 0); 465 } else 466 data = i2c_op(pd, OP_RX, 0); 467 468 if (real_pos >= 0) 469 pd->msg->buf[real_pos] = data; 470 } while (0); 471 472 pd->pos++; 473 return pd->pos == (pd->msg->len + 2); 474 } 475 476 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) 477 { 478 struct sh_mobile_i2c_data *pd = dev_id; 479 unsigned char sr; 480 int wakeup = 0; 481 482 sr = iic_rd(pd, ICSR); 483 pd->sr |= sr; /* remember state */ 484 485 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, 486 (pd->msg->flags & I2C_M_RD) ? "read" : "write", 487 pd->pos, pd->msg->len); 488 489 /* Kick off TxDMA after preface was done */ 490 if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0) 491 iic_set_clr(pd, ICIC, ICIC_TDMAE, 0); 492 else if (sr & (ICSR_AL | ICSR_TACK)) 493 /* don't interrupt transaction - continue to issue stop */ 494 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK)); 495 else if (pd->msg->flags & I2C_M_RD) 496 wakeup = sh_mobile_i2c_isr_rx(pd); 497 else 498 wakeup = sh_mobile_i2c_isr_tx(pd); 499 500 /* Kick off RxDMA after preface was done */ 501 if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1) 502 iic_set_clr(pd, ICIC, ICIC_RDMAE, 0); 503 504 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ 505 iic_wr(pd, ICSR, sr & ~ICSR_WAIT); 506 507 if (wakeup) { 508 pd->sr |= SW_DONE; 509 wake_up(&pd->wait); 510 } 511 512 /* defeat write posting to avoid spurious WAIT interrupts */ 513 iic_rd(pd, ICSR); 514 515 return IRQ_HANDLED; 516 } 517 518 static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd) 519 { 520 struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE 521 ? pd->dma_rx : pd->dma_tx; 522 523 dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg), 524 pd->msg->len, pd->dma_direction); 525 526 pd->dma_direction = DMA_NONE; 527 } 528 529 static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd) 530 { 531 if (pd->dma_direction == DMA_NONE) 532 return; 533 else if (pd->dma_direction == DMA_FROM_DEVICE) 534 dmaengine_terminate_all(pd->dma_rx); 535 else if (pd->dma_direction == DMA_TO_DEVICE) 536 dmaengine_terminate_all(pd->dma_tx); 537 538 sh_mobile_i2c_dma_unmap(pd); 539 } 540 541 static void sh_mobile_i2c_dma_callback(void *data) 542 { 543 struct sh_mobile_i2c_data *pd = data; 544 545 sh_mobile_i2c_dma_unmap(pd); 546 pd->pos = pd->msg->len; 547 pd->stop_after_dma = true; 548 549 iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE); 550 } 551 552 static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev, 553 enum dma_transfer_direction dir, dma_addr_t port_addr) 554 { 555 struct dma_chan *chan; 556 struct dma_slave_config cfg; 557 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 558 int ret; 559 560 chan = dma_request_slave_channel_reason(dev, chan_name); 561 if (IS_ERR(chan)) { 562 ret = PTR_ERR(chan); 563 dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret); 564 return chan; 565 } 566 567 memset(&cfg, 0, sizeof(cfg)); 568 cfg.direction = dir; 569 if (dir == DMA_MEM_TO_DEV) { 570 cfg.dst_addr = port_addr; 571 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 572 } else { 573 cfg.src_addr = port_addr; 574 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 575 } 576 577 ret = dmaengine_slave_config(chan, &cfg); 578 if (ret) { 579 dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret); 580 dma_release_channel(chan); 581 return ERR_PTR(ret); 582 } 583 584 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 585 return chan; 586 } 587 588 static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd) 589 { 590 bool read = pd->msg->flags & I2C_M_RD; 591 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 592 struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx; 593 struct dma_async_tx_descriptor *txdesc; 594 dma_addr_t dma_addr; 595 dma_cookie_t cookie; 596 597 if (PTR_ERR(chan) == -EPROBE_DEFER) { 598 if (read) 599 chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM, 600 pd->res->start + ICDR); 601 else 602 chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV, 603 pd->res->start + ICDR); 604 } 605 606 if (IS_ERR(chan)) 607 return; 608 609 dma_addr = dma_map_single(chan->device->dev, pd->msg->buf, pd->msg->len, dir); 610 if (dma_mapping_error(pd->dev, dma_addr)) { 611 dev_dbg(pd->dev, "dma map failed, using PIO\n"); 612 return; 613 } 614 615 sg_dma_len(&pd->sg) = pd->msg->len; 616 sg_dma_address(&pd->sg) = dma_addr; 617 618 pd->dma_direction = dir; 619 620 txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1, 621 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 622 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 623 if (!txdesc) { 624 dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n"); 625 sh_mobile_i2c_cleanup_dma(pd); 626 return; 627 } 628 629 txdesc->callback = sh_mobile_i2c_dma_callback; 630 txdesc->callback_param = pd; 631 632 cookie = dmaengine_submit(txdesc); 633 if (dma_submit_error(cookie)) { 634 dev_dbg(pd->dev, "submitting dma failed, using PIO\n"); 635 sh_mobile_i2c_cleanup_dma(pd); 636 return; 637 } 638 639 dma_async_issue_pending(chan); 640 } 641 642 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg, 643 bool do_init) 644 { 645 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) { 646 dev_err(pd->dev, "Unsupported zero length i2c read\n"); 647 return -EOPNOTSUPP; 648 } 649 650 if (do_init) { 651 /* Initialize channel registers */ 652 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 653 654 /* Enable channel and configure rx ack */ 655 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 656 657 /* Set the clock */ 658 iic_wr(pd, ICCL, pd->iccl & 0xff); 659 iic_wr(pd, ICCH, pd->icch & 0xff); 660 } 661 662 pd->msg = usr_msg; 663 pd->pos = -1; 664 pd->sr = 0; 665 666 if (pd->msg->len > 8) 667 sh_mobile_i2c_xfer_dma(pd); 668 669 /* Enable all interrupts to begin with */ 670 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 671 return 0; 672 } 673 674 static int poll_dte(struct sh_mobile_i2c_data *pd) 675 { 676 int i; 677 678 for (i = 1000; i; i--) { 679 u_int8_t val = iic_rd(pd, ICSR); 680 681 if (val & ICSR_DTE) 682 break; 683 684 if (val & ICSR_TACK) 685 return -ENXIO; 686 687 udelay(10); 688 } 689 690 return i ? 0 : -ETIMEDOUT; 691 } 692 693 static int poll_busy(struct sh_mobile_i2c_data *pd) 694 { 695 int i; 696 697 for (i = 1000; i; i--) { 698 u_int8_t val = iic_rd(pd, ICSR); 699 700 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); 701 702 /* the interrupt handler may wake us up before the 703 * transfer is finished, so poll the hardware 704 * until we're done. 705 */ 706 if (!(val & ICSR_BUSY)) { 707 /* handle missing acknowledge and arbitration lost */ 708 val |= pd->sr; 709 if (val & ICSR_TACK) 710 return -ENXIO; 711 if (val & ICSR_AL) 712 return -EAGAIN; 713 break; 714 } 715 716 udelay(10); 717 } 718 719 return i ? 0 : -ETIMEDOUT; 720 } 721 722 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter, 723 struct i2c_msg *msgs, 724 int num) 725 { 726 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); 727 struct i2c_msg *msg; 728 int err = 0; 729 int i, k; 730 731 activate_ch(pd); 732 733 /* Process all messages */ 734 for (i = 0; i < num; i++) { 735 bool do_start = pd->send_stop || !i; 736 msg = &msgs[i]; 737 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP; 738 pd->stop_after_dma = false; 739 740 err = start_ch(pd, msg, do_start); 741 if (err) 742 break; 743 744 if (do_start) 745 i2c_op(pd, OP_START, 0); 746 747 /* The interrupt handler takes care of the rest... */ 748 k = wait_event_timeout(pd->wait, 749 pd->sr & (ICSR_TACK | SW_DONE), 750 5 * HZ); 751 if (!k) { 752 dev_err(pd->dev, "Transfer request timed out\n"); 753 if (pd->dma_direction != DMA_NONE) 754 sh_mobile_i2c_cleanup_dma(pd); 755 756 err = -ETIMEDOUT; 757 break; 758 } 759 760 if (pd->send_stop) 761 err = poll_busy(pd); 762 else 763 err = poll_dte(pd); 764 if (err < 0) 765 break; 766 } 767 768 deactivate_ch(pd); 769 770 if (!err) 771 err = num; 772 return err; 773 } 774 775 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter) 776 { 777 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 778 } 779 780 static struct i2c_algorithm sh_mobile_i2c_algorithm = { 781 .functionality = sh_mobile_i2c_func, 782 .master_xfer = sh_mobile_i2c_xfer, 783 }; 784 785 static const struct sh_mobile_dt_config default_dt_config = { 786 .clks_per_count = 1, 787 }; 788 789 static const struct sh_mobile_dt_config fast_clock_dt_config = { 790 .clks_per_count = 2, 791 }; 792 793 static const struct of_device_id sh_mobile_i2c_dt_ids[] = { 794 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config }, 795 { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config }, 796 { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config }, 797 { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config }, 798 { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config }, 799 { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config }, 800 { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config }, 801 { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config }, 802 {}, 803 }; 804 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids); 805 806 static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd) 807 { 808 if (!IS_ERR(pd->dma_tx)) { 809 dma_release_channel(pd->dma_tx); 810 pd->dma_tx = ERR_PTR(-EPROBE_DEFER); 811 } 812 813 if (!IS_ERR(pd->dma_rx)) { 814 dma_release_channel(pd->dma_rx); 815 pd->dma_rx = ERR_PTR(-EPROBE_DEFER); 816 } 817 } 818 819 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd) 820 { 821 struct resource *res; 822 resource_size_t n; 823 int k = 0, ret; 824 825 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) { 826 for (n = res->start; n <= res->end; n++) { 827 ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr, 828 0, dev_name(&dev->dev), pd); 829 if (ret) { 830 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n); 831 return ret; 832 } 833 } 834 k++; 835 } 836 837 return k > 0 ? 0 : -ENOENT; 838 } 839 840 static int sh_mobile_i2c_probe(struct platform_device *dev) 841 { 842 struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev); 843 struct sh_mobile_i2c_data *pd; 844 struct i2c_adapter *adap; 845 struct resource *res; 846 int ret; 847 u32 bus_speed; 848 849 pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL); 850 if (!pd) 851 return -ENOMEM; 852 853 pd->clk = devm_clk_get(&dev->dev, NULL); 854 if (IS_ERR(pd->clk)) { 855 dev_err(&dev->dev, "cannot get clock\n"); 856 return PTR_ERR(pd->clk); 857 } 858 859 ret = sh_mobile_i2c_hook_irqs(dev, pd); 860 if (ret) 861 return ret; 862 863 pd->dev = &dev->dev; 864 platform_set_drvdata(dev, pd); 865 866 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 867 868 pd->res = res; 869 pd->reg = devm_ioremap_resource(&dev->dev, res); 870 if (IS_ERR(pd->reg)) 871 return PTR_ERR(pd->reg); 872 873 /* Use platform data bus speed or STANDARD_MODE */ 874 ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed); 875 pd->bus_speed = ret ? STANDARD_MODE : bus_speed; 876 877 pd->clks_per_count = 1; 878 879 if (dev->dev.of_node) { 880 const struct of_device_id *match; 881 882 match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev); 883 if (match) { 884 const struct sh_mobile_dt_config *config; 885 886 config = match->data; 887 pd->clks_per_count = config->clks_per_count; 888 } 889 } else { 890 if (pdata && pdata->bus_speed) 891 pd->bus_speed = pdata->bus_speed; 892 if (pdata && pdata->clks_per_count) 893 pd->clks_per_count = pdata->clks_per_count; 894 } 895 896 /* The IIC blocks on SH-Mobile ARM processors 897 * come with two new bits in ICIC. 898 */ 899 if (resource_size(res) > 0x17) 900 pd->flags |= IIC_FLAG_HAS_ICIC67; 901 902 ret = sh_mobile_i2c_init(pd); 903 if (ret) 904 return ret; 905 906 /* Init DMA */ 907 sg_init_table(&pd->sg, 1); 908 pd->dma_direction = DMA_NONE; 909 pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER); 910 911 /* Enable Runtime PM for this device. 912 * 913 * Also tell the Runtime PM core to ignore children 914 * for this device since it is valid for us to suspend 915 * this I2C master driver even though the slave devices 916 * on the I2C bus may not be suspended. 917 * 918 * The state of the I2C hardware bus is unaffected by 919 * the Runtime PM state. 920 */ 921 pm_suspend_ignore_children(&dev->dev, true); 922 pm_runtime_enable(&dev->dev); 923 924 /* setup the private data */ 925 adap = &pd->adap; 926 i2c_set_adapdata(adap, pd); 927 928 adap->owner = THIS_MODULE; 929 adap->algo = &sh_mobile_i2c_algorithm; 930 adap->dev.parent = &dev->dev; 931 adap->retries = 5; 932 adap->nr = dev->id; 933 adap->dev.of_node = dev->dev.of_node; 934 935 strlcpy(adap->name, dev->name, sizeof(adap->name)); 936 937 spin_lock_init(&pd->lock); 938 init_waitqueue_head(&pd->wait); 939 940 ret = i2c_add_numbered_adapter(adap); 941 if (ret < 0) { 942 sh_mobile_i2c_release_dma(pd); 943 dev_err(&dev->dev, "cannot add numbered adapter\n"); 944 return ret; 945 } 946 947 dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed); 948 949 return 0; 950 } 951 952 static int sh_mobile_i2c_remove(struct platform_device *dev) 953 { 954 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 955 956 i2c_del_adapter(&pd->adap); 957 sh_mobile_i2c_release_dma(pd); 958 pm_runtime_disable(&dev->dev); 959 return 0; 960 } 961 962 static int sh_mobile_i2c_runtime_nop(struct device *dev) 963 { 964 /* Runtime PM callback shared between ->runtime_suspend() 965 * and ->runtime_resume(). Simply returns success. 966 * 967 * This driver re-initializes all registers after 968 * pm_runtime_get_sync() anyway so there is no need 969 * to save and restore registers here. 970 */ 971 return 0; 972 } 973 974 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = { 975 .runtime_suspend = sh_mobile_i2c_runtime_nop, 976 .runtime_resume = sh_mobile_i2c_runtime_nop, 977 }; 978 979 static struct platform_driver sh_mobile_i2c_driver = { 980 .driver = { 981 .name = "i2c-sh_mobile", 982 .pm = &sh_mobile_i2c_dev_pm_ops, 983 .of_match_table = sh_mobile_i2c_dt_ids, 984 }, 985 .probe = sh_mobile_i2c_probe, 986 .remove = sh_mobile_i2c_remove, 987 }; 988 989 static int __init sh_mobile_i2c_adap_init(void) 990 { 991 return platform_driver_register(&sh_mobile_i2c_driver); 992 } 993 subsys_initcall(sh_mobile_i2c_adap_init); 994 995 static void __exit sh_mobile_i2c_adap_exit(void) 996 { 997 platform_driver_unregister(&sh_mobile_i2c_driver); 998 } 999 module_exit(sh_mobile_i2c_adap_exit); 1000 1001 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver"); 1002 MODULE_AUTHOR("Magnus Damm and Wolfram Sang"); 1003 MODULE_LICENSE("GPL v2"); 1004 MODULE_ALIAS("platform:i2c-sh_mobile"); 1005