1 /* 2 * SuperH Mobile I2C Controller 3 * 4 * Copyright (C) 2008 Magnus Damm 5 * 6 * Portions of the code based on out-of-tree driver i2c-sh7343.c 7 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/init.h> 26 #include <linux/delay.h> 27 #include <linux/platform_device.h> 28 #include <linux/interrupt.h> 29 #include <linux/i2c.h> 30 #include <linux/err.h> 31 #include <linux/clk.h> 32 #include <linux/io.h> 33 34 /* Transmit operation: */ 35 /* */ 36 /* 0 byte transmit */ 37 /* BUS: S A8 ACK P */ 38 /* IRQ: DTE WAIT */ 39 /* ICIC: */ 40 /* ICCR: 0x94 0x90 */ 41 /* ICDR: A8 */ 42 /* */ 43 /* 1 byte transmit */ 44 /* BUS: S A8 ACK D8(1) ACK P */ 45 /* IRQ: DTE WAIT WAIT */ 46 /* ICIC: -DTE */ 47 /* ICCR: 0x94 0x90 */ 48 /* ICDR: A8 D8(1) */ 49 /* */ 50 /* 2 byte transmit */ 51 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P */ 52 /* IRQ: DTE WAIT WAIT WAIT */ 53 /* ICIC: -DTE */ 54 /* ICCR: 0x94 0x90 */ 55 /* ICDR: A8 D8(1) D8(2) */ 56 /* */ 57 /* 3 bytes or more, +---------+ gets repeated */ 58 /* */ 59 /* */ 60 /* Receive operation: */ 61 /* */ 62 /* 0 byte receive - not supported since slave may hold SDA low */ 63 /* */ 64 /* 1 byte receive [TX] | [RX] */ 65 /* BUS: S A8 ACK | D8(1) ACK P */ 66 /* IRQ: DTE WAIT | WAIT DTE */ 67 /* ICIC: -DTE | +DTE */ 68 /* ICCR: 0x94 0x81 | 0xc0 */ 69 /* ICDR: A8 | D8(1) */ 70 /* */ 71 /* 2 byte receive [TX]| [RX] */ 72 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P */ 73 /* IRQ: DTE WAIT | WAIT WAIT DTE */ 74 /* ICIC: -DTE | +DTE */ 75 /* ICCR: 0x94 0x81 | 0xc0 */ 76 /* ICDR: A8 | D8(1) D8(2) */ 77 /* */ 78 /* 3 byte receive [TX] | [RX] */ 79 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */ 80 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */ 81 /* ICIC: -DTE | +DTE */ 82 /* ICCR: 0x94 0x81 | 0xc0 */ 83 /* ICDR: A8 | D8(1) D8(2) D8(3) */ 84 /* */ 85 /* 4 bytes or more, this part is repeated +---------+ */ 86 /* */ 87 /* */ 88 /* Interrupt order and BUSY flag */ 89 /* ___ _ */ 90 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */ 91 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */ 92 /* */ 93 /* S D7 D6 D5 D4 D3 D2 D1 D0 P */ 94 /* ___ */ 95 /* WAIT IRQ ________________________________/ \___________ */ 96 /* TACK IRQ ____________________________________/ \_______ */ 97 /* DTE IRQ __________________________________________/ \_ */ 98 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 99 /* _______________________________________________ */ 100 /* BUSY __/ \_ */ 101 /* */ 102 103 enum sh_mobile_i2c_op { 104 OP_START = 0, 105 OP_TX_FIRST, 106 OP_TX, 107 OP_TX_STOP, 108 OP_TX_TO_RX, 109 OP_RX, 110 OP_RX_STOP, 111 OP_RX_STOP_DATA, 112 }; 113 114 struct sh_mobile_i2c_data { 115 struct device *dev; 116 void __iomem *reg; 117 struct i2c_adapter adap; 118 119 struct clk *clk; 120 u_int8_t iccl; 121 u_int8_t icch; 122 123 spinlock_t lock; 124 wait_queue_head_t wait; 125 struct i2c_msg *msg; 126 int pos; 127 int sr; 128 }; 129 130 #define NORMAL_SPEED 100000 /* FAST_SPEED 400000 */ 131 132 /* Register offsets */ 133 #define ICDR(pd) (pd->reg + 0x00) 134 #define ICCR(pd) (pd->reg + 0x04) 135 #define ICSR(pd) (pd->reg + 0x08) 136 #define ICIC(pd) (pd->reg + 0x0c) 137 #define ICCL(pd) (pd->reg + 0x10) 138 #define ICCH(pd) (pd->reg + 0x14) 139 140 /* Register bits */ 141 #define ICCR_ICE 0x80 142 #define ICCR_RACK 0x40 143 #define ICCR_TRS 0x10 144 #define ICCR_BBSY 0x04 145 #define ICCR_SCP 0x01 146 147 #define ICSR_SCLM 0x80 148 #define ICSR_SDAM 0x40 149 #define SW_DONE 0x20 150 #define ICSR_BUSY 0x10 151 #define ICSR_AL 0x08 152 #define ICSR_TACK 0x04 153 #define ICSR_WAIT 0x02 154 #define ICSR_DTE 0x01 155 156 #define ICIC_ALE 0x08 157 #define ICIC_TACKE 0x04 158 #define ICIC_WAITE 0x02 159 #define ICIC_DTEE 0x01 160 161 static void activate_ch(struct sh_mobile_i2c_data *pd) 162 { 163 /* Make sure the clock is enabled */ 164 clk_enable(pd->clk); 165 166 /* Enable channel and configure rx ack */ 167 iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd)); 168 169 /* Mask all interrupts */ 170 iowrite8(0, ICIC(pd)); 171 172 /* Set the clock */ 173 iowrite8(pd->iccl, ICCL(pd)); 174 iowrite8(pd->icch, ICCH(pd)); 175 } 176 177 static void deactivate_ch(struct sh_mobile_i2c_data *pd) 178 { 179 /* Clear/disable interrupts */ 180 iowrite8(0, ICSR(pd)); 181 iowrite8(0, ICIC(pd)); 182 183 /* Disable channel */ 184 iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd)); 185 186 /* Disable clock */ 187 clk_disable(pd->clk); 188 } 189 190 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, 191 enum sh_mobile_i2c_op op, unsigned char data) 192 { 193 unsigned char ret = 0; 194 unsigned long flags; 195 196 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data); 197 198 spin_lock_irqsave(&pd->lock, flags); 199 200 switch (op) { 201 case OP_START: /* issue start and trigger DTE interrupt */ 202 iowrite8(0x94, ICCR(pd)); 203 break; 204 case OP_TX_FIRST: /* disable DTE interrupt and write data */ 205 iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE, ICIC(pd)); 206 iowrite8(data, ICDR(pd)); 207 break; 208 case OP_TX: /* write data */ 209 iowrite8(data, ICDR(pd)); 210 break; 211 case OP_TX_STOP: /* write data and issue a stop afterwards */ 212 iowrite8(data, ICDR(pd)); 213 iowrite8(0x90, ICCR(pd)); 214 break; 215 case OP_TX_TO_RX: /* select read mode */ 216 iowrite8(0x81, ICCR(pd)); 217 break; 218 case OP_RX: /* just read data */ 219 ret = ioread8(ICDR(pd)); 220 break; 221 case OP_RX_STOP: /* enable DTE interrupt, issue stop */ 222 iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE, 223 ICIC(pd)); 224 iowrite8(0xc0, ICCR(pd)); 225 break; 226 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ 227 iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE, 228 ICIC(pd)); 229 ret = ioread8(ICDR(pd)); 230 iowrite8(0xc0, ICCR(pd)); 231 break; 232 } 233 234 spin_unlock_irqrestore(&pd->lock, flags); 235 236 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret); 237 return ret; 238 } 239 240 static int sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd) 241 { 242 if (pd->pos == -1) 243 return 1; 244 245 return 0; 246 } 247 248 static int sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd) 249 { 250 if (pd->pos == (pd->msg->len - 1)) 251 return 1; 252 253 return 0; 254 } 255 256 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd, 257 unsigned char *buf) 258 { 259 switch (pd->pos) { 260 case -1: 261 *buf = (pd->msg->addr & 0x7f) << 1; 262 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0; 263 break; 264 default: 265 *buf = pd->msg->buf[pd->pos]; 266 } 267 } 268 269 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd) 270 { 271 unsigned char data; 272 273 if (pd->pos == pd->msg->len) 274 return 1; 275 276 sh_mobile_i2c_get_data(pd, &data); 277 278 if (sh_mobile_i2c_is_last_byte(pd)) 279 i2c_op(pd, OP_TX_STOP, data); 280 else if (sh_mobile_i2c_is_first_byte(pd)) 281 i2c_op(pd, OP_TX_FIRST, data); 282 else 283 i2c_op(pd, OP_TX, data); 284 285 pd->pos++; 286 return 0; 287 } 288 289 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd) 290 { 291 unsigned char data; 292 int real_pos; 293 294 do { 295 if (pd->pos <= -1) { 296 sh_mobile_i2c_get_data(pd, &data); 297 298 if (sh_mobile_i2c_is_first_byte(pd)) 299 i2c_op(pd, OP_TX_FIRST, data); 300 else 301 i2c_op(pd, OP_TX, data); 302 break; 303 } 304 305 if (pd->pos == 0) { 306 i2c_op(pd, OP_TX_TO_RX, 0); 307 break; 308 } 309 310 real_pos = pd->pos - 2; 311 312 if (pd->pos == pd->msg->len) { 313 if (real_pos < 0) { 314 i2c_op(pd, OP_RX_STOP, 0); 315 break; 316 } 317 data = i2c_op(pd, OP_RX_STOP_DATA, 0); 318 } else 319 data = i2c_op(pd, OP_RX, 0); 320 321 pd->msg->buf[real_pos] = data; 322 } while (0); 323 324 pd->pos++; 325 return pd->pos == (pd->msg->len + 2); 326 } 327 328 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) 329 { 330 struct platform_device *dev = dev_id; 331 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 332 unsigned char sr; 333 int wakeup; 334 335 sr = ioread8(ICSR(pd)); 336 pd->sr |= sr; /* remember state */ 337 338 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, 339 (pd->msg->flags & I2C_M_RD) ? "read" : "write", 340 pd->pos, pd->msg->len); 341 342 if (sr & (ICSR_AL | ICSR_TACK)) { 343 /* don't interrupt transaction - continue to issue stop */ 344 iowrite8(sr & ~(ICSR_AL | ICSR_TACK), ICSR(pd)); 345 wakeup = 0; 346 } else if (pd->msg->flags & I2C_M_RD) 347 wakeup = sh_mobile_i2c_isr_rx(pd); 348 else 349 wakeup = sh_mobile_i2c_isr_tx(pd); 350 351 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ 352 iowrite8(sr & ~ICSR_WAIT, ICSR(pd)); 353 354 if (wakeup) { 355 pd->sr |= SW_DONE; 356 wake_up(&pd->wait); 357 } 358 359 return IRQ_HANDLED; 360 } 361 362 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg) 363 { 364 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) { 365 dev_err(pd->dev, "Unsupported zero length i2c read\n"); 366 return -EIO; 367 } 368 369 /* Initialize channel registers */ 370 iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd)); 371 372 /* Enable channel and configure rx ack */ 373 iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd)); 374 375 /* Set the clock */ 376 iowrite8(pd->iccl, ICCL(pd)); 377 iowrite8(pd->icch, ICCH(pd)); 378 379 pd->msg = usr_msg; 380 pd->pos = -1; 381 pd->sr = 0; 382 383 /* Enable all interrupts to begin with */ 384 iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE | ICIC_DTEE, ICIC(pd)); 385 return 0; 386 } 387 388 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter, 389 struct i2c_msg *msgs, 390 int num) 391 { 392 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); 393 struct i2c_msg *msg; 394 int err = 0; 395 u_int8_t val; 396 int i, k, retry_count; 397 398 activate_ch(pd); 399 400 /* Process all messages */ 401 for (i = 0; i < num; i++) { 402 msg = &msgs[i]; 403 404 err = start_ch(pd, msg); 405 if (err) 406 break; 407 408 i2c_op(pd, OP_START, 0); 409 410 /* The interrupt handler takes care of the rest... */ 411 k = wait_event_timeout(pd->wait, 412 pd->sr & (ICSR_TACK | SW_DONE), 413 5 * HZ); 414 if (!k) 415 dev_err(pd->dev, "Transfer request timed out\n"); 416 417 retry_count = 1000; 418 again: 419 val = ioread8(ICSR(pd)); 420 421 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); 422 423 /* the interrupt handler may wake us up before the 424 * transfer is finished, so poll the hardware 425 * until we're done. 426 */ 427 if (val & ICSR_BUSY) { 428 udelay(10); 429 if (retry_count--) 430 goto again; 431 432 err = -EIO; 433 dev_err(pd->dev, "Polling timed out\n"); 434 break; 435 } 436 437 /* handle missing acknowledge and arbitration lost */ 438 if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) { 439 err = -EIO; 440 break; 441 } 442 } 443 444 deactivate_ch(pd); 445 446 if (!err) 447 err = num; 448 return err; 449 } 450 451 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter) 452 { 453 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 454 } 455 456 static struct i2c_algorithm sh_mobile_i2c_algorithm = { 457 .functionality = sh_mobile_i2c_func, 458 .master_xfer = sh_mobile_i2c_xfer, 459 }; 460 461 static void sh_mobile_i2c_setup_channel(struct platform_device *dev) 462 { 463 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 464 unsigned long peripheral_clk = clk_get_rate(pd->clk); 465 u_int32_t num; 466 u_int32_t denom; 467 u_int32_t tmp; 468 469 spin_lock_init(&pd->lock); 470 init_waitqueue_head(&pd->wait); 471 472 /* Calculate the value for iccl. From the data sheet: 473 * iccl = (p clock / transfer rate) * (L / (L + H)) 474 * where L and H are the SCL low/high ratio (5/4 in this case). 475 * We also round off the result. 476 */ 477 num = peripheral_clk * 5; 478 denom = NORMAL_SPEED * 9; 479 tmp = num * 10 / denom; 480 if (tmp % 10 >= 5) 481 pd->iccl = (u_int8_t)((num/denom) + 1); 482 else 483 pd->iccl = (u_int8_t)(num/denom); 484 485 /* Calculate the value for icch. From the data sheet: 486 icch = (p clock / transfer rate) * (H / (L + H)) */ 487 num = peripheral_clk * 4; 488 tmp = num * 10 / denom; 489 if (tmp % 10 >= 5) 490 pd->icch = (u_int8_t)((num/denom) + 1); 491 else 492 pd->icch = (u_int8_t)(num/denom); 493 } 494 495 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook) 496 { 497 struct resource *res; 498 int ret = -ENXIO; 499 int q, m; 500 int k = 0; 501 int n = 0; 502 503 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) { 504 for (n = res->start; hook && n <= res->end; n++) { 505 if (request_irq(n, sh_mobile_i2c_isr, IRQF_DISABLED, 506 dev->dev.bus_id, dev)) 507 goto rollback; 508 } 509 k++; 510 } 511 512 if (hook) 513 return k > 0 ? 0 : -ENOENT; 514 515 k--; 516 ret = 0; 517 518 rollback: 519 for (q = k; k >= 0; k--) { 520 for (m = n; m >= res->start; m--) 521 free_irq(m, dev); 522 523 res = platform_get_resource(dev, IORESOURCE_IRQ, k - 1); 524 m = res->end; 525 } 526 527 return ret; 528 } 529 530 static int sh_mobile_i2c_probe(struct platform_device *dev) 531 { 532 struct sh_mobile_i2c_data *pd; 533 struct i2c_adapter *adap; 534 struct resource *res; 535 int size; 536 int ret; 537 538 pd = kzalloc(sizeof(struct sh_mobile_i2c_data), GFP_KERNEL); 539 if (pd == NULL) { 540 dev_err(&dev->dev, "cannot allocate private data\n"); 541 return -ENOMEM; 542 } 543 544 pd->clk = clk_get(&dev->dev, "peripheral_clk"); 545 if (IS_ERR(pd->clk)) { 546 dev_err(&dev->dev, "cannot get peripheral clock\n"); 547 ret = PTR_ERR(pd->clk); 548 goto err; 549 } 550 551 ret = sh_mobile_i2c_hook_irqs(dev, 1); 552 if (ret) { 553 dev_err(&dev->dev, "cannot request IRQ\n"); 554 goto err_clk; 555 } 556 557 pd->dev = &dev->dev; 558 platform_set_drvdata(dev, pd); 559 560 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 561 if (res == NULL) { 562 dev_err(&dev->dev, "cannot find IO resource\n"); 563 ret = -ENOENT; 564 goto err_irq; 565 } 566 567 size = (res->end - res->start) + 1; 568 569 pd->reg = ioremap(res->start, size); 570 if (pd->reg == NULL) { 571 dev_err(&dev->dev, "cannot map IO\n"); 572 ret = -ENXIO; 573 goto err_irq; 574 } 575 576 /* setup the private data */ 577 adap = &pd->adap; 578 i2c_set_adapdata(adap, pd); 579 580 adap->owner = THIS_MODULE; 581 adap->algo = &sh_mobile_i2c_algorithm; 582 adap->dev.parent = &dev->dev; 583 adap->retries = 5; 584 adap->nr = dev->id; 585 586 strlcpy(adap->name, dev->name, sizeof(adap->name)); 587 588 sh_mobile_i2c_setup_channel(dev); 589 590 ret = i2c_add_numbered_adapter(adap); 591 if (ret < 0) { 592 dev_err(&dev->dev, "cannot add numbered adapter\n"); 593 goto err_all; 594 } 595 596 return 0; 597 598 err_all: 599 iounmap(pd->reg); 600 err_irq: 601 sh_mobile_i2c_hook_irqs(dev, 0); 602 err_clk: 603 clk_put(pd->clk); 604 err: 605 kfree(pd); 606 return ret; 607 } 608 609 static int sh_mobile_i2c_remove(struct platform_device *dev) 610 { 611 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 612 613 i2c_del_adapter(&pd->adap); 614 iounmap(pd->reg); 615 sh_mobile_i2c_hook_irqs(dev, 0); 616 clk_put(pd->clk); 617 kfree(pd); 618 return 0; 619 } 620 621 static struct platform_driver sh_mobile_i2c_driver = { 622 .driver = { 623 .name = "i2c-sh_mobile", 624 .owner = THIS_MODULE, 625 }, 626 .probe = sh_mobile_i2c_probe, 627 .remove = sh_mobile_i2c_remove, 628 }; 629 630 static int __init sh_mobile_i2c_adap_init(void) 631 { 632 return platform_driver_register(&sh_mobile_i2c_driver); 633 } 634 635 static void __exit sh_mobile_i2c_adap_exit(void) 636 { 637 platform_driver_unregister(&sh_mobile_i2c_driver); 638 } 639 640 module_init(sh_mobile_i2c_adap_init); 641 module_exit(sh_mobile_i2c_adap_exit); 642 643 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver"); 644 MODULE_AUTHOR("Magnus Damm"); 645 MODULE_LICENSE("GPL v2"); 646