1 /* 2 * I2C bus driver for the SH7760 I2C Interfaces. 3 * 4 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 5 * 6 * licensed under the terms outlined in the file COPYING. 7 * 8 */ 9 10 #include <linux/completion.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/i2c.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/ioport.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/io.h> 20 #include <linux/module.h> 21 22 #include <asm/clock.h> 23 #include <asm/i2c-sh7760.h> 24 25 /* register offsets */ 26 #define I2CSCR 0x0 /* slave ctrl */ 27 #define I2CMCR 0x4 /* master ctrl */ 28 #define I2CSSR 0x8 /* slave status */ 29 #define I2CMSR 0xC /* master status */ 30 #define I2CSIER 0x10 /* slave irq enable */ 31 #define I2CMIER 0x14 /* master irq enable */ 32 #define I2CCCR 0x18 /* clock dividers */ 33 #define I2CSAR 0x1c /* slave address */ 34 #define I2CMAR 0x20 /* master address */ 35 #define I2CRXTX 0x24 /* data port */ 36 #define I2CFCR 0x28 /* fifo control */ 37 #define I2CFSR 0x2C /* fifo status */ 38 #define I2CFIER 0x30 /* fifo irq enable */ 39 #define I2CRFDR 0x34 /* rx fifo count */ 40 #define I2CTFDR 0x38 /* tx fifo count */ 41 42 #define REGSIZE 0x3C 43 44 #define MCR_MDBS 0x80 /* non-fifo mode switch */ 45 #define MCR_FSCL 0x40 /* override SCL pin */ 46 #define MCR_FSDA 0x20 /* override SDA pin */ 47 #define MCR_OBPC 0x10 /* override pins */ 48 #define MCR_MIE 0x08 /* master if enable */ 49 #define MCR_TSBE 0x04 50 #define MCR_FSB 0x02 /* force stop bit */ 51 #define MCR_ESG 0x01 /* en startbit gen. */ 52 53 #define MSR_MNR 0x40 /* nack received */ 54 #define MSR_MAL 0x20 /* arbitration lost */ 55 #define MSR_MST 0x10 /* sent a stop */ 56 #define MSR_MDE 0x08 57 #define MSR_MDT 0x04 58 #define MSR_MDR 0x02 59 #define MSR_MAT 0x01 /* slave addr xfer done */ 60 61 #define MIE_MNRE 0x40 /* nack irq en */ 62 #define MIE_MALE 0x20 /* arblos irq en */ 63 #define MIE_MSTE 0x10 /* stop irq en */ 64 #define MIE_MDEE 0x08 65 #define MIE_MDTE 0x04 66 #define MIE_MDRE 0x02 67 #define MIE_MATE 0x01 /* address sent irq en */ 68 69 #define FCR_RFRST 0x02 /* reset rx fifo */ 70 #define FCR_TFRST 0x01 /* reset tx fifo */ 71 72 #define FSR_TEND 0x04 /* last byte sent */ 73 #define FSR_RDF 0x02 /* rx fifo trigger */ 74 #define FSR_TDFE 0x01 /* tx fifo empty */ 75 76 #define FIER_TEIE 0x04 /* tx fifo empty irq en */ 77 #define FIER_RXIE 0x02 /* rx fifo trig irq en */ 78 #define FIER_TXIE 0x01 /* tx fifo trig irq en */ 79 80 #define FIFO_SIZE 16 81 82 struct cami2c { 83 void __iomem *iobase; 84 struct i2c_adapter adap; 85 86 /* message processing */ 87 struct i2c_msg *msg; 88 #define IDF_SEND 1 89 #define IDF_RECV 2 90 #define IDF_STOP 4 91 int flags; 92 93 #define IDS_DONE 1 94 #define IDS_ARBLOST 2 95 #define IDS_NACK 4 96 int status; 97 struct completion xfer_done; 98 99 int irq; 100 struct resource *ioarea; 101 }; 102 103 static inline void OUT32(struct cami2c *cam, int reg, unsigned long val) 104 { 105 __raw_writel(val, (unsigned long)cam->iobase + reg); 106 } 107 108 static inline unsigned long IN32(struct cami2c *cam, int reg) 109 { 110 return __raw_readl((unsigned long)cam->iobase + reg); 111 } 112 113 static irqreturn_t sh7760_i2c_irq(int irq, void *ptr) 114 { 115 struct cami2c *id = ptr; 116 struct i2c_msg *msg = id->msg; 117 char *data = msg->buf; 118 unsigned long msr, fsr, fier, len; 119 120 msr = IN32(id, I2CMSR); 121 fsr = IN32(id, I2CFSR); 122 123 /* arbitration lost */ 124 if (msr & MSR_MAL) { 125 OUT32(id, I2CMCR, 0); 126 OUT32(id, I2CSCR, 0); 127 OUT32(id, I2CSAR, 0); 128 id->status |= IDS_DONE | IDS_ARBLOST; 129 goto out; 130 } 131 132 if (msr & MSR_MNR) { 133 /* NACK handling is very screwed up. After receiving a 134 * NAK IRQ one has to wait a bit before writing to any 135 * registers, or the ctl will lock up. After that delay 136 * do a normal i2c stop. Then wait at least 1 ms before 137 * attempting another transfer or ctl will stop working 138 */ 139 udelay(100); /* wait or risk ctl hang */ 140 OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST); 141 OUT32(id, I2CMCR, MCR_MIE | MCR_FSB); 142 OUT32(id, I2CFIER, 0); 143 OUT32(id, I2CMIER, MIE_MSTE); 144 OUT32(id, I2CSCR, 0); 145 OUT32(id, I2CSAR, 0); 146 id->status |= IDS_NACK; 147 msr &= ~MSR_MAT; 148 fsr = 0; 149 /* In some cases the MST bit is also set. */ 150 } 151 152 /* i2c-stop was sent */ 153 if (msr & MSR_MST) { 154 id->status |= IDS_DONE; 155 goto out; 156 } 157 158 /* i2c slave addr was sent; set to "normal" operation */ 159 if (msr & MSR_MAT) 160 OUT32(id, I2CMCR, MCR_MIE); 161 162 fier = IN32(id, I2CFIER); 163 164 if (fsr & FSR_RDF) { 165 len = IN32(id, I2CRFDR); 166 if (msg->len <= len) { 167 if (id->flags & IDF_STOP) { 168 OUT32(id, I2CMCR, MCR_MIE | MCR_FSB); 169 OUT32(id, I2CFIER, 0); 170 /* manual says: wait >= 0.5 SCL times */ 171 udelay(5); 172 /* next int should be MST */ 173 } else { 174 id->status |= IDS_DONE; 175 /* keep the RDF bit: ctrl holds SCL low 176 * until the setup for the next i2c_msg 177 * clears this bit. 178 */ 179 fsr &= ~FSR_RDF; 180 } 181 } 182 while (msg->len && len) { 183 *data++ = IN32(id, I2CRXTX); 184 msg->len--; 185 len--; 186 } 187 188 if (msg->len) { 189 len = (msg->len >= FIFO_SIZE) ? FIFO_SIZE - 1 190 : msg->len - 1; 191 192 OUT32(id, I2CFCR, FCR_TFRST | ((len & 0xf) << 4)); 193 } 194 195 } else if (id->flags & IDF_SEND) { 196 if ((fsr & FSR_TEND) && (msg->len < 1)) { 197 if (id->flags & IDF_STOP) { 198 OUT32(id, I2CMCR, MCR_MIE | MCR_FSB); 199 } else { 200 id->status |= IDS_DONE; 201 /* keep the TEND bit: ctl holds SCL low 202 * until the setup for the next i2c_msg 203 * clears this bit. 204 */ 205 fsr &= ~FSR_TEND; 206 } 207 } 208 if (fsr & FSR_TDFE) { 209 while (msg->len && (IN32(id, I2CTFDR) < FIFO_SIZE)) { 210 OUT32(id, I2CRXTX, *data++); 211 msg->len--; 212 } 213 214 if (msg->len < 1) { 215 fier &= ~FIER_TXIE; 216 OUT32(id, I2CFIER, fier); 217 } else { 218 len = (msg->len >= FIFO_SIZE) ? 2 : 0; 219 OUT32(id, I2CFCR, 220 FCR_RFRST | ((len & 3) << 2)); 221 } 222 } 223 } 224 out: 225 if (id->status & IDS_DONE) { 226 OUT32(id, I2CMIER, 0); 227 OUT32(id, I2CFIER, 0); 228 id->msg = NULL; 229 complete(&id->xfer_done); 230 } 231 /* clear status flags and ctrl resumes work */ 232 OUT32(id, I2CMSR, ~msr); 233 OUT32(id, I2CFSR, ~fsr); 234 OUT32(id, I2CSSR, 0); 235 236 return IRQ_HANDLED; 237 } 238 239 240 /* prepare and start a master receive operation */ 241 static void sh7760_i2c_mrecv(struct cami2c *id) 242 { 243 int len; 244 245 id->flags |= IDF_RECV; 246 247 /* set the slave addr reg; otherwise rcv wont work! */ 248 OUT32(id, I2CSAR, 0xfe); 249 OUT32(id, I2CMAR, (id->msg->addr << 1) | 1); 250 251 /* adjust rx fifo trigger */ 252 if (id->msg->len >= FIFO_SIZE) 253 len = FIFO_SIZE - 1; /* trigger at fifo full */ 254 else 255 len = id->msg->len - 1; /* trigger before all received */ 256 257 OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST); 258 OUT32(id, I2CFCR, FCR_TFRST | ((len & 0xF) << 4)); 259 260 OUT32(id, I2CMSR, 0); 261 OUT32(id, I2CMCR, MCR_MIE | MCR_ESG); 262 OUT32(id, I2CMIER, MIE_MNRE | MIE_MALE | MIE_MSTE | MIE_MATE); 263 OUT32(id, I2CFIER, FIER_RXIE); 264 } 265 266 /* prepare and start a master send operation */ 267 static void sh7760_i2c_msend(struct cami2c *id) 268 { 269 int len; 270 271 id->flags |= IDF_SEND; 272 273 /* set the slave addr reg; otherwise xmit wont work! */ 274 OUT32(id, I2CSAR, 0xfe); 275 OUT32(id, I2CMAR, (id->msg->addr << 1) | 0); 276 277 /* adjust tx fifo trigger */ 278 if (id->msg->len >= FIFO_SIZE) 279 len = 2; /* trig: 2 bytes left in TX fifo */ 280 else 281 len = 0; /* trig: 8 bytes left in TX fifo */ 282 283 OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST); 284 OUT32(id, I2CFCR, FCR_RFRST | ((len & 3) << 2)); 285 286 while (id->msg->len && IN32(id, I2CTFDR) < FIFO_SIZE) { 287 OUT32(id, I2CRXTX, *(id->msg->buf)); 288 (id->msg->len)--; 289 (id->msg->buf)++; 290 } 291 292 OUT32(id, I2CMSR, 0); 293 OUT32(id, I2CMCR, MCR_MIE | MCR_ESG); 294 OUT32(id, I2CFSR, 0); 295 OUT32(id, I2CMIER, MIE_MNRE | MIE_MALE | MIE_MSTE | MIE_MATE); 296 OUT32(id, I2CFIER, FIER_TEIE | (id->msg->len ? FIER_TXIE : 0)); 297 } 298 299 static inline int sh7760_i2c_busy_check(struct cami2c *id) 300 { 301 return (IN32(id, I2CMCR) & MCR_FSDA); 302 } 303 304 static int sh7760_i2c_master_xfer(struct i2c_adapter *adap, 305 struct i2c_msg *msgs, 306 int num) 307 { 308 struct cami2c *id = adap->algo_data; 309 int i, retr; 310 311 if (sh7760_i2c_busy_check(id)) { 312 dev_err(&adap->dev, "sh7760-i2c%d: bus busy!\n", adap->nr); 313 return -EBUSY; 314 } 315 316 i = 0; 317 while (i < num) { 318 retr = adap->retries; 319 retry: 320 id->flags = ((i == (num-1)) ? IDF_STOP : 0); 321 id->status = 0; 322 id->msg = msgs; 323 init_completion(&id->xfer_done); 324 325 if (msgs->flags & I2C_M_RD) 326 sh7760_i2c_mrecv(id); 327 else 328 sh7760_i2c_msend(id); 329 330 wait_for_completion(&id->xfer_done); 331 332 if (id->status == 0) { 333 num = -EIO; 334 break; 335 } 336 337 if (id->status & IDS_NACK) { 338 /* wait a bit or i2c module stops working */ 339 mdelay(1); 340 num = -EREMOTEIO; 341 break; 342 } 343 344 if (id->status & IDS_ARBLOST) { 345 if (retr--) { 346 mdelay(2); 347 goto retry; 348 } 349 num = -EREMOTEIO; 350 break; 351 } 352 353 msgs++; 354 i++; 355 } 356 357 id->msg = NULL; 358 id->flags = 0; 359 id->status = 0; 360 361 OUT32(id, I2CMCR, 0); 362 OUT32(id, I2CMSR, 0); 363 OUT32(id, I2CMIER, 0); 364 OUT32(id, I2CFIER, 0); 365 366 /* reset slave module registers too: master mode enables slave 367 * module for receive ops (ack, data). Without this reset, 368 * eternal bus activity might be reported after NACK / ARBLOST. 369 */ 370 OUT32(id, I2CSCR, 0); 371 OUT32(id, I2CSAR, 0); 372 OUT32(id, I2CSSR, 0); 373 374 return num; 375 } 376 377 static u32 sh7760_i2c_func(struct i2c_adapter *adap) 378 { 379 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 380 } 381 382 static const struct i2c_algorithm sh7760_i2c_algo = { 383 .master_xfer = sh7760_i2c_master_xfer, 384 .functionality = sh7760_i2c_func, 385 }; 386 387 /* calculate CCR register setting for a desired scl clock. SCL clock is 388 * derived from I2C module clock (iclk) which in turn is derived from 389 * peripheral module clock (mclk, usually around 33MHz): 390 * iclk = mclk/(CDF + 1). iclk must be < 20MHz. 391 * scl = iclk/(SCGD*8 + 20). 392 */ 393 static int calc_CCR(unsigned long scl_hz) 394 { 395 struct clk *mclk; 396 unsigned long mck, m1, dff, odff, iclk; 397 signed char cdf, cdfm; 398 int scgd, scgdm, scgds; 399 400 mclk = clk_get(NULL, "peripheral_clk"); 401 if (IS_ERR(mclk)) { 402 return PTR_ERR(mclk); 403 } else { 404 mck = mclk->rate; 405 clk_put(mclk); 406 } 407 408 odff = scl_hz; 409 scgdm = cdfm = m1 = 0; 410 for (cdf = 3; cdf >= 0; cdf--) { 411 iclk = mck / (1 + cdf); 412 if (iclk >= 20000000) 413 continue; 414 scgds = ((iclk / scl_hz) - 20) >> 3; 415 for (scgd = scgds; (scgd < 63) && scgd <= scgds + 1; scgd++) { 416 m1 = iclk / (20 + (scgd << 3)); 417 dff = abs(scl_hz - m1); 418 if (dff < odff) { 419 odff = dff; 420 cdfm = cdf; 421 scgdm = scgd; 422 } 423 } 424 } 425 /* fail if more than 25% off of requested SCL */ 426 if (odff > (scl_hz >> 2)) 427 return -EINVAL; 428 429 /* create a CCR register value */ 430 return ((scgdm << 2) | cdfm); 431 } 432 433 static int sh7760_i2c_probe(struct platform_device *pdev) 434 { 435 struct sh7760_i2c_platdata *pd; 436 struct resource *res; 437 struct cami2c *id; 438 int ret; 439 440 pd = dev_get_platdata(&pdev->dev); 441 if (!pd) { 442 dev_err(&pdev->dev, "no platform_data!\n"); 443 ret = -ENODEV; 444 goto out0; 445 } 446 447 id = kzalloc(sizeof(struct cami2c), GFP_KERNEL); 448 if (!id) { 449 dev_err(&pdev->dev, "no mem for private data\n"); 450 ret = -ENOMEM; 451 goto out0; 452 } 453 454 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 455 if (!res) { 456 dev_err(&pdev->dev, "no mmio resources\n"); 457 ret = -ENODEV; 458 goto out1; 459 } 460 461 id->ioarea = request_mem_region(res->start, REGSIZE, pdev->name); 462 if (!id->ioarea) { 463 dev_err(&pdev->dev, "mmio already reserved\n"); 464 ret = -EBUSY; 465 goto out1; 466 } 467 468 id->iobase = ioremap(res->start, REGSIZE); 469 if (!id->iobase) { 470 dev_err(&pdev->dev, "cannot ioremap\n"); 471 ret = -ENODEV; 472 goto out2; 473 } 474 475 id->irq = platform_get_irq(pdev, 0); 476 477 id->adap.nr = pdev->id; 478 id->adap.algo = &sh7760_i2c_algo; 479 id->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 480 id->adap.retries = 3; 481 id->adap.algo_data = id; 482 id->adap.dev.parent = &pdev->dev; 483 snprintf(id->adap.name, sizeof(id->adap.name), 484 "SH7760 I2C at %08lx", (unsigned long)res->start); 485 486 OUT32(id, I2CMCR, 0); 487 OUT32(id, I2CMSR, 0); 488 OUT32(id, I2CMIER, 0); 489 OUT32(id, I2CMAR, 0); 490 OUT32(id, I2CSIER, 0); 491 OUT32(id, I2CSAR, 0); 492 OUT32(id, I2CSCR, 0); 493 OUT32(id, I2CSSR, 0); 494 OUT32(id, I2CFIER, 0); 495 OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST); 496 OUT32(id, I2CFSR, 0); 497 498 ret = calc_CCR(pd->speed_khz * 1000); 499 if (ret < 0) { 500 dev_err(&pdev->dev, "invalid SCL clock: %dkHz\n", 501 pd->speed_khz); 502 goto out3; 503 } 504 OUT32(id, I2CCCR, ret); 505 506 if (request_irq(id->irq, sh7760_i2c_irq, 0, 507 SH7760_I2C_DEVNAME, id)) { 508 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq); 509 ret = -EBUSY; 510 goto out3; 511 } 512 513 ret = i2c_add_numbered_adapter(&id->adap); 514 if (ret < 0) { 515 dev_err(&pdev->dev, "reg adap failed: %d\n", ret); 516 goto out4; 517 } 518 519 platform_set_drvdata(pdev, id); 520 521 dev_info(&pdev->dev, "%d kHz mmio %08x irq %d\n", 522 pd->speed_khz, res->start, id->irq); 523 524 return 0; 525 526 out4: 527 free_irq(id->irq, id); 528 out3: 529 iounmap(id->iobase); 530 out2: 531 release_resource(id->ioarea); 532 kfree(id->ioarea); 533 out1: 534 kfree(id); 535 out0: 536 return ret; 537 } 538 539 static int sh7760_i2c_remove(struct platform_device *pdev) 540 { 541 struct cami2c *id = platform_get_drvdata(pdev); 542 543 i2c_del_adapter(&id->adap); 544 free_irq(id->irq, id); 545 iounmap(id->iobase); 546 release_resource(id->ioarea); 547 kfree(id->ioarea); 548 kfree(id); 549 550 return 0; 551 } 552 553 static struct platform_driver sh7760_i2c_drv = { 554 .driver = { 555 .name = SH7760_I2C_DEVNAME, 556 .owner = THIS_MODULE, 557 }, 558 .probe = sh7760_i2c_probe, 559 .remove = sh7760_i2c_remove, 560 }; 561 562 module_platform_driver(sh7760_i2c_drv); 563 564 MODULE_LICENSE("GPL"); 565 MODULE_DESCRIPTION("SH7760 I2C bus driver"); 566 MODULE_AUTHOR("Manuel Lauss <mano@roarinelk.homelinux.net>"); 567