1a26c20b1SManuel Lauss /*
2a26c20b1SManuel Lauss * I2C bus driver for the SH7760 I2C Interfaces.
3a26c20b1SManuel Lauss *
4a26c20b1SManuel Lauss * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
5a26c20b1SManuel Lauss *
6a26c20b1SManuel Lauss * licensed under the terms outlined in the file COPYING.
7a26c20b1SManuel Lauss *
8a26c20b1SManuel Lauss */
9a26c20b1SManuel Lauss
10a26c20b1SManuel Lauss #include <linux/completion.h>
11a26c20b1SManuel Lauss #include <linux/delay.h>
12a26c20b1SManuel Lauss #include <linux/err.h>
13a26c20b1SManuel Lauss #include <linux/i2c.h>
14a26c20b1SManuel Lauss #include <linux/interrupt.h>
15a26c20b1SManuel Lauss #include <linux/ioport.h>
16a26c20b1SManuel Lauss #include <linux/platform_device.h>
17a26c20b1SManuel Lauss #include <linux/slab.h>
1821782180SH Hartley Sweeten #include <linux/io.h>
1993cf5d75SPaul Gortmaker #include <linux/module.h>
20a26c20b1SManuel Lauss
21a26c20b1SManuel Lauss #include <asm/clock.h>
22a26c20b1SManuel Lauss #include <asm/i2c-sh7760.h>
23a26c20b1SManuel Lauss
24a26c20b1SManuel Lauss /* register offsets */
25a26c20b1SManuel Lauss #define I2CSCR 0x0 /* slave ctrl */
26a26c20b1SManuel Lauss #define I2CMCR 0x4 /* master ctrl */
27a26c20b1SManuel Lauss #define I2CSSR 0x8 /* slave status */
28a26c20b1SManuel Lauss #define I2CMSR 0xC /* master status */
29a26c20b1SManuel Lauss #define I2CSIER 0x10 /* slave irq enable */
30a26c20b1SManuel Lauss #define I2CMIER 0x14 /* master irq enable */
31a26c20b1SManuel Lauss #define I2CCCR 0x18 /* clock dividers */
32a26c20b1SManuel Lauss #define I2CSAR 0x1c /* slave address */
33a26c20b1SManuel Lauss #define I2CMAR 0x20 /* master address */
34a26c20b1SManuel Lauss #define I2CRXTX 0x24 /* data port */
35a26c20b1SManuel Lauss #define I2CFCR 0x28 /* fifo control */
36a26c20b1SManuel Lauss #define I2CFSR 0x2C /* fifo status */
37a26c20b1SManuel Lauss #define I2CFIER 0x30 /* fifo irq enable */
38a26c20b1SManuel Lauss #define I2CRFDR 0x34 /* rx fifo count */
39a26c20b1SManuel Lauss #define I2CTFDR 0x38 /* tx fifo count */
40a26c20b1SManuel Lauss
41a26c20b1SManuel Lauss #define REGSIZE 0x3C
42a26c20b1SManuel Lauss
43a26c20b1SManuel Lauss #define MCR_MDBS 0x80 /* non-fifo mode switch */
44a26c20b1SManuel Lauss #define MCR_FSCL 0x40 /* override SCL pin */
45a26c20b1SManuel Lauss #define MCR_FSDA 0x20 /* override SDA pin */
46a26c20b1SManuel Lauss #define MCR_OBPC 0x10 /* override pins */
47a26c20b1SManuel Lauss #define MCR_MIE 0x08 /* master if enable */
48a26c20b1SManuel Lauss #define MCR_TSBE 0x04
49a26c20b1SManuel Lauss #define MCR_FSB 0x02 /* force stop bit */
50a26c20b1SManuel Lauss #define MCR_ESG 0x01 /* en startbit gen. */
51a26c20b1SManuel Lauss
52a26c20b1SManuel Lauss #define MSR_MNR 0x40 /* nack received */
53a26c20b1SManuel Lauss #define MSR_MAL 0x20 /* arbitration lost */
54a26c20b1SManuel Lauss #define MSR_MST 0x10 /* sent a stop */
55a26c20b1SManuel Lauss #define MSR_MDE 0x08
56a26c20b1SManuel Lauss #define MSR_MDT 0x04
57a26c20b1SManuel Lauss #define MSR_MDR 0x02
58a26c20b1SManuel Lauss #define MSR_MAT 0x01 /* slave addr xfer done */
59a26c20b1SManuel Lauss
60a26c20b1SManuel Lauss #define MIE_MNRE 0x40 /* nack irq en */
61a26c20b1SManuel Lauss #define MIE_MALE 0x20 /* arblos irq en */
62a26c20b1SManuel Lauss #define MIE_MSTE 0x10 /* stop irq en */
63a26c20b1SManuel Lauss #define MIE_MDEE 0x08
64a26c20b1SManuel Lauss #define MIE_MDTE 0x04
65a26c20b1SManuel Lauss #define MIE_MDRE 0x02
66a26c20b1SManuel Lauss #define MIE_MATE 0x01 /* address sent irq en */
67a26c20b1SManuel Lauss
68a26c20b1SManuel Lauss #define FCR_RFRST 0x02 /* reset rx fifo */
69a26c20b1SManuel Lauss #define FCR_TFRST 0x01 /* reset tx fifo */
70a26c20b1SManuel Lauss
71a26c20b1SManuel Lauss #define FSR_TEND 0x04 /* last byte sent */
72a26c20b1SManuel Lauss #define FSR_RDF 0x02 /* rx fifo trigger */
73a26c20b1SManuel Lauss #define FSR_TDFE 0x01 /* tx fifo empty */
74a26c20b1SManuel Lauss
75a26c20b1SManuel Lauss #define FIER_TEIE 0x04 /* tx fifo empty irq en */
76a26c20b1SManuel Lauss #define FIER_RXIE 0x02 /* rx fifo trig irq en */
77a26c20b1SManuel Lauss #define FIER_TXIE 0x01 /* tx fifo trig irq en */
78a26c20b1SManuel Lauss
79a26c20b1SManuel Lauss #define FIFO_SIZE 16
80a26c20b1SManuel Lauss
81a26c20b1SManuel Lauss struct cami2c {
82a26c20b1SManuel Lauss void __iomem *iobase;
83a26c20b1SManuel Lauss struct i2c_adapter adap;
84a26c20b1SManuel Lauss
85a26c20b1SManuel Lauss /* message processing */
86a26c20b1SManuel Lauss struct i2c_msg *msg;
87a26c20b1SManuel Lauss #define IDF_SEND 1
88a26c20b1SManuel Lauss #define IDF_RECV 2
89a26c20b1SManuel Lauss #define IDF_STOP 4
90a26c20b1SManuel Lauss int flags;
91a26c20b1SManuel Lauss
92a26c20b1SManuel Lauss #define IDS_DONE 1
93a26c20b1SManuel Lauss #define IDS_ARBLOST 2
94a26c20b1SManuel Lauss #define IDS_NACK 4
95a26c20b1SManuel Lauss int status;
96a26c20b1SManuel Lauss struct completion xfer_done;
97a26c20b1SManuel Lauss
98a26c20b1SManuel Lauss int irq;
99a26c20b1SManuel Lauss struct resource *ioarea;
100a26c20b1SManuel Lauss };
101a26c20b1SManuel Lauss
OUT32(struct cami2c * cam,int reg,unsigned long val)102a26c20b1SManuel Lauss static inline void OUT32(struct cami2c *cam, int reg, unsigned long val)
103a26c20b1SManuel Lauss {
1048df39901SNobuhiro Iwamatsu __raw_writel(val, (unsigned long)cam->iobase + reg);
105a26c20b1SManuel Lauss }
106a26c20b1SManuel Lauss
IN32(struct cami2c * cam,int reg)107a26c20b1SManuel Lauss static inline unsigned long IN32(struct cami2c *cam, int reg)
108a26c20b1SManuel Lauss {
1098df39901SNobuhiro Iwamatsu return __raw_readl((unsigned long)cam->iobase + reg);
110a26c20b1SManuel Lauss }
111a26c20b1SManuel Lauss
sh7760_i2c_irq(int irq,void * ptr)112a26c20b1SManuel Lauss static irqreturn_t sh7760_i2c_irq(int irq, void *ptr)
113a26c20b1SManuel Lauss {
114a26c20b1SManuel Lauss struct cami2c *id = ptr;
115a26c20b1SManuel Lauss struct i2c_msg *msg = id->msg;
116a26c20b1SManuel Lauss char *data = msg->buf;
117a26c20b1SManuel Lauss unsigned long msr, fsr, fier, len;
118a26c20b1SManuel Lauss
119a26c20b1SManuel Lauss msr = IN32(id, I2CMSR);
120a26c20b1SManuel Lauss fsr = IN32(id, I2CFSR);
121a26c20b1SManuel Lauss
122a26c20b1SManuel Lauss /* arbitration lost */
123a26c20b1SManuel Lauss if (msr & MSR_MAL) {
124a26c20b1SManuel Lauss OUT32(id, I2CMCR, 0);
125a26c20b1SManuel Lauss OUT32(id, I2CSCR, 0);
126a26c20b1SManuel Lauss OUT32(id, I2CSAR, 0);
127a26c20b1SManuel Lauss id->status |= IDS_DONE | IDS_ARBLOST;
128a26c20b1SManuel Lauss goto out;
129a26c20b1SManuel Lauss }
130a26c20b1SManuel Lauss
131a26c20b1SManuel Lauss if (msr & MSR_MNR) {
132a26c20b1SManuel Lauss /* NACK handling is very screwed up. After receiving a
133a26c20b1SManuel Lauss * NAK IRQ one has to wait a bit before writing to any
134a26c20b1SManuel Lauss * registers, or the ctl will lock up. After that delay
135a26c20b1SManuel Lauss * do a normal i2c stop. Then wait at least 1 ms before
136a26c20b1SManuel Lauss * attempting another transfer or ctl will stop working
137a26c20b1SManuel Lauss */
138a26c20b1SManuel Lauss udelay(100); /* wait or risk ctl hang */
139a26c20b1SManuel Lauss OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
140a26c20b1SManuel Lauss OUT32(id, I2CMCR, MCR_MIE | MCR_FSB);
141a26c20b1SManuel Lauss OUT32(id, I2CFIER, 0);
142a26c20b1SManuel Lauss OUT32(id, I2CMIER, MIE_MSTE);
143a26c20b1SManuel Lauss OUT32(id, I2CSCR, 0);
144a26c20b1SManuel Lauss OUT32(id, I2CSAR, 0);
145a26c20b1SManuel Lauss id->status |= IDS_NACK;
146a26c20b1SManuel Lauss msr &= ~MSR_MAT;
147a26c20b1SManuel Lauss fsr = 0;
148a26c20b1SManuel Lauss /* In some cases the MST bit is also set. */
149a26c20b1SManuel Lauss }
150a26c20b1SManuel Lauss
151a26c20b1SManuel Lauss /* i2c-stop was sent */
152a26c20b1SManuel Lauss if (msr & MSR_MST) {
153a26c20b1SManuel Lauss id->status |= IDS_DONE;
154a26c20b1SManuel Lauss goto out;
155a26c20b1SManuel Lauss }
156a26c20b1SManuel Lauss
157a26c20b1SManuel Lauss /* i2c slave addr was sent; set to "normal" operation */
158a26c20b1SManuel Lauss if (msr & MSR_MAT)
159a26c20b1SManuel Lauss OUT32(id, I2CMCR, MCR_MIE);
160a26c20b1SManuel Lauss
161a26c20b1SManuel Lauss fier = IN32(id, I2CFIER);
162a26c20b1SManuel Lauss
163a26c20b1SManuel Lauss if (fsr & FSR_RDF) {
164a26c20b1SManuel Lauss len = IN32(id, I2CRFDR);
165a26c20b1SManuel Lauss if (msg->len <= len) {
166a26c20b1SManuel Lauss if (id->flags & IDF_STOP) {
167a26c20b1SManuel Lauss OUT32(id, I2CMCR, MCR_MIE | MCR_FSB);
168a26c20b1SManuel Lauss OUT32(id, I2CFIER, 0);
169a26c20b1SManuel Lauss /* manual says: wait >= 0.5 SCL times */
170a26c20b1SManuel Lauss udelay(5);
171a26c20b1SManuel Lauss /* next int should be MST */
172a26c20b1SManuel Lauss } else {
173a26c20b1SManuel Lauss id->status |= IDS_DONE;
174a26c20b1SManuel Lauss /* keep the RDF bit: ctrl holds SCL low
175a26c20b1SManuel Lauss * until the setup for the next i2c_msg
176a26c20b1SManuel Lauss * clears this bit.
177a26c20b1SManuel Lauss */
178a26c20b1SManuel Lauss fsr &= ~FSR_RDF;
179a26c20b1SManuel Lauss }
180a26c20b1SManuel Lauss }
181a26c20b1SManuel Lauss while (msg->len && len) {
182a26c20b1SManuel Lauss *data++ = IN32(id, I2CRXTX);
183a26c20b1SManuel Lauss msg->len--;
184a26c20b1SManuel Lauss len--;
185a26c20b1SManuel Lauss }
186a26c20b1SManuel Lauss
187a26c20b1SManuel Lauss if (msg->len) {
188a26c20b1SManuel Lauss len = (msg->len >= FIFO_SIZE) ? FIFO_SIZE - 1
189a26c20b1SManuel Lauss : msg->len - 1;
190a26c20b1SManuel Lauss
191a26c20b1SManuel Lauss OUT32(id, I2CFCR, FCR_TFRST | ((len & 0xf) << 4));
192a26c20b1SManuel Lauss }
193a26c20b1SManuel Lauss
194a26c20b1SManuel Lauss } else if (id->flags & IDF_SEND) {
195a26c20b1SManuel Lauss if ((fsr & FSR_TEND) && (msg->len < 1)) {
196a26c20b1SManuel Lauss if (id->flags & IDF_STOP) {
197a26c20b1SManuel Lauss OUT32(id, I2CMCR, MCR_MIE | MCR_FSB);
198a26c20b1SManuel Lauss } else {
199a26c20b1SManuel Lauss id->status |= IDS_DONE;
200a26c20b1SManuel Lauss /* keep the TEND bit: ctl holds SCL low
201a26c20b1SManuel Lauss * until the setup for the next i2c_msg
202a26c20b1SManuel Lauss * clears this bit.
203a26c20b1SManuel Lauss */
204a26c20b1SManuel Lauss fsr &= ~FSR_TEND;
205a26c20b1SManuel Lauss }
206a26c20b1SManuel Lauss }
207a26c20b1SManuel Lauss if (fsr & FSR_TDFE) {
208a26c20b1SManuel Lauss while (msg->len && (IN32(id, I2CTFDR) < FIFO_SIZE)) {
209a26c20b1SManuel Lauss OUT32(id, I2CRXTX, *data++);
210a26c20b1SManuel Lauss msg->len--;
211a26c20b1SManuel Lauss }
212a26c20b1SManuel Lauss
213a26c20b1SManuel Lauss if (msg->len < 1) {
214a26c20b1SManuel Lauss fier &= ~FIER_TXIE;
215a26c20b1SManuel Lauss OUT32(id, I2CFIER, fier);
216a26c20b1SManuel Lauss } else {
217a26c20b1SManuel Lauss len = (msg->len >= FIFO_SIZE) ? 2 : 0;
218a26c20b1SManuel Lauss OUT32(id, I2CFCR,
219a26c20b1SManuel Lauss FCR_RFRST | ((len & 3) << 2));
220a26c20b1SManuel Lauss }
221a26c20b1SManuel Lauss }
222a26c20b1SManuel Lauss }
223a26c20b1SManuel Lauss out:
224a26c20b1SManuel Lauss if (id->status & IDS_DONE) {
225a26c20b1SManuel Lauss OUT32(id, I2CMIER, 0);
226a26c20b1SManuel Lauss OUT32(id, I2CFIER, 0);
227a26c20b1SManuel Lauss id->msg = NULL;
228a26c20b1SManuel Lauss complete(&id->xfer_done);
229a26c20b1SManuel Lauss }
230a26c20b1SManuel Lauss /* clear status flags and ctrl resumes work */
231a26c20b1SManuel Lauss OUT32(id, I2CMSR, ~msr);
232a26c20b1SManuel Lauss OUT32(id, I2CFSR, ~fsr);
233a26c20b1SManuel Lauss OUT32(id, I2CSSR, 0);
234a26c20b1SManuel Lauss
235a26c20b1SManuel Lauss return IRQ_HANDLED;
236a26c20b1SManuel Lauss }
237a26c20b1SManuel Lauss
238a26c20b1SManuel Lauss
239a26c20b1SManuel Lauss /* prepare and start a master receive operation */
sh7760_i2c_mrecv(struct cami2c * id)240a26c20b1SManuel Lauss static void sh7760_i2c_mrecv(struct cami2c *id)
241a26c20b1SManuel Lauss {
242a26c20b1SManuel Lauss int len;
243a26c20b1SManuel Lauss
244a26c20b1SManuel Lauss id->flags |= IDF_RECV;
245a26c20b1SManuel Lauss
246a26c20b1SManuel Lauss /* set the slave addr reg; otherwise rcv wont work! */
247a26c20b1SManuel Lauss OUT32(id, I2CSAR, 0xfe);
248a26c20b1SManuel Lauss OUT32(id, I2CMAR, (id->msg->addr << 1) | 1);
249a26c20b1SManuel Lauss
250a26c20b1SManuel Lauss /* adjust rx fifo trigger */
251a26c20b1SManuel Lauss if (id->msg->len >= FIFO_SIZE)
252a26c20b1SManuel Lauss len = FIFO_SIZE - 1; /* trigger at fifo full */
253a26c20b1SManuel Lauss else
254a26c20b1SManuel Lauss len = id->msg->len - 1; /* trigger before all received */
255a26c20b1SManuel Lauss
256a26c20b1SManuel Lauss OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
257a26c20b1SManuel Lauss OUT32(id, I2CFCR, FCR_TFRST | ((len & 0xF) << 4));
258a26c20b1SManuel Lauss
259a26c20b1SManuel Lauss OUT32(id, I2CMSR, 0);
260a26c20b1SManuel Lauss OUT32(id, I2CMCR, MCR_MIE | MCR_ESG);
261a26c20b1SManuel Lauss OUT32(id, I2CMIER, MIE_MNRE | MIE_MALE | MIE_MSTE | MIE_MATE);
262a26c20b1SManuel Lauss OUT32(id, I2CFIER, FIER_RXIE);
263a26c20b1SManuel Lauss }
264a26c20b1SManuel Lauss
265a26c20b1SManuel Lauss /* prepare and start a master send operation */
sh7760_i2c_msend(struct cami2c * id)266a26c20b1SManuel Lauss static void sh7760_i2c_msend(struct cami2c *id)
267a26c20b1SManuel Lauss {
268a26c20b1SManuel Lauss int len;
269a26c20b1SManuel Lauss
270a26c20b1SManuel Lauss id->flags |= IDF_SEND;
271a26c20b1SManuel Lauss
272a26c20b1SManuel Lauss /* set the slave addr reg; otherwise xmit wont work! */
273a26c20b1SManuel Lauss OUT32(id, I2CSAR, 0xfe);
274a26c20b1SManuel Lauss OUT32(id, I2CMAR, (id->msg->addr << 1) | 0);
275a26c20b1SManuel Lauss
276a26c20b1SManuel Lauss /* adjust tx fifo trigger */
277a26c20b1SManuel Lauss if (id->msg->len >= FIFO_SIZE)
278a26c20b1SManuel Lauss len = 2; /* trig: 2 bytes left in TX fifo */
279a26c20b1SManuel Lauss else
280a26c20b1SManuel Lauss len = 0; /* trig: 8 bytes left in TX fifo */
281a26c20b1SManuel Lauss
282a26c20b1SManuel Lauss OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
283a26c20b1SManuel Lauss OUT32(id, I2CFCR, FCR_RFRST | ((len & 3) << 2));
284a26c20b1SManuel Lauss
285a26c20b1SManuel Lauss while (id->msg->len && IN32(id, I2CTFDR) < FIFO_SIZE) {
286a26c20b1SManuel Lauss OUT32(id, I2CRXTX, *(id->msg->buf));
287a26c20b1SManuel Lauss (id->msg->len)--;
288a26c20b1SManuel Lauss (id->msg->buf)++;
289a26c20b1SManuel Lauss }
290a26c20b1SManuel Lauss
291a26c20b1SManuel Lauss OUT32(id, I2CMSR, 0);
292a26c20b1SManuel Lauss OUT32(id, I2CMCR, MCR_MIE | MCR_ESG);
293a26c20b1SManuel Lauss OUT32(id, I2CFSR, 0);
294a26c20b1SManuel Lauss OUT32(id, I2CMIER, MIE_MNRE | MIE_MALE | MIE_MSTE | MIE_MATE);
295a26c20b1SManuel Lauss OUT32(id, I2CFIER, FIER_TEIE | (id->msg->len ? FIER_TXIE : 0));
296a26c20b1SManuel Lauss }
297a26c20b1SManuel Lauss
sh7760_i2c_busy_check(struct cami2c * id)298a26c20b1SManuel Lauss static inline int sh7760_i2c_busy_check(struct cami2c *id)
299a26c20b1SManuel Lauss {
300a26c20b1SManuel Lauss return (IN32(id, I2CMCR) & MCR_FSDA);
301a26c20b1SManuel Lauss }
302a26c20b1SManuel Lauss
sh7760_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)303a26c20b1SManuel Lauss static int sh7760_i2c_master_xfer(struct i2c_adapter *adap,
304a26c20b1SManuel Lauss struct i2c_msg *msgs,
305a26c20b1SManuel Lauss int num)
306a26c20b1SManuel Lauss {
307a26c20b1SManuel Lauss struct cami2c *id = adap->algo_data;
308a26c20b1SManuel Lauss int i, retr;
309a26c20b1SManuel Lauss
310a26c20b1SManuel Lauss if (sh7760_i2c_busy_check(id)) {
311a26c20b1SManuel Lauss dev_err(&adap->dev, "sh7760-i2c%d: bus busy!\n", adap->nr);
312a26c20b1SManuel Lauss return -EBUSY;
313a26c20b1SManuel Lauss }
314a26c20b1SManuel Lauss
315a26c20b1SManuel Lauss i = 0;
316a26c20b1SManuel Lauss while (i < num) {
317a26c20b1SManuel Lauss retr = adap->retries;
318a26c20b1SManuel Lauss retry:
319a26c20b1SManuel Lauss id->flags = ((i == (num-1)) ? IDF_STOP : 0);
320a26c20b1SManuel Lauss id->status = 0;
321a26c20b1SManuel Lauss id->msg = msgs;
322a26c20b1SManuel Lauss init_completion(&id->xfer_done);
323a26c20b1SManuel Lauss
324a26c20b1SManuel Lauss if (msgs->flags & I2C_M_RD)
325a26c20b1SManuel Lauss sh7760_i2c_mrecv(id);
326a26c20b1SManuel Lauss else
327a26c20b1SManuel Lauss sh7760_i2c_msend(id);
328a26c20b1SManuel Lauss
329a26c20b1SManuel Lauss wait_for_completion(&id->xfer_done);
330a26c20b1SManuel Lauss
331a26c20b1SManuel Lauss if (id->status == 0) {
332a26c20b1SManuel Lauss num = -EIO;
333a26c20b1SManuel Lauss break;
334a26c20b1SManuel Lauss }
335a26c20b1SManuel Lauss
336a26c20b1SManuel Lauss if (id->status & IDS_NACK) {
337a26c20b1SManuel Lauss /* wait a bit or i2c module stops working */
338a26c20b1SManuel Lauss mdelay(1);
339a26c20b1SManuel Lauss num = -EREMOTEIO;
340a26c20b1SManuel Lauss break;
341a26c20b1SManuel Lauss }
342a26c20b1SManuel Lauss
343a26c20b1SManuel Lauss if (id->status & IDS_ARBLOST) {
344a26c20b1SManuel Lauss if (retr--) {
345a26c20b1SManuel Lauss mdelay(2);
346a26c20b1SManuel Lauss goto retry;
347a26c20b1SManuel Lauss }
348a26c20b1SManuel Lauss num = -EREMOTEIO;
349a26c20b1SManuel Lauss break;
350a26c20b1SManuel Lauss }
351a26c20b1SManuel Lauss
352a26c20b1SManuel Lauss msgs++;
353a26c20b1SManuel Lauss i++;
354a26c20b1SManuel Lauss }
355a26c20b1SManuel Lauss
356a26c20b1SManuel Lauss id->msg = NULL;
357a26c20b1SManuel Lauss id->flags = 0;
358a26c20b1SManuel Lauss id->status = 0;
359a26c20b1SManuel Lauss
360a26c20b1SManuel Lauss OUT32(id, I2CMCR, 0);
361a26c20b1SManuel Lauss OUT32(id, I2CMSR, 0);
362a26c20b1SManuel Lauss OUT32(id, I2CMIER, 0);
363a26c20b1SManuel Lauss OUT32(id, I2CFIER, 0);
364a26c20b1SManuel Lauss
365a26c20b1SManuel Lauss /* reset slave module registers too: master mode enables slave
366a26c20b1SManuel Lauss * module for receive ops (ack, data). Without this reset,
367a26c20b1SManuel Lauss * eternal bus activity might be reported after NACK / ARBLOST.
368a26c20b1SManuel Lauss */
369a26c20b1SManuel Lauss OUT32(id, I2CSCR, 0);
370a26c20b1SManuel Lauss OUT32(id, I2CSAR, 0);
371a26c20b1SManuel Lauss OUT32(id, I2CSSR, 0);
372a26c20b1SManuel Lauss
373a26c20b1SManuel Lauss return num;
374a26c20b1SManuel Lauss }
375a26c20b1SManuel Lauss
sh7760_i2c_func(struct i2c_adapter * adap)376a26c20b1SManuel Lauss static u32 sh7760_i2c_func(struct i2c_adapter *adap)
377a26c20b1SManuel Lauss {
378a26c20b1SManuel Lauss return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
379a26c20b1SManuel Lauss }
380a26c20b1SManuel Lauss
381a26c20b1SManuel Lauss static const struct i2c_algorithm sh7760_i2c_algo = {
382a26c20b1SManuel Lauss .master_xfer = sh7760_i2c_master_xfer,
383a26c20b1SManuel Lauss .functionality = sh7760_i2c_func,
384a26c20b1SManuel Lauss };
385a26c20b1SManuel Lauss
386a26c20b1SManuel Lauss /* calculate CCR register setting for a desired scl clock. SCL clock is
387a26c20b1SManuel Lauss * derived from I2C module clock (iclk) which in turn is derived from
388a26c20b1SManuel Lauss * peripheral module clock (mclk, usually around 33MHz):
389a26c20b1SManuel Lauss * iclk = mclk/(CDF + 1). iclk must be < 20MHz.
390a26c20b1SManuel Lauss * scl = iclk/(SCGD*8 + 20).
391a26c20b1SManuel Lauss */
calc_CCR(unsigned long scl_hz)3920b255e92SBill Pemberton static int calc_CCR(unsigned long scl_hz)
393a26c20b1SManuel Lauss {
394a26c20b1SManuel Lauss struct clk *mclk;
395a26c20b1SManuel Lauss unsigned long mck, m1, dff, odff, iclk;
396a26c20b1SManuel Lauss signed char cdf, cdfm;
397a26c20b1SManuel Lauss int scgd, scgdm, scgds;
398a26c20b1SManuel Lauss
399af777ce4SPaul Mundt mclk = clk_get(NULL, "peripheral_clk");
400a26c20b1SManuel Lauss if (IS_ERR(mclk)) {
401a26c20b1SManuel Lauss return PTR_ERR(mclk);
402a26c20b1SManuel Lauss } else {
403a26c20b1SManuel Lauss mck = mclk->rate;
404a26c20b1SManuel Lauss clk_put(mclk);
405a26c20b1SManuel Lauss }
406a26c20b1SManuel Lauss
407a26c20b1SManuel Lauss odff = scl_hz;
408a26c20b1SManuel Lauss scgdm = cdfm = m1 = 0;
409a26c20b1SManuel Lauss for (cdf = 3; cdf >= 0; cdf--) {
410a26c20b1SManuel Lauss iclk = mck / (1 + cdf);
411a26c20b1SManuel Lauss if (iclk >= 20000000)
412a26c20b1SManuel Lauss continue;
413a26c20b1SManuel Lauss scgds = ((iclk / scl_hz) - 20) >> 3;
414a26c20b1SManuel Lauss for (scgd = scgds; (scgd < 63) && scgd <= scgds + 1; scgd++) {
415a26c20b1SManuel Lauss m1 = iclk / (20 + (scgd << 3));
416a26c20b1SManuel Lauss dff = abs(scl_hz - m1);
417a26c20b1SManuel Lauss if (dff < odff) {
418a26c20b1SManuel Lauss odff = dff;
419a26c20b1SManuel Lauss cdfm = cdf;
420a26c20b1SManuel Lauss scgdm = scgd;
421a26c20b1SManuel Lauss }
422a26c20b1SManuel Lauss }
423a26c20b1SManuel Lauss }
424a26c20b1SManuel Lauss /* fail if more than 25% off of requested SCL */
425a26c20b1SManuel Lauss if (odff > (scl_hz >> 2))
426a26c20b1SManuel Lauss return -EINVAL;
427a26c20b1SManuel Lauss
428a26c20b1SManuel Lauss /* create a CCR register value */
429a26c20b1SManuel Lauss return ((scgdm << 2) | cdfm);
430a26c20b1SManuel Lauss }
431a26c20b1SManuel Lauss
sh7760_i2c_probe(struct platform_device * pdev)4320b255e92SBill Pemberton static int sh7760_i2c_probe(struct platform_device *pdev)
433a26c20b1SManuel Lauss {
434a26c20b1SManuel Lauss struct sh7760_i2c_platdata *pd;
435a26c20b1SManuel Lauss struct resource *res;
436a26c20b1SManuel Lauss struct cami2c *id;
437a26c20b1SManuel Lauss int ret;
438a26c20b1SManuel Lauss
4396d4028c6SJingoo Han pd = dev_get_platdata(&pdev->dev);
440a26c20b1SManuel Lauss if (!pd) {
441a26c20b1SManuel Lauss dev_err(&pdev->dev, "no platform_data!\n");
442a26c20b1SManuel Lauss ret = -ENODEV;
443a26c20b1SManuel Lauss goto out0;
444a26c20b1SManuel Lauss }
445a26c20b1SManuel Lauss
44606e98957SMarkus Elfring id = kzalloc(sizeof(*id), GFP_KERNEL);
447a26c20b1SManuel Lauss if (!id) {
448a26c20b1SManuel Lauss ret = -ENOMEM;
449a26c20b1SManuel Lauss goto out0;
450a26c20b1SManuel Lauss }
451a26c20b1SManuel Lauss
452a26c20b1SManuel Lauss res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
453a26c20b1SManuel Lauss if (!res) {
454a26c20b1SManuel Lauss dev_err(&pdev->dev, "no mmio resources\n");
455a26c20b1SManuel Lauss ret = -ENODEV;
456a26c20b1SManuel Lauss goto out1;
457a26c20b1SManuel Lauss }
458a26c20b1SManuel Lauss
459a26c20b1SManuel Lauss id->ioarea = request_mem_region(res->start, REGSIZE, pdev->name);
460a26c20b1SManuel Lauss if (!id->ioarea) {
461a26c20b1SManuel Lauss dev_err(&pdev->dev, "mmio already reserved\n");
462a26c20b1SManuel Lauss ret = -EBUSY;
463a26c20b1SManuel Lauss goto out1;
464a26c20b1SManuel Lauss }
465a26c20b1SManuel Lauss
466a26c20b1SManuel Lauss id->iobase = ioremap(res->start, REGSIZE);
467a26c20b1SManuel Lauss if (!id->iobase) {
468a26c20b1SManuel Lauss dev_err(&pdev->dev, "cannot ioremap\n");
469a26c20b1SManuel Lauss ret = -ENODEV;
470a26c20b1SManuel Lauss goto out2;
471a26c20b1SManuel Lauss }
472a26c20b1SManuel Lauss
473e5b2e3e7SSergey Shtylyov ret = platform_get_irq(pdev, 0);
474e5b2e3e7SSergey Shtylyov if (ret < 0)
47592dfb272SSergey Shtylyov goto out3;
476e5b2e3e7SSergey Shtylyov id->irq = ret;
477a26c20b1SManuel Lauss
478a26c20b1SManuel Lauss id->adap.nr = pdev->id;
479a26c20b1SManuel Lauss id->adap.algo = &sh7760_i2c_algo;
480*9fd12f38SHeiner Kallweit id->adap.class = I2C_CLASS_HWMON;
481a26c20b1SManuel Lauss id->adap.retries = 3;
482a26c20b1SManuel Lauss id->adap.algo_data = id;
483a26c20b1SManuel Lauss id->adap.dev.parent = &pdev->dev;
484a26c20b1SManuel Lauss snprintf(id->adap.name, sizeof(id->adap.name),
485a26c20b1SManuel Lauss "SH7760 I2C at %08lx", (unsigned long)res->start);
486a26c20b1SManuel Lauss
487a26c20b1SManuel Lauss OUT32(id, I2CMCR, 0);
488a26c20b1SManuel Lauss OUT32(id, I2CMSR, 0);
489a26c20b1SManuel Lauss OUT32(id, I2CMIER, 0);
490a26c20b1SManuel Lauss OUT32(id, I2CMAR, 0);
491a26c20b1SManuel Lauss OUT32(id, I2CSIER, 0);
492a26c20b1SManuel Lauss OUT32(id, I2CSAR, 0);
493a26c20b1SManuel Lauss OUT32(id, I2CSCR, 0);
494a26c20b1SManuel Lauss OUT32(id, I2CSSR, 0);
495a26c20b1SManuel Lauss OUT32(id, I2CFIER, 0);
496a26c20b1SManuel Lauss OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
497a26c20b1SManuel Lauss OUT32(id, I2CFSR, 0);
498a26c20b1SManuel Lauss
499a26c20b1SManuel Lauss ret = calc_CCR(pd->speed_khz * 1000);
500a26c20b1SManuel Lauss if (ret < 0) {
501a26c20b1SManuel Lauss dev_err(&pdev->dev, "invalid SCL clock: %dkHz\n",
502a26c20b1SManuel Lauss pd->speed_khz);
503a26c20b1SManuel Lauss goto out3;
504a26c20b1SManuel Lauss }
505a26c20b1SManuel Lauss OUT32(id, I2CCCR, ret);
506a26c20b1SManuel Lauss
5074311051cSYong Zhang if (request_irq(id->irq, sh7760_i2c_irq, 0,
508a26c20b1SManuel Lauss SH7760_I2C_DEVNAME, id)) {
509a26c20b1SManuel Lauss dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
510a26c20b1SManuel Lauss ret = -EBUSY;
511a26c20b1SManuel Lauss goto out3;
512a26c20b1SManuel Lauss }
513a26c20b1SManuel Lauss
514a26c20b1SManuel Lauss ret = i2c_add_numbered_adapter(&id->adap);
515ea734404SWolfram Sang if (ret < 0)
516a26c20b1SManuel Lauss goto out4;
517a26c20b1SManuel Lauss
518a26c20b1SManuel Lauss platform_set_drvdata(pdev, id);
519a26c20b1SManuel Lauss
520a26c20b1SManuel Lauss dev_info(&pdev->dev, "%d kHz mmio %08x irq %d\n",
521a26c20b1SManuel Lauss pd->speed_khz, res->start, id->irq);
522a26c20b1SManuel Lauss
523a26c20b1SManuel Lauss return 0;
524a26c20b1SManuel Lauss
525a26c20b1SManuel Lauss out4:
526a26c20b1SManuel Lauss free_irq(id->irq, id);
527a26c20b1SManuel Lauss out3:
528a26c20b1SManuel Lauss iounmap(id->iobase);
529a26c20b1SManuel Lauss out2:
530a26c20b1SManuel Lauss release_resource(id->ioarea);
531a26c20b1SManuel Lauss kfree(id->ioarea);
532a26c20b1SManuel Lauss out1:
533a26c20b1SManuel Lauss kfree(id);
534a26c20b1SManuel Lauss out0:
535a26c20b1SManuel Lauss return ret;
536a26c20b1SManuel Lauss }
537a26c20b1SManuel Lauss
sh7760_i2c_remove(struct platform_device * pdev)538e190a0c3SUwe Kleine-König static void sh7760_i2c_remove(struct platform_device *pdev)
539a26c20b1SManuel Lauss {
540a26c20b1SManuel Lauss struct cami2c *id = platform_get_drvdata(pdev);
541a26c20b1SManuel Lauss
542a26c20b1SManuel Lauss i2c_del_adapter(&id->adap);
543a26c20b1SManuel Lauss free_irq(id->irq, id);
544a26c20b1SManuel Lauss iounmap(id->iobase);
545a26c20b1SManuel Lauss release_resource(id->ioarea);
546a26c20b1SManuel Lauss kfree(id->ioarea);
547a26c20b1SManuel Lauss kfree(id);
548a26c20b1SManuel Lauss }
549a26c20b1SManuel Lauss
550a26c20b1SManuel Lauss static struct platform_driver sh7760_i2c_drv = {
551a26c20b1SManuel Lauss .driver = {
552a26c20b1SManuel Lauss .name = SH7760_I2C_DEVNAME,
553a26c20b1SManuel Lauss },
554a26c20b1SManuel Lauss .probe = sh7760_i2c_probe,
555e190a0c3SUwe Kleine-König .remove_new = sh7760_i2c_remove,
556a26c20b1SManuel Lauss };
557a26c20b1SManuel Lauss
558a3664b51SAxel Lin module_platform_driver(sh7760_i2c_drv);
559a26c20b1SManuel Lauss
560a26c20b1SManuel Lauss MODULE_LICENSE("GPL");
561a26c20b1SManuel Lauss MODULE_DESCRIPTION("SH7760 I2C bus driver");
562a26c20b1SManuel Lauss MODULE_AUTHOR("Manuel Lauss <mano@roarinelk.homelinux.net>");
563