1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/i2c/busses/i2c-s3c2410.c 3 * 4 * Copyright (C) 2004,2005,2009 Simtec Electronics 5 * Ben Dooks <ben@simtec.co.uk> 6 * 7 * S3C2410 I2C Controller 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 13 #include <linux/i2c.h> 14 #include <linux/init.h> 15 #include <linux/time.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/errno.h> 19 #include <linux/err.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/clk.h> 23 #include <linux/cpufreq.h> 24 #include <linux/slab.h> 25 #include <linux/io.h> 26 #include <linux/of.h> 27 #include <linux/gpio/consumer.h> 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/mfd/syscon.h> 30 #include <linux/regmap.h> 31 32 #include <asm/irq.h> 33 34 #include <linux/platform_data/i2c-s3c2410.h> 35 36 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */ 37 38 #define S3C2410_IICCON 0x00 39 #define S3C2410_IICSTAT 0x04 40 #define S3C2410_IICADD 0x08 41 #define S3C2410_IICDS 0x0C 42 #define S3C2440_IICLC 0x10 43 44 #define S3C2410_IICCON_ACKEN (1 << 7) 45 #define S3C2410_IICCON_TXDIV_16 (0 << 6) 46 #define S3C2410_IICCON_TXDIV_512 (1 << 6) 47 #define S3C2410_IICCON_IRQEN (1 << 5) 48 #define S3C2410_IICCON_IRQPEND (1 << 4) 49 #define S3C2410_IICCON_SCALE(x) ((x) & 0xf) 50 #define S3C2410_IICCON_SCALEMASK (0xf) 51 52 #define S3C2410_IICSTAT_MASTER_RX (2 << 6) 53 #define S3C2410_IICSTAT_MASTER_TX (3 << 6) 54 #define S3C2410_IICSTAT_SLAVE_RX (0 << 6) 55 #define S3C2410_IICSTAT_SLAVE_TX (1 << 6) 56 #define S3C2410_IICSTAT_MODEMASK (3 << 6) 57 58 #define S3C2410_IICSTAT_START (1 << 5) 59 #define S3C2410_IICSTAT_BUSBUSY (1 << 5) 60 #define S3C2410_IICSTAT_TXRXEN (1 << 4) 61 #define S3C2410_IICSTAT_ARBITR (1 << 3) 62 #define S3C2410_IICSTAT_ASSLAVE (1 << 2) 63 #define S3C2410_IICSTAT_ADDR0 (1 << 1) 64 #define S3C2410_IICSTAT_LASTBIT (1 << 0) 65 66 #define S3C2410_IICLC_SDA_DELAY0 (0 << 0) 67 #define S3C2410_IICLC_SDA_DELAY5 (1 << 0) 68 #define S3C2410_IICLC_SDA_DELAY10 (2 << 0) 69 #define S3C2410_IICLC_SDA_DELAY15 (3 << 0) 70 #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0) 71 72 #define S3C2410_IICLC_FILTER_ON (1 << 2) 73 74 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */ 75 #define QUIRK_S3C2440 (1 << 0) 76 #define QUIRK_HDMIPHY (1 << 1) 77 #define QUIRK_NO_GPIO (1 << 2) 78 #define QUIRK_POLL (1 << 3) 79 #define QUIRK_ATOMIC (1 << 4) 80 81 /* Max time to wait for bus to become idle after a xfer (in us) */ 82 #define S3C2410_IDLE_TIMEOUT 5000 83 84 /* Exynos5 Sysreg offset */ 85 #define EXYNOS5_SYS_I2C_CFG 0x0234 86 87 /* i2c controller state */ 88 enum s3c24xx_i2c_state { 89 STATE_IDLE, 90 STATE_START, 91 STATE_READ, 92 STATE_WRITE, 93 STATE_STOP 94 }; 95 96 struct s3c24xx_i2c { 97 wait_queue_head_t wait; 98 kernel_ulong_t quirks; 99 100 struct i2c_msg *msg; 101 unsigned int msg_num; 102 unsigned int msg_idx; 103 unsigned int msg_ptr; 104 105 unsigned int tx_setup; 106 unsigned int irq; 107 108 enum s3c24xx_i2c_state state; 109 unsigned long clkrate; 110 111 void __iomem *regs; 112 struct clk *clk; 113 struct device *dev; 114 struct i2c_adapter adap; 115 116 struct s3c2410_platform_i2c *pdata; 117 struct gpio_desc *gpios[2]; 118 struct pinctrl *pctrl; 119 struct regmap *sysreg; 120 unsigned int sys_i2c_cfg; 121 }; 122 123 static const struct platform_device_id s3c24xx_driver_ids[] = { 124 { 125 .name = "s3c2410-i2c", 126 .driver_data = 0, 127 }, { 128 .name = "s3c2440-i2c", 129 .driver_data = QUIRK_S3C2440, 130 }, { 131 .name = "s3c2440-hdmiphy-i2c", 132 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO, 133 }, { } 134 }; 135 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); 136 137 static void i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat); 138 139 #ifdef CONFIG_OF 140 static const struct of_device_id s3c24xx_i2c_match[] = { 141 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 }, 142 { .compatible = "samsung,s3c2440-hdmiphy-i2c", 143 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) }, 144 { .compatible = "samsung,exynos5-sata-phy-i2c", 145 .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) }, 146 {}, 147 }; 148 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match); 149 #endif 150 151 /* 152 * Get controller type either from device tree or platform device variant. 153 */ 154 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev) 155 { 156 if (pdev->dev.of_node) 157 return (kernel_ulong_t)of_device_get_match_data(&pdev->dev); 158 159 return platform_get_device_id(pdev)->driver_data; 160 } 161 162 /* 163 * Complete the message and wake up the caller, using the given return code, 164 * or zero to mean ok. 165 */ 166 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) 167 { 168 dev_dbg(i2c->dev, "master_complete %d\n", ret); 169 170 i2c->msg_ptr = 0; 171 i2c->msg = NULL; 172 i2c->msg_idx++; 173 i2c->msg_num = 0; 174 if (ret) 175 i2c->msg_idx = ret; 176 177 if (!(i2c->quirks & (QUIRK_POLL | QUIRK_ATOMIC))) 178 wake_up(&i2c->wait); 179 } 180 181 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) 182 { 183 unsigned long tmp; 184 185 tmp = readl(i2c->regs + S3C2410_IICCON); 186 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 187 } 188 189 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) 190 { 191 unsigned long tmp; 192 193 tmp = readl(i2c->regs + S3C2410_IICCON); 194 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 195 } 196 197 /* irq enable/disable functions */ 198 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) 199 { 200 unsigned long tmp; 201 202 tmp = readl(i2c->regs + S3C2410_IICCON); 203 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 204 } 205 206 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) 207 { 208 unsigned long tmp; 209 210 tmp = readl(i2c->regs + S3C2410_IICCON); 211 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 212 } 213 214 static bool is_ack(struct s3c24xx_i2c *i2c) 215 { 216 int tries; 217 218 for (tries = 50; tries; --tries) { 219 unsigned long tmp = readl(i2c->regs + S3C2410_IICCON); 220 221 if (!(tmp & S3C2410_IICCON_ACKEN)) { 222 /* 223 * Wait a bit for the bus to stabilize, 224 * delay estimated experimentally. 225 */ 226 usleep_range(100, 200); 227 return true; 228 } 229 if (tmp & S3C2410_IICCON_IRQPEND) { 230 if (!(readl(i2c->regs + S3C2410_IICSTAT) 231 & S3C2410_IICSTAT_LASTBIT)) 232 return true; 233 } 234 usleep_range(1000, 2000); 235 } 236 dev_err(i2c->dev, "ack was not received\n"); 237 return false; 238 } 239 240 /* 241 * put the start of a message onto the bus 242 */ 243 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, 244 struct i2c_msg *msg) 245 { 246 unsigned int addr = (msg->addr & 0x7f) << 1; 247 unsigned long stat; 248 unsigned long iiccon; 249 250 stat = 0; 251 stat |= S3C2410_IICSTAT_TXRXEN; 252 253 if (msg->flags & I2C_M_RD) { 254 stat |= S3C2410_IICSTAT_MASTER_RX; 255 addr |= 1; 256 } else 257 stat |= S3C2410_IICSTAT_MASTER_TX; 258 259 if (msg->flags & I2C_M_REV_DIR_ADDR) 260 addr ^= 1; 261 262 /* todo - check for whether ack wanted or not */ 263 s3c24xx_i2c_enable_ack(i2c); 264 265 iiccon = readl(i2c->regs + S3C2410_IICCON); 266 writel(stat, i2c->regs + S3C2410_IICSTAT); 267 268 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); 269 writeb(addr, i2c->regs + S3C2410_IICDS); 270 271 /* 272 * delay here to ensure the data byte has gotten onto the bus 273 * before the transaction is started 274 */ 275 ndelay(i2c->tx_setup); 276 277 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); 278 writel(iiccon, i2c->regs + S3C2410_IICCON); 279 280 stat |= S3C2410_IICSTAT_START; 281 writel(stat, i2c->regs + S3C2410_IICSTAT); 282 } 283 284 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) 285 { 286 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); 287 288 dev_dbg(i2c->dev, "STOP\n"); 289 290 /* 291 * The datasheet says that the STOP sequence should be: 292 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP') 293 * 2) I2CCON.4 = 0 - Clear IRQPEND 294 * 3) Wait until the stop condition takes effect. 295 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN 296 * 297 * Where, step "4*" is only for buses with the "HDMIPHY" quirk. 298 * 299 * However, after much experimentation, it appears that: 300 * a) normal buses automatically clear BUSY and transition from 301 * Master->Slave when they complete generating a STOP condition. 302 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4 303 * after starting the STOP generation here. 304 * b) HDMIPHY bus does neither, so there is no way to do step 3. 305 * There is no indication when this bus has finished generating 306 * STOP. 307 * 308 * In fact, we have found that as soon as the IRQPEND bit is cleared in 309 * step 2, the HDMIPHY bus generates the STOP condition, and then 310 * immediately starts transferring another data byte, even though the 311 * bus is supposedly stopped. This is presumably because the bus is 312 * still in "Master" mode, and its BUSY bit is still set. 313 * 314 * To avoid these extra post-STOP transactions on HDMI phy devices, we 315 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly, 316 * instead of first generating a proper STOP condition. This should 317 * float SDA & SCK terminating the transfer. Subsequent transfers 318 * start with a proper START condition, and proceed normally. 319 * 320 * The HDMIPHY bus is an internal bus that always has exactly two 321 * devices, the host as Master and the HDMIPHY device as the slave. 322 * Skipping the STOP condition has been tested on this bus and works. 323 */ 324 if (i2c->quirks & QUIRK_HDMIPHY) { 325 /* Stop driving the I2C pins */ 326 iicstat &= ~S3C2410_IICSTAT_TXRXEN; 327 } else { 328 /* stop the transfer */ 329 iicstat &= ~S3C2410_IICSTAT_START; 330 } 331 writel(iicstat, i2c->regs + S3C2410_IICSTAT); 332 333 i2c->state = STATE_STOP; 334 335 s3c24xx_i2c_master_complete(i2c, ret); 336 s3c24xx_i2c_disable_irq(i2c); 337 } 338 339 /* 340 * helper functions to determine the current state in the set of 341 * messages we are sending 342 */ 343 344 /* 345 * returns TRUE if the current message is the last in the set 346 */ 347 static inline int is_lastmsg(struct s3c24xx_i2c *i2c) 348 { 349 return i2c->msg_idx >= (i2c->msg_num - 1); 350 } 351 352 /* 353 * returns TRUE if we this is the last byte in the current message 354 */ 355 static inline int is_msglast(struct s3c24xx_i2c *i2c) 356 { 357 /* 358 * msg->len is always 1 for the first byte of smbus block read. 359 * Actual length will be read from slave. More bytes will be 360 * read according to the length then. 361 */ 362 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) 363 return 0; 364 365 return i2c->msg_ptr == i2c->msg->len-1; 366 } 367 368 /* 369 * returns TRUE if we reached the end of the current message 370 */ 371 static inline int is_msgend(struct s3c24xx_i2c *i2c) 372 { 373 return i2c->msg_ptr >= i2c->msg->len; 374 } 375 376 /* 377 * process an interrupt and work out what to do 378 */ 379 static void i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) 380 { 381 unsigned long tmp; 382 unsigned char byte; 383 384 switch (i2c->state) { 385 386 case STATE_IDLE: 387 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); 388 goto out; 389 390 case STATE_STOP: 391 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); 392 s3c24xx_i2c_disable_irq(i2c); 393 goto out_ack; 394 395 case STATE_START: 396 /* 397 * last thing we did was send a start condition on the 398 * bus, or started a new i2c message 399 */ 400 if (iicstat & S3C2410_IICSTAT_LASTBIT && 401 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 402 /* ack was not received... */ 403 dev_dbg(i2c->dev, "ack was not received\n"); 404 s3c24xx_i2c_stop(i2c, -ENXIO); 405 goto out_ack; 406 } 407 408 if (i2c->msg->flags & I2C_M_RD) 409 i2c->state = STATE_READ; 410 else 411 i2c->state = STATE_WRITE; 412 413 /* 414 * Terminate the transfer if there is nothing to do 415 * as this is used by the i2c probe to find devices. 416 */ 417 if (is_lastmsg(i2c) && i2c->msg->len == 0) { 418 s3c24xx_i2c_stop(i2c, 0); 419 goto out_ack; 420 } 421 422 if (i2c->state == STATE_READ) 423 goto prepare_read; 424 425 /* 426 * fall through to the write state, as we will need to 427 * send a byte as well 428 */ 429 fallthrough; 430 case STATE_WRITE: 431 /* 432 * we are writing data to the device... check for the 433 * end of the message, and if so, work out what to do 434 */ 435 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 436 if (iicstat & S3C2410_IICSTAT_LASTBIT) { 437 dev_dbg(i2c->dev, "WRITE: No Ack\n"); 438 439 s3c24xx_i2c_stop(i2c, -ECONNREFUSED); 440 goto out_ack; 441 } 442 } 443 444 retry_write: 445 446 if (!is_msgend(i2c)) { 447 byte = i2c->msg->buf[i2c->msg_ptr++]; 448 writeb(byte, i2c->regs + S3C2410_IICDS); 449 450 /* 451 * delay after writing the byte to allow the 452 * data setup time on the bus, as writing the 453 * data to the register causes the first bit 454 * to appear on SDA, and SCL will change as 455 * soon as the interrupt is acknowledged 456 */ 457 ndelay(i2c->tx_setup); 458 459 } else if (!is_lastmsg(i2c)) { 460 /* we need to go to the next i2c message */ 461 462 dev_dbg(i2c->dev, "WRITE: Next Message\n"); 463 464 i2c->msg_ptr = 0; 465 i2c->msg_idx++; 466 i2c->msg++; 467 468 /* check to see if we need to do another message */ 469 if (i2c->msg->flags & I2C_M_NOSTART) { 470 471 if (i2c->msg->flags & I2C_M_RD) { 472 /* 473 * cannot do this, the controller 474 * forces us to send a new START 475 * when we change direction 476 */ 477 dev_dbg(i2c->dev, 478 "missing START before write->read\n"); 479 s3c24xx_i2c_stop(i2c, -EINVAL); 480 break; 481 } 482 483 goto retry_write; 484 } else { 485 /* send the new start */ 486 s3c24xx_i2c_message_start(i2c, i2c->msg); 487 i2c->state = STATE_START; 488 } 489 490 } else { 491 /* send stop */ 492 s3c24xx_i2c_stop(i2c, 0); 493 } 494 break; 495 496 case STATE_READ: 497 /* 498 * we have a byte of data in the data register, do 499 * something with it, and then work out whether we are 500 * going to do any more read/write 501 */ 502 byte = readb(i2c->regs + S3C2410_IICDS); 503 i2c->msg->buf[i2c->msg_ptr++] = byte; 504 505 /* Add actual length to read for smbus block read */ 506 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) { 507 if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) { 508 s3c24xx_i2c_stop(i2c, -EPROTO); 509 break; 510 } 511 i2c->msg->len += byte; 512 } 513 prepare_read: 514 if (is_msglast(i2c)) { 515 /* last byte of buffer */ 516 517 if (is_lastmsg(i2c)) 518 s3c24xx_i2c_disable_ack(i2c); 519 520 } else if (is_msgend(i2c)) { 521 /* 522 * ok, we've read the entire buffer, see if there 523 * is anything else we need to do 524 */ 525 if (is_lastmsg(i2c)) { 526 /* last message, send stop and complete */ 527 dev_dbg(i2c->dev, "READ: Send Stop\n"); 528 529 s3c24xx_i2c_stop(i2c, 0); 530 } else { 531 /* go to the next transfer */ 532 dev_dbg(i2c->dev, "READ: Next Transfer\n"); 533 534 i2c->msg_ptr = 0; 535 i2c->msg_idx++; 536 i2c->msg++; 537 } 538 } 539 540 break; 541 } 542 543 /* acknowlegde the IRQ and get back on with the work */ 544 545 out_ack: 546 tmp = readl(i2c->regs + S3C2410_IICCON); 547 tmp &= ~S3C2410_IICCON_IRQPEND; 548 writel(tmp, i2c->regs + S3C2410_IICCON); 549 out: 550 return; 551 } 552 553 /* 554 * top level IRQ servicing routine 555 */ 556 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) 557 { 558 struct s3c24xx_i2c *i2c = dev_id; 559 unsigned long status; 560 unsigned long tmp; 561 562 status = readl(i2c->regs + S3C2410_IICSTAT); 563 564 if (status & S3C2410_IICSTAT_ARBITR) { 565 /* deal with arbitration loss */ 566 dev_err(i2c->dev, "deal with arbitration loss\n"); 567 } 568 569 if (i2c->state == STATE_IDLE) { 570 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); 571 572 tmp = readl(i2c->regs + S3C2410_IICCON); 573 tmp &= ~S3C2410_IICCON_IRQPEND; 574 writel(tmp, i2c->regs + S3C2410_IICCON); 575 goto out; 576 } 577 578 /* 579 * pretty much this leaves us with the fact that we've 580 * transmitted or received whatever byte we last sent 581 */ 582 i2c_s3c_irq_nextbyte(i2c, status); 583 584 out: 585 return IRQ_HANDLED; 586 } 587 588 /* 589 * Disable the bus so that we won't get any interrupts from now on, or try 590 * to drive any lines. This is the default state when we don't have 591 * anything to send/receive. 592 * 593 * If there is an event on the bus, or we have a pre-existing event at 594 * kernel boot time, we may not notice the event and the I2C controller 595 * will lock the bus with the I2C clock line low indefinitely. 596 */ 597 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c) 598 { 599 unsigned long tmp; 600 601 /* Stop driving the I2C pins */ 602 tmp = readl(i2c->regs + S3C2410_IICSTAT); 603 tmp &= ~S3C2410_IICSTAT_TXRXEN; 604 writel(tmp, i2c->regs + S3C2410_IICSTAT); 605 606 /* We don't expect any interrupts now, and don't want send acks */ 607 tmp = readl(i2c->regs + S3C2410_IICCON); 608 tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND | 609 S3C2410_IICCON_ACKEN); 610 writel(tmp, i2c->regs + S3C2410_IICCON); 611 } 612 613 614 /* 615 * get the i2c bus for a master transaction 616 */ 617 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) 618 { 619 unsigned long iicstat; 620 int timeout = 400; 621 622 while (timeout-- > 0) { 623 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 624 625 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) 626 return 0; 627 628 msleep(1); 629 } 630 631 return -ETIMEDOUT; 632 } 633 634 /* 635 * wait for the i2c bus to become idle. 636 */ 637 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c) 638 { 639 unsigned long iicstat; 640 ktime_t start, now; 641 unsigned long delay; 642 int spins; 643 644 /* ensure the stop has been through the bus */ 645 646 dev_dbg(i2c->dev, "waiting for bus idle\n"); 647 648 start = now = ktime_get(); 649 650 /* 651 * Most of the time, the bus is already idle within a few usec of the 652 * end of a transaction. However, really slow i2c devices can stretch 653 * the clock, delaying STOP generation. 654 * 655 * On slower SoCs this typically happens within a very small number of 656 * instructions so busy wait briefly to avoid scheduling overhead. 657 */ 658 spins = 3; 659 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 660 while ((iicstat & S3C2410_IICSTAT_START) && --spins) { 661 cpu_relax(); 662 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 663 } 664 665 /* 666 * If we do get an appreciable delay as a compromise between idle 667 * detection latency for the normal, fast case, and system load in the 668 * slow device case, use an exponential back off in the polling loop, 669 * up to 1/10th of the total timeout, then continue to poll at a 670 * constant rate up to the timeout. 671 */ 672 delay = 1; 673 while ((iicstat & S3C2410_IICSTAT_START) && 674 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) { 675 usleep_range(delay, 2 * delay); 676 if (delay < S3C2410_IDLE_TIMEOUT / 10) 677 delay <<= 1; 678 now = ktime_get(); 679 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 680 } 681 682 if (iicstat & S3C2410_IICSTAT_START) 683 dev_warn(i2c->dev, "timeout waiting for bus idle\n"); 684 } 685 686 /* 687 * this starts an i2c transfer 688 */ 689 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, 690 struct i2c_msg *msgs, int num) 691 { 692 long time_left = 0; 693 int ret; 694 695 ret = s3c24xx_i2c_set_master(i2c); 696 if (ret != 0) { 697 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); 698 ret = -EAGAIN; 699 goto out; 700 } 701 702 i2c->msg = msgs; 703 i2c->msg_num = num; 704 i2c->msg_ptr = 0; 705 i2c->msg_idx = 0; 706 i2c->state = STATE_START; 707 708 s3c24xx_i2c_enable_irq(i2c); 709 s3c24xx_i2c_message_start(i2c, msgs); 710 711 if (i2c->quirks & (QUIRK_POLL | QUIRK_ATOMIC)) { 712 while ((i2c->msg_num != 0) && is_ack(i2c)) { 713 unsigned long stat = readl(i2c->regs + S3C2410_IICSTAT); 714 715 i2c_s3c_irq_nextbyte(i2c, stat); 716 717 stat = readl(i2c->regs + S3C2410_IICSTAT); 718 if (stat & S3C2410_IICSTAT_ARBITR) 719 dev_err(i2c->dev, "deal with arbitration loss\n"); 720 } 721 } else { 722 time_left = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 723 } 724 725 ret = i2c->msg_idx; 726 727 /* 728 * Having these next two as dev_err() makes life very 729 * noisy when doing an i2cdetect 730 */ 731 if (time_left == 0) 732 dev_dbg(i2c->dev, "timeout\n"); 733 else if (ret != num) 734 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); 735 736 /* For QUIRK_HDMIPHY, bus is already disabled */ 737 if (i2c->quirks & QUIRK_HDMIPHY) 738 goto out; 739 740 s3c24xx_i2c_wait_idle(i2c); 741 742 s3c24xx_i2c_disable_bus(i2c); 743 744 out: 745 i2c->state = STATE_IDLE; 746 747 return ret; 748 } 749 750 /* 751 * first port of call from the i2c bus code when an message needs 752 * transferring across the i2c bus. 753 */ 754 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, 755 struct i2c_msg *msgs, int num) 756 { 757 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; 758 int retry; 759 int ret; 760 761 ret = clk_enable(i2c->clk); 762 if (ret) 763 return ret; 764 765 for (retry = 0; retry < adap->retries; retry++) { 766 767 ret = s3c24xx_i2c_doxfer(i2c, msgs, num); 768 769 if (ret != -EAGAIN) { 770 clk_disable(i2c->clk); 771 return ret; 772 } 773 774 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); 775 776 udelay(100); 777 } 778 779 clk_disable(i2c->clk); 780 return -EREMOTEIO; 781 } 782 783 static int s3c24xx_i2c_xfer_atomic(struct i2c_adapter *adap, 784 struct i2c_msg *msgs, int num) 785 { 786 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; 787 int ret; 788 789 disable_irq(i2c->irq); 790 i2c->quirks |= QUIRK_ATOMIC; 791 ret = s3c24xx_i2c_xfer(adap, msgs, num); 792 i2c->quirks &= ~QUIRK_ATOMIC; 793 enable_irq(i2c->irq); 794 795 return ret; 796 } 797 798 /* declare our i2c functionality */ 799 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) 800 { 801 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL_ALL | I2C_FUNC_NOSTART | 802 I2C_FUNC_PROTOCOL_MANGLING; 803 } 804 805 /* i2c bus registration info */ 806 static const struct i2c_algorithm s3c24xx_i2c_algorithm = { 807 .xfer = s3c24xx_i2c_xfer, 808 .xfer_atomic = s3c24xx_i2c_xfer_atomic, 809 .functionality = s3c24xx_i2c_func, 810 }; 811 812 /* 813 * return the divisor settings for a given frequency 814 */ 815 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, 816 unsigned int *div1, unsigned int *divs) 817 { 818 unsigned int calc_divs = clkin / wanted; 819 unsigned int calc_div1; 820 821 if (calc_divs > (16*16)) 822 calc_div1 = 512; 823 else 824 calc_div1 = 16; 825 826 calc_divs += calc_div1-1; 827 calc_divs /= calc_div1; 828 829 if (calc_divs == 0) 830 calc_divs = 1; 831 if (calc_divs > 17) 832 calc_divs = 17; 833 834 *divs = calc_divs; 835 *div1 = calc_div1; 836 837 return clkin / (calc_divs * calc_div1); 838 } 839 840 /* 841 * work out a divisor for the user requested frequency setting, 842 * either by the requested frequency, or scanning the acceptable 843 * range of frequencies until something is found 844 */ 845 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) 846 { 847 struct s3c2410_platform_i2c *pdata = i2c->pdata; 848 unsigned long clkin = clk_get_rate(i2c->clk); 849 unsigned int divs, div1; 850 unsigned long target_frequency; 851 u32 iiccon; 852 int freq; 853 854 i2c->clkrate = clkin; 855 clkin /= 1000; /* clkin now in KHz */ 856 857 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); 858 859 target_frequency = pdata->frequency ?: I2C_MAX_STANDARD_MODE_FREQ; 860 861 target_frequency /= 1000; /* Target frequency now in KHz */ 862 863 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); 864 865 if (freq > target_frequency) { 866 dev_err(i2c->dev, 867 "Unable to achieve desired frequency %luKHz." \ 868 " Lowest achievable %dKHz\n", target_frequency, freq); 869 return -EINVAL; 870 } 871 872 *got = freq; 873 874 iiccon = readl(i2c->regs + S3C2410_IICCON); 875 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); 876 iiccon |= (divs-1); 877 878 if (div1 == 512) 879 iiccon |= S3C2410_IICCON_TXDIV_512; 880 881 if (i2c->quirks & QUIRK_POLL) 882 iiccon |= S3C2410_IICCON_SCALE(2); 883 884 writel(iiccon, i2c->regs + S3C2410_IICCON); 885 886 if (i2c->quirks & QUIRK_S3C2440) { 887 unsigned long sda_delay; 888 889 if (pdata->sda_delay) { 890 sda_delay = clkin * pdata->sda_delay; 891 sda_delay = DIV_ROUND_UP(sda_delay, 1000000); 892 sda_delay = DIV_ROUND_UP(sda_delay, 5); 893 if (sda_delay > 3) 894 sda_delay = 3; 895 sda_delay |= S3C2410_IICLC_FILTER_ON; 896 } else 897 sda_delay = 0; 898 899 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); 900 writel(sda_delay, i2c->regs + S3C2440_IICLC); 901 } 902 903 return 0; 904 } 905 906 #ifdef CONFIG_OF 907 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 908 { 909 int i; 910 911 if (i2c->quirks & QUIRK_NO_GPIO) 912 return 0; 913 914 for (i = 0; i < 2; i++) { 915 i2c->gpios[i] = devm_gpiod_get_index(i2c->dev, NULL, 916 i, GPIOD_ASIS); 917 if (IS_ERR(i2c->gpios[i])) { 918 dev_err(i2c->dev, "i2c gpio invalid at index %d\n", i); 919 return -EINVAL; 920 } 921 } 922 return 0; 923 } 924 925 #else 926 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 927 { 928 return 0; 929 } 930 #endif 931 932 /* 933 * initialise the controller, set the IO lines and frequency 934 */ 935 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) 936 { 937 struct s3c2410_platform_i2c *pdata; 938 unsigned int freq; 939 940 /* get the plafrom data */ 941 942 pdata = i2c->pdata; 943 944 /* write slave address */ 945 946 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); 947 948 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); 949 950 writel(0, i2c->regs + S3C2410_IICCON); 951 writel(0, i2c->regs + S3C2410_IICSTAT); 952 953 /* we need to work out the divisors for the clock... */ 954 955 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { 956 dev_err(i2c->dev, "cannot meet bus frequency required\n"); 957 return -EINVAL; 958 } 959 960 /* todo - check that the i2c lines aren't being dragged anywhere */ 961 962 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); 963 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n", 964 readl(i2c->regs + S3C2410_IICCON)); 965 966 return 0; 967 } 968 969 #ifdef CONFIG_OF 970 /* 971 * Parse the device tree node and retreive the platform data. 972 */ 973 static void 974 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) 975 { 976 struct s3c2410_platform_i2c *pdata = i2c->pdata; 977 int id; 978 979 if (!np) 980 return; 981 982 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */ 983 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay); 984 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); 985 of_property_read_u32(np, "samsung,i2c-max-bus-freq", 986 (u32 *)&pdata->frequency); 987 /* 988 * Exynos5's legacy i2c controller and new high speed i2c 989 * controller have muxed interrupt sources. By default the 990 * interrupts for 4-channel HS-I2C controller are enabled. 991 * If nodes for first four channels of legacy i2c controller 992 * are available then re-configure the interrupts via the 993 * system register. 994 */ 995 id = of_alias_get_id(np, "i2c"); 996 i2c->sysreg = syscon_regmap_lookup_by_phandle(np, 997 "samsung,sysreg-phandle"); 998 if (IS_ERR(i2c->sysreg)) 999 return; 1000 1001 regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0); 1002 } 1003 #else 1004 static void 1005 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { } 1006 #endif 1007 1008 static int s3c24xx_i2c_probe(struct platform_device *pdev) 1009 { 1010 struct s3c24xx_i2c *i2c; 1011 struct s3c2410_platform_i2c *pdata = NULL; 1012 struct resource *res; 1013 int ret; 1014 1015 if (!pdev->dev.of_node) { 1016 pdata = dev_get_platdata(&pdev->dev); 1017 if (!pdata) { 1018 dev_err(&pdev->dev, "no platform data\n"); 1019 return -EINVAL; 1020 } 1021 } 1022 1023 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); 1024 if (!i2c) 1025 return -ENOMEM; 1026 1027 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1028 if (!i2c->pdata) 1029 return -ENOMEM; 1030 1031 i2c->quirks = s3c24xx_get_device_quirks(pdev); 1032 i2c->sysreg = ERR_PTR(-ENOENT); 1033 if (pdata) 1034 memcpy(i2c->pdata, pdata, sizeof(*pdata)); 1035 else 1036 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); 1037 1038 strscpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); 1039 i2c->adap.owner = THIS_MODULE; 1040 i2c->adap.algo = &s3c24xx_i2c_algorithm; 1041 i2c->adap.retries = 2; 1042 i2c->adap.class = I2C_CLASS_DEPRECATED; 1043 i2c->tx_setup = 50; 1044 1045 init_waitqueue_head(&i2c->wait); 1046 1047 /* find the clock and enable it */ 1048 i2c->dev = &pdev->dev; 1049 i2c->clk = devm_clk_get(&pdev->dev, "i2c"); 1050 if (IS_ERR(i2c->clk)) { 1051 dev_err(&pdev->dev, "cannot get clock\n"); 1052 return -ENOENT; 1053 } 1054 1055 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); 1056 1057 /* map the registers */ 1058 i2c->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1059 if (IS_ERR(i2c->regs)) 1060 return PTR_ERR(i2c->regs); 1061 1062 dev_dbg(&pdev->dev, "registers %p (%p)\n", 1063 i2c->regs, res); 1064 1065 /* setup info block for the i2c core */ 1066 i2c->adap.algo_data = i2c; 1067 i2c->adap.dev.parent = &pdev->dev; 1068 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev); 1069 1070 /* inititalise the i2c gpio lines */ 1071 if (i2c->pdata->cfg_gpio) 1072 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev)); 1073 else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) 1074 return -EINVAL; 1075 1076 /* initialise the i2c controller */ 1077 ret = clk_prepare_enable(i2c->clk); 1078 if (ret) { 1079 dev_err(&pdev->dev, "I2C clock enable failed\n"); 1080 return ret; 1081 } 1082 1083 ret = s3c24xx_i2c_init(i2c); 1084 clk_disable(i2c->clk); 1085 if (ret != 0) { 1086 dev_err(&pdev->dev, "I2C controller init failed\n"); 1087 clk_unprepare(i2c->clk); 1088 return ret; 1089 } 1090 1091 /* 1092 * find the IRQ for this unit (note, this relies on the init call to 1093 * ensure no current IRQs pending 1094 */ 1095 if (!(i2c->quirks & QUIRK_POLL)) { 1096 i2c->irq = ret = platform_get_irq(pdev, 0); 1097 if (ret < 0) { 1098 clk_unprepare(i2c->clk); 1099 return ret; 1100 } 1101 1102 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 1103 0, dev_name(&pdev->dev), i2c); 1104 if (ret != 0) { 1105 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); 1106 clk_unprepare(i2c->clk); 1107 return ret; 1108 } 1109 } 1110 1111 /* 1112 * Note, previous versions of the driver used i2c_add_adapter() 1113 * to add the bus at any number. We now pass the bus number via 1114 * the platform data, so if unset it will now default to always 1115 * being bus 0. 1116 */ 1117 i2c->adap.nr = i2c->pdata->bus_num; 1118 i2c->adap.dev.of_node = pdev->dev.of_node; 1119 1120 platform_set_drvdata(pdev, i2c); 1121 1122 pm_runtime_enable(&pdev->dev); 1123 1124 ret = i2c_add_numbered_adapter(&i2c->adap); 1125 if (ret < 0) { 1126 pm_runtime_disable(&pdev->dev); 1127 clk_unprepare(i2c->clk); 1128 return ret; 1129 } 1130 1131 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); 1132 return 0; 1133 } 1134 1135 static void s3c24xx_i2c_remove(struct platform_device *pdev) 1136 { 1137 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1138 1139 clk_unprepare(i2c->clk); 1140 1141 pm_runtime_disable(&pdev->dev); 1142 1143 i2c_del_adapter(&i2c->adap); 1144 } 1145 1146 static int s3c24xx_i2c_suspend_noirq(struct device *dev) 1147 { 1148 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev); 1149 1150 i2c_mark_adapter_suspended(&i2c->adap); 1151 1152 if (!IS_ERR(i2c->sysreg)) 1153 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg); 1154 1155 return 0; 1156 } 1157 1158 static int s3c24xx_i2c_resume_noirq(struct device *dev) 1159 { 1160 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev); 1161 int ret; 1162 1163 if (!IS_ERR(i2c->sysreg)) 1164 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg); 1165 1166 ret = clk_enable(i2c->clk); 1167 if (ret) 1168 return ret; 1169 s3c24xx_i2c_init(i2c); 1170 clk_disable(i2c->clk); 1171 i2c_mark_adapter_resumed(&i2c->adap); 1172 1173 return 0; 1174 } 1175 1176 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { 1177 NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq, 1178 s3c24xx_i2c_resume_noirq) 1179 }; 1180 1181 static struct platform_driver s3c24xx_i2c_driver = { 1182 .probe = s3c24xx_i2c_probe, 1183 .remove = s3c24xx_i2c_remove, 1184 .id_table = s3c24xx_driver_ids, 1185 .driver = { 1186 .name = "s3c-i2c", 1187 .pm = pm_sleep_ptr(&s3c24xx_i2c_dev_pm_ops), 1188 .of_match_table = of_match_ptr(s3c24xx_i2c_match), 1189 }, 1190 }; 1191 1192 static int __init i2c_adap_s3c_init(void) 1193 { 1194 return platform_driver_register(&s3c24xx_i2c_driver); 1195 } 1196 subsys_initcall(i2c_adap_s3c_init); 1197 1198 static void __exit i2c_adap_s3c_exit(void) 1199 { 1200 platform_driver_unregister(&s3c24xx_i2c_driver); 1201 } 1202 module_exit(i2c_adap_s3c_exit); 1203 1204 MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); 1205 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 1206 MODULE_LICENSE("GPL"); 1207