1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/bits.h> 4 #include <linux/clk.h> 5 #include <linux/i2c.h> 6 #include <linux/i2c-mux.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/mfd/syscon.h> 9 #include <linux/mutex.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 #include <linux/unaligned.h> 13 14 enum rtl9300_bus_freq { 15 RTL9300_I2C_STD_FREQ, // 100kHz 16 RTL9300_I2C_FAST_FREQ, // 400kHz 17 RTL9300_I2C_SUPER_FAST_FREQ, // 2.5MHz 18 RTL9300_I2C_SLOW_FREQ, // 50kHz 19 }; 20 21 #define RTL9300_I2C_MAX_SUPER_FAST_FREQ 2500000 22 #define RTL9300_I2C_MAX_SLOW_FREQ 50000 23 24 25 struct rtl9300_i2c; 26 27 struct rtl9300_i2c_chan { 28 struct i2c_adapter adap; 29 struct rtl9300_i2c *i2c; 30 enum rtl9300_bus_freq bus_freq; 31 u8 sda_num; 32 u32 clk_div; 33 }; 34 35 enum rtl9300_i2c_reg_scope { 36 REG_SCOPE_GLOBAL, 37 REG_SCOPE_MASTER, 38 }; 39 40 struct rtl9300_i2c_reg_field { 41 struct reg_field field; 42 enum rtl9300_i2c_reg_scope scope; 43 }; 44 45 enum rtl9300_i2c_reg_fields { 46 F_DATA_WIDTH = 0, 47 F_DEV_ADDR, 48 F_I2C_FAIL, 49 F_I2C_TRIG, 50 F_MEM_ADDR, 51 F_MEM_ADDR_WIDTH, 52 F_RD_MODE, 53 F_RWOP, 54 F_SCL_FREQ, 55 F_SCL_SEL, 56 F_SDA_OUT_SEL, 57 F_SDA_SEL, 58 F_BUSY, 59 F_CLK_DIV, 60 F_EXT_SCK_5MS, 61 62 /* keep last */ 63 F_NUM_FIELDS 64 }; 65 66 struct rtl9300_i2c_drv_data { 67 struct rtl9300_i2c_reg_field field_desc[F_NUM_FIELDS]; 68 int (*select_scl)(struct rtl9300_i2c *i2c, u8 scl); 69 int (*config_chan)(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan); 70 void (*config_clock)(u32 clock_freq, struct rtl9300_i2c_chan *chan); 71 int (*misc_init)(struct rtl9300_i2c *i2c); 72 u32 rd_reg; 73 u32 wd_reg; 74 u8 max_nchan; 75 u8 max_data_len; 76 u8 reg_addr_8bit_len; 77 }; 78 79 #define RTL9300_I2C_MUX_NCHAN 8 80 #define RTL9310_I2C_MUX_NCHAN 12 81 #define RTL9607_I2C_MUX_NCHAN 1 82 83 #define RTL9300_I2C_MAX_DATA_LEN 16 84 #define RTL9607_I2C_MAX_DATA_LEN 4 85 86 struct rtl9300_i2c { 87 struct regmap *regmap; 88 struct device *dev; 89 struct rtl9300_i2c_chan chans[RTL9310_I2C_MUX_NCHAN]; 90 struct regmap_field *fields[F_NUM_FIELDS]; 91 u32 reg_base; 92 u32 rd_reg; 93 u32 wd_reg; 94 u8 scl_num; 95 u8 sda_num; 96 struct mutex lock; 97 struct clk *clk; 98 }; 99 100 DEFINE_GUARD(rtl9300_i2c, struct rtl9300_i2c *, mutex_lock(&_T->lock), mutex_unlock(&_T->lock)) 101 102 enum rtl9300_i2c_xfer_type { 103 RTL9300_I2C_XFER_BYTE, 104 RTL9300_I2C_XFER_WORD, 105 RTL9300_I2C_XFER_BLOCK, 106 }; 107 108 struct rtl9300_i2c_xfer { 109 enum rtl9300_i2c_xfer_type type; 110 u16 dev_addr; 111 u8 reg_addr; 112 u8 reg_addr_len; 113 u8 *data; 114 u8 data_len; 115 bool write; 116 }; 117 118 #define RTL9300_I2C_MST_CTRL1 0x0 119 #define RTL9300_I2C_MST_CTRL2 0x4 120 #define RTL9300_I2C_MST_DATA_WORD0 0x8 121 #define RTL9300_I2C_MST_DATA_WORD1 0xc 122 #define RTL9300_I2C_MST_DATA_WORD2 0x10 123 #define RTL9300_I2C_MST_DATA_WORD3 0x14 124 #define RTL9300_I2C_MST_GLB_CTRL 0x384 125 #define RTL9300_REG_ADDR_8BIT_LEN 1 126 127 #define RTL9310_I2C_MST_IF_CTRL 0x1004 128 #define RTL9310_I2C_MST_IF_SEL 0x1008 129 #define RTL9310_I2C_MST_CTRL 0x0 130 #define RTL9310_I2C_MST_MEMADDR_CTRL 0x4 131 #define RTL9310_I2C_MST_DATA_CTRL 0x8 132 133 #define RTL9607_I2C_CONFIG 0x22f50 134 #define RTL9607_IO_MODE_EN 0x23014 135 #define RTL9607_I2C_IND_WD 0x0 136 #define RTL9607_I2C_IND_ADR 0x8 137 #define RTL9607_I2C_IND_CMD 0x10 138 #define RTL9607_I2C_IND_RD 0x18 139 #define RTL9607_REG_ADDR_8BIT_LEN 0 140 141 static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len) 142 { 143 int ret; 144 145 ret = regmap_field_write(i2c->fields[F_MEM_ADDR_WIDTH], len); 146 if (ret) 147 return ret; 148 149 return regmap_field_write(i2c->fields[F_MEM_ADDR], reg); 150 } 151 152 static int rtl9300_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl) 153 { 154 return regmap_field_write(i2c->fields[F_SCL_SEL], 1); 155 } 156 157 static int rtl9310_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl) 158 { 159 return regmap_field_update_bits(i2c->fields[F_SCL_SEL], BIT(scl), BIT(scl)); 160 } 161 162 static int rtl9300_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan) 163 { 164 const struct rtl9300_i2c_drv_data *drv_data; 165 int ret; 166 167 if (i2c->sda_num == chan->sda_num) 168 return 0; 169 170 ret = regmap_field_write(i2c->fields[F_SCL_FREQ], chan->bus_freq); 171 if (ret) 172 return ret; 173 174 drv_data = device_get_match_data(i2c->dev); 175 ret = drv_data->select_scl(i2c, i2c->scl_num); 176 if (ret) 177 return ret; 178 179 ret = regmap_field_update_bits(i2c->fields[F_SDA_SEL], BIT(chan->sda_num), 180 BIT(chan->sda_num)); 181 if (ret) 182 return ret; 183 184 ret = regmap_field_write(i2c->fields[F_SDA_OUT_SEL], chan->sda_num); 185 if (ret) 186 return ret; 187 188 i2c->sda_num = chan->sda_num; 189 return 0; 190 } 191 192 static int rtl9607_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan) 193 { 194 const struct rtl9300_i2c_drv_data *drv_data; 195 int ret; 196 197 if (i2c->sda_num == chan->sda_num) 198 return 0; 199 200 ret = regmap_field_write(i2c->fields[F_CLK_DIV], chan->clk_div); 201 if (ret) 202 return ret; 203 204 drv_data = device_get_match_data(i2c->dev); 205 ret = drv_data->select_scl(i2c, i2c->scl_num); 206 if (ret) 207 return ret; 208 209 i2c->sda_num = chan->sda_num; 210 return 0; 211 } 212 213 static void rtl9300_i2c_config_clock(u32 clock_freq, struct rtl9300_i2c_chan *chan) 214 { 215 struct rtl9300_i2c *i2c = chan->i2c; 216 217 switch (clock_freq) { 218 case I2C_MAX_STANDARD_MODE_FREQ: 219 chan->bus_freq = RTL9300_I2C_STD_FREQ; 220 break; 221 case I2C_MAX_FAST_MODE_FREQ: 222 chan->bus_freq = RTL9300_I2C_FAST_FREQ; 223 break; 224 case RTL9300_I2C_MAX_SUPER_FAST_FREQ: 225 chan->bus_freq = RTL9300_I2C_SUPER_FAST_FREQ; 226 break; 227 case RTL9300_I2C_MAX_SLOW_FREQ: 228 chan->bus_freq = RTL9300_I2C_SLOW_FREQ; 229 break; 230 default: 231 dev_warn(i2c->dev, "SDA%d clock-frequency %d not supported using default\n", 232 chan->sda_num, clock_freq); 233 break; 234 } 235 } 236 237 static void rtl9607_i2c_config_clock(u32 clock_freq, struct rtl9300_i2c_chan *chan) 238 { 239 struct rtl9300_i2c *i2c = chan->i2c; 240 241 chan->clk_div = clk_get_rate(i2c->clk) / clock_freq - 1; 242 } 243 244 static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, u8 len) 245 { 246 u32 vals[4] = {}; 247 int i, ret; 248 249 if (len > 16) 250 return -EIO; 251 252 ret = regmap_bulk_read(i2c->regmap, i2c->rd_reg, vals, ARRAY_SIZE(vals)); 253 if (ret) 254 return ret; 255 256 for (i = 0; i < len; i++) { 257 buf[i] = vals[i/4] & 0xff; 258 vals[i/4] >>= 8; 259 } 260 261 return 0; 262 } 263 264 static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, u8 len) 265 { 266 u32 vals[4] = {}; 267 int i; 268 269 if (len > 16) 270 return -EIO; 271 272 for (i = 0; i < len; i++) { 273 unsigned int shift = (i % 4) * 8; 274 unsigned int reg = i / 4; 275 276 vals[reg] |= buf[i] << shift; 277 } 278 279 return regmap_bulk_write(i2c->regmap, i2c->wd_reg, vals, ARRAY_SIZE(vals)); 280 } 281 282 static int rtl9300_i2c_writel(struct rtl9300_i2c *i2c, u32 data) 283 { 284 return regmap_write(i2c->regmap, i2c->wd_reg, data); 285 } 286 287 static int rtl9300_i2c_prepare_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_xfer *xfer) 288 { 289 const struct rtl9300_i2c_drv_data *drv_data; 290 int ret; 291 292 drv_data = device_get_match_data(i2c->dev); 293 if (xfer->data_len < 1 || xfer->data_len > drv_data->max_data_len) 294 return -EINVAL; 295 296 ret = regmap_field_write(i2c->fields[F_DEV_ADDR], xfer->dev_addr); 297 if (ret) 298 return ret; 299 300 ret = rtl9300_i2c_reg_addr_set(i2c, xfer->reg_addr, xfer->reg_addr_len); 301 if (ret) 302 return ret; 303 304 ret = regmap_field_write(i2c->fields[F_RWOP], xfer->write); 305 if (ret) 306 return ret; 307 308 ret = regmap_field_write(i2c->fields[F_DATA_WIDTH], (xfer->data_len - 1) & 0xf); 309 if (ret) 310 return ret; 311 312 if (xfer->write) { 313 switch (xfer->type) { 314 case RTL9300_I2C_XFER_BYTE: 315 ret = rtl9300_i2c_writel(i2c, *xfer->data); 316 break; 317 case RTL9300_I2C_XFER_WORD: 318 ret = rtl9300_i2c_writel(i2c, get_unaligned((const u16 *)xfer->data)); 319 break; 320 default: 321 ret = rtl9300_i2c_write(i2c, xfer->data, xfer->data_len); 322 break; 323 } 324 } 325 326 return ret; 327 } 328 329 static int rtl9300_i2c_do_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_xfer *xfer) 330 { 331 u32 val; 332 int ret; 333 334 ret = regmap_field_write(i2c->fields[F_I2C_TRIG], 1); 335 if (ret) 336 return ret; 337 338 ret = regmap_field_read_poll_timeout(i2c->fields[F_BUSY], val, !val, 100, 100000); 339 if (ret) 340 return ret; 341 342 ret = regmap_field_read(i2c->fields[F_I2C_FAIL], &val); 343 if (ret) 344 return ret; 345 if (val) 346 return -EIO; 347 348 if (!xfer->write) { 349 switch (xfer->type) { 350 case RTL9300_I2C_XFER_BYTE: 351 ret = regmap_read(i2c->regmap, i2c->rd_reg, &val); 352 if (ret) 353 return ret; 354 355 *xfer->data = val & 0xff; 356 break; 357 case RTL9300_I2C_XFER_WORD: 358 ret = regmap_read(i2c->regmap, i2c->rd_reg, &val); 359 if (ret) 360 return ret; 361 362 put_unaligned(val & 0xffff, (u16*)xfer->data); 363 break; 364 default: 365 ret = rtl9300_i2c_read(i2c, xfer->data, xfer->data_len); 366 if (ret) 367 return ret; 368 break; 369 } 370 } 371 372 return 0; 373 } 374 375 static int rtl9300_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, unsigned short flags, 376 char read_write, u8 command, int size, 377 union i2c_smbus_data *data) 378 { 379 struct rtl9300_i2c_chan *chan = i2c_get_adapdata(adap); 380 const struct rtl9300_i2c_drv_data *drv_data; 381 struct rtl9300_i2c *i2c = chan->i2c; 382 struct rtl9300_i2c_xfer xfer = {0}; 383 int ret; 384 385 if (addr > 0x7f) 386 return -EINVAL; 387 388 guard(rtl9300_i2c)(i2c); 389 390 drv_data = device_get_match_data(i2c->dev); 391 ret = drv_data->config_chan(i2c, chan); 392 if (ret) 393 return ret; 394 395 xfer.dev_addr = addr & 0x7f; 396 xfer.write = (read_write == I2C_SMBUS_WRITE); 397 xfer.reg_addr = command; 398 xfer.reg_addr_len = drv_data->reg_addr_8bit_len; 399 400 switch (size) { 401 case I2C_SMBUS_BYTE: 402 xfer.data = (read_write == I2C_SMBUS_READ) ? &data->byte : &command; 403 xfer.data_len = 1; 404 xfer.reg_addr = 0; 405 xfer.reg_addr_len = 0; 406 xfer.type = RTL9300_I2C_XFER_BYTE; 407 break; 408 case I2C_SMBUS_BYTE_DATA: 409 xfer.data = &data->byte; 410 xfer.data_len = 1; 411 xfer.type = RTL9300_I2C_XFER_BYTE; 412 break; 413 case I2C_SMBUS_WORD_DATA: 414 xfer.data = (u8 *)&data->word; 415 xfer.data_len = 2; 416 xfer.type = RTL9300_I2C_XFER_WORD; 417 break; 418 case I2C_SMBUS_BLOCK_DATA: 419 xfer.data = &data->block[0]; 420 xfer.data_len = data->block[0] + 1; 421 xfer.type = RTL9300_I2C_XFER_BLOCK; 422 break; 423 case I2C_SMBUS_I2C_BLOCK_DATA: 424 xfer.data = &data->block[1]; 425 xfer.data_len = data->block[0]; 426 xfer.type = RTL9300_I2C_XFER_BLOCK; 427 break; 428 default: 429 dev_err(&adap->dev, "Unsupported transaction %d\n", size); 430 return -EOPNOTSUPP; 431 } 432 433 ret = rtl9300_i2c_prepare_xfer(i2c, &xfer); 434 if (ret) 435 return ret; 436 437 return rtl9300_i2c_do_xfer(i2c, &xfer); 438 } 439 440 static u32 rtl9300_i2c_func(struct i2c_adapter *a) 441 { 442 return I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | 443 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA | 444 I2C_FUNC_SMBUS_I2C_BLOCK; 445 } 446 447 static const struct i2c_algorithm rtl9300_i2c_algo = { 448 .smbus_xfer = rtl9300_i2c_smbus_xfer, 449 .functionality = rtl9300_i2c_func, 450 }; 451 452 static struct i2c_adapter_quirks rtl9300_i2c_quirks = { 453 .flags = I2C_AQ_NO_CLK_STRETCH | I2C_AQ_NO_ZERO_LEN, 454 .max_read_len = 16, 455 .max_write_len = 16, 456 }; 457 458 static int rtl9300_i2c_init(struct rtl9300_i2c *i2c) 459 { 460 /* only use standard read format */ 461 return regmap_field_write(i2c->fields[F_RD_MODE], 0); 462 } 463 464 static int rtl9607_i2c_init(struct rtl9300_i2c *i2c) 465 { 466 return regmap_field_write(i2c->fields[F_EXT_SCK_5MS], 1); 467 } 468 469 static int rtl9300_i2c_probe(struct platform_device *pdev) 470 { 471 struct device *dev = &pdev->dev; 472 struct rtl9300_i2c *i2c; 473 const struct rtl9300_i2c_drv_data *drv_data; 474 struct reg_field fields[F_NUM_FIELDS]; 475 u32 clock_freq, scl_num, sda_num; 476 int ret, i = 0; 477 478 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); 479 if (!i2c) 480 return -ENOMEM; 481 482 i2c->regmap = syscon_node_to_regmap(dev->parent->of_node); 483 if (IS_ERR(i2c->regmap)) 484 return PTR_ERR(i2c->regmap); 485 i2c->dev = dev; 486 487 mutex_init(&i2c->lock); 488 489 ret = device_property_read_u32(dev, "reg", &i2c->reg_base); 490 if (ret) 491 return ret; 492 493 ret = device_property_read_u32(dev, "realtek,scl", &scl_num); 494 if (ret || scl_num != 1) 495 scl_num = 0; 496 i2c->scl_num = (u8)scl_num; 497 498 platform_set_drvdata(pdev, i2c); 499 500 drv_data = device_get_match_data(i2c->dev); 501 if (device_get_child_node_count(dev) > drv_data->max_nchan) 502 return dev_err_probe(dev, -EINVAL, "Too many channels\n"); 503 504 i2c->rd_reg = i2c->reg_base + drv_data->rd_reg; 505 i2c->wd_reg = i2c->reg_base + drv_data->wd_reg; 506 for (i = 0; i < F_NUM_FIELDS; i++) { 507 fields[i] = drv_data->field_desc[i].field; 508 if (drv_data->field_desc[i].scope == REG_SCOPE_MASTER) 509 fields[i].reg += i2c->reg_base; 510 } 511 ret = devm_regmap_field_bulk_alloc(dev, i2c->regmap, i2c->fields, 512 fields, F_NUM_FIELDS); 513 if (ret) 514 return ret; 515 516 i2c->clk = devm_clk_get_optional_enabled(dev, NULL); 517 if (IS_ERR(i2c->clk)) 518 return dev_err_probe(dev, PTR_ERR(i2c->clk), "Failed to enable i2c clock\n"); 519 520 i = 0; 521 for_each_child_of_node_scoped(dev->of_node, child) { 522 struct rtl9300_i2c_chan *chan = &i2c->chans[i]; 523 struct i2c_adapter *adap = &chan->adap; 524 525 ret = of_property_read_u32(child, "reg", &sda_num); 526 if (ret) 527 return ret; 528 529 ret = of_property_read_u32(child, "clock-frequency", &clock_freq); 530 if (ret) 531 clock_freq = I2C_MAX_STANDARD_MODE_FREQ; 532 533 chan->sda_num = sda_num; 534 chan->i2c = i2c; 535 536 drv_data->config_clock(clock_freq, chan); 537 538 adap = &i2c->chans[i].adap; 539 adap->owner = THIS_MODULE; 540 adap->algo = &rtl9300_i2c_algo; 541 adap->quirks = &rtl9300_i2c_quirks; 542 adap->retries = 3; 543 adap->dev.parent = dev; 544 i2c_set_adapdata(adap, chan); 545 adap->dev.of_node = child; 546 snprintf(adap->name, sizeof(adap->name), "%s SDA%d\n", dev_name(dev), sda_num); 547 i++; 548 549 ret = devm_i2c_add_adapter(dev, adap); 550 if (ret) 551 return ret; 552 } 553 i2c->sda_num = 0xff; 554 555 ret = drv_data->misc_init(i2c); 556 if (ret) 557 return ret; 558 559 return 0; 560 } 561 562 #define GLB_REG_FIELD(reg, msb, lsb) \ 563 { .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_GLOBAL } 564 #define MST_REG_FIELD(reg, msb, lsb) \ 565 { .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_MASTER } 566 567 static const struct rtl9300_i2c_drv_data rtl9300_i2c_drv_data = { 568 .field_desc = { 569 [F_MEM_ADDR] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 8, 31), 570 [F_SDA_OUT_SEL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 4, 6), 571 [F_SCL_SEL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 3, 3), 572 [F_RWOP] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 2, 2), 573 [F_I2C_FAIL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 1, 1), 574 [F_I2C_TRIG] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 0, 0), 575 [F_RD_MODE] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 15, 15), 576 [F_DEV_ADDR] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 8, 14), 577 [F_DATA_WIDTH] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 4, 7), 578 [F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 2, 3), 579 [F_SCL_FREQ] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 0, 1), 580 [F_SDA_SEL] = GLB_REG_FIELD(RTL9300_I2C_MST_GLB_CTRL, 0, 7), 581 [F_BUSY] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 0, 0), 582 }, 583 .select_scl = rtl9300_i2c_select_scl, 584 .config_chan = rtl9300_i2c_config_chan, 585 .config_clock = rtl9300_i2c_config_clock, 586 .misc_init = rtl9300_i2c_init, 587 .rd_reg = RTL9300_I2C_MST_DATA_WORD0, 588 .wd_reg = RTL9300_I2C_MST_DATA_WORD0, 589 .max_nchan = RTL9300_I2C_MUX_NCHAN, 590 .max_data_len = RTL9300_I2C_MAX_DATA_LEN, 591 .reg_addr_8bit_len = RTL9300_REG_ADDR_8BIT_LEN, 592 }; 593 594 static const struct rtl9300_i2c_drv_data rtl9310_i2c_drv_data = { 595 .field_desc = { 596 [F_SCL_SEL] = GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 12, 13), 597 [F_SDA_SEL] = GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 0, 11), 598 [F_SCL_FREQ] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 30, 31), 599 [F_DEV_ADDR] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 11, 17), 600 [F_SDA_OUT_SEL] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 18, 21), 601 [F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 9, 10), 602 [F_DATA_WIDTH] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 5, 8), 603 [F_RD_MODE] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 4, 4), 604 [F_RWOP] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 2, 2), 605 [F_I2C_FAIL] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 1, 1), 606 [F_I2C_TRIG] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 0, 0), 607 [F_MEM_ADDR] = MST_REG_FIELD(RTL9310_I2C_MST_MEMADDR_CTRL, 0, 23), 608 [F_BUSY] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 0, 0), 609 }, 610 .select_scl = rtl9310_i2c_select_scl, 611 .config_chan = rtl9300_i2c_config_chan, 612 .config_clock = rtl9300_i2c_config_clock, 613 .misc_init = rtl9300_i2c_init, 614 .rd_reg = RTL9310_I2C_MST_DATA_CTRL, 615 .wd_reg = RTL9310_I2C_MST_DATA_CTRL, 616 .max_nchan = RTL9310_I2C_MUX_NCHAN, 617 .max_data_len = RTL9300_I2C_MAX_DATA_LEN, 618 .reg_addr_8bit_len = RTL9300_REG_ADDR_8BIT_LEN, 619 }; 620 621 static const struct rtl9300_i2c_drv_data rtl9607_i2c_drv_data = { 622 .field_desc = { 623 [F_SCL_SEL] = GLB_REG_FIELD(RTL9607_IO_MODE_EN, 13, 14), 624 [F_EXT_SCK_5MS] = MST_REG_FIELD(RTL9607_I2C_CONFIG, 26, 26), 625 [F_DEV_ADDR] = MST_REG_FIELD(RTL9607_I2C_CONFIG, 14, 20), 626 [F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9607_I2C_CONFIG, 12, 13), 627 [F_DATA_WIDTH] = MST_REG_FIELD(RTL9607_I2C_CONFIG, 10, 11), 628 [F_CLK_DIV] = MST_REG_FIELD(RTL9607_I2C_CONFIG, 0, 9), 629 [F_I2C_FAIL] = MST_REG_FIELD(RTL9607_I2C_IND_CMD, 3, 3), 630 [F_BUSY] = MST_REG_FIELD(RTL9607_I2C_IND_CMD, 2, 2), 631 [F_RWOP] = MST_REG_FIELD(RTL9607_I2C_IND_CMD, 1, 1), 632 [F_I2C_TRIG] = MST_REG_FIELD(RTL9607_I2C_IND_CMD, 0, 0), 633 [F_MEM_ADDR] = MST_REG_FIELD(RTL9607_I2C_IND_ADR, 0, 31), 634 }, 635 .select_scl = rtl9310_i2c_select_scl, 636 .config_chan = rtl9607_i2c_config_chan, 637 .config_clock = rtl9607_i2c_config_clock, 638 .misc_init = rtl9607_i2c_init, 639 .rd_reg = RTL9607_I2C_IND_RD, 640 .wd_reg = RTL9607_I2C_IND_WD, 641 .max_nchan = RTL9607_I2C_MUX_NCHAN, 642 .max_data_len = RTL9607_I2C_MAX_DATA_LEN, 643 .reg_addr_8bit_len = RTL9607_REG_ADDR_8BIT_LEN, 644 }; 645 646 static const struct of_device_id i2c_rtl9300_dt_ids[] = { 647 { .compatible = "realtek,rtl9301-i2c", .data = (void *) &rtl9300_i2c_drv_data }, 648 { .compatible = "realtek,rtl9302b-i2c", .data = (void *) &rtl9300_i2c_drv_data }, 649 { .compatible = "realtek,rtl9302c-i2c", .data = (void *) &rtl9300_i2c_drv_data }, 650 { .compatible = "realtek,rtl9303-i2c", .data = (void *) &rtl9300_i2c_drv_data }, 651 { .compatible = "realtek,rtl9310-i2c", .data = (void *) &rtl9310_i2c_drv_data }, 652 { .compatible = "realtek,rtl9311-i2c", .data = (void *) &rtl9310_i2c_drv_data }, 653 { .compatible = "realtek,rtl9312-i2c", .data = (void *) &rtl9310_i2c_drv_data }, 654 { .compatible = "realtek,rtl9313-i2c", .data = (void *) &rtl9310_i2c_drv_data }, 655 { .compatible = "realtek,rtl9607-i2c", .data = (void *) &rtl9607_i2c_drv_data }, 656 {} 657 }; 658 MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids); 659 660 static struct platform_driver rtl9300_i2c_driver = { 661 .probe = rtl9300_i2c_probe, 662 .driver = { 663 .name = "i2c-rtl9300", 664 .of_match_table = i2c_rtl9300_dt_ids, 665 }, 666 }; 667 668 module_platform_driver(rtl9300_i2c_driver); 669 670 MODULE_DESCRIPTION("RTL9300 I2C controller driver"); 671 MODULE_LICENSE("GPL"); 672