1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/bits.h> 4 #include <linux/i2c.h> 5 #include <linux/i2c-mux.h> 6 #include <linux/mod_devicetable.h> 7 #include <linux/mfd/syscon.h> 8 #include <linux/mutex.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 enum rtl9300_bus_freq { 13 RTL9300_I2C_STD_FREQ, 14 RTL9300_I2C_FAST_FREQ, 15 }; 16 17 struct rtl9300_i2c; 18 19 struct rtl9300_i2c_chan { 20 struct i2c_adapter adap; 21 struct rtl9300_i2c *i2c; 22 enum rtl9300_bus_freq bus_freq; 23 u8 sda_pin; 24 }; 25 26 #define RTL9300_I2C_MUX_NCHAN 8 27 28 struct rtl9300_i2c { 29 struct regmap *regmap; 30 struct device *dev; 31 struct rtl9300_i2c_chan chans[RTL9300_I2C_MUX_NCHAN]; 32 u32 reg_base; 33 u8 sda_pin; 34 struct mutex lock; 35 }; 36 37 #define RTL9300_I2C_MST_CTRL1 0x0 38 #define RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS 8 39 #define RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK GENMASK(31, 8) 40 #define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS 4 41 #define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK GENMASK(6, 4) 42 #define RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL BIT(3) 43 #define RTL9300_I2C_MST_CTRL1_RWOP BIT(2) 44 #define RTL9300_I2C_MST_CTRL1_I2C_FAIL BIT(1) 45 #define RTL9300_I2C_MST_CTRL1_I2C_TRIG BIT(0) 46 #define RTL9300_I2C_MST_CTRL2 0x4 47 #define RTL9300_I2C_MST_CTRL2_RD_MODE BIT(15) 48 #define RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS 8 49 #define RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK GENMASK(14, 8) 50 #define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS 4 51 #define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK GENMASK(7, 4) 52 #define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS 2 53 #define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK GENMASK(3, 2) 54 #define RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS 0 55 #define RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK GENMASK(1, 0) 56 #define RTL9300_I2C_MST_DATA_WORD0 0x8 57 #define RTL9300_I2C_MST_DATA_WORD1 0xc 58 #define RTL9300_I2C_MST_DATA_WORD2 0x10 59 #define RTL9300_I2C_MST_DATA_WORD3 0x14 60 61 #define RTL9300_I2C_MST_GLB_CTRL 0x384 62 63 static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len) 64 { 65 u32 val, mask; 66 int ret; 67 68 val = len << RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS; 69 mask = RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK; 70 71 ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val); 72 if (ret) 73 return ret; 74 75 val = reg << RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS; 76 mask = RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK; 77 78 return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val); 79 } 80 81 static int rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, u8 sda_pin) 82 { 83 int ret; 84 u32 val, mask; 85 86 ret = regmap_update_bits(i2c->regmap, RTL9300_I2C_MST_GLB_CTRL, BIT(sda_pin), BIT(sda_pin)); 87 if (ret) 88 return ret; 89 90 val = (sda_pin << RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS) | 91 RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL; 92 mask = RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK | RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL; 93 94 return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val); 95 } 96 97 static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan, 98 u16 addr, u16 len) 99 { 100 u32 val, mask; 101 102 val = chan->bus_freq << RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS; 103 mask = RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK; 104 105 val |= addr << RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS; 106 mask |= RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK; 107 108 val |= ((len - 1) & 0xf) << RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS; 109 mask |= RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK; 110 111 mask |= RTL9300_I2C_MST_CTRL2_RD_MODE; 112 113 return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val); 114 } 115 116 static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len) 117 { 118 u32 vals[4] = {}; 119 int i, ret; 120 121 if (len > 16) 122 return -EIO; 123 124 ret = regmap_bulk_read(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, 125 vals, ARRAY_SIZE(vals)); 126 if (ret) 127 return ret; 128 129 for (i = 0; i < len; i++) { 130 buf[i] = vals[i/4] & 0xff; 131 vals[i/4] >>= 8; 132 } 133 134 return 0; 135 } 136 137 static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len) 138 { 139 u32 vals[4] = {}; 140 int i; 141 142 if (len > 16) 143 return -EIO; 144 145 for (i = 0; i < len; i++) { 146 if (i % 4 == 0) 147 vals[i/4] = 0; 148 vals[i/4] <<= 8; 149 vals[i/4] |= buf[i]; 150 } 151 152 return regmap_bulk_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, 153 vals, ARRAY_SIZE(vals)); 154 } 155 156 static int rtl9300_i2c_writel(struct rtl9300_i2c *i2c, u32 data) 157 { 158 return regmap_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, data); 159 } 160 161 static int rtl9300_i2c_execute_xfer(struct rtl9300_i2c *i2c, char read_write, 162 int size, union i2c_smbus_data *data, int len) 163 { 164 u32 val, mask; 165 int ret; 166 167 val = read_write == I2C_SMBUS_WRITE ? RTL9300_I2C_MST_CTRL1_RWOP : 0; 168 mask = RTL9300_I2C_MST_CTRL1_RWOP; 169 170 val |= RTL9300_I2C_MST_CTRL1_I2C_TRIG; 171 mask |= RTL9300_I2C_MST_CTRL1_I2C_TRIG; 172 173 ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val); 174 if (ret) 175 return ret; 176 177 ret = regmap_read_poll_timeout(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, 178 val, !(val & RTL9300_I2C_MST_CTRL1_I2C_TRIG), 100, 2000); 179 if (ret) 180 return ret; 181 182 if (val & RTL9300_I2C_MST_CTRL1_I2C_FAIL) 183 return -EIO; 184 185 if (read_write == I2C_SMBUS_READ) { 186 if (size == I2C_SMBUS_BYTE || size == I2C_SMBUS_BYTE_DATA) { 187 ret = regmap_read(i2c->regmap, 188 i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val); 189 if (ret) 190 return ret; 191 data->byte = val & 0xff; 192 } else if (size == I2C_SMBUS_WORD_DATA) { 193 ret = regmap_read(i2c->regmap, 194 i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val); 195 if (ret) 196 return ret; 197 data->word = val & 0xffff; 198 } else { 199 ret = rtl9300_i2c_read(i2c, &data->block[0], len); 200 if (ret) 201 return ret; 202 } 203 } 204 205 return 0; 206 } 207 208 static int rtl9300_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, unsigned short flags, 209 char read_write, u8 command, int size, 210 union i2c_smbus_data *data) 211 { 212 struct rtl9300_i2c_chan *chan = i2c_get_adapdata(adap); 213 struct rtl9300_i2c *i2c = chan->i2c; 214 int len = 0, ret; 215 216 mutex_lock(&i2c->lock); 217 if (chan->sda_pin != i2c->sda_pin) { 218 ret = rtl9300_i2c_config_io(i2c, chan->sda_pin); 219 if (ret) 220 goto out_unlock; 221 i2c->sda_pin = chan->sda_pin; 222 } 223 224 switch (size) { 225 case I2C_SMBUS_QUICK: 226 ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 0); 227 if (ret) 228 goto out_unlock; 229 ret = rtl9300_i2c_reg_addr_set(i2c, 0, 0); 230 if (ret) 231 goto out_unlock; 232 break; 233 234 case I2C_SMBUS_BYTE: 235 if (read_write == I2C_SMBUS_WRITE) { 236 ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 0); 237 if (ret) 238 goto out_unlock; 239 ret = rtl9300_i2c_reg_addr_set(i2c, command, 1); 240 if (ret) 241 goto out_unlock; 242 } else { 243 ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 1); 244 if (ret) 245 goto out_unlock; 246 ret = rtl9300_i2c_reg_addr_set(i2c, 0, 0); 247 if (ret) 248 goto out_unlock; 249 } 250 break; 251 252 case I2C_SMBUS_BYTE_DATA: 253 ret = rtl9300_i2c_reg_addr_set(i2c, command, 1); 254 if (ret) 255 goto out_unlock; 256 ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 1); 257 if (ret) 258 goto out_unlock; 259 if (read_write == I2C_SMBUS_WRITE) { 260 ret = rtl9300_i2c_writel(i2c, data->byte); 261 if (ret) 262 goto out_unlock; 263 } 264 break; 265 266 case I2C_SMBUS_WORD_DATA: 267 ret = rtl9300_i2c_reg_addr_set(i2c, command, 1); 268 if (ret) 269 goto out_unlock; 270 ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 2); 271 if (ret) 272 goto out_unlock; 273 if (read_write == I2C_SMBUS_WRITE) { 274 ret = rtl9300_i2c_writel(i2c, data->word); 275 if (ret) 276 goto out_unlock; 277 } 278 break; 279 280 case I2C_SMBUS_BLOCK_DATA: 281 ret = rtl9300_i2c_reg_addr_set(i2c, command, 1); 282 if (ret) 283 goto out_unlock; 284 ret = rtl9300_i2c_config_xfer(i2c, chan, addr, data->block[0]); 285 if (ret) 286 goto out_unlock; 287 if (read_write == I2C_SMBUS_WRITE) { 288 ret = rtl9300_i2c_write(i2c, &data->block[1], data->block[0]); 289 if (ret) 290 goto out_unlock; 291 } 292 len = data->block[0]; 293 break; 294 295 default: 296 dev_err(&adap->dev, "Unsupported transaction %d\n", size); 297 ret = -EOPNOTSUPP; 298 goto out_unlock; 299 } 300 301 ret = rtl9300_i2c_execute_xfer(i2c, read_write, size, data, len); 302 303 out_unlock: 304 mutex_unlock(&i2c->lock); 305 306 return ret; 307 } 308 309 static u32 rtl9300_i2c_func(struct i2c_adapter *a) 310 { 311 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 312 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 313 I2C_FUNC_SMBUS_BLOCK_DATA; 314 } 315 316 static const struct i2c_algorithm rtl9300_i2c_algo = { 317 .smbus_xfer = rtl9300_i2c_smbus_xfer, 318 .functionality = rtl9300_i2c_func, 319 }; 320 321 static struct i2c_adapter_quirks rtl9300_i2c_quirks = { 322 .flags = I2C_AQ_NO_CLK_STRETCH, 323 .max_read_len = 16, 324 .max_write_len = 16, 325 }; 326 327 static int rtl9300_i2c_probe(struct platform_device *pdev) 328 { 329 struct device *dev = &pdev->dev; 330 struct rtl9300_i2c *i2c; 331 u32 clock_freq, sda_pin; 332 int ret, i = 0; 333 struct fwnode_handle *child; 334 335 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); 336 if (!i2c) 337 return -ENOMEM; 338 339 i2c->regmap = syscon_node_to_regmap(dev->parent->of_node); 340 if (IS_ERR(i2c->regmap)) 341 return PTR_ERR(i2c->regmap); 342 i2c->dev = dev; 343 344 mutex_init(&i2c->lock); 345 346 ret = device_property_read_u32(dev, "reg", &i2c->reg_base); 347 if (ret) 348 return ret; 349 350 platform_set_drvdata(pdev, i2c); 351 352 if (device_get_child_node_count(dev) >= RTL9300_I2C_MUX_NCHAN) 353 return dev_err_probe(dev, -EINVAL, "Too many channels\n"); 354 355 device_for_each_child_node(dev, child) { 356 struct rtl9300_i2c_chan *chan = &i2c->chans[i]; 357 struct i2c_adapter *adap = &chan->adap; 358 359 ret = fwnode_property_read_u32(child, "reg", &sda_pin); 360 if (ret) 361 return ret; 362 363 ret = fwnode_property_read_u32(child, "clock-frequency", &clock_freq); 364 if (ret) 365 clock_freq = I2C_MAX_STANDARD_MODE_FREQ; 366 367 switch (clock_freq) { 368 case I2C_MAX_STANDARD_MODE_FREQ: 369 chan->bus_freq = RTL9300_I2C_STD_FREQ; 370 break; 371 372 case I2C_MAX_FAST_MODE_FREQ: 373 chan->bus_freq = RTL9300_I2C_FAST_FREQ; 374 break; 375 default: 376 dev_warn(i2c->dev, "SDA%d clock-frequency %d not supported using default\n", 377 sda_pin, clock_freq); 378 break; 379 } 380 381 chan->sda_pin = sda_pin; 382 chan->i2c = i2c; 383 adap = &i2c->chans[i].adap; 384 adap->owner = THIS_MODULE; 385 adap->algo = &rtl9300_i2c_algo; 386 adap->quirks = &rtl9300_i2c_quirks; 387 adap->retries = 3; 388 adap->dev.parent = dev; 389 i2c_set_adapdata(adap, chan); 390 adap->dev.of_node = to_of_node(child); 391 snprintf(adap->name, sizeof(adap->name), "%s SDA%d\n", dev_name(dev), sda_pin); 392 i++; 393 394 ret = devm_i2c_add_adapter(dev, adap); 395 if (ret) 396 return ret; 397 } 398 i2c->sda_pin = 0xff; 399 400 return 0; 401 } 402 403 static const struct of_device_id i2c_rtl9300_dt_ids[] = { 404 { .compatible = "realtek,rtl9301-i2c" }, 405 { .compatible = "realtek,rtl9302b-i2c" }, 406 { .compatible = "realtek,rtl9302c-i2c" }, 407 { .compatible = "realtek,rtl9303-i2c" }, 408 {} 409 }; 410 MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids); 411 412 static struct platform_driver rtl9300_i2c_driver = { 413 .probe = rtl9300_i2c_probe, 414 .driver = { 415 .name = "i2c-rtl9300", 416 .of_match_table = i2c_rtl9300_dt_ids, 417 }, 418 }; 419 420 module_platform_driver(rtl9300_i2c_driver); 421 422 MODULE_DESCRIPTION("RTL9300 I2C controller driver"); 423 MODULE_LICENSE("GPL"); 424