1 /* 2 * Driver for I2C adapter in Rockchip RK3xxx SoC 3 * 4 * Max Schwarz <max.schwarz@online.de> 5 * based on the patches by Rockchip Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/i2c.h> 15 #include <linux/interrupt.h> 16 #include <linux/errno.h> 17 #include <linux/err.h> 18 #include <linux/platform_device.h> 19 #include <linux/io.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/spinlock.h> 23 #include <linux/clk.h> 24 #include <linux/wait.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/regmap.h> 27 #include <linux/math64.h> 28 29 30 /* Register Map */ 31 #define REG_CON 0x00 /* control register */ 32 #define REG_CLKDIV 0x04 /* clock divisor register */ 33 #define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */ 34 #define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */ 35 #define REG_MTXCNT 0x10 /* number of bytes to be transmitted */ 36 #define REG_MRXCNT 0x14 /* number of bytes to be received */ 37 #define REG_IEN 0x18 /* interrupt enable */ 38 #define REG_IPD 0x1c /* interrupt pending */ 39 #define REG_FCNT 0x20 /* finished count */ 40 41 /* Data buffer offsets */ 42 #define TXBUFFER_BASE 0x100 43 #define RXBUFFER_BASE 0x200 44 45 /* REG_CON bits */ 46 #define REG_CON_EN BIT(0) 47 enum { 48 REG_CON_MOD_TX = 0, /* transmit data */ 49 REG_CON_MOD_REGISTER_TX, /* select register and restart */ 50 REG_CON_MOD_RX, /* receive data */ 51 REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes 52 * register addr */ 53 }; 54 #define REG_CON_MOD(mod) ((mod) << 1) 55 #define REG_CON_MOD_MASK (BIT(1) | BIT(2)) 56 #define REG_CON_START BIT(3) 57 #define REG_CON_STOP BIT(4) 58 #define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */ 59 #define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */ 60 61 #define REG_CON_TUNING_MASK GENMASK_ULL(15, 8) 62 63 #define REG_CON_SDA_CFG(cfg) ((cfg) << 8) 64 #define REG_CON_STA_CFG(cfg) ((cfg) << 12) 65 #define REG_CON_STO_CFG(cfg) ((cfg) << 14) 66 67 /* REG_MRXADDR bits */ 68 #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */ 69 70 /* REG_IEN/REG_IPD bits */ 71 #define REG_INT_BTF BIT(0) /* a byte was transmitted */ 72 #define REG_INT_BRF BIT(1) /* a byte was received */ 73 #define REG_INT_MBTF BIT(2) /* master data transmit finished */ 74 #define REG_INT_MBRF BIT(3) /* master data receive finished */ 75 #define REG_INT_START BIT(4) /* START condition generated */ 76 #define REG_INT_STOP BIT(5) /* STOP condition generated */ 77 #define REG_INT_NAKRCV BIT(6) /* NACK received */ 78 #define REG_INT_ALL 0x7f 79 80 /* Constants */ 81 #define WAIT_TIMEOUT 1000 /* ms */ 82 #define DEFAULT_SCL_RATE (100 * 1000) /* Hz */ 83 84 /** 85 * struct i2c_spec_values: 86 * @min_hold_start_ns: min hold time (repeated) START condition 87 * @min_low_ns: min LOW period of the SCL clock 88 * @min_high_ns: min HIGH period of the SCL cloc 89 * @min_setup_start_ns: min set-up time for a repeated START conditio 90 * @max_data_hold_ns: max data hold time 91 * @min_data_setup_ns: min data set-up time 92 * @min_setup_stop_ns: min set-up time for STOP condition 93 * @min_hold_buffer_ns: min bus free time between a STOP and 94 * START condition 95 */ 96 struct i2c_spec_values { 97 unsigned long min_hold_start_ns; 98 unsigned long min_low_ns; 99 unsigned long min_high_ns; 100 unsigned long min_setup_start_ns; 101 unsigned long max_data_hold_ns; 102 unsigned long min_data_setup_ns; 103 unsigned long min_setup_stop_ns; 104 unsigned long min_hold_buffer_ns; 105 }; 106 107 static const struct i2c_spec_values standard_mode_spec = { 108 .min_hold_start_ns = 4000, 109 .min_low_ns = 4700, 110 .min_high_ns = 4000, 111 .min_setup_start_ns = 4700, 112 .max_data_hold_ns = 3450, 113 .min_data_setup_ns = 250, 114 .min_setup_stop_ns = 4000, 115 .min_hold_buffer_ns = 4700, 116 }; 117 118 static const struct i2c_spec_values fast_mode_spec = { 119 .min_hold_start_ns = 600, 120 .min_low_ns = 1300, 121 .min_high_ns = 600, 122 .min_setup_start_ns = 600, 123 .max_data_hold_ns = 900, 124 .min_data_setup_ns = 100, 125 .min_setup_stop_ns = 600, 126 .min_hold_buffer_ns = 1300, 127 }; 128 129 static const struct i2c_spec_values fast_mode_plus_spec = { 130 .min_hold_start_ns = 260, 131 .min_low_ns = 500, 132 .min_high_ns = 260, 133 .min_setup_start_ns = 260, 134 .max_data_hold_ns = 400, 135 .min_data_setup_ns = 50, 136 .min_setup_stop_ns = 260, 137 .min_hold_buffer_ns = 500, 138 }; 139 140 /** 141 * struct rk3x_i2c_calced_timings: 142 * @div_low: Divider output for low 143 * @div_high: Divider output for high 144 * @tuning: Used to adjust setup/hold data time, 145 * setup/hold start time and setup stop time for 146 * v1's calc_timings, the tuning should all be 0 147 * for old hardware anyone using v0's calc_timings. 148 */ 149 struct rk3x_i2c_calced_timings { 150 unsigned long div_low; 151 unsigned long div_high; 152 unsigned int tuning; 153 }; 154 155 enum rk3x_i2c_state { 156 STATE_IDLE, 157 STATE_START, 158 STATE_READ, 159 STATE_WRITE, 160 STATE_STOP 161 }; 162 163 /** 164 * struct rk3x_i2c_soc_data: 165 * @grf_offset: offset inside the grf regmap for setting the i2c type 166 * @calc_timings: Callback function for i2c timing information calculated 167 */ 168 struct rk3x_i2c_soc_data { 169 int grf_offset; 170 int (*calc_timings)(unsigned long, struct i2c_timings *, 171 struct rk3x_i2c_calced_timings *); 172 }; 173 174 /** 175 * struct rk3x_i2c - private data of the controller 176 * @adap: corresponding I2C adapter 177 * @dev: device for this controller 178 * @soc_data: related soc data struct 179 * @regs: virtual memory area 180 * @clk: function clk for rk3399 or function & Bus clks for others 181 * @pclk: Bus clk for rk3399 182 * @clk_rate_nb: i2c clk rate change notify 183 * @t: I2C known timing information 184 * @lock: spinlock for the i2c bus 185 * @wait: the waitqueue to wait for i2c transfer 186 * @busy: the condition for the event to wait for 187 * @msg: current i2c message 188 * @addr: addr of i2c slave device 189 * @mode: mode of i2c transfer 190 * @is_last_msg: flag determines whether it is the last msg in this transfer 191 * @state: state of i2c transfer 192 * @processed: byte length which has been send or received 193 * @error: error code for i2c transfer 194 */ 195 struct rk3x_i2c { 196 struct i2c_adapter adap; 197 struct device *dev; 198 const struct rk3x_i2c_soc_data *soc_data; 199 200 /* Hardware resources */ 201 void __iomem *regs; 202 struct clk *clk; 203 struct clk *pclk; 204 struct notifier_block clk_rate_nb; 205 206 /* Settings */ 207 struct i2c_timings t; 208 209 /* Synchronization & notification */ 210 spinlock_t lock; 211 wait_queue_head_t wait; 212 bool busy; 213 214 /* Current message */ 215 struct i2c_msg *msg; 216 u8 addr; 217 unsigned int mode; 218 bool is_last_msg; 219 220 /* I2C state machine */ 221 enum rk3x_i2c_state state; 222 unsigned int processed; 223 int error; 224 }; 225 226 static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value, 227 unsigned int offset) 228 { 229 writel(value, i2c->regs + offset); 230 } 231 232 static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset) 233 { 234 return readl(i2c->regs + offset); 235 } 236 237 /* Reset all interrupt pending bits */ 238 static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c) 239 { 240 i2c_writel(i2c, REG_INT_ALL, REG_IPD); 241 } 242 243 /** 244 * Generate a START condition, which triggers a REG_INT_START interrupt. 245 */ 246 static void rk3x_i2c_start(struct rk3x_i2c *i2c) 247 { 248 u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK; 249 250 i2c_writel(i2c, REG_INT_START, REG_IEN); 251 252 /* enable adapter with correct mode, send START condition */ 253 val |= REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START; 254 255 /* if we want to react to NACK, set ACTACK bit */ 256 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) 257 val |= REG_CON_ACTACK; 258 259 i2c_writel(i2c, val, REG_CON); 260 } 261 262 /** 263 * Generate a STOP condition, which triggers a REG_INT_STOP interrupt. 264 * 265 * @error: Error code to return in rk3x_i2c_xfer 266 */ 267 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error) 268 { 269 unsigned int ctrl; 270 271 i2c->processed = 0; 272 i2c->msg = NULL; 273 i2c->error = error; 274 275 if (i2c->is_last_msg) { 276 /* Enable stop interrupt */ 277 i2c_writel(i2c, REG_INT_STOP, REG_IEN); 278 279 i2c->state = STATE_STOP; 280 281 ctrl = i2c_readl(i2c, REG_CON); 282 ctrl |= REG_CON_STOP; 283 i2c_writel(i2c, ctrl, REG_CON); 284 } else { 285 /* Signal rk3x_i2c_xfer to start the next message. */ 286 i2c->busy = false; 287 i2c->state = STATE_IDLE; 288 289 /* 290 * The HW is actually not capable of REPEATED START. But we can 291 * get the intended effect by resetting its internal state 292 * and issuing an ordinary START. 293 */ 294 ctrl = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK; 295 i2c_writel(i2c, ctrl, REG_CON); 296 297 /* signal that we are finished with the current msg */ 298 wake_up(&i2c->wait); 299 } 300 } 301 302 /** 303 * Setup a read according to i2c->msg 304 */ 305 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c) 306 { 307 unsigned int len = i2c->msg->len - i2c->processed; 308 u32 con; 309 310 con = i2c_readl(i2c, REG_CON); 311 312 /* 313 * The hw can read up to 32 bytes at a time. If we need more than one 314 * chunk, send an ACK after the last byte of the current chunk. 315 */ 316 if (len > 32) { 317 len = 32; 318 con &= ~REG_CON_LASTACK; 319 } else { 320 con |= REG_CON_LASTACK; 321 } 322 323 /* make sure we are in plain RX mode if we read a second chunk */ 324 if (i2c->processed != 0) { 325 con &= ~REG_CON_MOD_MASK; 326 con |= REG_CON_MOD(REG_CON_MOD_RX); 327 } 328 329 i2c_writel(i2c, con, REG_CON); 330 i2c_writel(i2c, len, REG_MRXCNT); 331 } 332 333 /** 334 * Fill the transmit buffer with data from i2c->msg 335 */ 336 static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c) 337 { 338 unsigned int i, j; 339 u32 cnt = 0; 340 u32 val; 341 u8 byte; 342 343 for (i = 0; i < 8; ++i) { 344 val = 0; 345 for (j = 0; j < 4; ++j) { 346 if ((i2c->processed == i2c->msg->len) && (cnt != 0)) 347 break; 348 349 if (i2c->processed == 0 && cnt == 0) 350 byte = (i2c->addr & 0x7f) << 1; 351 else 352 byte = i2c->msg->buf[i2c->processed++]; 353 354 val |= byte << (j * 8); 355 cnt++; 356 } 357 358 i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i); 359 360 if (i2c->processed == i2c->msg->len) 361 break; 362 } 363 364 i2c_writel(i2c, cnt, REG_MTXCNT); 365 } 366 367 368 /* IRQ handlers for individual states */ 369 370 static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd) 371 { 372 if (!(ipd & REG_INT_START)) { 373 rk3x_i2c_stop(i2c, -EIO); 374 dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd); 375 rk3x_i2c_clean_ipd(i2c); 376 return; 377 } 378 379 /* ack interrupt */ 380 i2c_writel(i2c, REG_INT_START, REG_IPD); 381 382 /* disable start bit */ 383 i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON); 384 385 /* enable appropriate interrupts and transition */ 386 if (i2c->mode == REG_CON_MOD_TX) { 387 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN); 388 i2c->state = STATE_WRITE; 389 rk3x_i2c_fill_transmit_buf(i2c); 390 } else { 391 /* in any other case, we are going to be reading. */ 392 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN); 393 i2c->state = STATE_READ; 394 rk3x_i2c_prepare_read(i2c); 395 } 396 } 397 398 static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd) 399 { 400 if (!(ipd & REG_INT_MBTF)) { 401 rk3x_i2c_stop(i2c, -EIO); 402 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd); 403 rk3x_i2c_clean_ipd(i2c); 404 return; 405 } 406 407 /* ack interrupt */ 408 i2c_writel(i2c, REG_INT_MBTF, REG_IPD); 409 410 /* are we finished? */ 411 if (i2c->processed == i2c->msg->len) 412 rk3x_i2c_stop(i2c, i2c->error); 413 else 414 rk3x_i2c_fill_transmit_buf(i2c); 415 } 416 417 static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd) 418 { 419 unsigned int i; 420 unsigned int len = i2c->msg->len - i2c->processed; 421 u32 uninitialized_var(val); 422 u8 byte; 423 424 /* we only care for MBRF here. */ 425 if (!(ipd & REG_INT_MBRF)) 426 return; 427 428 /* ack interrupt */ 429 i2c_writel(i2c, REG_INT_MBRF, REG_IPD); 430 431 /* Can only handle a maximum of 32 bytes at a time */ 432 if (len > 32) 433 len = 32; 434 435 /* read the data from receive buffer */ 436 for (i = 0; i < len; ++i) { 437 if (i % 4 == 0) 438 val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4); 439 440 byte = (val >> ((i % 4) * 8)) & 0xff; 441 i2c->msg->buf[i2c->processed++] = byte; 442 } 443 444 /* are we finished? */ 445 if (i2c->processed == i2c->msg->len) 446 rk3x_i2c_stop(i2c, i2c->error); 447 else 448 rk3x_i2c_prepare_read(i2c); 449 } 450 451 static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd) 452 { 453 unsigned int con; 454 455 if (!(ipd & REG_INT_STOP)) { 456 rk3x_i2c_stop(i2c, -EIO); 457 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd); 458 rk3x_i2c_clean_ipd(i2c); 459 return; 460 } 461 462 /* ack interrupt */ 463 i2c_writel(i2c, REG_INT_STOP, REG_IPD); 464 465 /* disable STOP bit */ 466 con = i2c_readl(i2c, REG_CON); 467 con &= ~REG_CON_STOP; 468 i2c_writel(i2c, con, REG_CON); 469 470 i2c->busy = false; 471 i2c->state = STATE_IDLE; 472 473 /* signal rk3x_i2c_xfer that we are finished */ 474 wake_up(&i2c->wait); 475 } 476 477 static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id) 478 { 479 struct rk3x_i2c *i2c = dev_id; 480 unsigned int ipd; 481 482 spin_lock(&i2c->lock); 483 484 ipd = i2c_readl(i2c, REG_IPD); 485 if (i2c->state == STATE_IDLE) { 486 dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd); 487 rk3x_i2c_clean_ipd(i2c); 488 goto out; 489 } 490 491 dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd); 492 493 /* Clean interrupt bits we don't care about */ 494 ipd &= ~(REG_INT_BRF | REG_INT_BTF); 495 496 if (ipd & REG_INT_NAKRCV) { 497 /* 498 * We got a NACK in the last operation. Depending on whether 499 * IGNORE_NAK is set, we have to stop the operation and report 500 * an error. 501 */ 502 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD); 503 504 ipd &= ~REG_INT_NAKRCV; 505 506 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) 507 rk3x_i2c_stop(i2c, -ENXIO); 508 } 509 510 /* is there anything left to handle? */ 511 if ((ipd & REG_INT_ALL) == 0) 512 goto out; 513 514 switch (i2c->state) { 515 case STATE_START: 516 rk3x_i2c_handle_start(i2c, ipd); 517 break; 518 case STATE_WRITE: 519 rk3x_i2c_handle_write(i2c, ipd); 520 break; 521 case STATE_READ: 522 rk3x_i2c_handle_read(i2c, ipd); 523 break; 524 case STATE_STOP: 525 rk3x_i2c_handle_stop(i2c, ipd); 526 break; 527 case STATE_IDLE: 528 break; 529 } 530 531 out: 532 spin_unlock(&i2c->lock); 533 return IRQ_HANDLED; 534 } 535 536 /** 537 * Get timing values of I2C specification 538 * 539 * @speed: Desired SCL frequency 540 * 541 * Returns: Matched i2c spec values. 542 */ 543 static const struct i2c_spec_values *rk3x_i2c_get_spec(unsigned int speed) 544 { 545 if (speed <= 100000) 546 return &standard_mode_spec; 547 else if (speed <= 400000) 548 return &fast_mode_spec; 549 else 550 return &fast_mode_plus_spec; 551 } 552 553 /** 554 * Calculate divider values for desired SCL frequency 555 * 556 * @clk_rate: I2C input clock rate 557 * @t: Known I2C timing information 558 * @t_calc: Caculated rk3x private timings that would be written into regs 559 * 560 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case 561 * a best-effort divider value is returned in divs. If the target rate is 562 * too high, we silently use the highest possible rate. 563 */ 564 static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate, 565 struct i2c_timings *t, 566 struct rk3x_i2c_calced_timings *t_calc) 567 { 568 unsigned long min_low_ns, min_high_ns; 569 unsigned long max_low_ns, min_total_ns; 570 571 unsigned long clk_rate_khz, scl_rate_khz; 572 573 unsigned long min_low_div, min_high_div; 574 unsigned long max_low_div; 575 576 unsigned long min_div_for_hold, min_total_div; 577 unsigned long extra_div, extra_low_div, ideal_low_div; 578 579 unsigned long data_hold_buffer_ns = 50; 580 const struct i2c_spec_values *spec; 581 int ret = 0; 582 583 /* Only support standard-mode and fast-mode */ 584 if (WARN_ON(t->bus_freq_hz > 400000)) 585 t->bus_freq_hz = 400000; 586 587 /* prevent scl_rate_khz from becoming 0 */ 588 if (WARN_ON(t->bus_freq_hz < 1000)) 589 t->bus_freq_hz = 1000; 590 591 /* 592 * min_low_ns: The minimum number of ns we need to hold low to 593 * meet I2C specification, should include fall time. 594 * min_high_ns: The minimum number of ns we need to hold high to 595 * meet I2C specification, should include rise time. 596 * max_low_ns: The maximum number of ns we can hold low to meet 597 * I2C specification. 598 * 599 * Note: max_low_ns should be (maximum data hold time * 2 - buffer) 600 * This is because the i2c host on Rockchip holds the data line 601 * for half the low time. 602 */ 603 spec = rk3x_i2c_get_spec(t->bus_freq_hz); 604 min_high_ns = t->scl_rise_ns + spec->min_high_ns; 605 606 /* 607 * Timings for repeated start: 608 * - controller appears to drop SDA at .875x (7/8) programmed clk high. 609 * - controller appears to keep SCL high for 2x programmed clk high. 610 * 611 * We need to account for those rules in picking our "high" time so 612 * we meet tSU;STA and tHD;STA times. 613 */ 614 min_high_ns = max(min_high_ns, DIV_ROUND_UP( 615 (t->scl_rise_ns + spec->min_setup_start_ns) * 1000, 875)); 616 min_high_ns = max(min_high_ns, DIV_ROUND_UP( 617 (t->scl_rise_ns + spec->min_setup_start_ns + t->sda_fall_ns + 618 spec->min_high_ns), 2)); 619 620 min_low_ns = t->scl_fall_ns + spec->min_low_ns; 621 max_low_ns = spec->max_data_hold_ns * 2 - data_hold_buffer_ns; 622 min_total_ns = min_low_ns + min_high_ns; 623 624 /* Adjust to avoid overflow */ 625 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000); 626 scl_rate_khz = t->bus_freq_hz / 1000; 627 628 /* 629 * We need the total div to be >= this number 630 * so we don't clock too fast. 631 */ 632 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8); 633 634 /* These are the min dividers needed for min hold times. */ 635 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000); 636 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000); 637 min_div_for_hold = (min_low_div + min_high_div); 638 639 /* 640 * This is the maximum divider so we don't go over the maximum. 641 * We don't round up here (we round down) since this is a maximum. 642 */ 643 max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000); 644 645 if (min_low_div > max_low_div) { 646 WARN_ONCE(true, 647 "Conflicting, min_low_div %lu, max_low_div %lu\n", 648 min_low_div, max_low_div); 649 max_low_div = min_low_div; 650 } 651 652 if (min_div_for_hold > min_total_div) { 653 /* 654 * Time needed to meet hold requirements is important. 655 * Just use that. 656 */ 657 t_calc->div_low = min_low_div; 658 t_calc->div_high = min_high_div; 659 } else { 660 /* 661 * We've got to distribute some time among the low and high 662 * so we don't run too fast. 663 */ 664 extra_div = min_total_div - min_div_for_hold; 665 666 /* 667 * We'll try to split things up perfectly evenly, 668 * biasing slightly towards having a higher div 669 * for low (spend more time low). 670 */ 671 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 672 scl_rate_khz * 8 * min_total_ns); 673 674 /* Don't allow it to go over the maximum */ 675 if (ideal_low_div > max_low_div) 676 ideal_low_div = max_low_div; 677 678 /* 679 * Handle when the ideal low div is going to take up 680 * more than we have. 681 */ 682 if (ideal_low_div > min_low_div + extra_div) 683 ideal_low_div = min_low_div + extra_div; 684 685 /* Give low the "ideal" and give high whatever extra is left */ 686 extra_low_div = ideal_low_div - min_low_div; 687 t_calc->div_low = ideal_low_div; 688 t_calc->div_high = min_high_div + (extra_div - extra_low_div); 689 } 690 691 /* 692 * Adjust to the fact that the hardware has an implicit "+1". 693 * NOTE: Above calculations always produce div_low > 0 and div_high > 0. 694 */ 695 t_calc->div_low--; 696 t_calc->div_high--; 697 698 /* Give the tuning value 0, that would not update con register */ 699 t_calc->tuning = 0; 700 /* Maximum divider supported by hw is 0xffff */ 701 if (t_calc->div_low > 0xffff) { 702 t_calc->div_low = 0xffff; 703 ret = -EINVAL; 704 } 705 706 if (t_calc->div_high > 0xffff) { 707 t_calc->div_high = 0xffff; 708 ret = -EINVAL; 709 } 710 711 return ret; 712 } 713 714 /** 715 * Calculate timing values for desired SCL frequency 716 * 717 * @clk_rate: I2C input clock rate 718 * @t: Known I2C timing information 719 * @t_calc: Caculated rk3x private timings that would be written into regs 720 * 721 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case 722 * a best-effort divider value is returned in divs. If the target rate is 723 * too high, we silently use the highest possible rate. 724 * The following formulas are v1's method to calculate timings. 725 * 726 * l = divl + 1; 727 * h = divh + 1; 728 * s = sda_update_config + 1; 729 * u = start_setup_config + 1; 730 * p = stop_setup_config + 1; 731 * T = Tclk_i2c; 732 * 733 * tHigh = 8 * h * T; 734 * tLow = 8 * l * T; 735 * 736 * tHD;sda = (l * s + 1) * T; 737 * tSU;sda = [(8 - s) * l + 1] * T; 738 * tI2C = 8 * (l + h) * T; 739 * 740 * tSU;sta = (8h * u + 1) * T; 741 * tHD;sta = [8h * (u + 1) - 1] * T; 742 * tSU;sto = (8h * p + 1) * T; 743 */ 744 static int rk3x_i2c_v1_calc_timings(unsigned long clk_rate, 745 struct i2c_timings *t, 746 struct rk3x_i2c_calced_timings *t_calc) 747 { 748 unsigned long min_low_ns, min_high_ns; 749 unsigned long min_setup_start_ns, min_setup_data_ns; 750 unsigned long min_setup_stop_ns, max_hold_data_ns; 751 752 unsigned long clk_rate_khz, scl_rate_khz; 753 754 unsigned long min_low_div, min_high_div; 755 756 unsigned long min_div_for_hold, min_total_div; 757 unsigned long extra_div, extra_low_div; 758 unsigned long sda_update_cfg, stp_sta_cfg, stp_sto_cfg; 759 760 const struct i2c_spec_values *spec; 761 int ret = 0; 762 763 /* Support standard-mode, fast-mode and fast-mode plus */ 764 if (WARN_ON(t->bus_freq_hz > 1000000)) 765 t->bus_freq_hz = 1000000; 766 767 /* prevent scl_rate_khz from becoming 0 */ 768 if (WARN_ON(t->bus_freq_hz < 1000)) 769 t->bus_freq_hz = 1000; 770 771 /* 772 * min_low_ns: The minimum number of ns we need to hold low to 773 * meet I2C specification, should include fall time. 774 * min_high_ns: The minimum number of ns we need to hold high to 775 * meet I2C specification, should include rise time. 776 */ 777 spec = rk3x_i2c_get_spec(t->bus_freq_hz); 778 779 /* calculate min-divh and min-divl */ 780 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000); 781 scl_rate_khz = t->bus_freq_hz / 1000; 782 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8); 783 784 min_high_ns = t->scl_rise_ns + spec->min_high_ns; 785 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000); 786 787 min_low_ns = t->scl_fall_ns + spec->min_low_ns; 788 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000); 789 790 /* 791 * Final divh and divl must be greater than 0, otherwise the 792 * hardware would not output the i2c clk. 793 */ 794 min_high_div = (min_high_div < 1) ? 2 : min_high_div; 795 min_low_div = (min_low_div < 1) ? 2 : min_low_div; 796 797 /* These are the min dividers needed for min hold times. */ 798 min_div_for_hold = (min_low_div + min_high_div); 799 800 /* 801 * This is the maximum divider so we don't go over the maximum. 802 * We don't round up here (we round down) since this is a maximum. 803 */ 804 if (min_div_for_hold >= min_total_div) { 805 /* 806 * Time needed to meet hold requirements is important. 807 * Just use that. 808 */ 809 t_calc->div_low = min_low_div; 810 t_calc->div_high = min_high_div; 811 } else { 812 /* 813 * We've got to distribute some time among the low and high 814 * so we don't run too fast. 815 * We'll try to split things up by the scale of min_low_div and 816 * min_high_div, biasing slightly towards having a higher div 817 * for low (spend more time low). 818 */ 819 extra_div = min_total_div - min_div_for_hold; 820 extra_low_div = DIV_ROUND_UP(min_low_div * extra_div, 821 min_div_for_hold); 822 823 t_calc->div_low = min_low_div + extra_low_div; 824 t_calc->div_high = min_high_div + (extra_div - extra_low_div); 825 } 826 827 /* 828 * calculate sda data hold count by the rules, data_upd_st:3 829 * is a appropriate value to reduce calculated times. 830 */ 831 for (sda_update_cfg = 3; sda_update_cfg > 0; sda_update_cfg--) { 832 max_hold_data_ns = DIV_ROUND_UP((sda_update_cfg 833 * (t_calc->div_low) + 1) 834 * 1000000, clk_rate_khz); 835 min_setup_data_ns = DIV_ROUND_UP(((8 - sda_update_cfg) 836 * (t_calc->div_low) + 1) 837 * 1000000, clk_rate_khz); 838 if ((max_hold_data_ns < spec->max_data_hold_ns) && 839 (min_setup_data_ns > spec->min_data_setup_ns)) 840 break; 841 } 842 843 /* calculate setup start config */ 844 min_setup_start_ns = t->scl_rise_ns + spec->min_setup_start_ns; 845 stp_sta_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_start_ns 846 - 1000000, 8 * 1000000 * (t_calc->div_high)); 847 848 /* calculate setup stop config */ 849 min_setup_stop_ns = t->scl_rise_ns + spec->min_setup_stop_ns; 850 stp_sto_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_stop_ns 851 - 1000000, 8 * 1000000 * (t_calc->div_high)); 852 853 t_calc->tuning = REG_CON_SDA_CFG(--sda_update_cfg) | 854 REG_CON_STA_CFG(--stp_sta_cfg) | 855 REG_CON_STO_CFG(--stp_sto_cfg); 856 857 t_calc->div_low--; 858 t_calc->div_high--; 859 860 /* Maximum divider supported by hw is 0xffff */ 861 if (t_calc->div_low > 0xffff) { 862 t_calc->div_low = 0xffff; 863 ret = -EINVAL; 864 } 865 866 if (t_calc->div_high > 0xffff) { 867 t_calc->div_high = 0xffff; 868 ret = -EINVAL; 869 } 870 871 return ret; 872 } 873 874 static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate) 875 { 876 struct i2c_timings *t = &i2c->t; 877 struct rk3x_i2c_calced_timings calc; 878 u64 t_low_ns, t_high_ns; 879 unsigned long flags; 880 u32 val; 881 int ret; 882 883 ret = i2c->soc_data->calc_timings(clk_rate, t, &calc); 884 WARN_ONCE(ret != 0, "Could not reach SCL freq %u", t->bus_freq_hz); 885 886 clk_enable(i2c->pclk); 887 888 spin_lock_irqsave(&i2c->lock, flags); 889 val = i2c_readl(i2c, REG_CON); 890 val &= ~REG_CON_TUNING_MASK; 891 val |= calc.tuning; 892 i2c_writel(i2c, val, REG_CON); 893 i2c_writel(i2c, (calc.div_high << 16) | (calc.div_low & 0xffff), 894 REG_CLKDIV); 895 spin_unlock_irqrestore(&i2c->lock, flags); 896 897 clk_disable(i2c->pclk); 898 899 t_low_ns = div_u64(((u64)calc.div_low + 1) * 8 * 1000000000, clk_rate); 900 t_high_ns = div_u64(((u64)calc.div_high + 1) * 8 * 1000000000, 901 clk_rate); 902 dev_dbg(i2c->dev, 903 "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n", 904 clk_rate / 1000, 905 1000000000 / t->bus_freq_hz, 906 t_low_ns, t_high_ns); 907 } 908 909 /** 910 * rk3x_i2c_clk_notifier_cb - Clock rate change callback 911 * @nb: Pointer to notifier block 912 * @event: Notification reason 913 * @data: Pointer to notification data object 914 * 915 * The callback checks whether a valid bus frequency can be generated after the 916 * change. If so, the change is acknowledged, otherwise the change is aborted. 917 * New dividers are written to the HW in the pre- or post change notification 918 * depending on the scaling direction. 919 * 920 * Code adapted from i2c-cadence.c. 921 * 922 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK 923 * to acknowledge the change, NOTIFY_DONE if the notification is 924 * considered irrelevant. 925 */ 926 static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long 927 event, void *data) 928 { 929 struct clk_notifier_data *ndata = data; 930 struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb); 931 struct rk3x_i2c_calced_timings calc; 932 933 switch (event) { 934 case PRE_RATE_CHANGE: 935 /* 936 * Try the calculation (but don't store the result) ahead of 937 * time to see if we need to block the clock change. Timings 938 * shouldn't actually take effect until rk3x_i2c_adapt_div(). 939 */ 940 if (i2c->soc_data->calc_timings(ndata->new_rate, &i2c->t, 941 &calc) != 0) 942 return NOTIFY_STOP; 943 944 /* scale up */ 945 if (ndata->new_rate > ndata->old_rate) 946 rk3x_i2c_adapt_div(i2c, ndata->new_rate); 947 948 return NOTIFY_OK; 949 case POST_RATE_CHANGE: 950 /* scale down */ 951 if (ndata->new_rate < ndata->old_rate) 952 rk3x_i2c_adapt_div(i2c, ndata->new_rate); 953 return NOTIFY_OK; 954 case ABORT_RATE_CHANGE: 955 /* scale up */ 956 if (ndata->new_rate > ndata->old_rate) 957 rk3x_i2c_adapt_div(i2c, ndata->old_rate); 958 return NOTIFY_OK; 959 default: 960 return NOTIFY_DONE; 961 } 962 } 963 964 /** 965 * Setup I2C registers for an I2C operation specified by msgs, num. 966 * 967 * Must be called with i2c->lock held. 968 * 969 * @msgs: I2C msgs to process 970 * @num: Number of msgs 971 * 972 * returns: Number of I2C msgs processed or negative in case of error 973 */ 974 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num) 975 { 976 u32 addr = (msgs[0].addr & 0x7f) << 1; 977 int ret = 0; 978 979 /* 980 * The I2C adapter can issue a small (len < 4) write packet before 981 * reading. This speeds up SMBus-style register reads. 982 * The MRXADDR/MRXRADDR hold the slave address and the slave register 983 * address in this case. 984 */ 985 986 if (num >= 2 && msgs[0].len < 4 && 987 !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) { 988 u32 reg_addr = 0; 989 int i; 990 991 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n", 992 addr >> 1); 993 994 /* Fill MRXRADDR with the register address(es) */ 995 for (i = 0; i < msgs[0].len; ++i) { 996 reg_addr |= msgs[0].buf[i] << (i * 8); 997 reg_addr |= REG_MRXADDR_VALID(i); 998 } 999 1000 /* msgs[0] is handled by hw. */ 1001 i2c->msg = &msgs[1]; 1002 1003 i2c->mode = REG_CON_MOD_REGISTER_TX; 1004 1005 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR); 1006 i2c_writel(i2c, reg_addr, REG_MRXRADDR); 1007 1008 ret = 2; 1009 } else { 1010 /* 1011 * We'll have to do it the boring way and process the msgs 1012 * one-by-one. 1013 */ 1014 1015 if (msgs[0].flags & I2C_M_RD) { 1016 addr |= 1; /* set read bit */ 1017 1018 /* 1019 * We have to transmit the slave addr first. Use 1020 * MOD_REGISTER_TX for that purpose. 1021 */ 1022 i2c->mode = REG_CON_MOD_REGISTER_TX; 1023 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), 1024 REG_MRXADDR); 1025 i2c_writel(i2c, 0, REG_MRXRADDR); 1026 } else { 1027 i2c->mode = REG_CON_MOD_TX; 1028 } 1029 1030 i2c->msg = &msgs[0]; 1031 1032 ret = 1; 1033 } 1034 1035 i2c->addr = msgs[0].addr; 1036 i2c->busy = true; 1037 i2c->state = STATE_START; 1038 i2c->processed = 0; 1039 i2c->error = 0; 1040 1041 rk3x_i2c_clean_ipd(i2c); 1042 1043 return ret; 1044 } 1045 1046 static int rk3x_i2c_xfer(struct i2c_adapter *adap, 1047 struct i2c_msg *msgs, int num) 1048 { 1049 struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data; 1050 unsigned long timeout, flags; 1051 u32 val; 1052 int ret = 0; 1053 int i; 1054 1055 spin_lock_irqsave(&i2c->lock, flags); 1056 1057 clk_enable(i2c->clk); 1058 clk_enable(i2c->pclk); 1059 1060 i2c->is_last_msg = false; 1061 1062 /* 1063 * Process msgs. We can handle more than one message at once (see 1064 * rk3x_i2c_setup()). 1065 */ 1066 for (i = 0; i < num; i += ret) { 1067 ret = rk3x_i2c_setup(i2c, msgs + i, num - i); 1068 1069 if (ret < 0) { 1070 dev_err(i2c->dev, "rk3x_i2c_setup() failed\n"); 1071 break; 1072 } 1073 1074 if (i + ret >= num) 1075 i2c->is_last_msg = true; 1076 1077 spin_unlock_irqrestore(&i2c->lock, flags); 1078 1079 rk3x_i2c_start(i2c); 1080 1081 timeout = wait_event_timeout(i2c->wait, !i2c->busy, 1082 msecs_to_jiffies(WAIT_TIMEOUT)); 1083 1084 spin_lock_irqsave(&i2c->lock, flags); 1085 1086 if (timeout == 0) { 1087 dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n", 1088 i2c_readl(i2c, REG_IPD), i2c->state); 1089 1090 /* Force a STOP condition without interrupt */ 1091 i2c_writel(i2c, 0, REG_IEN); 1092 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK; 1093 val |= REG_CON_EN | REG_CON_STOP; 1094 i2c_writel(i2c, val, REG_CON); 1095 1096 i2c->state = STATE_IDLE; 1097 1098 ret = -ETIMEDOUT; 1099 break; 1100 } 1101 1102 if (i2c->error) { 1103 ret = i2c->error; 1104 break; 1105 } 1106 } 1107 1108 clk_disable(i2c->pclk); 1109 clk_disable(i2c->clk); 1110 1111 spin_unlock_irqrestore(&i2c->lock, flags); 1112 1113 return ret < 0 ? ret : num; 1114 } 1115 1116 static __maybe_unused int rk3x_i2c_resume(struct device *dev) 1117 { 1118 struct rk3x_i2c *i2c = dev_get_drvdata(dev); 1119 1120 rk3x_i2c_adapt_div(i2c, clk_get_rate(i2c->clk)); 1121 1122 return 0; 1123 } 1124 1125 static u32 rk3x_i2c_func(struct i2c_adapter *adap) 1126 { 1127 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 1128 } 1129 1130 static const struct i2c_algorithm rk3x_i2c_algorithm = { 1131 .master_xfer = rk3x_i2c_xfer, 1132 .functionality = rk3x_i2c_func, 1133 }; 1134 1135 static const struct rk3x_i2c_soc_data rv1108_soc_data = { 1136 .grf_offset = -1, 1137 .calc_timings = rk3x_i2c_v1_calc_timings, 1138 }; 1139 1140 static const struct rk3x_i2c_soc_data rk3066_soc_data = { 1141 .grf_offset = 0x154, 1142 .calc_timings = rk3x_i2c_v0_calc_timings, 1143 }; 1144 1145 static const struct rk3x_i2c_soc_data rk3188_soc_data = { 1146 .grf_offset = 0x0a4, 1147 .calc_timings = rk3x_i2c_v0_calc_timings, 1148 }; 1149 1150 static const struct rk3x_i2c_soc_data rk3228_soc_data = { 1151 .grf_offset = -1, 1152 .calc_timings = rk3x_i2c_v0_calc_timings, 1153 }; 1154 1155 static const struct rk3x_i2c_soc_data rk3288_soc_data = { 1156 .grf_offset = -1, 1157 .calc_timings = rk3x_i2c_v0_calc_timings, 1158 }; 1159 1160 static const struct rk3x_i2c_soc_data rk3399_soc_data = { 1161 .grf_offset = -1, 1162 .calc_timings = rk3x_i2c_v1_calc_timings, 1163 }; 1164 1165 static const struct of_device_id rk3x_i2c_match[] = { 1166 { 1167 .compatible = "rockchip,rv1108-i2c", 1168 .data = &rv1108_soc_data 1169 }, 1170 { 1171 .compatible = "rockchip,rk3066-i2c", 1172 .data = &rk3066_soc_data 1173 }, 1174 { 1175 .compatible = "rockchip,rk3188-i2c", 1176 .data = &rk3188_soc_data 1177 }, 1178 { 1179 .compatible = "rockchip,rk3228-i2c", 1180 .data = &rk3228_soc_data 1181 }, 1182 { 1183 .compatible = "rockchip,rk3288-i2c", 1184 .data = &rk3288_soc_data 1185 }, 1186 { 1187 .compatible = "rockchip,rk3399-i2c", 1188 .data = &rk3399_soc_data 1189 }, 1190 {}, 1191 }; 1192 MODULE_DEVICE_TABLE(of, rk3x_i2c_match); 1193 1194 static int rk3x_i2c_probe(struct platform_device *pdev) 1195 { 1196 struct device_node *np = pdev->dev.of_node; 1197 const struct of_device_id *match; 1198 struct rk3x_i2c *i2c; 1199 struct resource *mem; 1200 int ret = 0; 1201 int bus_nr; 1202 u32 value; 1203 int irq; 1204 unsigned long clk_rate; 1205 1206 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL); 1207 if (!i2c) 1208 return -ENOMEM; 1209 1210 match = of_match_node(rk3x_i2c_match, np); 1211 i2c->soc_data = match->data; 1212 1213 /* use common interface to get I2C timing properties */ 1214 i2c_parse_fw_timings(&pdev->dev, &i2c->t, true); 1215 1216 strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); 1217 i2c->adap.owner = THIS_MODULE; 1218 i2c->adap.algo = &rk3x_i2c_algorithm; 1219 i2c->adap.retries = 3; 1220 i2c->adap.dev.of_node = np; 1221 i2c->adap.algo_data = i2c; 1222 i2c->adap.dev.parent = &pdev->dev; 1223 1224 i2c->dev = &pdev->dev; 1225 1226 spin_lock_init(&i2c->lock); 1227 init_waitqueue_head(&i2c->wait); 1228 1229 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1230 i2c->regs = devm_ioremap_resource(&pdev->dev, mem); 1231 if (IS_ERR(i2c->regs)) 1232 return PTR_ERR(i2c->regs); 1233 1234 /* Try to set the I2C adapter number from dt */ 1235 bus_nr = of_alias_get_id(np, "i2c"); 1236 1237 /* 1238 * Switch to new interface if the SoC also offers the old one. 1239 * The control bit is located in the GRF register space. 1240 */ 1241 if (i2c->soc_data->grf_offset >= 0) { 1242 struct regmap *grf; 1243 1244 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1245 if (IS_ERR(grf)) { 1246 dev_err(&pdev->dev, 1247 "rk3x-i2c needs 'rockchip,grf' property\n"); 1248 return PTR_ERR(grf); 1249 } 1250 1251 if (bus_nr < 0) { 1252 dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias"); 1253 return -EINVAL; 1254 } 1255 1256 /* 27+i: write mask, 11+i: value */ 1257 value = BIT(27 + bus_nr) | BIT(11 + bus_nr); 1258 1259 ret = regmap_write(grf, i2c->soc_data->grf_offset, value); 1260 if (ret != 0) { 1261 dev_err(i2c->dev, "Could not write to GRF: %d\n", ret); 1262 return ret; 1263 } 1264 } 1265 1266 /* IRQ setup */ 1267 irq = platform_get_irq(pdev, 0); 1268 if (irq < 0) { 1269 dev_err(&pdev->dev, "cannot find rk3x IRQ\n"); 1270 return irq; 1271 } 1272 1273 ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq, 1274 0, dev_name(&pdev->dev), i2c); 1275 if (ret < 0) { 1276 dev_err(&pdev->dev, "cannot request IRQ\n"); 1277 return ret; 1278 } 1279 1280 platform_set_drvdata(pdev, i2c); 1281 1282 if (i2c->soc_data->calc_timings == rk3x_i2c_v0_calc_timings) { 1283 /* Only one clock to use for bus clock and peripheral clock */ 1284 i2c->clk = devm_clk_get(&pdev->dev, NULL); 1285 i2c->pclk = i2c->clk; 1286 } else { 1287 i2c->clk = devm_clk_get(&pdev->dev, "i2c"); 1288 i2c->pclk = devm_clk_get(&pdev->dev, "pclk"); 1289 } 1290 1291 if (IS_ERR(i2c->clk)) { 1292 ret = PTR_ERR(i2c->clk); 1293 if (ret != -EPROBE_DEFER) 1294 dev_err(&pdev->dev, "Can't get bus clk: %d\n", ret); 1295 return ret; 1296 } 1297 if (IS_ERR(i2c->pclk)) { 1298 ret = PTR_ERR(i2c->pclk); 1299 if (ret != -EPROBE_DEFER) 1300 dev_err(&pdev->dev, "Can't get periph clk: %d\n", ret); 1301 return ret; 1302 } 1303 1304 ret = clk_prepare(i2c->clk); 1305 if (ret < 0) { 1306 dev_err(&pdev->dev, "Can't prepare bus clk: %d\n", ret); 1307 return ret; 1308 } 1309 ret = clk_prepare(i2c->pclk); 1310 if (ret < 0) { 1311 dev_err(&pdev->dev, "Can't prepare periph clock: %d\n", ret); 1312 goto err_clk; 1313 } 1314 1315 i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb; 1316 ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb); 1317 if (ret != 0) { 1318 dev_err(&pdev->dev, "Unable to register clock notifier\n"); 1319 goto err_pclk; 1320 } 1321 1322 clk_rate = clk_get_rate(i2c->clk); 1323 rk3x_i2c_adapt_div(i2c, clk_rate); 1324 1325 ret = i2c_add_adapter(&i2c->adap); 1326 if (ret < 0) 1327 goto err_clk_notifier; 1328 1329 dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs); 1330 1331 return 0; 1332 1333 err_clk_notifier: 1334 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb); 1335 err_pclk: 1336 clk_unprepare(i2c->pclk); 1337 err_clk: 1338 clk_unprepare(i2c->clk); 1339 return ret; 1340 } 1341 1342 static int rk3x_i2c_remove(struct platform_device *pdev) 1343 { 1344 struct rk3x_i2c *i2c = platform_get_drvdata(pdev); 1345 1346 i2c_del_adapter(&i2c->adap); 1347 1348 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb); 1349 clk_unprepare(i2c->pclk); 1350 clk_unprepare(i2c->clk); 1351 1352 return 0; 1353 } 1354 1355 static SIMPLE_DEV_PM_OPS(rk3x_i2c_pm_ops, NULL, rk3x_i2c_resume); 1356 1357 static struct platform_driver rk3x_i2c_driver = { 1358 .probe = rk3x_i2c_probe, 1359 .remove = rk3x_i2c_remove, 1360 .driver = { 1361 .name = "rk3x-i2c", 1362 .of_match_table = rk3x_i2c_match, 1363 .pm = &rk3x_i2c_pm_ops, 1364 }, 1365 }; 1366 1367 module_platform_driver(rk3x_i2c_driver); 1368 1369 MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver"); 1370 MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>"); 1371 MODULE_LICENSE("GPL v2"); 1372